1// SPDX-License-Identifier: GPL-2.0 2#include "bcm283x.dtsi" 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/soc/bcm2835-pm.h> 6 7/ { 8 compatible = "brcm,bcm2711"; 9 10 #address-cells = <2>; 11 #size-cells = <1>; 12 13 interrupt-parent = <&gicv2>; 14 15 vc4: gpu { 16 compatible = "brcm,bcm2711-vc5"; 17 status = "disabled"; 18 }; 19 20 clk_27MHz: clk-27M { 21 #clock-cells = <0>; 22 compatible = "fixed-clock"; 23 clock-frequency = <27000000>; 24 clock-output-names = "27MHz-clock"; 25 }; 26 27 clk_108MHz: clk-108M { 28 #clock-cells = <0>; 29 compatible = "fixed-clock"; 30 clock-frequency = <108000000>; 31 clock-output-names = "108MHz-clock"; 32 }; 33 34 soc { 35 /* 36 * Defined ranges: 37 * Common BCM283x peripherals 38 * BCM2711-specific peripherals 39 * ARM-local peripherals 40 */ 41 ranges = <0x7e000000 0x0 0xfe000000 0x01800000>, 42 <0x7c000000 0x0 0xfc000000 0x02000000>, 43 <0x40000000 0x0 0xff800000 0x00800000>; 44 /* Emulate a contiguous 30-bit address range for DMA */ 45 dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>; 46 47 /* 48 * This node is the provider for the enable-method for 49 * bringing up secondary cores. 50 */ 51 local_intc: local_intc@40000000 { 52 compatible = "brcm,bcm2836-l1-intc"; 53 reg = <0x40000000 0x100>; 54 }; 55 56 gicv2: interrupt-controller@40041000 { 57 interrupt-controller; 58 #interrupt-cells = <3>; 59 compatible = "arm,gic-400"; 60 reg = <0x40041000 0x1000>, 61 <0x40042000 0x2000>, 62 <0x40044000 0x2000>, 63 <0x40046000 0x2000>; 64 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 65 IRQ_TYPE_LEVEL_HIGH)>; 66 }; 67 68 avs_monitor: avs-monitor@7d5d2000 { 69 compatible = "brcm,bcm2711-avs-monitor", 70 "syscon", "simple-mfd"; 71 reg = <0x7d5d2000 0xf00>; 72 73 thermal: thermal { 74 compatible = "brcm,bcm2711-thermal"; 75 #thermal-sensor-cells = <0>; 76 }; 77 }; 78 79 dma: dma@7e007000 { 80 compatible = "brcm,bcm2835-dma"; 81 reg = <0x7e007000 0xb00>; 82 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 89 /* DMA lite 7 - 10 */ 90 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 94 interrupt-names = "dma0", 95 "dma1", 96 "dma2", 97 "dma3", 98 "dma4", 99 "dma5", 100 "dma6", 101 "dma7", 102 "dma8", 103 "dma9", 104 "dma10"; 105 #dma-cells = <1>; 106 brcm,dma-channel-mask = <0x07f5>; 107 }; 108 109 pm: watchdog@7e100000 { 110 compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt"; 111 #power-domain-cells = <1>; 112 #reset-cells = <1>; 113 reg = <0x7e100000 0x114>, 114 <0x7e00a000 0x24>, 115 <0x7ec11000 0x20>; 116 clocks = <&clocks BCM2835_CLOCK_V3D>, 117 <&clocks BCM2835_CLOCK_PERI_IMAGE>, 118 <&clocks BCM2835_CLOCK_H264>, 119 <&clocks BCM2835_CLOCK_ISP>; 120 clock-names = "v3d", "peri_image", "h264", "isp"; 121 system-power-controller; 122 }; 123 124 rng@7e104000 { 125 compatible = "brcm,bcm2711-rng200"; 126 reg = <0x7e104000 0x28>; 127 }; 128 129 uart2: serial@7e201400 { 130 compatible = "arm,pl011", "arm,primecell"; 131 reg = <0x7e201400 0x200>; 132 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 133 clocks = <&clocks BCM2835_CLOCK_UART>, 134 <&clocks BCM2835_CLOCK_VPU>; 135 clock-names = "uartclk", "apb_pclk"; 136 arm,primecell-periphid = <0x00241011>; 137 status = "disabled"; 138 }; 139 140 uart3: serial@7e201600 { 141 compatible = "arm,pl011", "arm,primecell"; 142 reg = <0x7e201600 0x200>; 143 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 144 clocks = <&clocks BCM2835_CLOCK_UART>, 145 <&clocks BCM2835_CLOCK_VPU>; 146 clock-names = "uartclk", "apb_pclk"; 147 arm,primecell-periphid = <0x00241011>; 148 status = "disabled"; 149 }; 150 151 uart4: serial@7e201800 { 152 compatible = "arm,pl011", "arm,primecell"; 153 reg = <0x7e201800 0x200>; 154 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 155 clocks = <&clocks BCM2835_CLOCK_UART>, 156 <&clocks BCM2835_CLOCK_VPU>; 157 clock-names = "uartclk", "apb_pclk"; 158 arm,primecell-periphid = <0x00241011>; 159 status = "disabled"; 160 }; 161 162 uart5: serial@7e201a00 { 163 compatible = "arm,pl011", "arm,primecell"; 164 reg = <0x7e201a00 0x200>; 165 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 166 clocks = <&clocks BCM2835_CLOCK_UART>, 167 <&clocks BCM2835_CLOCK_VPU>; 168 clock-names = "uartclk", "apb_pclk"; 169 arm,primecell-periphid = <0x00241011>; 170 status = "disabled"; 171 }; 172 173 spi3: spi@7e204600 { 174 compatible = "brcm,bcm2835-spi"; 175 reg = <0x7e204600 0x0200>; 176 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 177 clocks = <&clocks BCM2835_CLOCK_VPU>; 178 #address-cells = <1>; 179 #size-cells = <0>; 180 status = "disabled"; 181 }; 182 183 spi4: spi@7e204800 { 184 compatible = "brcm,bcm2835-spi"; 185 reg = <0x7e204800 0x0200>; 186 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 187 clocks = <&clocks BCM2835_CLOCK_VPU>; 188 #address-cells = <1>; 189 #size-cells = <0>; 190 status = "disabled"; 191 }; 192 193 spi5: spi@7e204a00 { 194 compatible = "brcm,bcm2835-spi"; 195 reg = <0x7e204a00 0x0200>; 196 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 197 clocks = <&clocks BCM2835_CLOCK_VPU>; 198 #address-cells = <1>; 199 #size-cells = <0>; 200 status = "disabled"; 201 }; 202 203 spi6: spi@7e204c00 { 204 compatible = "brcm,bcm2835-spi"; 205 reg = <0x7e204c00 0x0200>; 206 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 207 clocks = <&clocks BCM2835_CLOCK_VPU>; 208 #address-cells = <1>; 209 #size-cells = <0>; 210 status = "disabled"; 211 }; 212 213 i2c3: i2c@7e205600 { 214 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 215 reg = <0x7e205600 0x200>; 216 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 217 clocks = <&clocks BCM2835_CLOCK_VPU>; 218 #address-cells = <1>; 219 #size-cells = <0>; 220 status = "disabled"; 221 }; 222 223 i2c4: i2c@7e205800 { 224 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 225 reg = <0x7e205800 0x200>; 226 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&clocks BCM2835_CLOCK_VPU>; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 status = "disabled"; 231 }; 232 233 i2c5: i2c@7e205a00 { 234 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 235 reg = <0x7e205a00 0x200>; 236 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&clocks BCM2835_CLOCK_VPU>; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 status = "disabled"; 241 }; 242 243 i2c6: i2c@7e205c00 { 244 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 245 reg = <0x7e205c00 0x200>; 246 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 247 clocks = <&clocks BCM2835_CLOCK_VPU>; 248 #address-cells = <1>; 249 #size-cells = <0>; 250 status = "disabled"; 251 }; 252 253 pixelvalve0: pixelvalve@7e206000 { 254 compatible = "brcm,bcm2711-pixelvalve0"; 255 reg = <0x7e206000 0x100>; 256 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 257 status = "disabled"; 258 }; 259 260 pixelvalve1: pixelvalve@7e207000 { 261 compatible = "brcm,bcm2711-pixelvalve1"; 262 reg = <0x7e207000 0x100>; 263 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 264 status = "disabled"; 265 }; 266 267 pixelvalve2: pixelvalve@7e20a000 { 268 compatible = "brcm,bcm2711-pixelvalve2"; 269 reg = <0x7e20a000 0x100>; 270 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 271 status = "disabled"; 272 }; 273 274 pwm1: pwm@7e20c800 { 275 compatible = "brcm,bcm2835-pwm"; 276 reg = <0x7e20c800 0x28>; 277 clocks = <&clocks BCM2835_CLOCK_PWM>; 278 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>; 279 assigned-clock-rates = <10000000>; 280 #pwm-cells = <2>; 281 status = "disabled"; 282 }; 283 284 pixelvalve4: pixelvalve@7e216000 { 285 compatible = "brcm,bcm2711-pixelvalve4"; 286 reg = <0x7e216000 0x100>; 287 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 288 status = "disabled"; 289 }; 290 291 hvs: hvs@7e400000 { 292 compatible = "brcm,bcm2711-hvs"; 293 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 294 }; 295 296 pixelvalve3: pixelvalve@7ec12000 { 297 compatible = "brcm,bcm2711-pixelvalve3"; 298 reg = <0x7ec12000 0x100>; 299 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 300 status = "disabled"; 301 }; 302 303 dvp: clock@7ef00000 { 304 compatible = "brcm,brcm2711-dvp"; 305 reg = <0x7ef00000 0x10>; 306 clocks = <&clk_108MHz>; 307 #clock-cells = <1>; 308 #reset-cells = <1>; 309 }; 310 311 hdmi0: hdmi@7ef00700 { 312 compatible = "brcm,bcm2711-hdmi0"; 313 reg = <0x7ef00700 0x300>, 314 <0x7ef00300 0x200>, 315 <0x7ef00f00 0x80>, 316 <0x7ef00f80 0x80>, 317 <0x7ef01b00 0x200>, 318 <0x7ef01f00 0x400>, 319 <0x7ef00200 0x80>, 320 <0x7ef04300 0x100>, 321 <0x7ef20000 0x100>; 322 reg-names = "hdmi", 323 "dvp", 324 "phy", 325 "rm", 326 "packet", 327 "metadata", 328 "csc", 329 "cec", 330 "hd"; 331 clock-names = "hdmi", "bvb", "audio", "cec"; 332 resets = <&dvp 0>; 333 ddc = <&ddc0>; 334 dmas = <&dma 10>; 335 dma-names = "audio-rx"; 336 status = "disabled"; 337 }; 338 339 ddc0: i2c@7ef04500 { 340 compatible = "brcm,bcm2711-hdmi-i2c"; 341 reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>; 342 reg-names = "bsc", "auto-i2c"; 343 clock-frequency = <97500>; 344 status = "disabled"; 345 }; 346 347 hdmi1: hdmi@7ef05700 { 348 compatible = "brcm,bcm2711-hdmi1"; 349 reg = <0x7ef05700 0x300>, 350 <0x7ef05300 0x200>, 351 <0x7ef05f00 0x80>, 352 <0x7ef05f80 0x80>, 353 <0x7ef06b00 0x200>, 354 <0x7ef06f00 0x400>, 355 <0x7ef00280 0x80>, 356 <0x7ef09300 0x100>, 357 <0x7ef20000 0x100>; 358 reg-names = "hdmi", 359 "dvp", 360 "phy", 361 "rm", 362 "packet", 363 "metadata", 364 "csc", 365 "cec", 366 "hd"; 367 ddc = <&ddc1>; 368 clock-names = "hdmi", "bvb", "audio", "cec"; 369 resets = <&dvp 1>; 370 dmas = <&dma 17>; 371 dma-names = "audio-rx"; 372 status = "disabled"; 373 }; 374 375 ddc1: i2c@7ef09500 { 376 compatible = "brcm,bcm2711-hdmi-i2c"; 377 reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>; 378 reg-names = "bsc", "auto-i2c"; 379 clock-frequency = <97500>; 380 status = "disabled"; 381 }; 382 }; 383 384 /* 385 * emmc2 has different DMA constraints based on SoC revisions. It was 386 * moved into its own bus, so as for RPi4's firmware to update them. 387 * The firmware will find whether the emmc2bus alias is defined, and if 388 * so, it'll edit the dma-ranges property below accordingly. 389 */ 390 emmc2bus: emmc2bus { 391 compatible = "simple-bus"; 392 #address-cells = <2>; 393 #size-cells = <1>; 394 395 ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>; 396 dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>; 397 398 emmc2: emmc2@7e340000 { 399 compatible = "brcm,bcm2711-emmc2"; 400 reg = <0x0 0x7e340000 0x100>; 401 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&clocks BCM2711_CLOCK_EMMC2>; 403 status = "disabled"; 404 }; 405 }; 406 407 arm-pmu { 408 compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3"; 409 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 413 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 414 }; 415 416 timer { 417 compatible = "arm,armv8-timer"; 418 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 419 IRQ_TYPE_LEVEL_LOW)>, 420 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 421 IRQ_TYPE_LEVEL_LOW)>, 422 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 423 IRQ_TYPE_LEVEL_LOW)>, 424 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 425 IRQ_TYPE_LEVEL_LOW)>; 426 /* This only applies to the ARMv7 stub */ 427 arm,cpu-registers-not-fw-configured; 428 }; 429 430 cpus: cpus { 431 #address-cells = <1>; 432 #size-cells = <0>; 433 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit 434 435 cpu0: cpu@0 { 436 device_type = "cpu"; 437 compatible = "arm,cortex-a72"; 438 reg = <0>; 439 enable-method = "spin-table"; 440 cpu-release-addr = <0x0 0x000000d8>; 441 }; 442 443 cpu1: cpu@1 { 444 device_type = "cpu"; 445 compatible = "arm,cortex-a72"; 446 reg = <1>; 447 enable-method = "spin-table"; 448 cpu-release-addr = <0x0 0x000000e0>; 449 }; 450 451 cpu2: cpu@2 { 452 device_type = "cpu"; 453 compatible = "arm,cortex-a72"; 454 reg = <2>; 455 enable-method = "spin-table"; 456 cpu-release-addr = <0x0 0x000000e8>; 457 }; 458 459 cpu3: cpu@3 { 460 device_type = "cpu"; 461 compatible = "arm,cortex-a72"; 462 reg = <3>; 463 enable-method = "spin-table"; 464 cpu-release-addr = <0x0 0x000000f0>; 465 }; 466 }; 467 468 scb { 469 compatible = "simple-bus"; 470 #address-cells = <2>; 471 #size-cells = <1>; 472 473 ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>, 474 <0x6 0x00000000 0x6 0x00000000 0x40000000>; 475 476 pcie0: pcie@7d500000 { 477 compatible = "brcm,bcm2711-pcie"; 478 reg = <0x0 0x7d500000 0x9310>; 479 device_type = "pci"; 480 #address-cells = <3>; 481 #interrupt-cells = <1>; 482 #size-cells = <2>; 483 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 485 interrupt-names = "pcie", "msi"; 486 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 487 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 488 IRQ_TYPE_LEVEL_HIGH>; 489 msi-controller; 490 msi-parent = <&pcie0>; 491 492 ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 493 0x0 0x04000000>; 494 /* 495 * The wrapper around the PCIe block has a bug 496 * preventing it from accessing beyond the first 3GB of 497 * memory. 498 */ 499 dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 500 0x0 0xc0000000>; 501 brcm,enable-ssc; 502 }; 503 504 genet: ethernet@7d580000 { 505 compatible = "brcm,bcm2711-genet-v5"; 506 reg = <0x0 0x7d580000 0x10000>; 507 #address-cells = <0x1>; 508 #size-cells = <0x1>; 509 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 511 status = "disabled"; 512 513 genet_mdio: mdio@e14 { 514 compatible = "brcm,genet-mdio-v5"; 515 reg = <0xe14 0x8>; 516 reg-names = "mdio"; 517 #address-cells = <0x0>; 518 #size-cells = <0x1>; 519 }; 520 }; 521 }; 522}; 523 524&clk_osc { 525 clock-frequency = <54000000>; 526}; 527 528&clocks { 529 compatible = "brcm,bcm2711-cprman"; 530}; 531 532&cpu_thermal { 533 coefficients = <(-487) 410040>; 534 thermal-sensors = <&thermal>; 535}; 536 537&dsi0 { 538 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 539}; 540 541&dsi1 { 542 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 543}; 544 545&gpio { 546 compatible = "brcm,bcm2711-gpio"; 547 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 551 552 gpclk0_gpio49: gpclk0_gpio49 { 553 pin-gpclk { 554 pins = "gpio49"; 555 function = "alt1"; 556 bias-disable; 557 }; 558 }; 559 gpclk1_gpio50: gpclk1_gpio50 { 560 pin-gpclk { 561 pins = "gpio50"; 562 function = "alt1"; 563 bias-disable; 564 }; 565 }; 566 gpclk2_gpio51: gpclk2_gpio51 { 567 pin-gpclk { 568 pins = "gpio51"; 569 function = "alt1"; 570 bias-disable; 571 }; 572 }; 573 574 i2c0_gpio46: i2c0_gpio46 { 575 pin-sda { 576 function = "alt0"; 577 pins = "gpio46"; 578 bias-pull-up; 579 }; 580 pin-scl { 581 function = "alt0"; 582 pins = "gpio47"; 583 bias-disable; 584 }; 585 }; 586 i2c1_gpio46: i2c1_gpio46 { 587 pin-sda { 588 function = "alt1"; 589 pins = "gpio46"; 590 bias-pull-up; 591 }; 592 pin-scl { 593 function = "alt1"; 594 pins = "gpio47"; 595 bias-disable; 596 }; 597 }; 598 i2c3_gpio2: i2c3_gpio2 { 599 pin-sda { 600 function = "alt5"; 601 pins = "gpio2"; 602 bias-pull-up; 603 }; 604 pin-scl { 605 function = "alt5"; 606 pins = "gpio3"; 607 bias-disable; 608 }; 609 }; 610 i2c3_gpio4: i2c3_gpio4 { 611 pin-sda { 612 function = "alt5"; 613 pins = "gpio4"; 614 bias-pull-up; 615 }; 616 pin-scl { 617 function = "alt5"; 618 pins = "gpio5"; 619 bias-disable; 620 }; 621 }; 622 i2c4_gpio6: i2c4_gpio6 { 623 pin-sda { 624 function = "alt5"; 625 pins = "gpio6"; 626 bias-pull-up; 627 }; 628 pin-scl { 629 function = "alt5"; 630 pins = "gpio7"; 631 bias-disable; 632 }; 633 }; 634 i2c4_gpio8: i2c4_gpio8 { 635 pin-sda { 636 function = "alt5"; 637 pins = "gpio8"; 638 bias-pull-up; 639 }; 640 pin-scl { 641 function = "alt5"; 642 pins = "gpio9"; 643 bias-disable; 644 }; 645 }; 646 i2c5_gpio10: i2c5_gpio10 { 647 pin-sda { 648 function = "alt5"; 649 pins = "gpio10"; 650 bias-pull-up; 651 }; 652 pin-scl { 653 function = "alt5"; 654 pins = "gpio11"; 655 bias-disable; 656 }; 657 }; 658 i2c5_gpio12: i2c5_gpio12 { 659 pin-sda { 660 function = "alt5"; 661 pins = "gpio12"; 662 bias-pull-up; 663 }; 664 pin-scl { 665 function = "alt5"; 666 pins = "gpio13"; 667 bias-disable; 668 }; 669 }; 670 i2c6_gpio0: i2c6_gpio0 { 671 pin-sda { 672 function = "alt5"; 673 pins = "gpio0"; 674 bias-pull-up; 675 }; 676 pin-scl { 677 function = "alt5"; 678 pins = "gpio1"; 679 bias-disable; 680 }; 681 }; 682 i2c6_gpio22: i2c6_gpio22 { 683 pin-sda { 684 function = "alt5"; 685 pins = "gpio22"; 686 bias-pull-up; 687 }; 688 pin-scl { 689 function = "alt5"; 690 pins = "gpio23"; 691 bias-disable; 692 }; 693 }; 694 i2c_slave_gpio8: i2c_slave_gpio8 { 695 pins-i2c-slave { 696 pins = "gpio8", 697 "gpio9", 698 "gpio10", 699 "gpio11"; 700 function = "alt3"; 701 }; 702 }; 703 704 jtag_gpio48: jtag_gpio48 { 705 pins-jtag { 706 pins = "gpio48", 707 "gpio49", 708 "gpio50", 709 "gpio51", 710 "gpio52", 711 "gpio53"; 712 function = "alt4"; 713 }; 714 }; 715 716 mii_gpio28: mii_gpio28 { 717 pins-mii { 718 pins = "gpio28", 719 "gpio29", 720 "gpio30", 721 "gpio31"; 722 function = "alt4"; 723 }; 724 }; 725 mii_gpio36: mii_gpio36 { 726 pins-mii { 727 pins = "gpio36", 728 "gpio37", 729 "gpio38", 730 "gpio39"; 731 function = "alt5"; 732 }; 733 }; 734 735 pcm_gpio50: pcm_gpio50 { 736 pins-pcm { 737 pins = "gpio50", 738 "gpio51", 739 "gpio52", 740 "gpio53"; 741 function = "alt2"; 742 }; 743 }; 744 745 pwm0_0_gpio12: pwm0_0_gpio12 { 746 pin-pwm { 747 pins = "gpio12"; 748 function = "alt0"; 749 bias-disable; 750 }; 751 }; 752 pwm0_0_gpio18: pwm0_0_gpio18 { 753 pin-pwm { 754 pins = "gpio18"; 755 function = "alt5"; 756 bias-disable; 757 }; 758 }; 759 pwm1_0_gpio40: pwm1_0_gpio40 { 760 pin-pwm { 761 pins = "gpio40"; 762 function = "alt0"; 763 bias-disable; 764 }; 765 }; 766 pwm0_1_gpio13: pwm0_1_gpio13 { 767 pin-pwm { 768 pins = "gpio13"; 769 function = "alt0"; 770 bias-disable; 771 }; 772 }; 773 pwm0_1_gpio19: pwm0_1_gpio19 { 774 pin-pwm { 775 pins = "gpio19"; 776 function = "alt5"; 777 bias-disable; 778 }; 779 }; 780 pwm1_1_gpio41: pwm1_1_gpio41 { 781 pin-pwm { 782 pins = "gpio41"; 783 function = "alt0"; 784 bias-disable; 785 }; 786 }; 787 pwm0_1_gpio45: pwm0_1_gpio45 { 788 pin-pwm { 789 pins = "gpio45"; 790 function = "alt0"; 791 bias-disable; 792 }; 793 }; 794 pwm0_0_gpio52: pwm0_0_gpio52 { 795 pin-pwm { 796 pins = "gpio52"; 797 function = "alt1"; 798 bias-disable; 799 }; 800 }; 801 pwm0_1_gpio53: pwm0_1_gpio53 { 802 pin-pwm { 803 pins = "gpio53"; 804 function = "alt1"; 805 bias-disable; 806 }; 807 }; 808 809 rgmii_gpio35: rgmii_gpio35 { 810 pin-start-stop { 811 pins = "gpio35"; 812 function = "alt4"; 813 }; 814 pin-rx-ok { 815 pins = "gpio36"; 816 function = "alt4"; 817 }; 818 }; 819 rgmii_irq_gpio34: rgmii_irq_gpio34 { 820 pin-irq { 821 pins = "gpio34"; 822 function = "alt5"; 823 }; 824 }; 825 rgmii_irq_gpio39: rgmii_irq_gpio39 { 826 pin-irq { 827 pins = "gpio39"; 828 function = "alt4"; 829 }; 830 }; 831 rgmii_mdio_gpio28: rgmii_mdio_gpio28 { 832 pins-mdio { 833 pins = "gpio28", 834 "gpio29"; 835 function = "alt5"; 836 }; 837 }; 838 rgmii_mdio_gpio37: rgmii_mdio_gpio37 { 839 pins-mdio { 840 pins = "gpio37", 841 "gpio38"; 842 function = "alt4"; 843 }; 844 }; 845 846 spi0_gpio46: spi0_gpio46 { 847 pins-spi { 848 pins = "gpio46", 849 "gpio47", 850 "gpio48", 851 "gpio49"; 852 function = "alt2"; 853 }; 854 }; 855 spi2_gpio46: spi2_gpio46 { 856 pins-spi { 857 pins = "gpio46", 858 "gpio47", 859 "gpio48", 860 "gpio49", 861 "gpio50"; 862 function = "alt5"; 863 }; 864 }; 865 spi3_gpio0: spi3_gpio0 { 866 pins-spi { 867 pins = "gpio0", 868 "gpio1", 869 "gpio2", 870 "gpio3"; 871 function = "alt3"; 872 }; 873 }; 874 spi4_gpio4: spi4_gpio4 { 875 pins-spi { 876 pins = "gpio4", 877 "gpio5", 878 "gpio6", 879 "gpio7"; 880 function = "alt3"; 881 }; 882 }; 883 spi5_gpio12: spi5_gpio12 { 884 pins-spi { 885 pins = "gpio12", 886 "gpio13", 887 "gpio14", 888 "gpio15"; 889 function = "alt3"; 890 }; 891 }; 892 spi6_gpio18: spi6_gpio18 { 893 pins-spi { 894 pins = "gpio18", 895 "gpio19", 896 "gpio20", 897 "gpio21"; 898 function = "alt3"; 899 }; 900 }; 901 902 uart2_gpio0: uart2_gpio0 { 903 pin-tx { 904 pins = "gpio0"; 905 function = "alt4"; 906 bias-disable; 907 }; 908 pin-rx { 909 pins = "gpio1"; 910 function = "alt4"; 911 bias-pull-up; 912 }; 913 }; 914 uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 { 915 pin-cts { 916 pins = "gpio2"; 917 function = "alt4"; 918 bias-pull-up; 919 }; 920 pin-rts { 921 pins = "gpio3"; 922 function = "alt4"; 923 bias-disable; 924 }; 925 }; 926 uart3_gpio4: uart3_gpio4 { 927 pin-tx { 928 pins = "gpio4"; 929 function = "alt4"; 930 bias-disable; 931 }; 932 pin-rx { 933 pins = "gpio5"; 934 function = "alt4"; 935 bias-pull-up; 936 }; 937 }; 938 uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 { 939 pin-cts { 940 pins = "gpio6"; 941 function = "alt4"; 942 bias-pull-up; 943 }; 944 pin-rts { 945 pins = "gpio7"; 946 function = "alt4"; 947 bias-disable; 948 }; 949 }; 950 uart4_gpio8: uart4_gpio8 { 951 pin-tx { 952 pins = "gpio8"; 953 function = "alt4"; 954 bias-disable; 955 }; 956 pin-rx { 957 pins = "gpio9"; 958 function = "alt4"; 959 bias-pull-up; 960 }; 961 }; 962 uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 { 963 pin-cts { 964 pins = "gpio10"; 965 function = "alt4"; 966 bias-pull-up; 967 }; 968 pin-rts { 969 pins = "gpio11"; 970 function = "alt4"; 971 bias-disable; 972 }; 973 }; 974 uart5_gpio12: uart5_gpio12 { 975 pin-tx { 976 pins = "gpio12"; 977 function = "alt4"; 978 bias-disable; 979 }; 980 pin-rx { 981 pins = "gpio13"; 982 function = "alt4"; 983 bias-pull-up; 984 }; 985 }; 986 uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 { 987 pin-cts { 988 pins = "gpio14"; 989 function = "alt4"; 990 bias-pull-up; 991 }; 992 pin-rts { 993 pins = "gpio15"; 994 function = "alt4"; 995 bias-disable; 996 }; 997 }; 998}; 999 1000&rmem { 1001 #address-cells = <2>; 1002}; 1003 1004&cma { 1005 /* 1006 * arm64 reserves the CMA by default somewhere in ZONE_DMA32, 1007 * that's not good enough for the BCM2711 as some devices can 1008 * only address the lower 1G of memory (ZONE_DMA). 1009 */ 1010 alloc-ranges = <0x0 0x00000000 0x40000000>; 1011}; 1012 1013&i2c0 { 1014 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 1015 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1016}; 1017 1018&i2c1 { 1019 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 1020 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1021}; 1022 1023&mailbox { 1024 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1025}; 1026 1027&sdhci { 1028 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1029}; 1030 1031&sdhost { 1032 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1033}; 1034 1035&spi { 1036 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1037}; 1038 1039&spi1 { 1040 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1041}; 1042 1043&spi2 { 1044 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1045}; 1046 1047&system_timer { 1048 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 1049 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1050 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 1051 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1052}; 1053 1054&txp { 1055 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1056}; 1057 1058&uart0 { 1059 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1060}; 1061 1062&uart1 { 1063 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1064}; 1065 1066&usb { 1067 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1068}; 1069 1070&vec { 1071 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1072}; 1073
