1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 /*
24 * dc_helper.c
25 *
26 * Created on: Aug 30, 2016
27 * Author: agrodzov
28 */
29 #include "dm_services.h"
30 #include <stdarg.h>
31
generic_reg_update_ex(const struct dc_context * ctx,uint32_t addr,uint32_t reg_val,int n,uint8_t shift1,uint32_t mask1,uint32_t field_value1,...)32 uint32_t generic_reg_update_ex(const struct dc_context *ctx,
33 uint32_t addr, uint32_t reg_val, int n,
34 uint8_t shift1, uint32_t mask1, uint32_t field_value1,
35 ...)
36 {
37 uint32_t shift, mask, field_value;
38 int i = 1;
39
40 va_list ap;
41 va_start(ap, field_value1);
42
43 reg_val = set_reg_field_value_ex(reg_val, field_value1, mask1, shift1);
44
45 while (i < n) {
46 shift = va_arg(ap, uint32_t);
47 mask = va_arg(ap, uint32_t);
48 field_value = va_arg(ap, uint32_t);
49
50 reg_val = set_reg_field_value_ex(reg_val, field_value, mask, shift);
51 i++;
52 }
53
54 dm_write_reg(ctx, addr, reg_val);
55 va_end(ap);
56
57 return reg_val;
58 }
59
generic_reg_get(const struct dc_context * ctx,uint32_t addr,uint8_t shift,uint32_t mask,uint32_t * field_value)60 uint32_t generic_reg_get(const struct dc_context *ctx, uint32_t addr,
61 uint8_t shift, uint32_t mask, uint32_t *field_value)
62 {
63 uint32_t reg_val = dm_read_reg(ctx, addr);
64 *field_value = get_reg_field_value_ex(reg_val, mask, shift);
65 return reg_val;
66 }
67
generic_reg_get2(const struct dc_context * ctx,uint32_t addr,uint8_t shift1,uint32_t mask1,uint32_t * field_value1,uint8_t shift2,uint32_t mask2,uint32_t * field_value2)68 uint32_t generic_reg_get2(const struct dc_context *ctx, uint32_t addr,
69 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
70 uint8_t shift2, uint32_t mask2, uint32_t *field_value2)
71 {
72 uint32_t reg_val = dm_read_reg(ctx, addr);
73 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
74 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
75 return reg_val;
76 }
77
generic_reg_get3(const struct dc_context * ctx,uint32_t addr,uint8_t shift1,uint32_t mask1,uint32_t * field_value1,uint8_t shift2,uint32_t mask2,uint32_t * field_value2,uint8_t shift3,uint32_t mask3,uint32_t * field_value3)78 uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr,
79 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
80 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
81 uint8_t shift3, uint32_t mask3, uint32_t *field_value3)
82 {
83 uint32_t reg_val = dm_read_reg(ctx, addr);
84 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
85 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
86 *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
87 return reg_val;
88 }
89
generic_reg_get4(const struct dc_context * ctx,uint32_t addr,uint8_t shift1,uint32_t mask1,uint32_t * field_value1,uint8_t shift2,uint32_t mask2,uint32_t * field_value2,uint8_t shift3,uint32_t mask3,uint32_t * field_value3,uint8_t shift4,uint32_t mask4,uint32_t * field_value4)90 uint32_t generic_reg_get4(const struct dc_context *ctx, uint32_t addr,
91 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
92 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
93 uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
94 uint8_t shift4, uint32_t mask4, uint32_t *field_value4)
95 {
96 uint32_t reg_val = dm_read_reg(ctx, addr);
97 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
98 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
99 *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
100 *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
101 return reg_val;
102 }
103
generic_reg_get5(const struct dc_context * ctx,uint32_t addr,uint8_t shift1,uint32_t mask1,uint32_t * field_value1,uint8_t shift2,uint32_t mask2,uint32_t * field_value2,uint8_t shift3,uint32_t mask3,uint32_t * field_value3,uint8_t shift4,uint32_t mask4,uint32_t * field_value4,uint8_t shift5,uint32_t mask5,uint32_t * field_value5)104 uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr,
105 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
106 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
107 uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
108 uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
109 uint8_t shift5, uint32_t mask5, uint32_t *field_value5)
110 {
111 uint32_t reg_val = dm_read_reg(ctx, addr);
112 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
113 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
114 *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
115 *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
116 *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);
117 return reg_val;
118 }
119
generic_reg_get6(const struct dc_context * ctx,uint32_t addr,uint8_t shift1,uint32_t mask1,uint32_t * field_value1,uint8_t shift2,uint32_t mask2,uint32_t * field_value2,uint8_t shift3,uint32_t mask3,uint32_t * field_value3,uint8_t shift4,uint32_t mask4,uint32_t * field_value4,uint8_t shift5,uint32_t mask5,uint32_t * field_value5,uint8_t shift6,uint32_t mask6,uint32_t * field_value6)120 uint32_t generic_reg_get6(const struct dc_context *ctx, uint32_t addr,
121 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
122 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
123 uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
124 uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
125 uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
126 uint8_t shift6, uint32_t mask6, uint32_t *field_value6)
127 {
128 uint32_t reg_val = dm_read_reg(ctx, addr);
129 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
130 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
131 *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
132 *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
133 *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);
134 *field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6);
135 return reg_val;
136 }
137
generic_reg_get7(const struct dc_context * ctx,uint32_t addr,uint8_t shift1,uint32_t mask1,uint32_t * field_value1,uint8_t shift2,uint32_t mask2,uint32_t * field_value2,uint8_t shift3,uint32_t mask3,uint32_t * field_value3,uint8_t shift4,uint32_t mask4,uint32_t * field_value4,uint8_t shift5,uint32_t mask5,uint32_t * field_value5,uint8_t shift6,uint32_t mask6,uint32_t * field_value6,uint8_t shift7,uint32_t mask7,uint32_t * field_value7)138 uint32_t generic_reg_get7(const struct dc_context *ctx, uint32_t addr,
139 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
140 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
141 uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
142 uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
143 uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
144 uint8_t shift6, uint32_t mask6, uint32_t *field_value6,
145 uint8_t shift7, uint32_t mask7, uint32_t *field_value7)
146 {
147 uint32_t reg_val = dm_read_reg(ctx, addr);
148 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
149 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
150 *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
151 *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
152 *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);
153 *field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6);
154 *field_value7 = get_reg_field_value_ex(reg_val, mask7, shift7);
155 return reg_val;
156 }
157
generic_reg_get8(const struct dc_context * ctx,uint32_t addr,uint8_t shift1,uint32_t mask1,uint32_t * field_value1,uint8_t shift2,uint32_t mask2,uint32_t * field_value2,uint8_t shift3,uint32_t mask3,uint32_t * field_value3,uint8_t shift4,uint32_t mask4,uint32_t * field_value4,uint8_t shift5,uint32_t mask5,uint32_t * field_value5,uint8_t shift6,uint32_t mask6,uint32_t * field_value6,uint8_t shift7,uint32_t mask7,uint32_t * field_value7,uint8_t shift8,uint32_t mask8,uint32_t * field_value8)158 uint32_t generic_reg_get8(const struct dc_context *ctx, uint32_t addr,
159 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
160 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
161 uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
162 uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
163 uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
164 uint8_t shift6, uint32_t mask6, uint32_t *field_value6,
165 uint8_t shift7, uint32_t mask7, uint32_t *field_value7,
166 uint8_t shift8, uint32_t mask8, uint32_t *field_value8)
167 {
168 uint32_t reg_val = dm_read_reg(ctx, addr);
169 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
170 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
171 *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
172 *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
173 *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);
174 *field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6);
175 *field_value7 = get_reg_field_value_ex(reg_val, mask7, shift7);
176 *field_value8 = get_reg_field_value_ex(reg_val, mask8, shift8);
177 return reg_val;
178 }
179 /* note: va version of this is pretty bad idea, since there is a output parameter pass by pointer
180 * compiler won't be able to check for size match and is prone to stack corruption type of bugs
181
182 uint32_t generic_reg_get(const struct dc_context *ctx,
183 uint32_t addr, int n, ...)
184 {
185 uint32_t shift, mask;
186 uint32_t *field_value;
187 uint32_t reg_val;
188 int i = 0;
189
190 reg_val = dm_read_reg(ctx, addr);
191
192 va_list ap;
193 va_start(ap, n);
194
195 while (i < n) {
196 shift = va_arg(ap, uint32_t);
197 mask = va_arg(ap, uint32_t);
198 field_value = va_arg(ap, uint32_t *);
199
200 *field_value = get_reg_field_value_ex(reg_val, mask, shift);
201 i++;
202 }
203
204 va_end(ap);
205
206 return reg_val;
207 }
208 */
209
generic_reg_wait(const struct dc_context * ctx,uint32_t addr,uint32_t shift,uint32_t mask,uint32_t condition_value,unsigned int delay_between_poll_us,unsigned int time_out_num_tries,const char * func_name,int line)210 uint32_t generic_reg_wait(const struct dc_context *ctx,
211 uint32_t addr, uint32_t shift, uint32_t mask, uint32_t condition_value,
212 unsigned int delay_between_poll_us, unsigned int time_out_num_tries,
213 const char *func_name, int line)
214 {
215 uint32_t field_value;
216 uint32_t reg_val;
217 int i;
218
219 /* something is terribly wrong if time out is > 200ms. (5Hz) */
220 ASSERT(delay_between_poll_us * time_out_num_tries <= 200000);
221
222 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
223 /* 35 seconds */
224 delay_between_poll_us = 35000;
225 time_out_num_tries = 1000;
226 }
227
228 for (i = 0; i <= time_out_num_tries; i++) {
229 if (i) {
230 if (delay_between_poll_us >= 1000)
231 msleep(delay_between_poll_us/1000);
232 else if (delay_between_poll_us > 0)
233 udelay(delay_between_poll_us);
234 }
235
236 reg_val = dm_read_reg(ctx, addr);
237
238 field_value = get_reg_field_value_ex(reg_val, mask, shift);
239
240 if (field_value == condition_value) {
241 if (i * delay_between_poll_us > 1000)
242 dm_output_to_console("REG_WAIT taking a while: %dms in %s line:%d\n",
243 delay_between_poll_us * i / 1000,
244 func_name, line);
245 return reg_val;
246 }
247 }
248
249 dm_error("REG_WAIT timeout %dus * %d tries - %s line:%d\n",
250 delay_between_poll_us, time_out_num_tries,
251 func_name, line);
252
253 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
254 BREAK_TO_DEBUGGER();
255
256 return reg_val;
257 }
258
generic_write_indirect_reg(const struct dc_context * ctx,uint32_t addr_index,uint32_t addr_data,uint32_t index,uint32_t data)259 void generic_write_indirect_reg(const struct dc_context *ctx,
260 uint32_t addr_index, uint32_t addr_data,
261 uint32_t index, uint32_t data)
262 {
263 dm_write_reg(ctx, addr_index, index);
264 dm_write_reg(ctx, addr_data, data);
265 }
266
generic_read_indirect_reg(const struct dc_context * ctx,uint32_t addr_index,uint32_t addr_data,uint32_t index)267 uint32_t generic_read_indirect_reg(const struct dc_context *ctx,
268 uint32_t addr_index, uint32_t addr_data,
269 uint32_t index)
270 {
271 uint32_t value = 0;
272
273 dm_write_reg(ctx, addr_index, index);
274 value = dm_read_reg(ctx, addr_data);
275
276 return value;
277 }
278
279
generic_indirect_reg_update_ex(const struct dc_context * ctx,uint32_t addr_index,uint32_t addr_data,uint32_t index,uint32_t reg_val,int n,uint8_t shift1,uint32_t mask1,uint32_t field_value1,...)280 uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx,
281 uint32_t addr_index, uint32_t addr_data,
282 uint32_t index, uint32_t reg_val, int n,
283 uint8_t shift1, uint32_t mask1, uint32_t field_value1,
284 ...)
285 {
286 uint32_t shift, mask, field_value;
287 int i = 1;
288
289 va_list ap;
290
291 va_start(ap, field_value1);
292
293 reg_val = set_reg_field_value_ex(reg_val, field_value1, mask1, shift1);
294
295 while (i < n) {
296 shift = va_arg(ap, uint32_t);
297 mask = va_arg(ap, uint32_t);
298 field_value = va_arg(ap, uint32_t);
299
300 reg_val = set_reg_field_value_ex(reg_val, field_value, mask, shift);
301 i++;
302 }
303
304 generic_write_indirect_reg(ctx, addr_index, addr_data, index, reg_val);
305 va_end(ap);
306
307 return reg_val;
308 }
309
