1 /*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #ifndef __CXGB4_H__
36 #define __CXGB4_H__
37
38 #include "t4_hw.h"
39
40 #include <linux/bitops.h>
41 #include <linux/cache.h>
42 #include <linux/interrupt.h>
43 #include <linux/list.h>
44 #include <linux/netdevice.h>
45 #include <linux/pci.h>
46 #include <linux/spinlock.h>
47 #include <linux/timer.h>
48 #include <linux/vmalloc.h>
49 #include <linux/rhashtable.h>
50 #include <linux/etherdevice.h>
51 #include <linux/net_tstamp.h>
52 #include <linux/ptp_clock_kernel.h>
53 #include <linux/ptp_classify.h>
54 #include <linux/crash_dump.h>
55 #include <asm/io.h>
56 #include "t4_chip_type.h"
57 #include "cxgb4_uld.h"
58
59 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
60 extern struct list_head adapter_list;
61 extern struct mutex uld_mutex;
62
63 /* Suspend an Ethernet Tx queue with fewer available descriptors than this.
64 * This is the same as calc_tx_descs() for a TSO packet with
65 * nr_frags == MAX_SKB_FRAGS.
66 */
67 #define ETHTXQ_STOP_THRES \
68 (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8))
69
70 enum {
71 MAX_NPORTS = 4, /* max # of ports */
72 SERNUM_LEN = 24, /* Serial # length */
73 EC_LEN = 16, /* E/C length */
74 ID_LEN = 16, /* ID length */
75 PN_LEN = 16, /* Part Number length */
76 MACADDR_LEN = 12, /* MAC Address length */
77 };
78
79 enum {
80 T4_REGMAP_SIZE = (160 * 1024),
81 T5_REGMAP_SIZE = (332 * 1024),
82 };
83
84 enum {
85 MEM_EDC0,
86 MEM_EDC1,
87 MEM_MC,
88 MEM_MC0 = MEM_MC,
89 MEM_MC1,
90 MEM_HMA,
91 };
92
93 enum {
94 MEMWIN0_APERTURE = 2048,
95 MEMWIN0_BASE = 0x1b800,
96 MEMWIN1_APERTURE = 32768,
97 MEMWIN1_BASE = 0x28000,
98 MEMWIN1_BASE_T5 = 0x52000,
99 MEMWIN2_APERTURE = 65536,
100 MEMWIN2_BASE = 0x30000,
101 MEMWIN2_APERTURE_T5 = 131072,
102 MEMWIN2_BASE_T5 = 0x60000,
103 };
104
105 enum dev_master {
106 MASTER_CANT,
107 MASTER_MAY,
108 MASTER_MUST
109 };
110
111 enum dev_state {
112 DEV_STATE_UNINIT,
113 DEV_STATE_INIT,
114 DEV_STATE_ERR
115 };
116
117 enum cc_pause {
118 PAUSE_RX = 1 << 0,
119 PAUSE_TX = 1 << 1,
120 PAUSE_AUTONEG = 1 << 2
121 };
122
123 enum cc_fec {
124 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */
125 FEC_RS = 1 << 1, /* Reed-Solomon */
126 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */
127 };
128
129 struct port_stats {
130 u64 tx_octets; /* total # of octets in good frames */
131 u64 tx_frames; /* all good frames */
132 u64 tx_bcast_frames; /* all broadcast frames */
133 u64 tx_mcast_frames; /* all multicast frames */
134 u64 tx_ucast_frames; /* all unicast frames */
135 u64 tx_error_frames; /* all error frames */
136
137 u64 tx_frames_64; /* # of Tx frames in a particular range */
138 u64 tx_frames_65_127;
139 u64 tx_frames_128_255;
140 u64 tx_frames_256_511;
141 u64 tx_frames_512_1023;
142 u64 tx_frames_1024_1518;
143 u64 tx_frames_1519_max;
144
145 u64 tx_drop; /* # of dropped Tx frames */
146 u64 tx_pause; /* # of transmitted pause frames */
147 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
148 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
149 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
150 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
151 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
152 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
153 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
154 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
155
156 u64 rx_octets; /* total # of octets in good frames */
157 u64 rx_frames; /* all good frames */
158 u64 rx_bcast_frames; /* all broadcast frames */
159 u64 rx_mcast_frames; /* all multicast frames */
160 u64 rx_ucast_frames; /* all unicast frames */
161 u64 rx_too_long; /* # of frames exceeding MTU */
162 u64 rx_jabber; /* # of jabber frames */
163 u64 rx_fcs_err; /* # of received frames with bad FCS */
164 u64 rx_len_err; /* # of received frames with length error */
165 u64 rx_symbol_err; /* symbol errors */
166 u64 rx_runt; /* # of short frames */
167
168 u64 rx_frames_64; /* # of Rx frames in a particular range */
169 u64 rx_frames_65_127;
170 u64 rx_frames_128_255;
171 u64 rx_frames_256_511;
172 u64 rx_frames_512_1023;
173 u64 rx_frames_1024_1518;
174 u64 rx_frames_1519_max;
175
176 u64 rx_pause; /* # of received pause frames */
177 u64 rx_ppp0; /* # of received PPP prio 0 frames */
178 u64 rx_ppp1; /* # of received PPP prio 1 frames */
179 u64 rx_ppp2; /* # of received PPP prio 2 frames */
180 u64 rx_ppp3; /* # of received PPP prio 3 frames */
181 u64 rx_ppp4; /* # of received PPP prio 4 frames */
182 u64 rx_ppp5; /* # of received PPP prio 5 frames */
183 u64 rx_ppp6; /* # of received PPP prio 6 frames */
184 u64 rx_ppp7; /* # of received PPP prio 7 frames */
185
186 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
187 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
188 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
189 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
190 u64 rx_trunc0; /* buffer-group 0 truncated packets */
191 u64 rx_trunc1; /* buffer-group 1 truncated packets */
192 u64 rx_trunc2; /* buffer-group 2 truncated packets */
193 u64 rx_trunc3; /* buffer-group 3 truncated packets */
194 };
195
196 struct lb_port_stats {
197 u64 octets;
198 u64 frames;
199 u64 bcast_frames;
200 u64 mcast_frames;
201 u64 ucast_frames;
202 u64 error_frames;
203
204 u64 frames_64;
205 u64 frames_65_127;
206 u64 frames_128_255;
207 u64 frames_256_511;
208 u64 frames_512_1023;
209 u64 frames_1024_1518;
210 u64 frames_1519_max;
211
212 u64 drop;
213
214 u64 ovflow0;
215 u64 ovflow1;
216 u64 ovflow2;
217 u64 ovflow3;
218 u64 trunc0;
219 u64 trunc1;
220 u64 trunc2;
221 u64 trunc3;
222 };
223
224 struct tp_tcp_stats {
225 u32 tcp_out_rsts;
226 u64 tcp_in_segs;
227 u64 tcp_out_segs;
228 u64 tcp_retrans_segs;
229 };
230
231 struct tp_usm_stats {
232 u32 frames;
233 u32 drops;
234 u64 octets;
235 };
236
237 struct tp_fcoe_stats {
238 u32 frames_ddp;
239 u32 frames_drop;
240 u64 octets_ddp;
241 };
242
243 struct tp_err_stats {
244 u32 mac_in_errs[4];
245 u32 hdr_in_errs[4];
246 u32 tcp_in_errs[4];
247 u32 tnl_cong_drops[4];
248 u32 ofld_chan_drops[4];
249 u32 tnl_tx_drops[4];
250 u32 ofld_vlan_drops[4];
251 u32 tcp6_in_errs[4];
252 u32 ofld_no_neigh;
253 u32 ofld_cong_defer;
254 };
255
256 struct tp_cpl_stats {
257 u32 req[4];
258 u32 rsp[4];
259 };
260
261 struct tp_rdma_stats {
262 u32 rqe_dfr_pkt;
263 u32 rqe_dfr_mod;
264 };
265
266 struct sge_params {
267 u32 hps; /* host page size for our PF/VF */
268 u32 eq_qpp; /* egress queues/page for our PF/VF */
269 u32 iq_qpp; /* egress queues/page for our PF/VF */
270 };
271
272 struct tp_params {
273 unsigned int tre; /* log2 of core clocks per TP tick */
274 unsigned int la_mask; /* what events are recorded by TP LA */
275 unsigned short tx_modq_map; /* TX modulation scheduler queue to */
276 /* channel map */
277
278 uint32_t dack_re; /* DACK timer resolution */
279 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
280
281 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */
282 u32 ingress_config; /* cached TP_INGRESS_CONFIG */
283
284 /* cached TP_OUT_CONFIG compressed error vector
285 * and passing outer header info for encapsulated packets.
286 */
287 int rx_pkt_encap;
288
289 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
290 * subset of the set of fields which may be present in the Compressed
291 * Filter Tuple portion of filters and TCP TCB connections. The
292 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
293 * Since a variable number of fields may or may not be present, their
294 * shifted field positions within the Compressed Filter Tuple may
295 * vary, or not even be present if the field isn't selected in
296 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various
297 * places we store their offsets here, or a -1 if the field isn't
298 * present.
299 */
300 int fcoe_shift;
301 int port_shift;
302 int vnic_shift;
303 int vlan_shift;
304 int tos_shift;
305 int protocol_shift;
306 int ethertype_shift;
307 int macmatch_shift;
308 int matchtype_shift;
309 int frag_shift;
310
311 u64 hash_filter_mask;
312 };
313
314 struct vpd_params {
315 unsigned int cclk;
316 u8 ec[EC_LEN + 1];
317 u8 sn[SERNUM_LEN + 1];
318 u8 id[ID_LEN + 1];
319 u8 pn[PN_LEN + 1];
320 u8 na[MACADDR_LEN + 1];
321 };
322
323 /* Maximum resources provisioned for a PCI PF.
324 */
325 struct pf_resources {
326 unsigned int nvi; /* N virtual interfaces */
327 unsigned int neq; /* N egress Qs */
328 unsigned int nethctrl; /* N egress ETH or CTRL Qs */
329 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */
330 unsigned int niq; /* N ingress Qs */
331 unsigned int tc; /* PCI-E traffic class */
332 unsigned int pmask; /* port access rights mask */
333 unsigned int nexactf; /* N exact MPS filters */
334 unsigned int r_caps; /* read capabilities */
335 unsigned int wx_caps; /* write/execute capabilities */
336 };
337
338 struct pci_params {
339 unsigned int vpd_cap_addr;
340 unsigned char speed;
341 unsigned char width;
342 };
343
344 struct devlog_params {
345 u32 memtype; /* which memory (EDC0, EDC1, MC) */
346 u32 start; /* start of log in firmware memory */
347 u32 size; /* size of log */
348 };
349
350 /* Stores chip specific parameters */
351 struct arch_specific_params {
352 u8 nchan;
353 u8 pm_stats_cnt;
354 u8 cng_ch_bits_log; /* congestion channel map bits width */
355 u16 mps_rplc_size;
356 u16 vfcount;
357 u32 sge_fl_db;
358 u16 mps_tcam_size;
359 };
360
361 struct adapter_params {
362 struct sge_params sge;
363 struct tp_params tp;
364 struct vpd_params vpd;
365 struct pf_resources pfres;
366 struct pci_params pci;
367 struct devlog_params devlog;
368 enum pcie_memwin drv_memwin;
369
370 unsigned int cim_la_size;
371
372 unsigned int sf_size; /* serial flash size in bytes */
373 unsigned int sf_nsec; /* # of flash sectors */
374
375 unsigned int fw_vers; /* firmware version */
376 unsigned int bs_vers; /* bootstrap version */
377 unsigned int tp_vers; /* TP microcode version */
378 unsigned int er_vers; /* expansion ROM version */
379 unsigned int scfg_vers; /* Serial Configuration version */
380 unsigned int vpd_vers; /* VPD Version */
381 u8 api_vers[7];
382
383 unsigned short mtus[NMTUS];
384 unsigned short a_wnd[NCCTRL_WIN];
385 unsigned short b_wnd[NCCTRL_WIN];
386
387 unsigned char nports; /* # of ethernet ports */
388 unsigned char portvec;
389 enum chip_type chip; /* chip code */
390 struct arch_specific_params arch; /* chip specific params */
391 unsigned char offload;
392 unsigned char crypto; /* HW capability for crypto */
393
394 unsigned char bypass;
395 unsigned char hash_filter;
396
397 unsigned int ofldq_wr_cred;
398 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
399
400 unsigned int nsched_cls; /* number of traffic classes */
401 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */
402 unsigned int max_ird_adapter; /* Max read depth per adapter */
403 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */
404 u8 fw_caps_support; /* 32-bit Port Capabilities */
405 bool filter2_wr_support; /* FW support for FILTER2_WR */
406
407 /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is
408 * used by the Port
409 */
410 u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */
411 bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */
412 bool write_cmpl_support; /* FW supports WRITE_CMPL */
413 };
414
415 /* State needed to monitor the forward progress of SGE Ingress DMA activities
416 * and possible hangs.
417 */
418 struct sge_idma_monitor_state {
419 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */
420 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */
421 unsigned int idma_state[2]; /* IDMA Hang detect state */
422 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */
423 unsigned int idma_warn[2]; /* time to warning in HZ */
424 };
425
426 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format.
427 * The access and execute times are signed in order to accommodate negative
428 * error returns.
429 */
430 struct mbox_cmd {
431 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */
432 u64 timestamp; /* OS-dependent timestamp */
433 u32 seqno; /* sequence number */
434 s16 access; /* time (ms) to access mailbox */
435 s16 execute; /* time (ms) to execute */
436 };
437
438 struct mbox_cmd_log {
439 unsigned int size; /* number of entries in the log */
440 unsigned int cursor; /* next position in the log to write */
441 u32 seqno; /* next sequence number */
442 /* variable length mailbox command log starts here */
443 };
444
445 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index,
446 * return a pointer to the specified entry.
447 */
mbox_cmd_log_entry(struct mbox_cmd_log * log,unsigned int entry_idx)448 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log,
449 unsigned int entry_idx)
450 {
451 return &((struct mbox_cmd *)&(log)[1])[entry_idx];
452 }
453
454 #include "t4fw_api.h"
455
456 #define FW_VERSION(chip) ( \
457 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
458 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
459 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
460 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
461 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
462
463 struct fw_info {
464 u8 chip;
465 char *fs_name;
466 char *fw_mod_name;
467 struct fw_hdr fw_hdr;
468 };
469
470 struct trace_params {
471 u32 data[TRACE_LEN / 4];
472 u32 mask[TRACE_LEN / 4];
473 unsigned short snap_len;
474 unsigned short min_len;
475 unsigned char skip_ofst;
476 unsigned char skip_len;
477 unsigned char invert;
478 unsigned char port;
479 };
480
481 /* Firmware Port Capabilities types. */
482
483 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */
484 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */
485
486 enum fw_caps {
487 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */
488 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */
489 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */
490 };
491
492 struct link_config {
493 fw_port_cap32_t pcaps; /* link capabilities */
494 fw_port_cap32_t def_acaps; /* default advertised capabilities */
495 fw_port_cap32_t acaps; /* advertised capabilities */
496 fw_port_cap32_t lpacaps; /* peer advertised capabilities */
497
498 fw_port_cap32_t speed_caps; /* speed(s) user has requested */
499 unsigned int speed; /* actual link speed (Mb/s) */
500
501 enum cc_pause requested_fc; /* flow control user has requested */
502 enum cc_pause fc; /* actual link flow control */
503
504 enum cc_fec requested_fec; /* Forward Error Correction: */
505 enum cc_fec fec; /* requested and actual in use */
506
507 unsigned char autoneg; /* autonegotiating? */
508
509 unsigned char link_ok; /* link up? */
510 unsigned char link_down_rc; /* link down reason */
511
512 bool new_module; /* ->OS Transceiver Module inserted */
513 bool redo_l1cfg; /* ->CC redo current "sticky" L1 CFG */
514 };
515
516 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
517
518 enum {
519 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
520 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */
521 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
522 };
523
524 enum {
525 MAX_TXQ_ENTRIES = 16384,
526 MAX_CTRL_TXQ_ENTRIES = 1024,
527 MAX_RSPQ_ENTRIES = 16384,
528 MAX_RX_BUFFERS = 16384,
529 MIN_TXQ_ENTRIES = 32,
530 MIN_CTRL_TXQ_ENTRIES = 32,
531 MIN_RSPQ_ENTRIES = 128,
532 MIN_FL_ENTRIES = 16
533 };
534
535 enum {
536 INGQ_EXTRAS = 2, /* firmware event queue and */
537 /* forwarded interrupts */
538 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS,
539 };
540
541 enum {
542 PRIV_FLAG_PORT_TX_VM_BIT,
543 };
544
545 #define PRIV_FLAG_PORT_TX_VM BIT(PRIV_FLAG_PORT_TX_VM_BIT)
546
547 #define PRIV_FLAGS_ADAP 0
548 #define PRIV_FLAGS_PORT PRIV_FLAG_PORT_TX_VM
549
550 struct adapter;
551 struct sge_rspq;
552
553 #include "cxgb4_dcb.h"
554
555 #ifdef CONFIG_CHELSIO_T4_FCOE
556 #include "cxgb4_fcoe.h"
557 #endif /* CONFIG_CHELSIO_T4_FCOE */
558
559 struct port_info {
560 struct adapter *adapter;
561 u16 viid;
562 s16 xact_addr_filt; /* index of exact MAC address filter */
563 u16 rss_size; /* size of VI's RSS table slice */
564 s8 mdio_addr;
565 enum fw_port_type port_type;
566 u8 mod_type;
567 u8 port_id;
568 u8 tx_chan;
569 u8 lport; /* associated offload logical port */
570 u8 nqsets; /* # of qsets */
571 u8 first_qset; /* index of first qset */
572 u8 rss_mode;
573 struct link_config link_cfg;
574 u16 *rss;
575 struct port_stats stats_base;
576 #ifdef CONFIG_CHELSIO_T4_DCB
577 struct port_dcb_info dcb; /* Data Center Bridging support */
578 #endif
579 #ifdef CONFIG_CHELSIO_T4_FCOE
580 struct cxgb_fcoe fcoe;
581 #endif /* CONFIG_CHELSIO_T4_FCOE */
582 bool rxtstamp; /* Enable TS */
583 struct hwtstamp_config tstamp_config;
584 bool ptp_enable;
585 struct sched_table *sched_tbl;
586 u32 eth_flags;
587 };
588
589 struct dentry;
590 struct work_struct;
591
592 enum { /* adapter flags */
593 FULL_INIT_DONE = (1 << 0),
594 DEV_ENABLED = (1 << 1),
595 USING_MSI = (1 << 2),
596 USING_MSIX = (1 << 3),
597 FW_OK = (1 << 4),
598 RSS_TNLALLLOOKUP = (1 << 5),
599 USING_SOFT_PARAMS = (1 << 6),
600 MASTER_PF = (1 << 7),
601 FW_OFLD_CONN = (1 << 9),
602 ROOT_NO_RELAXED_ORDERING = (1 << 10),
603 SHUTTING_DOWN = (1 << 11),
604 };
605
606 enum {
607 ULP_CRYPTO_LOOKASIDE = 1 << 0,
608 ULP_CRYPTO_IPSEC_INLINE = 1 << 1,
609 };
610
611 struct rx_sw_desc;
612
613 struct sge_fl { /* SGE free-buffer queue state */
614 unsigned int avail; /* # of available Rx buffers */
615 unsigned int pend_cred; /* new buffers since last FL DB ring */
616 unsigned int cidx; /* consumer index */
617 unsigned int pidx; /* producer index */
618 unsigned long alloc_failed; /* # of times buffer allocation failed */
619 unsigned long large_alloc_failed;
620 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */
621 unsigned long low; /* # of times momentarily starving */
622 unsigned long starving;
623 /* RO fields */
624 unsigned int cntxt_id; /* SGE context id for the free list */
625 unsigned int size; /* capacity of free list */
626 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
627 __be64 *desc; /* address of HW Rx descriptor ring */
628 dma_addr_t addr; /* bus address of HW ring start */
629 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
630 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
631 };
632
633 /* A packet gather list */
634 struct pkt_gl {
635 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */
636 struct page_frag frags[MAX_SKB_FRAGS];
637 void *va; /* virtual address of first byte */
638 unsigned int nfrags; /* # of fragments */
639 unsigned int tot_len; /* total length of fragments */
640 };
641
642 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
643 const struct pkt_gl *gl);
644 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q);
645 /* LRO related declarations for ULD */
646 struct t4_lro_mgr {
647 #define MAX_LRO_SESSIONS 64
648 u8 lro_session_cnt; /* # of sessions to aggregate */
649 unsigned long lro_pkts; /* # of LRO super packets */
650 unsigned long lro_merged; /* # of wire packets merged by LRO */
651 struct sk_buff_head lroq; /* list of aggregated sessions */
652 };
653
654 struct sge_rspq { /* state for an SGE response queue */
655 struct napi_struct napi;
656 const __be64 *cur_desc; /* current descriptor in queue */
657 unsigned int cidx; /* consumer index */
658 u8 gen; /* current generation bit */
659 u8 intr_params; /* interrupt holdoff parameters */
660 u8 next_intr_params; /* holdoff params for next interrupt */
661 u8 adaptive_rx;
662 u8 pktcnt_idx; /* interrupt packet threshold */
663 u8 uld; /* ULD handling this queue */
664 u8 idx; /* queue index within its group */
665 int offset; /* offset into current Rx buffer */
666 u16 cntxt_id; /* SGE context id for the response q */
667 u16 abs_id; /* absolute SGE id for the response q */
668 __be64 *desc; /* address of HW response ring */
669 dma_addr_t phys_addr; /* physical address of the ring */
670 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
671 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
672 unsigned int iqe_len; /* entry size */
673 unsigned int size; /* capacity of response queue */
674 struct adapter *adap;
675 struct net_device *netdev; /* associated net device */
676 rspq_handler_t handler;
677 rspq_flush_handler_t flush_handler;
678 struct t4_lro_mgr lro_mgr;
679 };
680
681 struct sge_eth_stats { /* Ethernet queue statistics */
682 unsigned long pkts; /* # of ethernet packets */
683 unsigned long lro_pkts; /* # of LRO super packets */
684 unsigned long lro_merged; /* # of wire packets merged by LRO */
685 unsigned long rx_cso; /* # of Rx checksum offloads */
686 unsigned long vlan_ex; /* # of Rx VLAN extractions */
687 unsigned long rx_drops; /* # of packets dropped due to no mem */
688 };
689
690 struct sge_eth_rxq { /* SW Ethernet Rx queue */
691 struct sge_rspq rspq;
692 struct sge_fl fl;
693 struct sge_eth_stats stats;
694 } ____cacheline_aligned_in_smp;
695
696 struct sge_ofld_stats { /* offload queue statistics */
697 unsigned long pkts; /* # of packets */
698 unsigned long imm; /* # of immediate-data packets */
699 unsigned long an; /* # of asynchronous notifications */
700 unsigned long nomem; /* # of responses deferred due to no mem */
701 };
702
703 struct sge_ofld_rxq { /* SW offload Rx queue */
704 struct sge_rspq rspq;
705 struct sge_fl fl;
706 struct sge_ofld_stats stats;
707 } ____cacheline_aligned_in_smp;
708
709 struct tx_desc {
710 __be64 flit[8];
711 };
712
713 struct tx_sw_desc;
714
715 struct sge_txq {
716 unsigned int in_use; /* # of in-use Tx descriptors */
717 unsigned int q_type; /* Q type Eth/Ctrl/Ofld */
718 unsigned int size; /* # of descriptors */
719 unsigned int cidx; /* SW consumer index */
720 unsigned int pidx; /* producer index */
721 unsigned long stops; /* # of times q has been stopped */
722 unsigned long restarts; /* # of queue restarts */
723 unsigned int cntxt_id; /* SGE context id for the Tx q */
724 struct tx_desc *desc; /* address of HW Tx descriptor ring */
725 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
726 struct sge_qstat *stat; /* queue status entry */
727 dma_addr_t phys_addr; /* physical address of the ring */
728 spinlock_t db_lock;
729 int db_disabled;
730 unsigned short db_pidx;
731 unsigned short db_pidx_inc;
732 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
733 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
734 };
735
736 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
737 struct sge_txq q;
738 struct netdev_queue *txq; /* associated netdev TX queue */
739 #ifdef CONFIG_CHELSIO_T4_DCB
740 u8 dcb_prio; /* DCB Priority bound to queue */
741 #endif
742 unsigned long tso; /* # of TSO requests */
743 unsigned long tx_cso; /* # of Tx checksum offloads */
744 unsigned long vlan_ins; /* # of Tx VLAN insertions */
745 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
746 } ____cacheline_aligned_in_smp;
747
748 struct sge_uld_txq { /* state for an SGE offload Tx queue */
749 struct sge_txq q;
750 struct adapter *adap;
751 struct sk_buff_head sendq; /* list of backpressured packets */
752 struct tasklet_struct qresume_tsk; /* restarts the queue */
753 bool service_ofldq_running; /* service_ofldq() is processing sendq */
754 u8 full; /* the Tx ring is full */
755 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
756 } ____cacheline_aligned_in_smp;
757
758 struct sge_ctrl_txq { /* state for an SGE control Tx queue */
759 struct sge_txq q;
760 struct adapter *adap;
761 struct sk_buff_head sendq; /* list of backpressured packets */
762 struct tasklet_struct qresume_tsk; /* restarts the queue */
763 u8 full; /* the Tx ring is full */
764 } ____cacheline_aligned_in_smp;
765
766 struct sge_uld_rxq_info {
767 char name[IFNAMSIZ]; /* name of ULD driver */
768 struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */
769 u16 *msix_tbl; /* msix_tbl for uld */
770 u16 *rspq_id; /* response queue id's of rxq */
771 u16 nrxq; /* # of ingress uld queues */
772 u16 nciq; /* # of completion queues */
773 u8 uld; /* uld type */
774 };
775
776 struct sge_uld_txq_info {
777 struct sge_uld_txq *uldtxq; /* Txq's for ULD */
778 atomic_t users; /* num users */
779 u16 ntxq; /* # of egress uld queues */
780 };
781
782 struct sge {
783 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
784 struct sge_eth_txq ptptxq;
785 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
786
787 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
788 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
789 struct sge_uld_rxq_info **uld_rxq_info;
790 struct sge_uld_txq_info **uld_txq_info;
791
792 struct sge_rspq intrq ____cacheline_aligned_in_smp;
793 spinlock_t intrq_lock;
794
795 u16 max_ethqsets; /* # of available Ethernet queue sets */
796 u16 ethqsets; /* # of active Ethernet queue sets */
797 u16 ethtxq_rover; /* Tx queue to clean up next */
798 u16 ofldqsets; /* # of active ofld queue sets */
799 u16 nqs_per_uld; /* # of Rx queues per ULD */
800 u16 timer_val[SGE_NTIMERS];
801 u8 counter_val[SGE_NCOUNTERS];
802 u32 fl_pg_order; /* large page allocation size */
803 u32 stat_len; /* length of status page at ring end */
804 u32 pktshift; /* padding between CPL & packet data */
805 u32 fl_align; /* response queue message alignment */
806 u32 fl_starve_thres; /* Free List starvation threshold */
807
808 struct sge_idma_monitor_state idma_monitor;
809 unsigned int egr_start;
810 unsigned int egr_sz;
811 unsigned int ingr_start;
812 unsigned int ingr_sz;
813 void **egr_map; /* qid->queue egress queue map */
814 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */
815 unsigned long *starving_fl;
816 unsigned long *txq_maperr;
817 unsigned long *blocked_fl;
818 struct timer_list rx_timer; /* refills starving FLs */
819 struct timer_list tx_timer; /* checks Tx queues */
820 };
821
822 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
823 #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
824
825 struct l2t_data;
826
827 #ifdef CONFIG_PCI_IOV
828
829 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial
830 * Configuration initialization for T5 only has SR-IOV functionality enabled
831 * on PF0-3 in order to simplify everything.
832 */
833 #define NUM_OF_PF_WITH_SRIOV 4
834
835 #endif
836
837 struct doorbell_stats {
838 u32 db_drop;
839 u32 db_empty;
840 u32 db_full;
841 };
842
843 struct hash_mac_addr {
844 struct list_head list;
845 u8 addr[ETH_ALEN];
846 };
847
848 struct uld_msix_bmap {
849 unsigned long *msix_bmap;
850 unsigned int mapsize;
851 spinlock_t lock; /* lock for acquiring bitmap */
852 };
853
854 struct uld_msix_info {
855 unsigned short vec;
856 char desc[IFNAMSIZ + 10];
857 unsigned int idx;
858 };
859
860 struct vf_info {
861 unsigned char vf_mac_addr[ETH_ALEN];
862 unsigned int tx_rate;
863 bool pf_set_mac;
864 u16 vlan;
865 };
866
867 enum {
868 HMA_DMA_MAPPED_FLAG = 1
869 };
870
871 struct hma_data {
872 unsigned char flags;
873 struct sg_table *sgt;
874 dma_addr_t *phy_addr; /* physical address of the page */
875 };
876
877 struct mbox_list {
878 struct list_head list;
879 };
880
881 struct mps_encap_entry {
882 atomic_t refcnt;
883 };
884
885 struct adapter {
886 void __iomem *regs;
887 void __iomem *bar2;
888 u32 t4_bar0;
889 struct pci_dev *pdev;
890 struct device *pdev_dev;
891 const char *name;
892 unsigned int mbox;
893 unsigned int pf;
894 unsigned int flags;
895 unsigned int adap_idx;
896 enum chip_type chip;
897 u32 eth_flags;
898
899 int msg_enable;
900 __be16 vxlan_port;
901 u8 vxlan_port_cnt;
902 __be16 geneve_port;
903 u8 geneve_port_cnt;
904
905 struct adapter_params params;
906 struct cxgb4_virt_res vres;
907 unsigned int swintr;
908
909 struct {
910 unsigned short vec;
911 char desc[IFNAMSIZ + 10];
912 } msix_info[MAX_INGQ + 1];
913 struct uld_msix_info *msix_info_ulds; /* msix info for uld's */
914 struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */
915 int msi_idx;
916
917 struct doorbell_stats db_stats;
918 struct sge sge;
919
920 struct net_device *port[MAX_NPORTS];
921 u8 chan_map[NCHAN]; /* channel -> port map */
922
923 struct vf_info *vfinfo;
924 u8 num_vfs;
925
926 u32 filter_mode;
927 unsigned int l2t_start;
928 unsigned int l2t_end;
929 struct l2t_data *l2t;
930 unsigned int clipt_start;
931 unsigned int clipt_end;
932 struct clip_tbl *clipt;
933 unsigned int rawf_start;
934 unsigned int rawf_cnt;
935 struct smt_data *smt;
936 struct mps_encap_entry *mps_encap;
937 struct cxgb4_uld_info *uld;
938 void *uld_handle[CXGB4_ULD_MAX];
939 unsigned int num_uld;
940 unsigned int num_ofld_uld;
941 struct list_head list_node;
942 struct list_head rcu_node;
943 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */
944
945 void *iscsi_ppm;
946
947 struct tid_info tids;
948 void **tid_release_head;
949 spinlock_t tid_release_lock;
950 struct workqueue_struct *workq;
951 struct work_struct tid_release_task;
952 struct work_struct db_full_task;
953 struct work_struct db_drop_task;
954 struct work_struct fatal_err_notify_task;
955 bool tid_release_task_busy;
956
957 /* lock for mailbox cmd list */
958 spinlock_t mbox_lock;
959 struct mbox_list mlist;
960
961 /* support for mailbox command/reply logging */
962 #define T4_OS_LOG_MBOX_CMDS 256
963 struct mbox_cmd_log *mbox_log;
964
965 struct mutex uld_mutex;
966
967 struct dentry *debugfs_root;
968 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */
969 bool trace_rss; /* 1 implies that different RSS flit per filter is
970 * used per filter else if 0 default RSS flit is
971 * used for all 4 filters.
972 */
973
974 struct ptp_clock *ptp_clock;
975 struct ptp_clock_info ptp_clock_info;
976 struct sk_buff *ptp_tx_skb;
977 /* ptp lock */
978 spinlock_t ptp_lock;
979 spinlock_t stats_lock;
980 spinlock_t win0_lock ____cacheline_aligned_in_smp;
981
982 /* TC u32 offload */
983 struct cxgb4_tc_u32_table *tc_u32;
984 struct chcr_stats_debug chcr_stats;
985
986 /* TC flower offload */
987 bool tc_flower_initialized;
988 struct rhashtable flower_tbl;
989 struct rhashtable_params flower_ht_params;
990 struct timer_list flower_stats_timer;
991 struct work_struct flower_stats_work;
992
993 /* Ethtool Dump */
994 struct ethtool_dump eth_dump;
995
996 /* HMA */
997 struct hma_data hma;
998
999 struct srq_data *srq;
1000
1001 /* Dump buffer for collecting logs in kdump kernel */
1002 struct vmcoredd_data vmcoredd;
1003 };
1004
1005 /* Support for "sched-class" command to allow a TX Scheduling Class to be
1006 * programmed with various parameters.
1007 */
1008 struct ch_sched_params {
1009 s8 type; /* packet or flow */
1010 union {
1011 struct {
1012 s8 level; /* scheduler hierarchy level */
1013 s8 mode; /* per-class or per-flow */
1014 s8 rateunit; /* bit or packet rate */
1015 s8 ratemode; /* %port relative or kbps absolute */
1016 s8 channel; /* scheduler channel [0..N] */
1017 s8 class; /* scheduler class [0..N] */
1018 s32 minrate; /* minimum rate */
1019 s32 maxrate; /* maximum rate */
1020 s16 weight; /* percent weight */
1021 s16 pktsize; /* average packet size */
1022 } params;
1023 } u;
1024 };
1025
1026 enum {
1027 SCHED_CLASS_TYPE_PACKET = 0, /* class type */
1028 };
1029
1030 enum {
1031 SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */
1032 };
1033
1034 enum {
1035 SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */
1036 };
1037
1038 enum {
1039 SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */
1040 };
1041
1042 enum {
1043 SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */
1044 };
1045
1046 struct tx_sw_desc { /* SW state per Tx descriptor */
1047 struct sk_buff *skb;
1048 struct ulptx_sgl *sgl;
1049 };
1050
1051 /* Support for "sched_queue" command to allow one or more NIC TX Queues
1052 * to be bound to a TX Scheduling Class.
1053 */
1054 struct ch_sched_queue {
1055 s8 queue; /* queue index */
1056 s8 class; /* class index */
1057 };
1058
1059 /* Defined bit width of user definable filter tuples
1060 */
1061 #define ETHTYPE_BITWIDTH 16
1062 #define FRAG_BITWIDTH 1
1063 #define MACIDX_BITWIDTH 9
1064 #define FCOE_BITWIDTH 1
1065 #define IPORT_BITWIDTH 3
1066 #define MATCHTYPE_BITWIDTH 3
1067 #define PROTO_BITWIDTH 8
1068 #define TOS_BITWIDTH 8
1069 #define PF_BITWIDTH 8
1070 #define VF_BITWIDTH 8
1071 #define IVLAN_BITWIDTH 16
1072 #define OVLAN_BITWIDTH 16
1073 #define ENCAP_VNI_BITWIDTH 24
1074
1075 /* Filter matching rules. These consist of a set of ingress packet field
1076 * (value, mask) tuples. The associated ingress packet field matches the
1077 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field
1078 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule
1079 * matches an ingress packet when all of the individual individual field
1080 * matching rules are true.
1081 *
1082 * Partial field masks are always valid, however, while it may be easy to
1083 * understand their meanings for some fields (e.g. IP address to match a
1084 * subnet), for others making sensible partial masks is less intuitive (e.g.
1085 * MPS match type) ...
1086 *
1087 * Most of the following data structures are modeled on T4 capabilities.
1088 * Drivers for earlier chips use the subsets which make sense for those chips.
1089 * We really need to come up with a hardware-independent mechanism to
1090 * represent hardware filter capabilities ...
1091 */
1092 struct ch_filter_tuple {
1093 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP
1094 * register selects which of these fields will participate in the
1095 * filter match rules -- up to a maximum of 36 bits. Because
1096 * TP_VLAN_PRI_MAP is a global register, all filters must use the same
1097 * set of fields.
1098 */
1099 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */
1100 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */
1101 uint32_t ivlan_vld:1; /* inner VLAN valid */
1102 uint32_t ovlan_vld:1; /* outer VLAN valid */
1103 uint32_t pfvf_vld:1; /* PF/VF valid */
1104 uint32_t encap_vld:1; /* Encapsulation valid */
1105 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */
1106 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */
1107 uint32_t iport:IPORT_BITWIDTH; /* ingress port */
1108 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */
1109 uint32_t proto:PROTO_BITWIDTH; /* protocol type */
1110 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */
1111 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */
1112 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */
1113 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */
1114 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */
1115 uint32_t vni:ENCAP_VNI_BITWIDTH; /* VNI of tunnel */
1116
1117 /* Uncompressed header matching field rules. These are always
1118 * available for field rules.
1119 */
1120 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */
1121 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */
1122 uint16_t lport; /* local port */
1123 uint16_t fport; /* foreign port */
1124 };
1125
1126 /* A filter ioctl command.
1127 */
1128 struct ch_filter_specification {
1129 /* Administrative fields for filter.
1130 */
1131 uint32_t hitcnts:1; /* count filter hits in TCB */
1132 uint32_t prio:1; /* filter has priority over active/server */
1133
1134 /* Fundamental filter typing. This is the one element of filter
1135 * matching that doesn't exist as a (value, mask) tuple.
1136 */
1137 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
1138 u32 hash:1; /* 0 => wild-card, 1 => exact-match */
1139
1140 /* Packet dispatch information. Ingress packets which match the
1141 * filter rules will be dropped, passed to the host or switched back
1142 * out as egress packets.
1143 */
1144 uint32_t action:2; /* drop, pass, switch */
1145
1146 uint32_t rpttid:1; /* report TID in RSS hash field */
1147
1148 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */
1149 uint32_t iq:10; /* ingress queue */
1150
1151 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */
1152 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
1153 /* 1 => TCB contains IQ ID */
1154
1155 /* Switch proxy/rewrite fields. An ingress packet which matches a
1156 * filter with "switch" set will be looped back out as an egress
1157 * packet -- potentially with some Ethernet header rewriting.
1158 */
1159 uint32_t eport:2; /* egress port to switch packet out */
1160 uint32_t newdmac:1; /* rewrite destination MAC address */
1161 uint32_t newsmac:1; /* rewrite source MAC address */
1162 uint32_t newvlan:2; /* rewrite VLAN Tag */
1163 uint32_t nat_mode:3; /* specify NAT operation mode */
1164 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */
1165 uint8_t smac[ETH_ALEN]; /* new source MAC address */
1166 uint16_t vlan; /* VLAN Tag to insert */
1167
1168 u8 nat_lip[16]; /* local IP to use after NAT'ing */
1169 u8 nat_fip[16]; /* foreign IP to use after NAT'ing */
1170 u16 nat_lport; /* local port to use after NAT'ing */
1171 u16 nat_fport; /* foreign port to use after NAT'ing */
1172
1173 /* reservation for future additions */
1174 u8 rsvd[24];
1175
1176 /* Filter rule value/mask pairs.
1177 */
1178 struct ch_filter_tuple val;
1179 struct ch_filter_tuple mask;
1180 };
1181
1182 enum {
1183 FILTER_PASS = 0, /* default */
1184 FILTER_DROP,
1185 FILTER_SWITCH
1186 };
1187
1188 enum {
1189 VLAN_NOCHANGE = 0, /* default */
1190 VLAN_REMOVE,
1191 VLAN_INSERT,
1192 VLAN_REWRITE
1193 };
1194
1195 enum {
1196 NAT_MODE_NONE = 0, /* No NAT performed */
1197 NAT_MODE_DIP, /* NAT on Dst IP */
1198 NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */
1199 NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */
1200 NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */
1201 NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */
1202 NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */
1203 NAT_MODE_ALL /* NAT on entire 4-tuple */
1204 };
1205
1206 /* Host shadow copy of ingress filter entry. This is in host native format
1207 * and doesn't match the ordering or bit order, etc. of the hardware of the
1208 * firmware command. The use of bit-field structure elements is purely to
1209 * remind ourselves of the field size limitations and save memory in the case
1210 * where the filter table is large.
1211 */
1212 struct filter_entry {
1213 /* Administrative fields for filter. */
1214 u32 valid:1; /* filter allocated and valid */
1215 u32 locked:1; /* filter is administratively locked */
1216
1217 u32 pending:1; /* filter action is pending firmware reply */
1218 struct filter_ctx *ctx; /* Caller's completion hook */
1219 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
1220 struct smt_entry *smt; /* Source Mac Table entry for smac */
1221 struct net_device *dev; /* Associated net device */
1222 u32 tid; /* This will store the actual tid */
1223
1224 /* The filter itself. Most of this is a straight copy of information
1225 * provided by the extended ioctl(). Some fields are translated to
1226 * internal forms -- for instance the Ingress Queue ID passed in from
1227 * the ioctl() is translated into the Absolute Ingress Queue ID.
1228 */
1229 struct ch_filter_specification fs;
1230 };
1231
is_offload(const struct adapter * adap)1232 static inline int is_offload(const struct adapter *adap)
1233 {
1234 return adap->params.offload;
1235 }
1236
is_hashfilter(const struct adapter * adap)1237 static inline int is_hashfilter(const struct adapter *adap)
1238 {
1239 return adap->params.hash_filter;
1240 }
1241
is_pci_uld(const struct adapter * adap)1242 static inline int is_pci_uld(const struct adapter *adap)
1243 {
1244 return adap->params.crypto;
1245 }
1246
is_uld(const struct adapter * adap)1247 static inline int is_uld(const struct adapter *adap)
1248 {
1249 return (adap->params.offload || adap->params.crypto);
1250 }
1251
t4_read_reg(struct adapter * adap,u32 reg_addr)1252 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
1253 {
1254 return readl(adap->regs + reg_addr);
1255 }
1256
t4_write_reg(struct adapter * adap,u32 reg_addr,u32 val)1257 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
1258 {
1259 writel(val, adap->regs + reg_addr);
1260 }
1261
1262 #ifndef readq
readq(const volatile void __iomem * addr)1263 static inline u64 readq(const volatile void __iomem *addr)
1264 {
1265 return readl(addr) + ((u64)readl(addr + 4) << 32);
1266 }
1267
writeq(u64 val,volatile void __iomem * addr)1268 static inline void writeq(u64 val, volatile void __iomem *addr)
1269 {
1270 writel(val, addr);
1271 writel(val >> 32, addr + 4);
1272 }
1273 #endif
1274
t4_read_reg64(struct adapter * adap,u32 reg_addr)1275 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
1276 {
1277 return readq(adap->regs + reg_addr);
1278 }
1279
t4_write_reg64(struct adapter * adap,u32 reg_addr,u64 val)1280 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
1281 {
1282 writeq(val, adap->regs + reg_addr);
1283 }
1284
1285 /**
1286 * t4_set_hw_addr - store a port's MAC address in SW
1287 * @adapter: the adapter
1288 * @port_idx: the port index
1289 * @hw_addr: the Ethernet address
1290 *
1291 * Store the Ethernet address of the given port in SW. Called by the common
1292 * code when it retrieves a port's Ethernet address from EEPROM.
1293 */
t4_set_hw_addr(struct adapter * adapter,int port_idx,u8 hw_addr[])1294 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx,
1295 u8 hw_addr[])
1296 {
1297 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr);
1298 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr);
1299 }
1300
1301 /**
1302 * netdev2pinfo - return the port_info structure associated with a net_device
1303 * @dev: the netdev
1304 *
1305 * Return the struct port_info associated with a net_device
1306 */
netdev2pinfo(const struct net_device * dev)1307 static inline struct port_info *netdev2pinfo(const struct net_device *dev)
1308 {
1309 return netdev_priv(dev);
1310 }
1311
1312 /**
1313 * adap2pinfo - return the port_info of a port
1314 * @adap: the adapter
1315 * @idx: the port index
1316 *
1317 * Return the port_info structure for the port of the given index.
1318 */
adap2pinfo(struct adapter * adap,int idx)1319 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
1320 {
1321 return netdev_priv(adap->port[idx]);
1322 }
1323
1324 /**
1325 * netdev2adap - return the adapter structure associated with a net_device
1326 * @dev: the netdev
1327 *
1328 * Return the struct adapter associated with a net_device
1329 */
netdev2adap(const struct net_device * dev)1330 static inline struct adapter *netdev2adap(const struct net_device *dev)
1331 {
1332 return netdev2pinfo(dev)->adapter;
1333 }
1334
1335 /* Return a version number to identify the type of adapter. The scheme is:
1336 * - bits 0..9: chip version
1337 * - bits 10..15: chip revision
1338 * - bits 16..23: register dump version
1339 */
mk_adap_vers(struct adapter * ap)1340 static inline unsigned int mk_adap_vers(struct adapter *ap)
1341 {
1342 return CHELSIO_CHIP_VERSION(ap->params.chip) |
1343 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1344 }
1345
1346 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */
qtimer_val(const struct adapter * adap,const struct sge_rspq * q)1347 static inline unsigned int qtimer_val(const struct adapter *adap,
1348 const struct sge_rspq *q)
1349 {
1350 unsigned int idx = q->intr_params >> 1;
1351
1352 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
1353 }
1354
1355 /* driver version & name used for ethtool_drvinfo */
1356 extern char cxgb4_driver_name[];
1357 extern const char cxgb4_driver_version[];
1358
1359 void t4_os_portmod_changed(struct adapter *adap, int port_id);
1360 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
1361
1362 void t4_free_sge_resources(struct adapter *adap);
1363 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q);
1364 irq_handler_t t4_intr_handler(struct adapter *adap);
1365 netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev);
1366 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1367 const struct pkt_gl *gl);
1368 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
1369 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
1370 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
1371 struct net_device *dev, int intr_idx,
1372 struct sge_fl *fl, rspq_handler_t hnd,
1373 rspq_flush_handler_t flush_handler, int cong);
1374 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
1375 struct net_device *dev, struct netdev_queue *netdevq,
1376 unsigned int iqid);
1377 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
1378 struct net_device *dev, unsigned int iqid,
1379 unsigned int cmplqid);
1380 int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid,
1381 unsigned int cmplqid);
1382 int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq,
1383 struct net_device *dev, unsigned int iqid,
1384 unsigned int uld_type);
1385 irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
1386 int t4_sge_init(struct adapter *adap);
1387 void t4_sge_start(struct adapter *adap);
1388 void t4_sge_stop(struct adapter *adap);
1389 void cxgb4_set_ethtool_ops(struct net_device *netdev);
1390 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues);
1391 enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb);
1392 extern int dbfifo_int_thresh;
1393
1394 #define for_each_port(adapter, iter) \
1395 for (iter = 0; iter < (adapter)->params.nports; ++iter)
1396
is_bypass(struct adapter * adap)1397 static inline int is_bypass(struct adapter *adap)
1398 {
1399 return adap->params.bypass;
1400 }
1401
is_bypass_device(int device)1402 static inline int is_bypass_device(int device)
1403 {
1404 /* this should be set based upon device capabilities */
1405 switch (device) {
1406 case 0x440b:
1407 case 0x440c:
1408 return 1;
1409 default:
1410 return 0;
1411 }
1412 }
1413
is_10gbt_device(int device)1414 static inline int is_10gbt_device(int device)
1415 {
1416 /* this should be set based upon device capabilities */
1417 switch (device) {
1418 case 0x4409:
1419 case 0x4486:
1420 return 1;
1421
1422 default:
1423 return 0;
1424 }
1425 }
1426
core_ticks_per_usec(const struct adapter * adap)1427 static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
1428 {
1429 return adap->params.vpd.cclk / 1000;
1430 }
1431
us_to_core_ticks(const struct adapter * adap,unsigned int us)1432 static inline unsigned int us_to_core_ticks(const struct adapter *adap,
1433 unsigned int us)
1434 {
1435 return (us * adap->params.vpd.cclk) / 1000;
1436 }
1437
core_ticks_to_us(const struct adapter * adapter,unsigned int ticks)1438 static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
1439 unsigned int ticks)
1440 {
1441 /* add Core Clock / 2 to round ticks to nearest uS */
1442 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
1443 adapter->params.vpd.cclk);
1444 }
1445
dack_ticks_to_usec(const struct adapter * adap,unsigned int ticks)1446 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap,
1447 unsigned int ticks)
1448 {
1449 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
1450 }
1451
1452 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
1453 u32 val);
1454
1455 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
1456 int size, void *rpl, bool sleep_ok, int timeout);
1457 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
1458 void *rpl, bool sleep_ok);
1459
t4_wr_mbox_timeout(struct adapter * adap,int mbox,const void * cmd,int size,void * rpl,int timeout)1460 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
1461 const void *cmd, int size, void *rpl,
1462 int timeout)
1463 {
1464 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
1465 timeout);
1466 }
1467
t4_wr_mbox(struct adapter * adap,int mbox,const void * cmd,int size,void * rpl)1468 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
1469 int size, void *rpl)
1470 {
1471 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
1472 }
1473
t4_wr_mbox_ns(struct adapter * adap,int mbox,const void * cmd,int size,void * rpl)1474 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
1475 int size, void *rpl)
1476 {
1477 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
1478 }
1479
1480 /**
1481 * hash_mac_addr - return the hash value of a MAC address
1482 * @addr: the 48-bit Ethernet MAC address
1483 *
1484 * Hashes a MAC address according to the hash function used by HW inexact
1485 * (hash) address matching.
1486 */
hash_mac_addr(const u8 * addr)1487 static inline int hash_mac_addr(const u8 *addr)
1488 {
1489 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
1490 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
1491
1492 a ^= b;
1493 a ^= (a >> 12);
1494 a ^= (a >> 6);
1495 return a & 0x3f;
1496 }
1497
1498 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
1499 unsigned int cnt);
init_rspq(struct adapter * adap,struct sge_rspq * q,unsigned int us,unsigned int cnt,unsigned int size,unsigned int iqe_size)1500 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
1501 unsigned int us, unsigned int cnt,
1502 unsigned int size, unsigned int iqe_size)
1503 {
1504 q->adap = adap;
1505 cxgb4_set_rspq_intr_params(q, us, cnt);
1506 q->iqe_len = iqe_size;
1507 q->size = size;
1508 }
1509
1510 /**
1511 * t4_is_inserted_mod_type - is a plugged in Firmware Module Type
1512 * @fw_mod_type: the Firmware Mofule Type
1513 *
1514 * Return whether the Firmware Module Type represents a real Transceiver
1515 * Module/Cable Module Type which has been inserted.
1516 */
t4_is_inserted_mod_type(unsigned int fw_mod_type)1517 static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type)
1518 {
1519 return (fw_mod_type != FW_PORT_MOD_TYPE_NONE &&
1520 fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED &&
1521 fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN &&
1522 fw_mod_type != FW_PORT_MOD_TYPE_ERROR);
1523 }
1524
1525 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
1526 unsigned int data_reg, const u32 *vals,
1527 unsigned int nregs, unsigned int start_idx);
1528 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
1529 unsigned int data_reg, u32 *vals, unsigned int nregs,
1530 unsigned int start_idx);
1531 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val);
1532
1533 struct fw_filter_wr;
1534
1535 void t4_intr_enable(struct adapter *adapter);
1536 void t4_intr_disable(struct adapter *adapter);
1537 int t4_slow_intr_handler(struct adapter *adapter);
1538
1539 int t4_wait_dev_ready(void __iomem *regs);
1540
1541 int t4_link_l1cfg_core(struct adapter *adap, unsigned int mbox,
1542 unsigned int port, struct link_config *lc,
1543 bool sleep_ok, int timeout);
1544
t4_link_l1cfg(struct adapter * adapter,unsigned int mbox,unsigned int port,struct link_config * lc)1545 static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox,
1546 unsigned int port, struct link_config *lc)
1547 {
1548 return t4_link_l1cfg_core(adapter, mbox, port, lc,
1549 true, FW_CMD_MAX_TIMEOUT);
1550 }
1551
t4_link_l1cfg_ns(struct adapter * adapter,unsigned int mbox,unsigned int port,struct link_config * lc)1552 static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox,
1553 unsigned int port, struct link_config *lc)
1554 {
1555 return t4_link_l1cfg_core(adapter, mbox, port, lc,
1556 false, FW_CMD_MAX_TIMEOUT);
1557 }
1558
1559 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
1560
1561 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg);
1562 u32 t4_get_util_window(struct adapter *adap);
1563 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window);
1564
1565 int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
1566 u32 *mem_base, u32 *mem_aperture);
1567 void t4_memory_update_win(struct adapter *adap, int win, u32 addr);
1568 void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf,
1569 int dir);
1570 #define T4_MEMORY_WRITE 0
1571 #define T4_MEMORY_READ 1
1572 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len,
1573 void *buf, int dir);
t4_memory_write(struct adapter * adap,int mtype,u32 addr,u32 len,__be32 * buf)1574 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr,
1575 u32 len, __be32 *buf)
1576 {
1577 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0);
1578 }
1579
1580 unsigned int t4_get_regs_len(struct adapter *adapter);
1581 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
1582
1583 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz);
1584 int t4_seeprom_wp(struct adapter *adapter, bool enable);
1585 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p);
1586 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
1587 int t4_get_pfres(struct adapter *adapter);
1588 int t4_read_flash(struct adapter *adapter, unsigned int addr,
1589 unsigned int nwords, u32 *data, int byte_oriented);
1590 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
1591 int t4_load_phy_fw(struct adapter *adap,
1592 int win, spinlock_t *lock,
1593 int (*phy_fw_version)(const u8 *, size_t),
1594 const u8 *phy_fw_data, size_t phy_fw_size);
1595 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver);
1596 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
1597 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
1598 const u8 *fw_data, unsigned int size, int force);
1599 int t4_fl_pkt_align(struct adapter *adap);
1600 unsigned int t4_flash_cfg_addr(struct adapter *adapter);
1601 int t4_check_fw_version(struct adapter *adap);
1602 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
1603 int t4_get_fw_version(struct adapter *adapter, u32 *vers);
1604 int t4_get_bs_version(struct adapter *adapter, u32 *vers);
1605 int t4_get_tp_version(struct adapter *adapter, u32 *vers);
1606 int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
1607 int t4_get_scfg_version(struct adapter *adapter, u32 *vers);
1608 int t4_get_vpd_version(struct adapter *adapter, u32 *vers);
1609 int t4_get_version_info(struct adapter *adapter);
1610 void t4_dump_version_info(struct adapter *adapter);
1611 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
1612 const u8 *fw_data, unsigned int fw_size,
1613 struct fw_hdr *card_fw, enum dev_state state, int *reset);
1614 int t4_prep_adapter(struct adapter *adapter);
1615 int t4_shutdown_adapter(struct adapter *adapter);
1616
1617 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
1618 int t4_bar2_sge_qregs(struct adapter *adapter,
1619 unsigned int qid,
1620 enum t4_bar2_qtype qtype,
1621 int user,
1622 u64 *pbar2_qoffset,
1623 unsigned int *pbar2_qid);
1624
1625 unsigned int qtimer_val(const struct adapter *adap,
1626 const struct sge_rspq *q);
1627
1628 int t4_init_devlog_params(struct adapter *adapter);
1629 int t4_init_sge_params(struct adapter *adapter);
1630 int t4_init_tp_params(struct adapter *adap, bool sleep_ok);
1631 int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
1632 int t4_init_rss_mode(struct adapter *adap, int mbox);
1633 int t4_init_portinfo(struct port_info *pi, int mbox,
1634 int port, int pf, int vf, u8 mac[]);
1635 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
1636 void t4_fatal_err(struct adapter *adapter);
1637 unsigned int t4_chip_rss_size(struct adapter *adapter);
1638 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1639 int start, int n, const u16 *rspq, unsigned int nrspq);
1640 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
1641 unsigned int flags);
1642 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
1643 unsigned int flags, unsigned int defq);
1644 int t4_read_rss(struct adapter *adapter, u16 *entries);
1645 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok);
1646 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
1647 bool sleep_ok);
1648 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
1649 u32 *valp, bool sleep_ok);
1650 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
1651 u32 *vfl, u32 *vfh, bool sleep_ok);
1652 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok);
1653 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok);
1654
1655 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx);
1656 unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx);
1657 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1658 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1659 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
1660 size_t n);
1661 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data,
1662 size_t n);
1663 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
1664 unsigned int *valp);
1665 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
1666 const unsigned int *valp);
1667 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
1668 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
1669 unsigned int *pif_req_wrptr,
1670 unsigned int *pif_rsp_wrptr);
1671 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
1672 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
1673 const char *t4_get_port_type_description(enum fw_port_type port_type);
1674 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
1675 void t4_get_port_stats_offset(struct adapter *adap, int idx,
1676 struct port_stats *stats,
1677 struct port_stats *offset);
1678 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
1679 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
1680 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
1681 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
1682 unsigned int mask, unsigned int val);
1683 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
1684 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
1685 bool sleep_ok);
1686 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
1687 bool sleep_ok);
1688 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
1689 bool sleep_ok);
1690 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
1691 bool sleep_ok);
1692 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
1693 struct tp_tcp_stats *v6, bool sleep_ok);
1694 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
1695 struct tp_fcoe_stats *st, bool sleep_ok);
1696 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
1697 const unsigned short *alpha, const unsigned short *beta);
1698
1699 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
1700
1701 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate);
1702 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
1703
1704 void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
1705 const u8 *addr);
1706 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
1707 u64 mask0, u64 mask1, unsigned int crc, bool enable);
1708
1709 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
1710 enum dev_master master, enum dev_state *state);
1711 int t4_fw_bye(struct adapter *adap, unsigned int mbox);
1712 int t4_early_init(struct adapter *adap, unsigned int mbox);
1713 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
1714 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
1715 unsigned int cache_line_size);
1716 int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
1717 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1718 unsigned int vf, unsigned int nparams, const u32 *params,
1719 u32 *val);
1720 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
1721 unsigned int vf, unsigned int nparams, const u32 *params,
1722 u32 *val);
1723 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
1724 unsigned int vf, unsigned int nparams, const u32 *params,
1725 u32 *val, int rw, bool sleep_ok);
1726 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
1727 unsigned int pf, unsigned int vf,
1728 unsigned int nparams, const u32 *params,
1729 const u32 *val, int timeout);
1730 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1731 unsigned int vf, unsigned int nparams, const u32 *params,
1732 const u32 *val);
1733 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
1734 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
1735 unsigned int rxqi, unsigned int rxq, unsigned int tc,
1736 unsigned int vi, unsigned int cmask, unsigned int pmask,
1737 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
1738 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
1739 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
1740 unsigned int *rss_size);
1741 int t4_free_vi(struct adapter *adap, unsigned int mbox,
1742 unsigned int pf, unsigned int vf,
1743 unsigned int viid);
1744 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
1745 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1746 bool sleep_ok);
1747 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
1748 const u8 *addr, const u8 *mask, unsigned int idx,
1749 u8 lookup_type, u8 port_id, bool sleep_ok);
1750 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx,
1751 bool sleep_ok);
1752 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
1753 const u8 *addr, const u8 *mask, unsigned int vni,
1754 unsigned int vni_mask, u8 dip_hit, u8 lookup_type,
1755 bool sleep_ok);
1756 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
1757 const u8 *addr, const u8 *mask, unsigned int idx,
1758 u8 lookup_type, u8 port_id, bool sleep_ok);
1759 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
1760 unsigned int viid, bool free, unsigned int naddr,
1761 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
1762 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
1763 unsigned int viid, unsigned int naddr,
1764 const u8 **addr, bool sleep_ok);
1765 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
1766 int idx, const u8 *addr, bool persist, bool add_smt);
1767 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
1768 bool ucast, u64 vec, bool sleep_ok);
1769 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
1770 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
1771 int t4_enable_pi_params(struct adapter *adap, unsigned int mbox,
1772 struct port_info *pi,
1773 bool rx_en, bool tx_en, bool dcb_en);
1774 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
1775 bool rx_en, bool tx_en);
1776 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
1777 unsigned int nblinks);
1778 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1779 unsigned int mmd, unsigned int reg, u16 *valp);
1780 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1781 unsigned int mmd, unsigned int reg, u16 val);
1782 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
1783 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1784 unsigned int fl0id, unsigned int fl1id);
1785 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1786 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1787 unsigned int fl0id, unsigned int fl1id);
1788 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1789 unsigned int vf, unsigned int eqid);
1790 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1791 unsigned int vf, unsigned int eqid);
1792 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1793 unsigned int vf, unsigned int eqid);
1794 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type);
1795 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl);
1796 int t4_update_port_info(struct port_info *pi);
1797 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
1798 unsigned int *speedp, unsigned int *mtup);
1799 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
1800 void t4_db_full(struct adapter *adapter);
1801 void t4_db_dropped(struct adapter *adapter);
1802 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
1803 int filter_index, int enable);
1804 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
1805 int filter_index, int *enabled);
1806 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
1807 u32 addr, u32 val);
1808 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]);
1809 void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
1810 unsigned int *kbps, unsigned int *ipg, bool sleep_ok);
1811 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
1812 enum ctxt_type ctype, u32 *data);
1813 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
1814 enum ctxt_type ctype, u32 *data);
1815 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
1816 int rateunit, int ratemode, int channel, int class,
1817 int minrate, int maxrate, int weight, int pktsize);
1818 void t4_sge_decode_idma_state(struct adapter *adapter, int state);
1819 void t4_idma_monitor_init(struct adapter *adapter,
1820 struct sge_idma_monitor_state *idma);
1821 void t4_idma_monitor(struct adapter *adapter,
1822 struct sge_idma_monitor_state *idma,
1823 int hz, int ticks);
1824 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
1825 unsigned int naddr, u8 *addr);
1826 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
1827 u32 start_index, bool sleep_ok);
1828 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
1829 u32 start_index, bool sleep_ok);
1830 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs,
1831 u32 start_index, bool sleep_ok);
1832
1833 void t4_uld_mem_free(struct adapter *adap);
1834 int t4_uld_mem_alloc(struct adapter *adap);
1835 void t4_uld_clean_up(struct adapter *adap);
1836 void t4_register_netevent_notifier(void);
1837 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port,
1838 unsigned int devid, unsigned int offset,
1839 unsigned int len, u8 *buf);
1840 void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl);
1841 void free_tx_desc(struct adapter *adap, struct sge_txq *q,
1842 unsigned int n, bool unmap);
1843 void free_txq(struct adapter *adap, struct sge_txq *q);
1844 void cxgb4_reclaim_completed_tx(struct adapter *adap,
1845 struct sge_txq *q, bool unmap);
1846 int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb,
1847 dma_addr_t *addr);
1848 void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q,
1849 void *pos);
1850 void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q,
1851 struct ulptx_sgl *sgl, u64 *end, unsigned int start,
1852 const dma_addr_t *addr);
1853 void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n);
1854 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
1855 u16 vlan);
1856 int cxgb4_dcb_enabled(const struct net_device *dev);
1857 #endif /* __CXGB4_H__ */
1858
