1/* 2 * Copyright Altera Corporation (C) 2014. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/reset/altr,rst-mgr-a10.h> 19 20/ { 21 #address-cells = <1>; 22 #size-cells = <1>; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 enable-method = "altr,socfpga-a10-smp"; 28 29 cpu@0 { 30 compatible = "arm,cortex-a9"; 31 device_type = "cpu"; 32 reg = <0>; 33 next-level-cache = <&L2>; 34 }; 35 cpu@1 { 36 compatible = "arm,cortex-a9"; 37 device_type = "cpu"; 38 reg = <1>; 39 next-level-cache = <&L2>; 40 }; 41 }; 42 43 intc: intc@ffffd000 { 44 compatible = "arm,cortex-a9-gic"; 45 #interrupt-cells = <3>; 46 interrupt-controller; 47 reg = <0xffffd000 0x1000>, 48 <0xffffc100 0x100>; 49 }; 50 51 soc { 52 #address-cells = <1>; 53 #size-cells = <1>; 54 compatible = "simple-bus"; 55 device_type = "soc"; 56 interrupt-parent = <&intc>; 57 ranges; 58 59 amba { 60 compatible = "simple-bus"; 61 #address-cells = <1>; 62 #size-cells = <1>; 63 ranges; 64 65 pdma: pdma@ffda1000 { 66 compatible = "arm,pl330", "arm,primecell"; 67 reg = <0xffda1000 0x1000>; 68 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>, 69 <0 84 IRQ_TYPE_LEVEL_HIGH>, 70 <0 85 IRQ_TYPE_LEVEL_HIGH>, 71 <0 86 IRQ_TYPE_LEVEL_HIGH>, 72 <0 87 IRQ_TYPE_LEVEL_HIGH>, 73 <0 88 IRQ_TYPE_LEVEL_HIGH>, 74 <0 89 IRQ_TYPE_LEVEL_HIGH>, 75 <0 90 IRQ_TYPE_LEVEL_HIGH>, 76 <0 91 IRQ_TYPE_LEVEL_HIGH>; 77 #dma-cells = <1>; 78 #dma-channels = <8>; 79 #dma-requests = <32>; 80 clocks = <&l4_main_clk>; 81 clock-names = "apb_pclk"; 82 }; 83 }; 84 85 base_fpga_region { 86 #address-cells = <0x1>; 87 #size-cells = <0x1>; 88 89 compatible = "fpga-region"; 90 fpga-mgr = <&fpga_mgr>; 91 }; 92 93 clkmgr@ffd04000 { 94 compatible = "altr,clk-mgr"; 95 reg = <0xffd04000 0x1000>; 96 97 clocks { 98 #address-cells = <1>; 99 #size-cells = <0>; 100 101 cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk { 102 #clock-cells = <0>; 103 compatible = "fixed-clock"; 104 }; 105 106 cb_intosc_ls_clk: cb_intosc_ls_clk { 107 #clock-cells = <0>; 108 compatible = "fixed-clock"; 109 }; 110 111 f2s_free_clk: f2s_free_clk { 112 #clock-cells = <0>; 113 compatible = "fixed-clock"; 114 }; 115 116 osc1: osc1 { 117 #clock-cells = <0>; 118 compatible = "fixed-clock"; 119 }; 120 121 main_pll: main_pll@40 { 122 #address-cells = <1>; 123 #size-cells = <0>; 124 #clock-cells = <0>; 125 compatible = "altr,socfpga-a10-pll-clock"; 126 clocks = <&osc1>, <&cb_intosc_ls_clk>, 127 <&f2s_free_clk>; 128 reg = <0x40>; 129 130 main_mpu_base_clk: main_mpu_base_clk { 131 #clock-cells = <0>; 132 compatible = "altr,socfpga-a10-perip-clk"; 133 clocks = <&main_pll>; 134 div-reg = <0x140 0 11>; 135 }; 136 137 main_noc_base_clk: main_noc_base_clk { 138 #clock-cells = <0>; 139 compatible = "altr,socfpga-a10-perip-clk"; 140 clocks = <&main_pll>; 141 div-reg = <0x144 0 11>; 142 }; 143 144 main_emaca_clk: main_emaca_clk@68 { 145 #clock-cells = <0>; 146 compatible = "altr,socfpga-a10-perip-clk"; 147 clocks = <&main_pll>; 148 reg = <0x68>; 149 }; 150 151 main_emacb_clk: main_emacb_clk@6c { 152 #clock-cells = <0>; 153 compatible = "altr,socfpga-a10-perip-clk"; 154 clocks = <&main_pll>; 155 reg = <0x6C>; 156 }; 157 158 main_emac_ptp_clk: main_emac_ptp_clk@70 { 159 #clock-cells = <0>; 160 compatible = "altr,socfpga-a10-perip-clk"; 161 clocks = <&main_pll>; 162 reg = <0x70>; 163 }; 164 165 main_gpio_db_clk: main_gpio_db_clk@74 { 166 #clock-cells = <0>; 167 compatible = "altr,socfpga-a10-perip-clk"; 168 clocks = <&main_pll>; 169 reg = <0x74>; 170 }; 171 172 main_sdmmc_clk: main_sdmmc_clk@78 { 173 #clock-cells = <0>; 174 compatible = "altr,socfpga-a10-perip-clk" 175; 176 clocks = <&main_pll>; 177 reg = <0x78>; 178 }; 179 180 main_s2f_usr0_clk: main_s2f_usr0_clk@7c { 181 #clock-cells = <0>; 182 compatible = "altr,socfpga-a10-perip-clk"; 183 clocks = <&main_pll>; 184 reg = <0x7C>; 185 }; 186 187 main_s2f_usr1_clk: main_s2f_usr1_clk@80 { 188 #clock-cells = <0>; 189 compatible = "altr,socfpga-a10-perip-clk"; 190 clocks = <&main_pll>; 191 reg = <0x80>; 192 }; 193 194 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 { 195 #clock-cells = <0>; 196 compatible = "altr,socfpga-a10-perip-clk"; 197 clocks = <&main_pll>; 198 reg = <0x84>; 199 }; 200 201 main_periph_ref_clk: main_periph_ref_clk@9c { 202 #clock-cells = <0>; 203 compatible = "altr,socfpga-a10-perip-clk"; 204 clocks = <&main_pll>; 205 reg = <0x9C>; 206 }; 207 }; 208 209 periph_pll: periph_pll@c0 { 210 #address-cells = <1>; 211 #size-cells = <0>; 212 #clock-cells = <0>; 213 compatible = "altr,socfpga-a10-pll-clock"; 214 clocks = <&osc1>, <&cb_intosc_ls_clk>, 215 <&f2s_free_clk>, <&main_periph_ref_clk>; 216 reg = <0xC0>; 217 218 peri_mpu_base_clk: peri_mpu_base_clk { 219 #clock-cells = <0>; 220 compatible = "altr,socfpga-a10-perip-clk"; 221 clocks = <&periph_pll>; 222 div-reg = <0x140 16 11>; 223 }; 224 225 peri_noc_base_clk: peri_noc_base_clk { 226 #clock-cells = <0>; 227 compatible = "altr,socfpga-a10-perip-clk"; 228 clocks = <&periph_pll>; 229 div-reg = <0x144 16 11>; 230 }; 231 232 peri_emaca_clk: peri_emaca_clk@e8 { 233 #clock-cells = <0>; 234 compatible = "altr,socfpga-a10-perip-clk"; 235 clocks = <&periph_pll>; 236 reg = <0xE8>; 237 }; 238 239 peri_emacb_clk: peri_emacb_clk@ec { 240 #clock-cells = <0>; 241 compatible = "altr,socfpga-a10-perip-clk"; 242 clocks = <&periph_pll>; 243 reg = <0xEC>; 244 }; 245 246 peri_emac_ptp_clk: peri_emac_ptp_clk@f0 { 247 #clock-cells = <0>; 248 compatible = "altr,socfpga-a10-perip-clk"; 249 clocks = <&periph_pll>; 250 reg = <0xF0>; 251 }; 252 253 peri_gpio_db_clk: peri_gpio_db_clk@f4 { 254 #clock-cells = <0>; 255 compatible = "altr,socfpga-a10-perip-clk"; 256 clocks = <&periph_pll>; 257 reg = <0xF4>; 258 }; 259 260 peri_sdmmc_clk: peri_sdmmc_clk@f8 { 261 #clock-cells = <0>; 262 compatible = "altr,socfpga-a10-perip-clk"; 263 clocks = <&periph_pll>; 264 reg = <0xF8>; 265 }; 266 267 peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc { 268 #clock-cells = <0>; 269 compatible = "altr,socfpga-a10-perip-clk"; 270 clocks = <&periph_pll>; 271 reg = <0xFC>; 272 }; 273 274 peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 { 275 #clock-cells = <0>; 276 compatible = "altr,socfpga-a10-perip-clk"; 277 clocks = <&periph_pll>; 278 reg = <0x100>; 279 }; 280 281 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 { 282 #clock-cells = <0>; 283 compatible = "altr,socfpga-a10-perip-clk"; 284 clocks = <&periph_pll>; 285 reg = <0x104>; 286 }; 287 }; 288 289 mpu_free_clk: mpu_free_clk@60 { 290 #clock-cells = <0>; 291 compatible = "altr,socfpga-a10-perip-clk"; 292 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>, 293 <&osc1>, <&cb_intosc_hs_div2_clk>, 294 <&f2s_free_clk>; 295 reg = <0x60>; 296 }; 297 298 noc_free_clk: noc_free_clk@64 { 299 #clock-cells = <0>; 300 compatible = "altr,socfpga-a10-perip-clk"; 301 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>, 302 <&osc1>, <&cb_intosc_hs_div2_clk>, 303 <&f2s_free_clk>; 304 reg = <0x64>; 305 }; 306 307 s2f_user1_free_clk: s2f_user1_free_clk@104 { 308 #clock-cells = <0>; 309 compatible = "altr,socfpga-a10-perip-clk"; 310 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>, 311 <&osc1>, <&cb_intosc_hs_div2_clk>, 312 <&f2s_free_clk>; 313 reg = <0x104>; 314 }; 315 316 sdmmc_free_clk: sdmmc_free_clk@f8 { 317 #clock-cells = <0>; 318 compatible = "altr,socfpga-a10-perip-clk"; 319 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>, 320 <&osc1>, <&cb_intosc_hs_div2_clk>, 321 <&f2s_free_clk>; 322 fixed-divider = <4>; 323 reg = <0xF8>; 324 }; 325 326 l4_sys_free_clk: l4_sys_free_clk { 327 #clock-cells = <0>; 328 compatible = "altr,socfpga-a10-perip-clk"; 329 clocks = <&noc_free_clk>; 330 fixed-divider = <4>; 331 }; 332 333 l4_main_clk: l4_main_clk { 334 #clock-cells = <0>; 335 compatible = "altr,socfpga-a10-gate-clk"; 336 clocks = <&noc_free_clk>; 337 div-reg = <0xA8 0 2>; 338 clk-gate = <0x48 1>; 339 }; 340 341 l4_mp_clk: l4_mp_clk { 342 #clock-cells = <0>; 343 compatible = "altr,socfpga-a10-gate-clk"; 344 clocks = <&noc_free_clk>; 345 div-reg = <0xA8 8 2>; 346 clk-gate = <0x48 2>; 347 }; 348 349 l4_sp_clk: l4_sp_clk { 350 #clock-cells = <0>; 351 compatible = "altr,socfpga-a10-gate-clk"; 352 clocks = <&noc_free_clk>; 353 div-reg = <0xA8 16 2>; 354 clk-gate = <0x48 3>; 355 }; 356 357 mpu_periph_clk: mpu_periph_clk { 358 #clock-cells = <0>; 359 compatible = "altr,socfpga-a10-gate-clk"; 360 clocks = <&mpu_free_clk>; 361 fixed-divider = <4>; 362 clk-gate = <0x48 0>; 363 }; 364 365 sdmmc_clk: sdmmc_clk { 366 #clock-cells = <0>; 367 compatible = "altr,socfpga-a10-gate-clk"; 368 clocks = <&sdmmc_free_clk>; 369 clk-gate = <0xC8 5>; 370 clk-phase = <0 135>; 371 }; 372 373 qspi_clk: qspi_clk { 374 #clock-cells = <0>; 375 compatible = "altr,socfpga-a10-gate-clk"; 376 clocks = <&l4_main_clk>; 377 clk-gate = <0xC8 11>; 378 }; 379 380 nand_clk: nand_clk { 381 #clock-cells = <0>; 382 compatible = "altr,socfpga-a10-gate-clk"; 383 clocks = <&l4_mp_clk>; 384 clk-gate = <0xC8 10>; 385 }; 386 387 spi_m_clk: spi_m_clk { 388 #clock-cells = <0>; 389 compatible = "altr,socfpga-a10-gate-clk"; 390 clocks = <&l4_main_clk>; 391 clk-gate = <0xC8 9>; 392 }; 393 394 usb_clk: usb_clk { 395 #clock-cells = <0>; 396 compatible = "altr,socfpga-a10-gate-clk"; 397 clocks = <&l4_mp_clk>; 398 clk-gate = <0xC8 8>; 399 }; 400 401 s2f_usr1_clk: s2f_usr1_clk { 402 #clock-cells = <0>; 403 compatible = "altr,socfpga-a10-gate-clk"; 404 clocks = <&peri_s2f_usr1_clk>; 405 clk-gate = <0xC8 6>; 406 }; 407 }; 408 }; 409 410 socfpga_axi_setup: stmmac-axi-config { 411 snps,wr_osr_lmt = <0xf>; 412 snps,rd_osr_lmt = <0xf>; 413 snps,blen = <0 0 0 0 16 0 0>; 414 }; 415 416 gmac0: ethernet@ff800000 { 417 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; 418 altr,sysmgr-syscon = <&sysmgr 0x44 0>; 419 reg = <0xff800000 0x2000>; 420 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; 421 interrupt-names = "macirq"; 422 /* Filled in by bootloader */ 423 mac-address = [00 00 00 00 00 00]; 424 snps,multicast-filter-bins = <256>; 425 snps,perfect-filter-entries = <128>; 426 tx-fifo-depth = <4096>; 427 rx-fifo-depth = <16384>; 428 clocks = <&l4_mp_clk>; 429 clock-names = "stmmaceth"; 430 resets = <&rst EMAC0_RESET>; 431 reset-names = "stmmaceth"; 432 snps,axi-config = <&socfpga_axi_setup>; 433 status = "disabled"; 434 }; 435 436 gmac1: ethernet@ff802000 { 437 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; 438 altr,sysmgr-syscon = <&sysmgr 0x48 0>; 439 reg = <0xff802000 0x2000>; 440 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; 441 interrupt-names = "macirq"; 442 /* Filled in by bootloader */ 443 mac-address = [00 00 00 00 00 00]; 444 snps,multicast-filter-bins = <256>; 445 snps,perfect-filter-entries = <128>; 446 tx-fifo-depth = <4096>; 447 rx-fifo-depth = <16384>; 448 clocks = <&l4_mp_clk>; 449 clock-names = "stmmaceth"; 450 resets = <&rst EMAC1_RESET>; 451 reset-names = "stmmaceth"; 452 snps,axi-config = <&socfpga_axi_setup>; 453 status = "disabled"; 454 }; 455 456 gmac2: ethernet@ff804000 { 457 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; 458 altr,sysmgr-syscon = <&sysmgr 0x4C 0>; 459 reg = <0xff804000 0x2000>; 460 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; 461 interrupt-names = "macirq"; 462 /* Filled in by bootloader */ 463 mac-address = [00 00 00 00 00 00]; 464 snps,multicast-filter-bins = <256>; 465 snps,perfect-filter-entries = <128>; 466 tx-fifo-depth = <4096>; 467 rx-fifo-depth = <16384>; 468 clocks = <&l4_mp_clk>; 469 clock-names = "stmmaceth"; 470 snps,axi-config = <&socfpga_axi_setup>; 471 status = "disabled"; 472 }; 473 474 gpio0: gpio@ffc02900 { 475 #address-cells = <1>; 476 #size-cells = <0>; 477 compatible = "snps,dw-apb-gpio"; 478 reg = <0xffc02900 0x100>; 479 status = "disabled"; 480 481 porta: gpio-controller@0 { 482 compatible = "snps,dw-apb-gpio-port"; 483 gpio-controller; 484 #gpio-cells = <2>; 485 snps,nr-gpios = <29>; 486 reg = <0>; 487 interrupt-controller; 488 #interrupt-cells = <2>; 489 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>; 490 }; 491 }; 492 493 gpio1: gpio@ffc02a00 { 494 #address-cells = <1>; 495 #size-cells = <0>; 496 compatible = "snps,dw-apb-gpio"; 497 reg = <0xffc02a00 0x100>; 498 status = "disabled"; 499 500 portb: gpio-controller@0 { 501 compatible = "snps,dw-apb-gpio-port"; 502 gpio-controller; 503 #gpio-cells = <2>; 504 snps,nr-gpios = <29>; 505 reg = <0>; 506 interrupt-controller; 507 #interrupt-cells = <2>; 508 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; 509 }; 510 }; 511 512 gpio2: gpio@ffc02b00 { 513 #address-cells = <1>; 514 #size-cells = <0>; 515 compatible = "snps,dw-apb-gpio"; 516 reg = <0xffc02b00 0x100>; 517 status = "disabled"; 518 519 portc: gpio-controller@0 { 520 compatible = "snps,dw-apb-gpio-port"; 521 gpio-controller; 522 #gpio-cells = <2>; 523 snps,nr-gpios = <27>; 524 reg = <0>; 525 interrupt-controller; 526 #interrupt-cells = <2>; 527 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; 528 }; 529 }; 530 531 fpga_mgr: fpga-mgr@ffd03000 { 532 compatible = "altr,socfpga-a10-fpga-mgr"; 533 reg = <0xffd03000 0x100 534 0xffcfe400 0x20>; 535 clocks = <&l4_mp_clk>; 536 resets = <&rst FPGAMGR_RESET>; 537 reset-names = "fpgamgr"; 538 }; 539 540 i2c0: i2c@ffc02200 { 541 #address-cells = <1>; 542 #size-cells = <0>; 543 compatible = "snps,designware-i2c"; 544 reg = <0xffc02200 0x100>; 545 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; 546 clocks = <&l4_sp_clk>; 547 status = "disabled"; 548 }; 549 550 i2c1: i2c@ffc02300 { 551 #address-cells = <1>; 552 #size-cells = <0>; 553 compatible = "snps,designware-i2c"; 554 reg = <0xffc02300 0x100>; 555 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <&l4_sp_clk>; 557 status = "disabled"; 558 }; 559 560 i2c2: i2c@ffc02400 { 561 #address-cells = <1>; 562 #size-cells = <0>; 563 compatible = "snps,designware-i2c"; 564 reg = <0xffc02400 0x100>; 565 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; 566 clocks = <&l4_sp_clk>; 567 status = "disabled"; 568 }; 569 570 i2c3: i2c@ffc02500 { 571 #address-cells = <1>; 572 #size-cells = <0>; 573 compatible = "snps,designware-i2c"; 574 reg = <0xffc02500 0x100>; 575 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; 576 clocks = <&l4_sp_clk>; 577 status = "disabled"; 578 }; 579 580 i2c4: i2c@ffc02600 { 581 #address-cells = <1>; 582 #size-cells = <0>; 583 compatible = "snps,designware-i2c"; 584 reg = <0xffc02600 0x100>; 585 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; 586 clocks = <&l4_sp_clk>; 587 status = "disabled"; 588 }; 589 590 spi0: spi@ffda4000 { 591 compatible = "snps,dw-apb-ssi"; 592 #address-cells = <1>; 593 #size-cells = <0>; 594 reg = <0xffda4000 0x100>; 595 interrupts = <0 101 4>; 596 num-cs = <4>; 597 /*32bit_access;*/ 598 clocks = <&spi_m_clk>; 599 status = "disabled"; 600 }; 601 602 spi1: spi@ffda5000 { 603 compatible = "snps,dw-apb-ssi"; 604 #address-cells = <1>; 605 #size-cells = <0>; 606 reg = <0xffda5000 0x100>; 607 interrupts = <0 102 4>; 608 num-cs = <4>; 609 /*32bit_access;*/ 610 tx-dma-channel = <&pdma 16>; 611 rx-dma-channel = <&pdma 17>; 612 clocks = <&spi_m_clk>; 613 status = "disabled"; 614 }; 615 616 sdr: sdr@ffc25000 { 617 compatible = "altr,sdr-ctl", "syscon"; 618 reg = <0xffcfb100 0x80>; 619 }; 620 621 L2: l2-cache@fffff000 { 622 compatible = "arm,pl310-cache"; 623 reg = <0xfffff000 0x1000>; 624 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; 625 cache-unified; 626 cache-level = <2>; 627 prefetch-data = <1>; 628 prefetch-instr = <1>; 629 arm,shared-override; 630 }; 631 632 mmc: dwmmc0@ff808000 { 633 #address-cells = <1>; 634 #size-cells = <0>; 635 compatible = "altr,socfpga-dw-mshc"; 636 reg = <0xff808000 0x1000>; 637 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; 638 fifo-depth = <0x400>; 639 clocks = <&l4_mp_clk>, <&sdmmc_clk>; 640 clock-names = "biu", "ciu"; 641 status = "disabled"; 642 }; 643 644 nand: nand@ffb90000 { 645 #address-cells = <1>; 646 #size-cells = <1>; 647 compatible = "altr,socfpga-denali-nand"; 648 reg = <0xffb90000 0x72000>, 649 <0xffb80000 0x10000>; 650 reg-names = "nand_data", "denali_reg"; 651 interrupts = <0 99 4>; 652 dma-mask = <0xffffffff>; 653 clocks = <&nand_clk>; 654 status = "disabled"; 655 }; 656 657 ocram: sram@ffe00000 { 658 compatible = "mmio-sram"; 659 reg = <0xffe00000 0x40000>; 660 }; 661 662 eccmgr: eccmgr { 663 compatible = "altr,socfpga-a10-ecc-manager"; 664 altr,sysmgr-syscon = <&sysmgr>; 665 #address-cells = <1>; 666 #size-cells = <1>; 667 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>, 668 <0 0 IRQ_TYPE_LEVEL_HIGH>; 669 interrupt-controller; 670 #interrupt-cells = <2>; 671 ranges; 672 673 sdramedac { 674 compatible = "altr,sdram-edac-a10"; 675 altr,sdr-syscon = <&sdr>; 676 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, 677 <49 IRQ_TYPE_LEVEL_HIGH>; 678 }; 679 680 l2-ecc@ffd06010 { 681 compatible = "altr,socfpga-a10-l2-ecc"; 682 reg = <0xffd06010 0x4>; 683 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, 684 <32 IRQ_TYPE_LEVEL_HIGH>; 685 }; 686 687 ocram-ecc@ff8c3000 { 688 compatible = "altr,socfpga-a10-ocram-ecc"; 689 reg = <0xff8c3000 0x400>; 690 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>, 691 <33 IRQ_TYPE_LEVEL_HIGH>; 692 }; 693 694 emac0-rx-ecc@ff8c0800 { 695 compatible = "altr,socfpga-eth-mac-ecc"; 696 reg = <0xff8c0800 0x400>; 697 altr,ecc-parent = <&gmac0>; 698 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>, 699 <36 IRQ_TYPE_LEVEL_HIGH>; 700 }; 701 702 emac0-tx-ecc@ff8c0c00 { 703 compatible = "altr,socfpga-eth-mac-ecc"; 704 reg = <0xff8c0c00 0x400>; 705 altr,ecc-parent = <&gmac0>; 706 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>, 707 <37 IRQ_TYPE_LEVEL_HIGH>; 708 }; 709 710 dma-ecc@ff8c8000 { 711 compatible = "altr,socfpga-dma-ecc"; 712 reg = <0xff8c8000 0x400>; 713 altr,ecc-parent = <&pdma>; 714 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, 715 <42 IRQ_TYPE_LEVEL_HIGH>; 716 }; 717 718 usb0-ecc@ff8c8800 { 719 compatible = "altr,socfpga-usb-ecc"; 720 reg = <0xff8c8800 0x400>; 721 altr,ecc-parent = <&usb0>; 722 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, 723 <34 IRQ_TYPE_LEVEL_HIGH>; 724 }; 725 }; 726 727 qspi: spi@ff809000 { 728 compatible = "cdns,qspi-nor"; 729 #address-cells = <1>; 730 #size-cells = <0>; 731 reg = <0xff809000 0x100>, 732 <0xffa00000 0x100000>; 733 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; 734 cdns,fifo-depth = <128>; 735 cdns,fifo-width = <4>; 736 cdns,trigger-address = <0x00000000>; 737 clocks = <&qspi_clk>; 738 status = "disabled"; 739 }; 740 741 rst: rstmgr@ffd05000 { 742 #reset-cells = <1>; 743 compatible = "altr,rst-mgr"; 744 reg = <0xffd05000 0x100>; 745 altr,modrst-offset = <0x20>; 746 }; 747 748 scu: snoop-control-unit@ffffc000 { 749 compatible = "arm,cortex-a9-scu"; 750 reg = <0xffffc000 0x100>; 751 }; 752 753 sysmgr: sysmgr@ffd06000 { 754 compatible = "altr,sys-mgr", "syscon"; 755 reg = <0xffd06000 0x300>; 756 cpu1-start-addr = <0xffd06230>; 757 }; 758 759 /* Local timer */ 760 timer@ffffc600 { 761 compatible = "arm,cortex-a9-twd-timer"; 762 reg = <0xffffc600 0x100>; 763 interrupts = <1 13 0xf04>; 764 clocks = <&mpu_periph_clk>; 765 }; 766 767 timer0: timer0@ffc02700 { 768 compatible = "snps,dw-apb-timer"; 769 interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>; 770 reg = <0xffc02700 0x100>; 771 clocks = <&l4_sp_clk>; 772 clock-names = "timer"; 773 }; 774 775 timer1: timer1@ffc02800 { 776 compatible = "snps,dw-apb-timer"; 777 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>; 778 reg = <0xffc02800 0x100>; 779 clocks = <&l4_sp_clk>; 780 clock-names = "timer"; 781 }; 782 783 timer2: timer2@ffd00000 { 784 compatible = "snps,dw-apb-timer"; 785 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>; 786 reg = <0xffd00000 0x100>; 787 clocks = <&l4_sys_free_clk>; 788 clock-names = "timer"; 789 }; 790 791 timer3: timer3@ffd00100 { 792 compatible = "snps,dw-apb-timer"; 793 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; 794 reg = <0xffd01000 0x100>; 795 clocks = <&l4_sys_free_clk>; 796 clock-names = "timer"; 797 }; 798 799 uart0: serial0@ffc02000 { 800 compatible = "snps,dw-apb-uart"; 801 reg = <0xffc02000 0x100>; 802 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; 803 reg-shift = <2>; 804 reg-io-width = <4>; 805 clocks = <&l4_sp_clk>; 806 status = "disabled"; 807 }; 808 809 uart1: serial1@ffc02100 { 810 compatible = "snps,dw-apb-uart"; 811 reg = <0xffc02100 0x100>; 812 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; 813 reg-shift = <2>; 814 reg-io-width = <4>; 815 clocks = <&l4_sp_clk>; 816 status = "disabled"; 817 }; 818 819 usbphy0: usbphy { 820 #phy-cells = <0>; 821 compatible = "usb-nop-xceiv"; 822 status = "okay"; 823 }; 824 825 usb0: usb@ffb00000 { 826 compatible = "snps,dwc2"; 827 reg = <0xffb00000 0xffff>; 828 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; 829 clocks = <&usb_clk>; 830 clock-names = "otg"; 831 resets = <&rst USB0_RESET>; 832 reset-names = "dwc2"; 833 phys = <&usbphy0>; 834 phy-names = "usb2-phy"; 835 status = "disabled"; 836 }; 837 838 usb1: usb@ffb40000 { 839 compatible = "snps,dwc2"; 840 reg = <0xffb40000 0xffff>; 841 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; 842 clocks = <&usb_clk>; 843 clock-names = "otg"; 844 resets = <&rst USB1_RESET>; 845 reset-names = "dwc2"; 846 phys = <&usbphy0>; 847 phy-names = "usb2-phy"; 848 status = "disabled"; 849 }; 850 851 watchdog0: watchdog@ffd00200 { 852 compatible = "snps,dw-wdt"; 853 reg = <0xffd00200 0x100>; 854 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>; 855 clocks = <&l4_sys_free_clk>; 856 status = "disabled"; 857 }; 858 859 watchdog1: watchdog@ffd00300 { 860 compatible = "snps,dw-wdt"; 861 reg = <0xffd00300 0x100>; 862 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; 863 clocks = <&l4_sys_free_clk>; 864 status = "disabled"; 865 }; 866 }; 867}; 868
