1 /*
2 * Copyright © 2006-2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 #ifndef _INTEL_DISPLAY_H_
26 #define _INTEL_DISPLAY_H_
27
28 enum pipe {
29 INVALID_PIPE = -1,
30
31 PIPE_A = 0,
32 PIPE_B,
33 PIPE_C,
34 _PIPE_EDP,
35
36 I915_MAX_PIPES = _PIPE_EDP
37 };
38
39 #define pipe_name(p) ((p) + 'A')
40
41 enum transcoder {
42 TRANSCODER_A = 0,
43 TRANSCODER_B,
44 TRANSCODER_C,
45 TRANSCODER_EDP,
46 TRANSCODER_DSI_A,
47 TRANSCODER_DSI_C,
48
49 I915_MAX_TRANSCODERS
50 };
51
transcoder_name(enum transcoder transcoder)52 static inline const char *transcoder_name(enum transcoder transcoder)
53 {
54 switch (transcoder) {
55 case TRANSCODER_A:
56 return "A";
57 case TRANSCODER_B:
58 return "B";
59 case TRANSCODER_C:
60 return "C";
61 case TRANSCODER_EDP:
62 return "EDP";
63 case TRANSCODER_DSI_A:
64 return "DSI A";
65 case TRANSCODER_DSI_C:
66 return "DSI C";
67 default:
68 return "<invalid>";
69 }
70 }
71
transcoder_is_dsi(enum transcoder transcoder)72 static inline bool transcoder_is_dsi(enum transcoder transcoder)
73 {
74 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
75 }
76
77 /*
78 * Global legacy plane identifier. Valid only for primary/sprite
79 * planes on pre-g4x, and only for primary planes on g4x-bdw.
80 */
81 enum i9xx_plane_id {
82 PLANE_A,
83 PLANE_B,
84 PLANE_C,
85 };
86
87 #define plane_name(p) ((p) + 'A')
88 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
89
90 /*
91 * Per-pipe plane identifier.
92 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
93 * number of planes per CRTC. Not all platforms really have this many planes,
94 * which means some arrays of size I915_MAX_PLANES may have unused entries
95 * between the topmost sprite plane and the cursor plane.
96 *
97 * This is expected to be passed to various register macros
98 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
99 */
100 enum plane_id {
101 PLANE_PRIMARY,
102 PLANE_SPRITE0,
103 PLANE_SPRITE1,
104 PLANE_SPRITE2,
105 PLANE_CURSOR,
106
107 I915_MAX_PLANES,
108 };
109
110 #define for_each_plane_id_on_crtc(__crtc, __p) \
111 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
112 for_each_if((__crtc)->plane_ids_mask & BIT(__p))
113
114 enum port {
115 PORT_NONE = -1,
116
117 PORT_A = 0,
118 PORT_B,
119 PORT_C,
120 PORT_D,
121 PORT_E,
122 PORT_F,
123
124 I915_MAX_PORTS
125 };
126
127 #define port_name(p) ((p) + 'A')
128
129 /*
130 * Ports identifier referenced from other drivers.
131 * Expected to remain stable over time
132 */
port_identifier(enum port port)133 static inline const char *port_identifier(enum port port)
134 {
135 switch (port) {
136 case PORT_A:
137 return "Port A";
138 case PORT_B:
139 return "Port B";
140 case PORT_C:
141 return "Port C";
142 case PORT_D:
143 return "Port D";
144 case PORT_E:
145 return "Port E";
146 case PORT_F:
147 return "Port F";
148 default:
149 return "<invalid>";
150 }
151 }
152
153 enum tc_port {
154 PORT_TC_NONE = -1,
155
156 PORT_TC1 = 0,
157 PORT_TC2,
158 PORT_TC3,
159 PORT_TC4,
160
161 I915_MAX_TC_PORTS
162 };
163
164 enum dpio_channel {
165 DPIO_CH0,
166 DPIO_CH1
167 };
168
169 enum dpio_phy {
170 DPIO_PHY0,
171 DPIO_PHY1,
172 DPIO_PHY2,
173 };
174
175 #define I915_NUM_PHYS_VLV 2
176
177 enum aux_ch {
178 AUX_CH_A,
179 AUX_CH_B,
180 AUX_CH_C,
181 AUX_CH_D,
182 AUX_CH_E, /* ICL+ */
183 AUX_CH_F,
184 };
185
186 #define aux_ch_name(a) ((a) + 'A')
187
188 enum intel_display_power_domain {
189 POWER_DOMAIN_PIPE_A,
190 POWER_DOMAIN_PIPE_B,
191 POWER_DOMAIN_PIPE_C,
192 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
193 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
194 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
195 POWER_DOMAIN_TRANSCODER_A,
196 POWER_DOMAIN_TRANSCODER_B,
197 POWER_DOMAIN_TRANSCODER_C,
198 POWER_DOMAIN_TRANSCODER_EDP,
199 POWER_DOMAIN_TRANSCODER_DSI_A,
200 POWER_DOMAIN_TRANSCODER_DSI_C,
201 POWER_DOMAIN_PORT_DDI_A_LANES,
202 POWER_DOMAIN_PORT_DDI_B_LANES,
203 POWER_DOMAIN_PORT_DDI_C_LANES,
204 POWER_DOMAIN_PORT_DDI_D_LANES,
205 POWER_DOMAIN_PORT_DDI_E_LANES,
206 POWER_DOMAIN_PORT_DDI_F_LANES,
207 POWER_DOMAIN_PORT_DDI_A_IO,
208 POWER_DOMAIN_PORT_DDI_B_IO,
209 POWER_DOMAIN_PORT_DDI_C_IO,
210 POWER_DOMAIN_PORT_DDI_D_IO,
211 POWER_DOMAIN_PORT_DDI_E_IO,
212 POWER_DOMAIN_PORT_DDI_F_IO,
213 POWER_DOMAIN_PORT_DSI,
214 POWER_DOMAIN_PORT_CRT,
215 POWER_DOMAIN_PORT_OTHER,
216 POWER_DOMAIN_VGA,
217 POWER_DOMAIN_AUDIO,
218 POWER_DOMAIN_PLLS,
219 POWER_DOMAIN_AUX_A,
220 POWER_DOMAIN_AUX_B,
221 POWER_DOMAIN_AUX_C,
222 POWER_DOMAIN_AUX_D,
223 POWER_DOMAIN_AUX_E,
224 POWER_DOMAIN_AUX_F,
225 POWER_DOMAIN_AUX_IO_A,
226 POWER_DOMAIN_AUX_TBT1,
227 POWER_DOMAIN_AUX_TBT2,
228 POWER_DOMAIN_AUX_TBT3,
229 POWER_DOMAIN_AUX_TBT4,
230 POWER_DOMAIN_GMBUS,
231 POWER_DOMAIN_MODESET,
232 POWER_DOMAIN_GT_IRQ,
233 POWER_DOMAIN_INIT,
234
235 POWER_DOMAIN_NUM,
236 };
237
238 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
239 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
240 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
241 #define POWER_DOMAIN_TRANSCODER(tran) \
242 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
243 (tran) + POWER_DOMAIN_TRANSCODER_A)
244
245 /* Used by dp and fdi links */
246 struct intel_link_m_n {
247 u32 tu;
248 u32 gmch_m;
249 u32 gmch_n;
250 u32 link_m;
251 u32 link_n;
252 };
253
254 #define for_each_pipe(__dev_priv, __p) \
255 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
256
257 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
258 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
259 for_each_if((__mask) & BIT(__p))
260
261 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
262 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \
263 for_each_if ((__mask) & (1 << (__t)))
264
265 #define for_each_universal_plane(__dev_priv, __pipe, __p) \
266 for ((__p) = 0; \
267 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
268 (__p)++)
269
270 #define for_each_sprite(__dev_priv, __p, __s) \
271 for ((__s) = 0; \
272 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
273 (__s)++)
274
275 #define for_each_port_masked(__port, __ports_mask) \
276 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
277 for_each_if((__ports_mask) & BIT(__port))
278
279 #define for_each_crtc(dev, crtc) \
280 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
281
282 #define for_each_intel_plane(dev, intel_plane) \
283 list_for_each_entry(intel_plane, \
284 &(dev)->mode_config.plane_list, \
285 base.head)
286
287 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
288 list_for_each_entry(intel_plane, \
289 &(dev)->mode_config.plane_list, \
290 base.head) \
291 for_each_if((plane_mask) & \
292 drm_plane_mask(&intel_plane->base)))
293
294 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
295 list_for_each_entry(intel_plane, \
296 &(dev)->mode_config.plane_list, \
297 base.head) \
298 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
299
300 #define for_each_intel_crtc(dev, intel_crtc) \
301 list_for_each_entry(intel_crtc, \
302 &(dev)->mode_config.crtc_list, \
303 base.head)
304
305 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
306 list_for_each_entry(intel_crtc, \
307 &(dev)->mode_config.crtc_list, \
308 base.head) \
309 for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base))
310
311 #define for_each_intel_encoder(dev, intel_encoder) \
312 list_for_each_entry(intel_encoder, \
313 &(dev)->mode_config.encoder_list, \
314 base.head)
315
316 #define for_each_intel_dp(dev, intel_encoder) \
317 for_each_intel_encoder(dev, intel_encoder) \
318 for_each_if(intel_encoder_is_dp(intel_encoder))
319
320 #define for_each_intel_connector_iter(intel_connector, iter) \
321 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
322
323 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
324 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
325 for_each_if((intel_encoder)->base.crtc == (__crtc))
326
327 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
328 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
329 for_each_if((intel_connector)->base.encoder == (__encoder))
330
331 #define for_each_power_domain(domain, mask) \
332 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
333 for_each_if(BIT_ULL(domain) & (mask))
334
335 #define for_each_power_well(__dev_priv, __power_well) \
336 for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
337 (__power_well) - (__dev_priv)->power_domains.power_wells < \
338 (__dev_priv)->power_domains.power_well_count; \
339 (__power_well)++)
340
341 #define for_each_power_well_rev(__dev_priv, __power_well) \
342 for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
343 (__dev_priv)->power_domains.power_well_count - 1; \
344 (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
345 (__power_well)--)
346
347 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
348 for_each_power_well(__dev_priv, __power_well) \
349 for_each_if((__power_well)->domains & (__domain_mask))
350
351 #define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
352 for_each_power_well_rev(__dev_priv, __power_well) \
353 for_each_if((__power_well)->domains & (__domain_mask))
354
355 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
356 for ((__i) = 0; \
357 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
358 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
359 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
360 (__i)++) \
361 for_each_if(plane)
362
363 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
364 for ((__i) = 0; \
365 (__i) < (__state)->base.dev->mode_config.num_crtc && \
366 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
367 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
368 (__i)++) \
369 for_each_if(crtc)
370
371 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
372 for ((__i) = 0; \
373 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
374 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
375 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
376 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
377 (__i)++) \
378 for_each_if(plane)
379
380 void intel_link_compute_m_n(int bpp, int nlanes,
381 int pixel_clock, int link_clock,
382 struct intel_link_m_n *m_n,
383 bool reduce_m_n);
384
385 #endif
386
