1 /*
2 * arch/arm/include/asm/cacheflush.h
3 *
4 * Copyright (C) 1999-2002 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10 #ifndef _ASMARM_CACHEFLUSH_H
11 #define _ASMARM_CACHEFLUSH_H
12
13 #include <linux/mm.h>
14
15 #include <asm/glue-cache.h>
16 #include <asm/shmparam.h>
17 #include <asm/cachetype.h>
18 #include <asm/outercache.h>
19
20 #define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
21
22 /*
23 * This flag is used to indicate that the page pointed to by a pte is clean
24 * and does not require cleaning before returning it to the user.
25 */
26 #define PG_dcache_clean PG_arch_1
27
28 /*
29 * MM Cache Management
30 * ===================
31 *
32 * The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
33 * implement these methods.
34 *
35 * Start addresses are inclusive and end addresses are exclusive;
36 * start addresses should be rounded down, end addresses up.
37 *
38 * See Documentation/core-api/cachetlb.rst for more information.
39 * Please note that the implementation of these, and the required
40 * effects are cache-type (VIVT/VIPT/PIPT) specific.
41 *
42 * flush_icache_all()
43 *
44 * Unconditionally clean and invalidate the entire icache.
45 * Currently only needed for cache-v6.S and cache-v7.S, see
46 * __flush_icache_all for the generic implementation.
47 *
48 * flush_kern_all()
49 *
50 * Unconditionally clean and invalidate the entire cache.
51 *
52 * flush_kern_louis()
53 *
54 * Flush data cache levels up to the level of unification
55 * inner shareable and invalidate the I-cache.
56 * Only needed from v7 onwards, falls back to flush_cache_all()
57 * for all other processor versions.
58 *
59 * flush_user_all()
60 *
61 * Clean and invalidate all user space cache entries
62 * before a change of page tables.
63 *
64 * flush_user_range(start, end, flags)
65 *
66 * Clean and invalidate a range of cache entries in the
67 * specified address space before a change of page tables.
68 * - start - user start address (inclusive, page aligned)
69 * - end - user end address (exclusive, page aligned)
70 * - flags - vma->vm_flags field
71 *
72 * coherent_kern_range(start, end)
73 *
74 * Ensure coherency between the Icache and the Dcache in the
75 * region described by start, end. If you have non-snooping
76 * Harvard caches, you need to implement this function.
77 * - start - virtual start address
78 * - end - virtual end address
79 *
80 * coherent_user_range(start, end)
81 *
82 * Ensure coherency between the Icache and the Dcache in the
83 * region described by start, end. If you have non-snooping
84 * Harvard caches, you need to implement this function.
85 * - start - virtual start address
86 * - end - virtual end address
87 *
88 * flush_kern_dcache_area(kaddr, size)
89 *
90 * Ensure that the data held in page is written back.
91 * - kaddr - page address
92 * - size - region size
93 *
94 * DMA Cache Coherency
95 * ===================
96 *
97 * dma_flush_range(start, end)
98 *
99 * Clean and invalidate the specified virtual address range.
100 * - start - virtual start address
101 * - end - virtual end address
102 */
103
104 struct cpu_cache_fns {
105 void (*flush_icache_all)(void);
106 void (*flush_kern_all)(void);
107 void (*flush_kern_louis)(void);
108 void (*flush_user_all)(void);
109 void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
110
111 void (*coherent_kern_range)(unsigned long, unsigned long);
112 int (*coherent_user_range)(unsigned long, unsigned long);
113 void (*flush_kern_dcache_area)(void *, size_t);
114
115 void (*dma_map_area)(const void *, size_t, int);
116 void (*dma_unmap_area)(const void *, size_t, int);
117
118 void (*dma_flush_range)(const void *, const void *);
119 } __no_randomize_layout;
120
121 /*
122 * Select the calling method
123 */
124 #ifdef MULTI_CACHE
125
126 extern struct cpu_cache_fns cpu_cache;
127
128 #define __cpuc_flush_icache_all cpu_cache.flush_icache_all
129 #define __cpuc_flush_kern_all cpu_cache.flush_kern_all
130 #define __cpuc_flush_kern_louis cpu_cache.flush_kern_louis
131 #define __cpuc_flush_user_all cpu_cache.flush_user_all
132 #define __cpuc_flush_user_range cpu_cache.flush_user_range
133 #define __cpuc_coherent_kern_range cpu_cache.coherent_kern_range
134 #define __cpuc_coherent_user_range cpu_cache.coherent_user_range
135 #define __cpuc_flush_dcache_area cpu_cache.flush_kern_dcache_area
136
137 /*
138 * These are private to the dma-mapping API. Do not use directly.
139 * Their sole purpose is to ensure that data held in the cache
140 * is visible to DMA, or data written by DMA to system memory is
141 * visible to the CPU.
142 */
143 #define dmac_flush_range cpu_cache.dma_flush_range
144
145 #else
146
147 extern void __cpuc_flush_icache_all(void);
148 extern void __cpuc_flush_kern_all(void);
149 extern void __cpuc_flush_kern_louis(void);
150 extern void __cpuc_flush_user_all(void);
151 extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
152 extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
153 extern int __cpuc_coherent_user_range(unsigned long, unsigned long);
154 extern void __cpuc_flush_dcache_area(void *, size_t);
155
156 /*
157 * These are private to the dma-mapping API. Do not use directly.
158 * Their sole purpose is to ensure that data held in the cache
159 * is visible to DMA, or data written by DMA to system memory is
160 * visible to the CPU.
161 */
162 extern void dmac_flush_range(const void *, const void *);
163
164 #endif
165
166 /*
167 * Copy user data from/to a page which is mapped into a different
168 * processes address space. Really, we want to allow our "user
169 * space" model to handle this.
170 */
171 extern void copy_to_user_page(struct vm_area_struct *, struct page *,
172 unsigned long, void *, const void *, unsigned long);
173 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
174 do { \
175 memcpy(dst, src, len); \
176 } while (0)
177
178 /*
179 * Convert calls to our calling convention.
180 */
181
182 /* Invalidate I-cache */
183 #define __flush_icache_all_generic() \
184 asm("mcr p15, 0, %0, c7, c5, 0" \
185 : : "r" (0));
186
187 /* Invalidate I-cache inner shareable */
188 #define __flush_icache_all_v7_smp() \
189 asm("mcr p15, 0, %0, c7, c1, 0" \
190 : : "r" (0));
191
192 /*
193 * Optimized __flush_icache_all for the common cases. Note that UP ARMv7
194 * will fall through to use __flush_icache_all_generic.
195 */
196 #if (defined(CONFIG_CPU_V7) && \
197 (defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K))) || \
198 defined(CONFIG_SMP_ON_UP)
199 #define __flush_icache_preferred __cpuc_flush_icache_all
200 #elif __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP)
201 #define __flush_icache_preferred __flush_icache_all_v7_smp
202 #elif __LINUX_ARM_ARCH__ == 6 && defined(CONFIG_ARM_ERRATA_411920)
203 #define __flush_icache_preferred __cpuc_flush_icache_all
204 #else
205 #define __flush_icache_preferred __flush_icache_all_generic
206 #endif
207
__flush_icache_all(void)208 static inline void __flush_icache_all(void)
209 {
210 __flush_icache_preferred();
211 dsb(ishst);
212 }
213
214 /*
215 * Flush caches up to Level of Unification Inner Shareable
216 */
217 #define flush_cache_louis() __cpuc_flush_kern_louis()
218
219 #define flush_cache_all() __cpuc_flush_kern_all()
220
vivt_flush_cache_mm(struct mm_struct * mm)221 static inline void vivt_flush_cache_mm(struct mm_struct *mm)
222 {
223 if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm)))
224 __cpuc_flush_user_all();
225 }
226
227 static inline void
vivt_flush_cache_range(struct vm_area_struct * vma,unsigned long start,unsigned long end)228 vivt_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
229 {
230 struct mm_struct *mm = vma->vm_mm;
231
232 if (!mm || cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm)))
233 __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
234 vma->vm_flags);
235 }
236
237 static inline void
vivt_flush_cache_page(struct vm_area_struct * vma,unsigned long user_addr,unsigned long pfn)238 vivt_flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
239 {
240 struct mm_struct *mm = vma->vm_mm;
241
242 if (!mm || cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm))) {
243 unsigned long addr = user_addr & PAGE_MASK;
244 __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
245 }
246 }
247
248 #ifndef CONFIG_CPU_CACHE_VIPT
249 #define flush_cache_mm(mm) \
250 vivt_flush_cache_mm(mm)
251 #define flush_cache_range(vma,start,end) \
252 vivt_flush_cache_range(vma,start,end)
253 #define flush_cache_page(vma,addr,pfn) \
254 vivt_flush_cache_page(vma,addr,pfn)
255 #else
256 extern void flush_cache_mm(struct mm_struct *mm);
257 extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
258 extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
259 #endif
260
261 #define flush_cache_dup_mm(mm) flush_cache_mm(mm)
262
263 /*
264 * flush_cache_user_range is used when we want to ensure that the
265 * Harvard caches are synchronised for the user space address range.
266 * This is used for the ARM private sys_cacheflush system call.
267 */
268 #define flush_cache_user_range(s,e) __cpuc_coherent_user_range(s,e)
269
270 /*
271 * Perform necessary cache operations to ensure that data previously
272 * stored within this range of addresses can be executed by the CPU.
273 */
274 #define flush_icache_range(s,e) __cpuc_coherent_kern_range(s,e)
275
276 /*
277 * Perform necessary cache operations to ensure that the TLB will
278 * see data written in the specified area.
279 */
280 #define clean_dcache_area(start,size) cpu_dcache_clean_area(start, size)
281
282 /*
283 * flush_dcache_page is used when the kernel has written to the page
284 * cache page at virtual address page->virtual.
285 *
286 * If this page isn't mapped (ie, page_mapping == NULL), or it might
287 * have userspace mappings, then we _must_ always clean + invalidate
288 * the dcache entries associated with the kernel mapping.
289 *
290 * Otherwise we can defer the operation, and clean the cache when we are
291 * about to change to user space. This is the same method as used on SPARC64.
292 * See update_mmu_cache for the user space part.
293 */
294 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
295 extern void flush_dcache_page(struct page *);
296
flush_kernel_vmap_range(void * addr,int size)297 static inline void flush_kernel_vmap_range(void *addr, int size)
298 {
299 if ((cache_is_vivt() || cache_is_vipt_aliasing()))
300 __cpuc_flush_dcache_area(addr, (size_t)size);
301 }
invalidate_kernel_vmap_range(void * addr,int size)302 static inline void invalidate_kernel_vmap_range(void *addr, int size)
303 {
304 if ((cache_is_vivt() || cache_is_vipt_aliasing()))
305 __cpuc_flush_dcache_area(addr, (size_t)size);
306 }
307
308 #define ARCH_HAS_FLUSH_ANON_PAGE
flush_anon_page(struct vm_area_struct * vma,struct page * page,unsigned long vmaddr)309 static inline void flush_anon_page(struct vm_area_struct *vma,
310 struct page *page, unsigned long vmaddr)
311 {
312 extern void __flush_anon_page(struct vm_area_struct *vma,
313 struct page *, unsigned long);
314 if (PageAnon(page))
315 __flush_anon_page(vma, page, vmaddr);
316 }
317
318 #define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
319 extern void flush_kernel_dcache_page(struct page *);
320
321 #define flush_dcache_mmap_lock(mapping) xa_lock_irq(&mapping->i_pages)
322 #define flush_dcache_mmap_unlock(mapping) xa_unlock_irq(&mapping->i_pages)
323
324 #define flush_icache_user_range(vma,page,addr,len) \
325 flush_dcache_page(page)
326
327 /*
328 * We don't appear to need to do anything here. In fact, if we did, we'd
329 * duplicate cache flushing elsewhere performed by flush_dcache_page().
330 */
331 #define flush_icache_page(vma,page) do { } while (0)
332
333 /*
334 * flush_cache_vmap() is used when creating mappings (eg, via vmap,
335 * vmalloc, ioremap etc) in kernel space for pages. On non-VIPT
336 * caches, since the direct-mappings of these pages may contain cached
337 * data, we need to do a full cache flush to ensure that writebacks
338 * don't corrupt data placed into these pages via the new mappings.
339 */
flush_cache_vmap(unsigned long start,unsigned long end)340 static inline void flush_cache_vmap(unsigned long start, unsigned long end)
341 {
342 if (!cache_is_vipt_nonaliasing())
343 flush_cache_all();
344 else
345 /*
346 * set_pte_at() called from vmap_pte_range() does not
347 * have a DSB after cleaning the cache line.
348 */
349 dsb(ishst);
350 }
351
flush_cache_vunmap(unsigned long start,unsigned long end)352 static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
353 {
354 if (!cache_is_vipt_nonaliasing())
355 flush_cache_all();
356 }
357
358 /*
359 * Memory synchronization helpers for mixed cached vs non cached accesses.
360 *
361 * Some synchronization algorithms have to set states in memory with the
362 * cache enabled or disabled depending on the code path. It is crucial
363 * to always ensure proper cache maintenance to update main memory right
364 * away in that case.
365 *
366 * Any cached write must be followed by a cache clean operation.
367 * Any cached read must be preceded by a cache invalidate operation.
368 * Yet, in the read case, a cache flush i.e. atomic clean+invalidate
369 * operation is needed to avoid discarding possible concurrent writes to the
370 * accessed memory.
371 *
372 * Also, in order to prevent a cached writer from interfering with an
373 * adjacent non-cached writer, each state variable must be located to
374 * a separate cache line.
375 */
376
377 /*
378 * This needs to be >= the max cache writeback size of all
379 * supported platforms included in the current kernel configuration.
380 * This is used to align state variables to their own cache lines.
381 */
382 #define __CACHE_WRITEBACK_ORDER 6 /* guessed from existing platforms */
383 #define __CACHE_WRITEBACK_GRANULE (1 << __CACHE_WRITEBACK_ORDER)
384
385 /*
386 * There is no __cpuc_clean_dcache_area but we use it anyway for
387 * code intent clarity, and alias it to __cpuc_flush_dcache_area.
388 */
389 #define __cpuc_clean_dcache_area __cpuc_flush_dcache_area
390
391 /*
392 * Ensure preceding writes to *p by this CPU are visible to
393 * subsequent reads by other CPUs:
394 */
__sync_cache_range_w(volatile void * p,size_t size)395 static inline void __sync_cache_range_w(volatile void *p, size_t size)
396 {
397 char *_p = (char *)p;
398
399 __cpuc_clean_dcache_area(_p, size);
400 outer_clean_range(__pa(_p), __pa(_p + size));
401 }
402
403 /*
404 * Ensure preceding writes to *p by other CPUs are visible to
405 * subsequent reads by this CPU. We must be careful not to
406 * discard data simultaneously written by another CPU, hence the
407 * usage of flush rather than invalidate operations.
408 */
__sync_cache_range_r(volatile void * p,size_t size)409 static inline void __sync_cache_range_r(volatile void *p, size_t size)
410 {
411 char *_p = (char *)p;
412
413 #ifdef CONFIG_OUTER_CACHE
414 if (outer_cache.flush_range) {
415 /*
416 * Ensure dirty data migrated from other CPUs into our cache
417 * are cleaned out safely before the outer cache is cleaned:
418 */
419 __cpuc_clean_dcache_area(_p, size);
420
421 /* Clean and invalidate stale data for *p from outer ... */
422 outer_flush_range(__pa(_p), __pa(_p + size));
423 }
424 #endif
425
426 /* ... and inner cache: */
427 __cpuc_flush_dcache_area(_p, size);
428 }
429
430 #define sync_cache_w(ptr) __sync_cache_range_w(ptr, sizeof *(ptr))
431 #define sync_cache_r(ptr) __sync_cache_range_r(ptr, sizeof *(ptr))
432
433 /*
434 * Disabling cache access for one CPU in an ARMv7 SMP system is tricky.
435 * To do so we must:
436 *
437 * - Clear the SCTLR.C bit to prevent further cache allocations
438 * - Flush the desired level of cache
439 * - Clear the ACTLR "SMP" bit to disable local coherency
440 *
441 * ... and so without any intervening memory access in between those steps,
442 * not even to the stack.
443 *
444 * WARNING -- After this has been called:
445 *
446 * - No ldrex/strex (and similar) instructions must be used.
447 * - The CPU is obviously no longer coherent with the other CPUs.
448 * - This is unlikely to work as expected if Linux is running non-secure.
449 *
450 * Note:
451 *
452 * - This is known to apply to several ARMv7 processor implementations,
453 * however some exceptions may exist. Caveat emptor.
454 *
455 * - The clobber list is dictated by the call to v7_flush_dcache_*.
456 * fp is preserved to the stack explicitly prior disabling the cache
457 * since adding it to the clobber list is incompatible with having
458 * CONFIG_FRAME_POINTER=y. ip is saved as well if ever r12-clobbering
459 * trampoline are inserted by the linker and to keep sp 64-bit aligned.
460 */
461 #define v7_exit_coherency_flush(level) \
462 asm volatile( \
463 ".arch armv7-a \n\t" \
464 "stmfd sp!, {fp, ip} \n\t" \
465 "mrc p15, 0, r0, c1, c0, 0 @ get SCTLR \n\t" \
466 "bic r0, r0, #"__stringify(CR_C)" \n\t" \
467 "mcr p15, 0, r0, c1, c0, 0 @ set SCTLR \n\t" \
468 "isb \n\t" \
469 "bl v7_flush_dcache_"__stringify(level)" \n\t" \
470 "mrc p15, 0, r0, c1, c0, 1 @ get ACTLR \n\t" \
471 "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" \
472 "mcr p15, 0, r0, c1, c0, 1 @ set ACTLR \n\t" \
473 "isb \n\t" \
474 "dsb \n\t" \
475 "ldmfd sp!, {fp, ip}" \
476 : : : "r0","r1","r2","r3","r4","r5","r6","r7", \
477 "r9","r10","lr","memory" )
478
479 void flush_uprobe_xol_access(struct page *page, unsigned long uaddr,
480 void *kaddr, unsigned long len);
481
482 #endif
483
