1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "core_types.h"
28
29 #include "ObjectID.h"
30 #include "atomfirmware.h"
31
32 #include "dc_bios_types.h"
33 #include "include/grph_object_ctrl_defs.h"
34 #include "include/bios_parser_interface.h"
35 #include "include/i2caux_interface.h"
36 #include "include/logger_interface.h"
37
38 #include "command_table2.h"
39
40 #include "bios_parser_helper.h"
41 #include "command_table_helper2.h"
42 #include "bios_parser2.h"
43 #include "bios_parser_types_internal2.h"
44 #include "bios_parser_interface.h"
45
46 #include "bios_parser_common.h"
47
48 #define DC_LOGGER \
49 bp->base.ctx->logger
50
51 #define LAST_RECORD_TYPE 0xff
52 #define SMU9_SYSPLL0_ID 0
53
54 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp,
55 struct atom_i2c_record *record,
56 struct graphics_object_i2c_info *info);
57
58 static enum bp_result bios_parser_get_firmware_info(
59 struct dc_bios *dcb,
60 struct dc_firmware_info *info);
61
62 static enum bp_result bios_parser_get_encoder_cap_info(
63 struct dc_bios *dcb,
64 struct graphics_object_id object_id,
65 struct bp_encoder_cap_info *info);
66
67 static enum bp_result get_firmware_info_v3_1(
68 struct bios_parser *bp,
69 struct dc_firmware_info *info);
70
71 static enum bp_result get_firmware_info_v3_2(
72 struct bios_parser *bp,
73 struct dc_firmware_info *info);
74
75 static enum bp_result get_firmware_info_v3_4(
76 struct bios_parser *bp,
77 struct dc_firmware_info *info);
78
79 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp,
80 struct atom_display_object_path_v2 *object);
81
82 static struct atom_encoder_caps_record *get_encoder_cap_record(
83 struct bios_parser *bp,
84 struct atom_display_object_path_v2 *object);
85
86 #define BIOS_IMAGE_SIZE_OFFSET 2
87 #define BIOS_IMAGE_SIZE_UNIT 512
88
89 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table)
90
bios_parser2_destruct(struct bios_parser * bp)91 static void bios_parser2_destruct(struct bios_parser *bp)
92 {
93 kfree(bp->base.bios_local_image);
94 kfree(bp->base.integrated_info);
95 }
96
firmware_parser_destroy(struct dc_bios ** dcb)97 static void firmware_parser_destroy(struct dc_bios **dcb)
98 {
99 struct bios_parser *bp = BP_FROM_DCB(*dcb);
100
101 if (!bp) {
102 BREAK_TO_DEBUGGER();
103 return;
104 }
105
106 bios_parser2_destruct(bp);
107
108 kfree(bp);
109 *dcb = NULL;
110 }
111
get_atom_data_table_revision(struct atom_common_table_header * atom_data_tbl,struct atom_data_revision * tbl_revision)112 static void get_atom_data_table_revision(
113 struct atom_common_table_header *atom_data_tbl,
114 struct atom_data_revision *tbl_revision)
115 {
116 if (!tbl_revision)
117 return;
118
119 /* initialize the revision to 0 which is invalid revision */
120 tbl_revision->major = 0;
121 tbl_revision->minor = 0;
122
123 if (!atom_data_tbl)
124 return;
125
126 tbl_revision->major =
127 (uint32_t) atom_data_tbl->format_revision & 0x3f;
128 tbl_revision->minor =
129 (uint32_t) atom_data_tbl->content_revision & 0x3f;
130 }
131
132 /* BIOS oject table displaypath is per connector.
133 * There is extra path not for connector. BIOS fill its encoderid as 0
134 */
bios_parser_get_connectors_number(struct dc_bios * dcb)135 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb)
136 {
137 struct bios_parser *bp = BP_FROM_DCB(dcb);
138 unsigned int count = 0;
139 unsigned int i;
140
141 switch (bp->object_info_tbl.revision.minor) {
142 default:
143 case 4:
144 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++)
145 if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0)
146 count++;
147
148 break;
149
150 case 5:
151 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++)
152 if (bp->object_info_tbl.v1_5->display_path[i].encoderobjid != 0)
153 count++;
154
155 break;
156 }
157 return count;
158 }
159
bios_parser_get_connector_id(struct dc_bios * dcb,uint8_t i)160 static struct graphics_object_id bios_parser_get_connector_id(
161 struct dc_bios *dcb,
162 uint8_t i)
163 {
164 struct bios_parser *bp = BP_FROM_DCB(dcb);
165 struct graphics_object_id object_id = dal_graphics_object_id_init(
166 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN);
167 struct object_info_table *tbl = &bp->object_info_tbl;
168 struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4;
169
170 struct display_object_info_table_v1_5 *v1_5 = tbl->v1_5;
171
172 switch (bp->object_info_tbl.revision.minor) {
173 default:
174 case 4:
175 if (v1_4->number_of_path > i) {
176 /* If display_objid is generic object id, the encoderObj
177 * /extencoderobjId should be 0
178 */
179 if (v1_4->display_path[i].encoderobjid != 0 &&
180 v1_4->display_path[i].display_objid != 0)
181 object_id = object_id_from_bios_object_id(
182 v1_4->display_path[i].display_objid);
183 }
184 break;
185
186 case 5:
187 if (v1_5->number_of_path > i) {
188 /* If display_objid is generic object id, the encoderObjId
189 * should be 0
190 */
191 if (v1_5->display_path[i].encoderobjid != 0 &&
192 v1_5->display_path[i].display_objid != 0)
193 object_id = object_id_from_bios_object_id(
194 v1_5->display_path[i].display_objid);
195 }
196 break;
197 }
198 return object_id;
199 }
200
bios_parser_get_src_obj(struct dc_bios * dcb,struct graphics_object_id object_id,uint32_t index,struct graphics_object_id * src_object_id)201 static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb,
202 struct graphics_object_id object_id, uint32_t index,
203 struct graphics_object_id *src_object_id)
204 {
205 struct bios_parser *bp = BP_FROM_DCB(dcb);
206 unsigned int i;
207 enum bp_result bp_result = BP_RESULT_BADINPUT;
208 struct graphics_object_id obj_id = { 0 };
209 struct object_info_table *tbl = &bp->object_info_tbl;
210
211 if (!src_object_id)
212 return bp_result;
213
214 switch (object_id.type) {
215 /* Encoder's Source is GPU. BIOS does not provide GPU, since all
216 * displaypaths point to same GPU (0x1100). Hardcode GPU object type
217 */
218 case OBJECT_TYPE_ENCODER:
219 /* TODO: since num of src must be less than 2.
220 * If found in for loop, should break.
221 * DAL2 implementation may be changed too
222 */
223 switch (bp->object_info_tbl.revision.minor) {
224 default:
225 case 4:
226 for (i = 0; i < tbl->v1_4->number_of_path; i++) {
227 obj_id = object_id_from_bios_object_id(
228 tbl->v1_4->display_path[i].encoderobjid);
229 if (object_id.type == obj_id.type &&
230 object_id.id == obj_id.id &&
231 object_id.enum_id == obj_id.enum_id) {
232 *src_object_id =
233 object_id_from_bios_object_id(
234 0x1100);
235 /* break; */
236 }
237 }
238 bp_result = BP_RESULT_OK;
239 break;
240
241 case 5:
242 for (i = 0; i < tbl->v1_5->number_of_path; i++) {
243 obj_id = object_id_from_bios_object_id(
244 tbl->v1_5->display_path[i].encoderobjid);
245 if (object_id.type == obj_id.type &&
246 object_id.id == obj_id.id &&
247 object_id.enum_id == obj_id.enum_id) {
248 *src_object_id =
249 object_id_from_bios_object_id(
250 0x1100);
251 /* break; */
252 }
253 }
254 bp_result = BP_RESULT_OK;
255 break;
256 }
257 break;
258 case OBJECT_TYPE_CONNECTOR:
259 switch (bp->object_info_tbl.revision.minor) {
260 default:
261 case 4:
262 for (i = 0; i < tbl->v1_4->number_of_path; i++) {
263 obj_id = object_id_from_bios_object_id(
264 tbl->v1_4->display_path[i]
265 .display_objid);
266
267 if (object_id.type == obj_id.type &&
268 object_id.id == obj_id.id &&
269 object_id.enum_id == obj_id.enum_id) {
270 *src_object_id =
271 object_id_from_bios_object_id(
272 tbl->v1_4
273 ->display_path[i]
274 .encoderobjid);
275 /* break; */
276 }
277 }
278 bp_result = BP_RESULT_OK;
279 break;
280 }
281 bp_result = BP_RESULT_OK;
282 break;
283 case 5:
284 for (i = 0; i < tbl->v1_5->number_of_path; i++) {
285 obj_id = object_id_from_bios_object_id(
286 tbl->v1_5->display_path[i].display_objid);
287
288 if (object_id.type == obj_id.type &&
289 object_id.id == obj_id.id &&
290 object_id.enum_id == obj_id.enum_id) {
291 *src_object_id = object_id_from_bios_object_id(
292 tbl->v1_5->display_path[i].encoderobjid);
293 /* break; */
294 }
295 }
296 bp_result = BP_RESULT_OK;
297 break;
298
299 default:
300 bp_result = BP_RESULT_OK;
301 break;
302 }
303
304 return bp_result;
305 }
306
307 /* from graphics_object_id, find display path which includes the object_id */
get_bios_object(struct bios_parser * bp,struct graphics_object_id id)308 static struct atom_display_object_path_v2 *get_bios_object(
309 struct bios_parser *bp,
310 struct graphics_object_id id)
311 {
312 unsigned int i;
313 struct graphics_object_id obj_id = {0};
314
315 switch (id.type) {
316 case OBJECT_TYPE_ENCODER:
317 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
318 obj_id = object_id_from_bios_object_id(
319 bp->object_info_tbl.v1_4->display_path[i].encoderobjid);
320 if (id.type == obj_id.type && id.id == obj_id.id
321 && id.enum_id == obj_id.enum_id)
322 return &bp->object_info_tbl.v1_4->display_path[i];
323 }
324 fallthrough;
325 case OBJECT_TYPE_CONNECTOR:
326 case OBJECT_TYPE_GENERIC:
327 /* Both Generic and Connector Object ID
328 * will be stored on display_objid
329 */
330 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
331 obj_id = object_id_from_bios_object_id(
332 bp->object_info_tbl.v1_4->display_path[i].display_objid);
333 if (id.type == obj_id.type && id.id == obj_id.id
334 && id.enum_id == obj_id.enum_id)
335 return &bp->object_info_tbl.v1_4->display_path[i];
336 }
337 fallthrough;
338 default:
339 return NULL;
340 }
341 }
342
343 /* from graphics_object_id, find display path which includes the object_id */
get_bios_object_from_path_v3(struct bios_parser * bp,struct graphics_object_id id)344 static struct atom_display_object_path_v3 *get_bios_object_from_path_v3(
345 struct bios_parser *bp,
346 struct graphics_object_id id)
347 {
348 unsigned int i;
349 struct graphics_object_id obj_id = {0};
350
351 switch (id.type) {
352 case OBJECT_TYPE_ENCODER:
353 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) {
354 obj_id = object_id_from_bios_object_id(
355 bp->object_info_tbl.v1_5->display_path[i].encoderobjid);
356 if (id.type == obj_id.type && id.id == obj_id.id
357 && id.enum_id == obj_id.enum_id)
358 return &bp->object_info_tbl.v1_5->display_path[i];
359 }
360 break;
361
362 case OBJECT_TYPE_CONNECTOR:
363 case OBJECT_TYPE_GENERIC:
364 /* Both Generic and Connector Object ID
365 * will be stored on display_objid
366 */
367 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) {
368 obj_id = object_id_from_bios_object_id(
369 bp->object_info_tbl.v1_5->display_path[i].display_objid);
370 if (id.type == obj_id.type && id.id == obj_id.id
371 && id.enum_id == obj_id.enum_id)
372 return &bp->object_info_tbl.v1_5->display_path[i];
373 }
374 break;
375
376 default:
377 return NULL;
378 }
379
380 return NULL;
381 }
382
bios_parser_get_i2c_info(struct dc_bios * dcb,struct graphics_object_id id,struct graphics_object_i2c_info * info)383 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb,
384 struct graphics_object_id id,
385 struct graphics_object_i2c_info *info)
386 {
387 uint32_t offset;
388 struct atom_display_object_path_v2 *object;
389
390 struct atom_display_object_path_v3 *object_path_v3;
391
392 struct atom_common_record_header *header;
393 struct atom_i2c_record *record;
394 struct atom_i2c_record dummy_record = {0};
395 struct bios_parser *bp = BP_FROM_DCB(dcb);
396
397 if (!info)
398 return BP_RESULT_BADINPUT;
399
400 if (id.type == OBJECT_TYPE_GENERIC) {
401 dummy_record.i2c_id = id.id;
402
403 if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK)
404 return BP_RESULT_OK;
405 else
406 return BP_RESULT_NORECORD;
407 }
408
409 switch (bp->object_info_tbl.revision.minor) {
410 case 4:
411 default:
412 object = get_bios_object(bp, id);
413
414 if (!object)
415 return BP_RESULT_BADINPUT;
416
417 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
418 break;
419 case 5:
420 object_path_v3 = get_bios_object_from_path_v3(bp, id);
421
422 if (!object_path_v3)
423 return BP_RESULT_BADINPUT;
424
425 offset = object_path_v3->disp_recordoffset + bp->object_info_tbl_offset;
426 break;
427 }
428
429 for (;;) {
430 header = GET_IMAGE(struct atom_common_record_header, offset);
431
432 if (!header)
433 return BP_RESULT_BADBIOSTABLE;
434
435 if (header->record_type == LAST_RECORD_TYPE ||
436 !header->record_size)
437 break;
438
439 if (header->record_type == ATOM_I2C_RECORD_TYPE
440 && sizeof(struct atom_i2c_record) <=
441 header->record_size) {
442 /* get the I2C info */
443 record = (struct atom_i2c_record *) header;
444
445 if (get_gpio_i2c_info(bp, record, info) ==
446 BP_RESULT_OK)
447 return BP_RESULT_OK;
448 }
449
450 offset += header->record_size;
451 }
452
453 return BP_RESULT_NORECORD;
454 }
455
get_gpio_i2c_info(struct bios_parser * bp,struct atom_i2c_record * record,struct graphics_object_i2c_info * info)456 static enum bp_result get_gpio_i2c_info(
457 struct bios_parser *bp,
458 struct atom_i2c_record *record,
459 struct graphics_object_i2c_info *info)
460 {
461 struct atom_gpio_pin_lut_v2_1 *header;
462 uint32_t count = 0;
463 unsigned int table_index = 0;
464 bool find_valid = false;
465
466 if (!info)
467 return BP_RESULT_BADINPUT;
468
469 /* get the GPIO_I2C info */
470 if (!DATA_TABLES(gpio_pin_lut))
471 return BP_RESULT_BADBIOSTABLE;
472
473 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1,
474 DATA_TABLES(gpio_pin_lut));
475 if (!header)
476 return BP_RESULT_BADBIOSTABLE;
477
478 if (sizeof(struct atom_common_table_header) +
479 sizeof(struct atom_gpio_pin_assignment) >
480 le16_to_cpu(header->table_header.structuresize))
481 return BP_RESULT_BADBIOSTABLE;
482
483 /* TODO: is version change? */
484 if (header->table_header.content_revision != 1)
485 return BP_RESULT_UNSUPPORTED;
486
487 /* get data count */
488 count = (le16_to_cpu(header->table_header.structuresize)
489 - sizeof(struct atom_common_table_header))
490 / sizeof(struct atom_gpio_pin_assignment);
491
492 for (table_index = 0; table_index < count; table_index++) {
493 if (((record->i2c_id & I2C_HW_CAP) == (
494 header->gpio_pin[table_index].gpio_id &
495 I2C_HW_CAP)) &&
496 ((record->i2c_id & I2C_HW_ENGINE_ID_MASK) ==
497 (header->gpio_pin[table_index].gpio_id &
498 I2C_HW_ENGINE_ID_MASK)) &&
499 ((record->i2c_id & I2C_HW_LANE_MUX) ==
500 (header->gpio_pin[table_index].gpio_id &
501 I2C_HW_LANE_MUX))) {
502 /* still valid */
503 find_valid = true;
504 break;
505 }
506 }
507
508 /* If we don't find the entry that we are looking for then
509 * we will return BP_Result_BadBiosTable.
510 */
511 if (find_valid == false)
512 return BP_RESULT_BADBIOSTABLE;
513
514 /* get the GPIO_I2C_INFO */
515 info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false;
516 info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX;
517 info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4;
518 info->i2c_slave_address = record->i2c_slave_addr;
519
520 /* TODO: check how to get register offset for en, Y, etc. */
521 info->gpio_info.clk_a_register_index =
522 le16_to_cpu(
523 header->gpio_pin[table_index].data_a_reg_index);
524 info->gpio_info.clk_a_shift =
525 header->gpio_pin[table_index].gpio_bitshift;
526
527 return BP_RESULT_OK;
528 }
529
get_hpd_record_for_path_v3(struct bios_parser * bp,struct atom_display_object_path_v3 * object)530 static struct atom_hpd_int_record *get_hpd_record_for_path_v3(
531 struct bios_parser *bp,
532 struct atom_display_object_path_v3 *object)
533 {
534 struct atom_common_record_header *header;
535 uint32_t offset;
536
537 if (!object) {
538 BREAK_TO_DEBUGGER(); /* Invalid object */
539 return NULL;
540 }
541
542 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
543
544 for (;;) {
545 header = GET_IMAGE(struct atom_common_record_header, offset);
546
547 if (!header)
548 return NULL;
549
550 if (header->record_type == ATOM_RECORD_END_TYPE ||
551 !header->record_size)
552 break;
553
554 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE
555 && sizeof(struct atom_hpd_int_record) <=
556 header->record_size)
557 return (struct atom_hpd_int_record *) header;
558
559 offset += header->record_size;
560 }
561
562 return NULL;
563 }
564
bios_parser_get_hpd_info(struct dc_bios * dcb,struct graphics_object_id id,struct graphics_object_hpd_info * info)565 static enum bp_result bios_parser_get_hpd_info(
566 struct dc_bios *dcb,
567 struct graphics_object_id id,
568 struct graphics_object_hpd_info *info)
569 {
570 struct bios_parser *bp = BP_FROM_DCB(dcb);
571 struct atom_display_object_path_v2 *object;
572 struct atom_display_object_path_v3 *object_path_v3;
573 struct atom_hpd_int_record *record = NULL;
574
575 if (!info)
576 return BP_RESULT_BADINPUT;
577
578 switch (bp->object_info_tbl.revision.minor) {
579 case 4:
580 default:
581 object = get_bios_object(bp, id);
582
583 if (!object)
584 return BP_RESULT_BADINPUT;
585
586 record = get_hpd_record(bp, object);
587
588 break;
589 case 5:
590 object_path_v3 = get_bios_object_from_path_v3(bp, id);
591
592 if (!object_path_v3)
593 return BP_RESULT_BADINPUT;
594
595 record = get_hpd_record_for_path_v3(bp, object_path_v3);
596 break;
597 }
598
599 if (record != NULL) {
600 info->hpd_int_gpio_uid = record->pin_id;
601 info->hpd_active = record->plugin_pin_state;
602 return BP_RESULT_OK;
603 }
604
605 return BP_RESULT_NORECORD;
606 }
607
get_hpd_record(struct bios_parser * bp,struct atom_display_object_path_v2 * object)608 static struct atom_hpd_int_record *get_hpd_record(
609 struct bios_parser *bp,
610 struct atom_display_object_path_v2 *object)
611 {
612 struct atom_common_record_header *header;
613 uint32_t offset;
614
615 if (!object) {
616 BREAK_TO_DEBUGGER(); /* Invalid object */
617 return NULL;
618 }
619
620 offset = le16_to_cpu(object->disp_recordoffset)
621 + bp->object_info_tbl_offset;
622
623 for (;;) {
624 header = GET_IMAGE(struct atom_common_record_header, offset);
625
626 if (!header)
627 return NULL;
628
629 if (header->record_type == LAST_RECORD_TYPE ||
630 !header->record_size)
631 break;
632
633 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE
634 && sizeof(struct atom_hpd_int_record) <=
635 header->record_size)
636 return (struct atom_hpd_int_record *) header;
637
638 offset += header->record_size;
639 }
640
641 return NULL;
642 }
643
644 /**
645 * bios_parser_get_gpio_pin_info
646 * Get GpioPin information of input gpio id
647 *
648 * @dcb: pointer to the DC BIOS
649 * @gpio_id: GPIO ID
650 * @info: GpioPin information structure
651 * return: Bios parser result code
652 * note:
653 * to get the GPIO PIN INFO, we need:
654 * 1. get the GPIO_ID from other object table, see GetHPDInfo()
655 * 2. in DATA_TABLE.GPIO_Pin_LUT, search all records,
656 * to get the registerA offset/mask
657 */
bios_parser_get_gpio_pin_info(struct dc_bios * dcb,uint32_t gpio_id,struct gpio_pin_info * info)658 static enum bp_result bios_parser_get_gpio_pin_info(
659 struct dc_bios *dcb,
660 uint32_t gpio_id,
661 struct gpio_pin_info *info)
662 {
663 struct bios_parser *bp = BP_FROM_DCB(dcb);
664 struct atom_gpio_pin_lut_v2_1 *header;
665 uint32_t count = 0;
666 uint32_t i = 0;
667
668 if (!DATA_TABLES(gpio_pin_lut))
669 return BP_RESULT_BADBIOSTABLE;
670
671 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1,
672 DATA_TABLES(gpio_pin_lut));
673 if (!header)
674 return BP_RESULT_BADBIOSTABLE;
675
676 if (sizeof(struct atom_common_table_header) +
677 sizeof(struct atom_gpio_pin_assignment)
678 > le16_to_cpu(header->table_header.structuresize))
679 return BP_RESULT_BADBIOSTABLE;
680
681 if (header->table_header.content_revision != 1)
682 return BP_RESULT_UNSUPPORTED;
683
684 /* Temporary hard code gpio pin info */
685 count = (le16_to_cpu(header->table_header.structuresize)
686 - sizeof(struct atom_common_table_header))
687 / sizeof(struct atom_gpio_pin_assignment);
688 for (i = 0; i < count; ++i) {
689 if (header->gpio_pin[i].gpio_id != gpio_id)
690 continue;
691
692 info->offset =
693 (uint32_t) le16_to_cpu(
694 header->gpio_pin[i].data_a_reg_index);
695 info->offset_y = info->offset + 2;
696 info->offset_en = info->offset + 1;
697 info->offset_mask = info->offset - 1;
698
699 info->mask = (uint32_t) (1 <<
700 header->gpio_pin[i].gpio_bitshift);
701 info->mask_y = info->mask + 2;
702 info->mask_en = info->mask + 1;
703 info->mask_mask = info->mask - 1;
704
705 return BP_RESULT_OK;
706 }
707
708 return BP_RESULT_NORECORD;
709 }
710
device_type_from_device_id(uint16_t device_id)711 static struct device_id device_type_from_device_id(uint16_t device_id)
712 {
713
714 struct device_id result_device_id;
715
716 result_device_id.raw_device_tag = device_id;
717
718 switch (device_id) {
719 case ATOM_DISPLAY_LCD1_SUPPORT:
720 result_device_id.device_type = DEVICE_TYPE_LCD;
721 result_device_id.enum_id = 1;
722 break;
723
724 case ATOM_DISPLAY_LCD2_SUPPORT:
725 result_device_id.device_type = DEVICE_TYPE_LCD;
726 result_device_id.enum_id = 2;
727 break;
728
729 case ATOM_DISPLAY_DFP1_SUPPORT:
730 result_device_id.device_type = DEVICE_TYPE_DFP;
731 result_device_id.enum_id = 1;
732 break;
733
734 case ATOM_DISPLAY_DFP2_SUPPORT:
735 result_device_id.device_type = DEVICE_TYPE_DFP;
736 result_device_id.enum_id = 2;
737 break;
738
739 case ATOM_DISPLAY_DFP3_SUPPORT:
740 result_device_id.device_type = DEVICE_TYPE_DFP;
741 result_device_id.enum_id = 3;
742 break;
743
744 case ATOM_DISPLAY_DFP4_SUPPORT:
745 result_device_id.device_type = DEVICE_TYPE_DFP;
746 result_device_id.enum_id = 4;
747 break;
748
749 case ATOM_DISPLAY_DFP5_SUPPORT:
750 result_device_id.device_type = DEVICE_TYPE_DFP;
751 result_device_id.enum_id = 5;
752 break;
753
754 case ATOM_DISPLAY_DFP6_SUPPORT:
755 result_device_id.device_type = DEVICE_TYPE_DFP;
756 result_device_id.enum_id = 6;
757 break;
758
759 default:
760 BREAK_TO_DEBUGGER(); /* Invalid device Id */
761 result_device_id.device_type = DEVICE_TYPE_UNKNOWN;
762 result_device_id.enum_id = 0;
763 }
764 return result_device_id;
765 }
766
bios_parser_get_device_tag(struct dc_bios * dcb,struct graphics_object_id connector_object_id,uint32_t device_tag_index,struct connector_device_tag_info * info)767 static enum bp_result bios_parser_get_device_tag(
768 struct dc_bios *dcb,
769 struct graphics_object_id connector_object_id,
770 uint32_t device_tag_index,
771 struct connector_device_tag_info *info)
772 {
773 struct bios_parser *bp = BP_FROM_DCB(dcb);
774 struct atom_display_object_path_v2 *object;
775
776 struct atom_display_object_path_v3 *object_path_v3;
777
778
779 if (!info)
780 return BP_RESULT_BADINPUT;
781
782 switch (bp->object_info_tbl.revision.minor) {
783 case 4:
784 default:
785 /* getBiosObject will return MXM object */
786 object = get_bios_object(bp, connector_object_id);
787
788 if (!object) {
789 BREAK_TO_DEBUGGER(); /* Invalid object id */
790 return BP_RESULT_BADINPUT;
791 }
792
793 info->acpi_device = 0; /* BIOS no longer provides this */
794 info->dev_id = device_type_from_device_id(object->device_tag);
795 break;
796 case 5:
797 object_path_v3 = get_bios_object_from_path_v3(bp, connector_object_id);
798
799 if (!object_path_v3) {
800 BREAK_TO_DEBUGGER(); /* Invalid object id */
801 return BP_RESULT_BADINPUT;
802 }
803 info->acpi_device = 0; /* BIOS no longer provides this */
804 info->dev_id = device_type_from_device_id(object_path_v3->device_tag);
805 break;
806 }
807
808 return BP_RESULT_OK;
809 }
810
get_ss_info_v4_1(struct bios_parser * bp,uint32_t id,uint32_t index,struct spread_spectrum_info * ss_info)811 static enum bp_result get_ss_info_v4_1(
812 struct bios_parser *bp,
813 uint32_t id,
814 uint32_t index,
815 struct spread_spectrum_info *ss_info)
816 {
817 enum bp_result result = BP_RESULT_OK;
818 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL;
819 struct atom_smu_info_v3_3 *smu_info = NULL;
820
821 if (!ss_info)
822 return BP_RESULT_BADINPUT;
823
824 if (!DATA_TABLES(dce_info))
825 return BP_RESULT_BADBIOSTABLE;
826
827 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1,
828 DATA_TABLES(dce_info));
829 if (!disp_cntl_tbl)
830 return BP_RESULT_BADBIOSTABLE;
831
832
833 ss_info->type.STEP_AND_DELAY_INFO = false;
834 ss_info->spread_percentage_divider = 1000;
835 /* BIOS no longer uses target clock. Always enable for now */
836 ss_info->target_clock_range = 0xffffffff;
837
838 switch (id) {
839 case AS_SIGNAL_TYPE_DVI:
840 ss_info->spread_spectrum_percentage =
841 disp_cntl_tbl->dvi_ss_percentage;
842 ss_info->spread_spectrum_range =
843 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
844 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
845 ss_info->type.CENTER_MODE = true;
846
847 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
848 break;
849 case AS_SIGNAL_TYPE_HDMI:
850 ss_info->spread_spectrum_percentage =
851 disp_cntl_tbl->hdmi_ss_percentage;
852 ss_info->spread_spectrum_range =
853 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
854 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
855 ss_info->type.CENTER_MODE = true;
856
857 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
858 break;
859 /* TODO LVDS not support anymore? */
860 case AS_SIGNAL_TYPE_DISPLAY_PORT:
861 ss_info->spread_spectrum_percentage =
862 disp_cntl_tbl->dp_ss_percentage;
863 ss_info->spread_spectrum_range =
864 disp_cntl_tbl->dp_ss_rate_10hz * 10;
865 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
866 ss_info->type.CENTER_MODE = true;
867
868 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
869 break;
870 case AS_SIGNAL_TYPE_GPU_PLL:
871 /* atom_firmware: DAL only get data from dce_info table.
872 * if data within smu_info is needed for DAL, VBIOS should
873 * copy it into dce_info
874 */
875 result = BP_RESULT_UNSUPPORTED;
876 break;
877 case AS_SIGNAL_TYPE_XGMI:
878 smu_info = GET_IMAGE(struct atom_smu_info_v3_3,
879 DATA_TABLES(smu_info));
880 if (!smu_info)
881 return BP_RESULT_BADBIOSTABLE;
882 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info->gpuclk_ss_percentage);
883 ss_info->spread_spectrum_percentage =
884 smu_info->waflclk_ss_percentage;
885 ss_info->spread_spectrum_range =
886 smu_info->gpuclk_ss_rate_10hz * 10;
887 if (smu_info->waflclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
888 ss_info->type.CENTER_MODE = true;
889
890 DC_LOG_BIOS("AS_SIGNAL_TYPE_XGMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
891 break;
892 default:
893 result = BP_RESULT_UNSUPPORTED;
894 }
895
896 return result;
897 }
898
get_ss_info_v4_2(struct bios_parser * bp,uint32_t id,uint32_t index,struct spread_spectrum_info * ss_info)899 static enum bp_result get_ss_info_v4_2(
900 struct bios_parser *bp,
901 uint32_t id,
902 uint32_t index,
903 struct spread_spectrum_info *ss_info)
904 {
905 enum bp_result result = BP_RESULT_OK;
906 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL;
907 struct atom_smu_info_v3_1 *smu_info = NULL;
908
909 if (!ss_info)
910 return BP_RESULT_BADINPUT;
911
912 if (!DATA_TABLES(dce_info))
913 return BP_RESULT_BADBIOSTABLE;
914
915 if (!DATA_TABLES(smu_info))
916 return BP_RESULT_BADBIOSTABLE;
917
918 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2,
919 DATA_TABLES(dce_info));
920 if (!disp_cntl_tbl)
921 return BP_RESULT_BADBIOSTABLE;
922
923 smu_info = GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info));
924 if (!smu_info)
925 return BP_RESULT_BADBIOSTABLE;
926
927 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info->gpuclk_ss_percentage);
928 ss_info->type.STEP_AND_DELAY_INFO = false;
929 ss_info->spread_percentage_divider = 1000;
930 /* BIOS no longer uses target clock. Always enable for now */
931 ss_info->target_clock_range = 0xffffffff;
932
933 switch (id) {
934 case AS_SIGNAL_TYPE_DVI:
935 ss_info->spread_spectrum_percentage =
936 disp_cntl_tbl->dvi_ss_percentage;
937 ss_info->spread_spectrum_range =
938 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
939 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
940 ss_info->type.CENTER_MODE = true;
941
942 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
943 break;
944 case AS_SIGNAL_TYPE_HDMI:
945 ss_info->spread_spectrum_percentage =
946 disp_cntl_tbl->hdmi_ss_percentage;
947 ss_info->spread_spectrum_range =
948 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
949 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
950 ss_info->type.CENTER_MODE = true;
951
952 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
953 break;
954 /* TODO LVDS not support anymore? */
955 case AS_SIGNAL_TYPE_DISPLAY_PORT:
956 ss_info->spread_spectrum_percentage =
957 smu_info->gpuclk_ss_percentage;
958 ss_info->spread_spectrum_range =
959 smu_info->gpuclk_ss_rate_10hz * 10;
960 if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
961 ss_info->type.CENTER_MODE = true;
962
963 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
964 break;
965 case AS_SIGNAL_TYPE_GPU_PLL:
966 /* atom_firmware: DAL only get data from dce_info table.
967 * if data within smu_info is needed for DAL, VBIOS should
968 * copy it into dce_info
969 */
970 result = BP_RESULT_UNSUPPORTED;
971 break;
972 default:
973 result = BP_RESULT_UNSUPPORTED;
974 }
975
976 return result;
977 }
978
get_ss_info_v4_5(struct bios_parser * bp,uint32_t id,uint32_t index,struct spread_spectrum_info * ss_info)979 static enum bp_result get_ss_info_v4_5(
980 struct bios_parser *bp,
981 uint32_t id,
982 uint32_t index,
983 struct spread_spectrum_info *ss_info)
984 {
985 enum bp_result result = BP_RESULT_OK;
986 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL;
987
988 if (!ss_info)
989 return BP_RESULT_BADINPUT;
990
991 if (!DATA_TABLES(dce_info))
992 return BP_RESULT_BADBIOSTABLE;
993
994 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5,
995 DATA_TABLES(dce_info));
996 if (!disp_cntl_tbl)
997 return BP_RESULT_BADBIOSTABLE;
998
999 ss_info->type.STEP_AND_DELAY_INFO = false;
1000 ss_info->spread_percentage_divider = 1000;
1001 /* BIOS no longer uses target clock. Always enable for now */
1002 ss_info->target_clock_range = 0xffffffff;
1003
1004 switch (id) {
1005 case AS_SIGNAL_TYPE_DVI:
1006 ss_info->spread_spectrum_percentage =
1007 disp_cntl_tbl->dvi_ss_percentage;
1008 ss_info->spread_spectrum_range =
1009 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
1010 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
1011 ss_info->type.CENTER_MODE = true;
1012
1013 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
1014 break;
1015 case AS_SIGNAL_TYPE_HDMI:
1016 ss_info->spread_spectrum_percentage =
1017 disp_cntl_tbl->hdmi_ss_percentage;
1018 ss_info->spread_spectrum_range =
1019 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
1020 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
1021 ss_info->type.CENTER_MODE = true;
1022
1023 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
1024 break;
1025 case AS_SIGNAL_TYPE_DISPLAY_PORT:
1026 ss_info->spread_spectrum_percentage =
1027 disp_cntl_tbl->dp_ss_percentage;
1028 ss_info->spread_spectrum_range =
1029 disp_cntl_tbl->dp_ss_rate_10hz * 10;
1030 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
1031 ss_info->type.CENTER_MODE = true;
1032
1033 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
1034 break;
1035 case AS_SIGNAL_TYPE_GPU_PLL:
1036 /* atom_smu_info_v4_0 does not have fields for SS for SMU Display PLL anymore.
1037 * SMU Display PLL supposed to be without spread.
1038 * Better place for it would be in atom_display_controller_info_v4_5 table.
1039 */
1040 result = BP_RESULT_UNSUPPORTED;
1041 break;
1042 default:
1043 result = BP_RESULT_UNSUPPORTED;
1044 break;
1045 }
1046
1047 return result;
1048 }
1049
1050 /**
1051 * bios_parser_get_spread_spectrum_info
1052 * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or
1053 * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info
1054 * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info
1055 * ver 3.1,
1056 * there is only one entry for each signal /ss id. However, there is
1057 * no planning of supporting multiple spread Sprectum entry for EverGreen
1058 * @dcb: pointer to the DC BIOS
1059 * @signal: ASSignalType to be converted to info index
1060 * @index: number of entries that match the converted info index
1061 * @ss_info: sprectrum information structure,
1062 * return: Bios parser result code
1063 */
bios_parser_get_spread_spectrum_info(struct dc_bios * dcb,enum as_signal_type signal,uint32_t index,struct spread_spectrum_info * ss_info)1064 static enum bp_result bios_parser_get_spread_spectrum_info(
1065 struct dc_bios *dcb,
1066 enum as_signal_type signal,
1067 uint32_t index,
1068 struct spread_spectrum_info *ss_info)
1069 {
1070 struct bios_parser *bp = BP_FROM_DCB(dcb);
1071 enum bp_result result = BP_RESULT_UNSUPPORTED;
1072 struct atom_common_table_header *header;
1073 struct atom_data_revision tbl_revision;
1074
1075 if (!ss_info) /* check for bad input */
1076 return BP_RESULT_BADINPUT;
1077
1078 if (!DATA_TABLES(dce_info))
1079 return BP_RESULT_UNSUPPORTED;
1080
1081 header = GET_IMAGE(struct atom_common_table_header,
1082 DATA_TABLES(dce_info));
1083 get_atom_data_table_revision(header, &tbl_revision);
1084
1085 switch (tbl_revision.major) {
1086 case 4:
1087 switch (tbl_revision.minor) {
1088 case 1:
1089 return get_ss_info_v4_1(bp, signal, index, ss_info);
1090 case 2:
1091 case 3:
1092 case 4:
1093 return get_ss_info_v4_2(bp, signal, index, ss_info);
1094 case 5:
1095 return get_ss_info_v4_5(bp, signal, index, ss_info);
1096
1097 default:
1098 ASSERT(0);
1099 break;
1100 }
1101 break;
1102 default:
1103 break;
1104 }
1105 /* there can not be more then one entry for SS Info table */
1106 return result;
1107 }
1108
get_soc_bb_info_v4_4(struct bios_parser * bp,struct bp_soc_bb_info * soc_bb_info)1109 static enum bp_result get_soc_bb_info_v4_4(
1110 struct bios_parser *bp,
1111 struct bp_soc_bb_info *soc_bb_info)
1112 {
1113 enum bp_result result = BP_RESULT_OK;
1114 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL;
1115
1116 if (!soc_bb_info)
1117 return BP_RESULT_BADINPUT;
1118
1119 if (!DATA_TABLES(dce_info))
1120 return BP_RESULT_BADBIOSTABLE;
1121
1122 if (!DATA_TABLES(smu_info))
1123 return BP_RESULT_BADBIOSTABLE;
1124
1125 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4,
1126 DATA_TABLES(dce_info));
1127 if (!disp_cntl_tbl)
1128 return BP_RESULT_BADBIOSTABLE;
1129
1130 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat;
1131 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat;
1132 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat;
1133
1134 return result;
1135 }
1136
get_soc_bb_info_v4_5(struct bios_parser * bp,struct bp_soc_bb_info * soc_bb_info)1137 static enum bp_result get_soc_bb_info_v4_5(
1138 struct bios_parser *bp,
1139 struct bp_soc_bb_info *soc_bb_info)
1140 {
1141 enum bp_result result = BP_RESULT_OK;
1142 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL;
1143
1144 if (!soc_bb_info)
1145 return BP_RESULT_BADINPUT;
1146
1147 if (!DATA_TABLES(dce_info))
1148 return BP_RESULT_BADBIOSTABLE;
1149
1150 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5,
1151 DATA_TABLES(dce_info));
1152 if (!disp_cntl_tbl)
1153 return BP_RESULT_BADBIOSTABLE;
1154
1155 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat;
1156 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat;
1157 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat;
1158
1159 return result;
1160 }
1161
bios_parser_get_soc_bb_info(struct dc_bios * dcb,struct bp_soc_bb_info * soc_bb_info)1162 static enum bp_result bios_parser_get_soc_bb_info(
1163 struct dc_bios *dcb,
1164 struct bp_soc_bb_info *soc_bb_info)
1165 {
1166 struct bios_parser *bp = BP_FROM_DCB(dcb);
1167 enum bp_result result = BP_RESULT_UNSUPPORTED;
1168 struct atom_common_table_header *header;
1169 struct atom_data_revision tbl_revision;
1170
1171 if (!soc_bb_info) /* check for bad input */
1172 return BP_RESULT_BADINPUT;
1173
1174 if (!DATA_TABLES(dce_info))
1175 return BP_RESULT_UNSUPPORTED;
1176
1177 header = GET_IMAGE(struct atom_common_table_header,
1178 DATA_TABLES(dce_info));
1179 get_atom_data_table_revision(header, &tbl_revision);
1180
1181 switch (tbl_revision.major) {
1182 case 4:
1183 switch (tbl_revision.minor) {
1184 case 1:
1185 case 2:
1186 case 3:
1187 break;
1188 case 4:
1189 result = get_soc_bb_info_v4_4(bp, soc_bb_info);
1190 break;
1191 case 5:
1192 result = get_soc_bb_info_v4_5(bp, soc_bb_info);
1193 break;
1194 default:
1195 break;
1196 }
1197 break;
1198 default:
1199 break;
1200 }
1201
1202 return result;
1203 }
1204
get_disp_caps_v4_1(struct bios_parser * bp,uint8_t * dce_caps)1205 static enum bp_result get_disp_caps_v4_1(
1206 struct bios_parser *bp,
1207 uint8_t *dce_caps)
1208 {
1209 enum bp_result result = BP_RESULT_OK;
1210 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL;
1211
1212 if (!dce_caps)
1213 return BP_RESULT_BADINPUT;
1214
1215 if (!DATA_TABLES(dce_info))
1216 return BP_RESULT_BADBIOSTABLE;
1217
1218 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1,
1219 DATA_TABLES(dce_info));
1220
1221 if (!disp_cntl_tbl)
1222 return BP_RESULT_BADBIOSTABLE;
1223
1224 *dce_caps = disp_cntl_tbl->display_caps;
1225
1226 return result;
1227 }
1228
get_disp_caps_v4_2(struct bios_parser * bp,uint8_t * dce_caps)1229 static enum bp_result get_disp_caps_v4_2(
1230 struct bios_parser *bp,
1231 uint8_t *dce_caps)
1232 {
1233 enum bp_result result = BP_RESULT_OK;
1234 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL;
1235
1236 if (!dce_caps)
1237 return BP_RESULT_BADINPUT;
1238
1239 if (!DATA_TABLES(dce_info))
1240 return BP_RESULT_BADBIOSTABLE;
1241
1242 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2,
1243 DATA_TABLES(dce_info));
1244
1245 if (!disp_cntl_tbl)
1246 return BP_RESULT_BADBIOSTABLE;
1247
1248 *dce_caps = disp_cntl_tbl->display_caps;
1249
1250 return result;
1251 }
1252
get_disp_caps_v4_3(struct bios_parser * bp,uint8_t * dce_caps)1253 static enum bp_result get_disp_caps_v4_3(
1254 struct bios_parser *bp,
1255 uint8_t *dce_caps)
1256 {
1257 enum bp_result result = BP_RESULT_OK;
1258 struct atom_display_controller_info_v4_3 *disp_cntl_tbl = NULL;
1259
1260 if (!dce_caps)
1261 return BP_RESULT_BADINPUT;
1262
1263 if (!DATA_TABLES(dce_info))
1264 return BP_RESULT_BADBIOSTABLE;
1265
1266 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_3,
1267 DATA_TABLES(dce_info));
1268
1269 if (!disp_cntl_tbl)
1270 return BP_RESULT_BADBIOSTABLE;
1271
1272 *dce_caps = disp_cntl_tbl->display_caps;
1273
1274 return result;
1275 }
1276
get_disp_caps_v4_4(struct bios_parser * bp,uint8_t * dce_caps)1277 static enum bp_result get_disp_caps_v4_4(
1278 struct bios_parser *bp,
1279 uint8_t *dce_caps)
1280 {
1281 enum bp_result result = BP_RESULT_OK;
1282 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL;
1283
1284 if (!dce_caps)
1285 return BP_RESULT_BADINPUT;
1286
1287 if (!DATA_TABLES(dce_info))
1288 return BP_RESULT_BADBIOSTABLE;
1289
1290 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4,
1291 DATA_TABLES(dce_info));
1292
1293 if (!disp_cntl_tbl)
1294 return BP_RESULT_BADBIOSTABLE;
1295
1296 *dce_caps = disp_cntl_tbl->display_caps;
1297
1298 return result;
1299 }
1300
get_disp_caps_v4_5(struct bios_parser * bp,uint8_t * dce_caps)1301 static enum bp_result get_disp_caps_v4_5(
1302 struct bios_parser *bp,
1303 uint8_t *dce_caps)
1304 {
1305 enum bp_result result = BP_RESULT_OK;
1306 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL;
1307
1308 if (!dce_caps)
1309 return BP_RESULT_BADINPUT;
1310
1311 if (!DATA_TABLES(dce_info))
1312 return BP_RESULT_BADBIOSTABLE;
1313
1314 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5,
1315 DATA_TABLES(dce_info));
1316
1317 if (!disp_cntl_tbl)
1318 return BP_RESULT_BADBIOSTABLE;
1319
1320 *dce_caps = disp_cntl_tbl->display_caps;
1321
1322 return result;
1323 }
1324
bios_parser_get_lttpr_interop(struct dc_bios * dcb,uint8_t * dce_caps)1325 static enum bp_result bios_parser_get_lttpr_interop(
1326 struct dc_bios *dcb,
1327 uint8_t *dce_caps)
1328 {
1329 struct bios_parser *bp = BP_FROM_DCB(dcb);
1330 enum bp_result result = BP_RESULT_UNSUPPORTED;
1331 struct atom_common_table_header *header;
1332 struct atom_data_revision tbl_revision;
1333
1334 if (!DATA_TABLES(dce_info))
1335 return BP_RESULT_UNSUPPORTED;
1336
1337 header = GET_IMAGE(struct atom_common_table_header,
1338 DATA_TABLES(dce_info));
1339 get_atom_data_table_revision(header, &tbl_revision);
1340 switch (tbl_revision.major) {
1341 case 4:
1342 switch (tbl_revision.minor) {
1343 case 1:
1344 result = get_disp_caps_v4_1(bp, dce_caps);
1345 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
1346 break;
1347 case 2:
1348 result = get_disp_caps_v4_2(bp, dce_caps);
1349 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
1350 break;
1351 case 3:
1352 result = get_disp_caps_v4_3(bp, dce_caps);
1353 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
1354 break;
1355 case 4:
1356 result = get_disp_caps_v4_4(bp, dce_caps);
1357 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
1358 break;
1359 case 5:
1360 result = get_disp_caps_v4_5(bp, dce_caps);
1361 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
1362 break;
1363
1364 default:
1365 break;
1366 }
1367 break;
1368 default:
1369 break;
1370 }
1371 DC_LOG_BIOS("DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE: %d tbl_revision.major = %d tbl_revision.minor = %d\n", *dce_caps, tbl_revision.major, tbl_revision.minor);
1372 return result;
1373 }
1374
bios_parser_get_lttpr_caps(struct dc_bios * dcb,uint8_t * dce_caps)1375 static enum bp_result bios_parser_get_lttpr_caps(
1376 struct dc_bios *dcb,
1377 uint8_t *dce_caps)
1378 {
1379 struct bios_parser *bp = BP_FROM_DCB(dcb);
1380 enum bp_result result = BP_RESULT_UNSUPPORTED;
1381 struct atom_common_table_header *header;
1382 struct atom_data_revision tbl_revision;
1383
1384 if (!DATA_TABLES(dce_info))
1385 return BP_RESULT_UNSUPPORTED;
1386
1387 *dce_caps = 0;
1388 header = GET_IMAGE(struct atom_common_table_header,
1389 DATA_TABLES(dce_info));
1390 get_atom_data_table_revision(header, &tbl_revision);
1391 switch (tbl_revision.major) {
1392 case 4:
1393 switch (tbl_revision.minor) {
1394 case 1:
1395 result = get_disp_caps_v4_1(bp, dce_caps);
1396 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
1397 break;
1398 case 2:
1399 result = get_disp_caps_v4_2(bp, dce_caps);
1400 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
1401 break;
1402 case 3:
1403 result = get_disp_caps_v4_3(bp, dce_caps);
1404 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
1405 break;
1406 case 4:
1407 result = get_disp_caps_v4_4(bp, dce_caps);
1408 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
1409 break;
1410 case 5:
1411 result = get_disp_caps_v4_5(bp, dce_caps);
1412 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
1413 break;
1414 default:
1415 break;
1416 }
1417 break;
1418 default:
1419 break;
1420 }
1421 DC_LOG_BIOS("DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE: %d tbl_revision.major = %d tbl_revision.minor = %d\n", *dce_caps, tbl_revision.major, tbl_revision.minor);
1422 if (dcb->ctx->dc->config.force_bios_enable_lttpr && *dce_caps == 0) {
1423 *dce_caps = 1;
1424 DC_LOG_BIOS("DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE: forced enabled");
1425 }
1426 return result;
1427 }
1428
get_embedded_panel_info_v2_1(struct bios_parser * bp,struct embedded_panel_info * info)1429 static enum bp_result get_embedded_panel_info_v2_1(
1430 struct bios_parser *bp,
1431 struct embedded_panel_info *info)
1432 {
1433 struct lcd_info_v2_1 *lvds;
1434
1435 if (!info)
1436 return BP_RESULT_BADINPUT;
1437
1438 if (!DATA_TABLES(lcd_info))
1439 return BP_RESULT_UNSUPPORTED;
1440
1441 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info));
1442
1443 if (!lvds)
1444 return BP_RESULT_BADBIOSTABLE;
1445
1446 /* TODO: previous vv1_3, should v2_1 */
1447 if (!((lvds->table_header.format_revision == 2)
1448 && (lvds->table_header.content_revision >= 1)))
1449 return BP_RESULT_UNSUPPORTED;
1450
1451 memset(info, 0, sizeof(struct embedded_panel_info));
1452
1453 /* We need to convert from 10KHz units into KHz units */
1454 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10;
1455 /* usHActive does not include borders, according to VBIOS team */
1456 info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active);
1457 /* usHBlanking_Time includes borders, so we should really be
1458 * subtractingborders duing this translation, but LVDS generally
1459 * doesn't have borders, so we should be okay leaving this as is for
1460 * now. May need to revisit if we ever have LVDS with borders
1461 */
1462 info->lcd_timing.horizontal_blanking_time = le16_to_cpu(lvds->lcd_timing.h_blanking_time);
1463 /* usVActive does not include borders, according to VBIOS team*/
1464 info->lcd_timing.vertical_addressable = le16_to_cpu(lvds->lcd_timing.v_active);
1465 /* usVBlanking_Time includes borders, so we should really be
1466 * subtracting borders duing this translation, but LVDS generally
1467 * doesn't have borders, so we should be okay leaving this as is for
1468 * now. May need to revisit if we ever have LVDS with borders
1469 */
1470 info->lcd_timing.vertical_blanking_time = le16_to_cpu(lvds->lcd_timing.v_blanking_time);
1471 info->lcd_timing.horizontal_sync_offset = le16_to_cpu(lvds->lcd_timing.h_sync_offset);
1472 info->lcd_timing.horizontal_sync_width = le16_to_cpu(lvds->lcd_timing.h_sync_width);
1473 info->lcd_timing.vertical_sync_offset = le16_to_cpu(lvds->lcd_timing.v_sync_offset);
1474 info->lcd_timing.vertical_sync_width = le16_to_cpu(lvds->lcd_timing.v_syncwidth);
1475 info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border;
1476 info->lcd_timing.vertical_border = lvds->lcd_timing.v_border;
1477
1478 /* not provided by VBIOS */
1479 info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0;
1480
1481 info->lcd_timing.misc_info.H_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo
1482 & ATOM_HSYNC_POLARITY);
1483 info->lcd_timing.misc_info.V_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo
1484 & ATOM_VSYNC_POLARITY);
1485
1486 /* not provided by VBIOS */
1487 info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0;
1488
1489 info->lcd_timing.misc_info.H_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo
1490 & ATOM_H_REPLICATIONBY2);
1491 info->lcd_timing.misc_info.V_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo
1492 & ATOM_V_REPLICATIONBY2);
1493 info->lcd_timing.misc_info.COMPOSITE_SYNC = !!(lvds->lcd_timing.miscinfo
1494 & ATOM_COMPOSITESYNC);
1495 info->lcd_timing.misc_info.INTERLACE = !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE);
1496
1497 /* not provided by VBIOS*/
1498 info->lcd_timing.misc_info.DOUBLE_CLOCK = 0;
1499 /* not provided by VBIOS*/
1500 info->ss_id = 0;
1501
1502 info->realtek_eDPToLVDS = !!(lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID);
1503
1504 return BP_RESULT_OK;
1505 }
1506
bios_parser_get_embedded_panel_info(struct dc_bios * dcb,struct embedded_panel_info * info)1507 static enum bp_result bios_parser_get_embedded_panel_info(
1508 struct dc_bios *dcb,
1509 struct embedded_panel_info *info)
1510 {
1511 struct bios_parser
1512 *bp = BP_FROM_DCB(dcb);
1513 struct atom_common_table_header *header;
1514 struct atom_data_revision tbl_revision;
1515
1516 if (!DATA_TABLES(lcd_info))
1517 return BP_RESULT_FAILURE;
1518
1519 header = GET_IMAGE(struct atom_common_table_header, DATA_TABLES(lcd_info));
1520
1521 if (!header)
1522 return BP_RESULT_BADBIOSTABLE;
1523
1524 get_atom_data_table_revision(header, &tbl_revision);
1525
1526 switch (tbl_revision.major) {
1527 case 2:
1528 switch (tbl_revision.minor) {
1529 case 1:
1530 return get_embedded_panel_info_v2_1(bp, info);
1531 default:
1532 break;
1533 }
1534 break;
1535 default:
1536 break;
1537 }
1538
1539 return BP_RESULT_FAILURE;
1540 }
1541
get_support_mask_for_device_id(struct device_id device_id)1542 static uint32_t get_support_mask_for_device_id(struct device_id device_id)
1543 {
1544 enum dal_device_type device_type = device_id.device_type;
1545 uint32_t enum_id = device_id.enum_id;
1546
1547 switch (device_type) {
1548 case DEVICE_TYPE_LCD:
1549 switch (enum_id) {
1550 case 1:
1551 return ATOM_DISPLAY_LCD1_SUPPORT;
1552 default:
1553 break;
1554 }
1555 break;
1556 case DEVICE_TYPE_DFP:
1557 switch (enum_id) {
1558 case 1:
1559 return ATOM_DISPLAY_DFP1_SUPPORT;
1560 case 2:
1561 return ATOM_DISPLAY_DFP2_SUPPORT;
1562 case 3:
1563 return ATOM_DISPLAY_DFP3_SUPPORT;
1564 case 4:
1565 return ATOM_DISPLAY_DFP4_SUPPORT;
1566 case 5:
1567 return ATOM_DISPLAY_DFP5_SUPPORT;
1568 case 6:
1569 return ATOM_DISPLAY_DFP6_SUPPORT;
1570 default:
1571 break;
1572 }
1573 break;
1574 default:
1575 break;
1576 }
1577
1578 /* Unidentified device ID, return empty support mask. */
1579 return 0;
1580 }
1581
bios_parser_is_device_id_supported(struct dc_bios * dcb,struct device_id id)1582 static bool bios_parser_is_device_id_supported(
1583 struct dc_bios *dcb,
1584 struct device_id id)
1585 {
1586 struct bios_parser *bp = BP_FROM_DCB(dcb);
1587
1588 uint32_t mask = get_support_mask_for_device_id(id);
1589
1590 switch (bp->object_info_tbl.revision.minor) {
1591 case 4:
1592 default:
1593 return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) & mask) != 0;
1594 break;
1595 case 5:
1596 return (le16_to_cpu(bp->object_info_tbl.v1_5->supporteddevices) & mask) != 0;
1597 break;
1598 }
1599
1600 return false;
1601 }
1602
bios_parser_get_ss_entry_number(struct dc_bios * dcb,enum as_signal_type signal)1603 static uint32_t bios_parser_get_ss_entry_number(
1604 struct dc_bios *dcb,
1605 enum as_signal_type signal)
1606 {
1607 /* TODO: DAL2 atomfirmware implementation does not need this.
1608 * why DAL3 need this?
1609 */
1610 return 1;
1611 }
1612
bios_parser_transmitter_control(struct dc_bios * dcb,struct bp_transmitter_control * cntl)1613 static enum bp_result bios_parser_transmitter_control(
1614 struct dc_bios *dcb,
1615 struct bp_transmitter_control *cntl)
1616 {
1617 struct bios_parser *bp = BP_FROM_DCB(dcb);
1618
1619 if (!bp->cmd_tbl.transmitter_control)
1620 return BP_RESULT_FAILURE;
1621
1622 return bp->cmd_tbl.transmitter_control(bp, cntl);
1623 }
1624
bios_parser_encoder_control(struct dc_bios * dcb,struct bp_encoder_control * cntl)1625 static enum bp_result bios_parser_encoder_control(
1626 struct dc_bios *dcb,
1627 struct bp_encoder_control *cntl)
1628 {
1629 struct bios_parser *bp = BP_FROM_DCB(dcb);
1630
1631 if (!bp->cmd_tbl.dig_encoder_control)
1632 return BP_RESULT_FAILURE;
1633
1634 return bp->cmd_tbl.dig_encoder_control(bp, cntl);
1635 }
1636
bios_parser_set_pixel_clock(struct dc_bios * dcb,struct bp_pixel_clock_parameters * bp_params)1637 static enum bp_result bios_parser_set_pixel_clock(
1638 struct dc_bios *dcb,
1639 struct bp_pixel_clock_parameters *bp_params)
1640 {
1641 struct bios_parser *bp = BP_FROM_DCB(dcb);
1642
1643 if (!bp->cmd_tbl.set_pixel_clock)
1644 return BP_RESULT_FAILURE;
1645
1646 return bp->cmd_tbl.set_pixel_clock(bp, bp_params);
1647 }
1648
bios_parser_set_dce_clock(struct dc_bios * dcb,struct bp_set_dce_clock_parameters * bp_params)1649 static enum bp_result bios_parser_set_dce_clock(
1650 struct dc_bios *dcb,
1651 struct bp_set_dce_clock_parameters *bp_params)
1652 {
1653 struct bios_parser *bp = BP_FROM_DCB(dcb);
1654
1655 if (!bp->cmd_tbl.set_dce_clock)
1656 return BP_RESULT_FAILURE;
1657
1658 return bp->cmd_tbl.set_dce_clock(bp, bp_params);
1659 }
1660
bios_parser_program_crtc_timing(struct dc_bios * dcb,struct bp_hw_crtc_timing_parameters * bp_params)1661 static enum bp_result bios_parser_program_crtc_timing(
1662 struct dc_bios *dcb,
1663 struct bp_hw_crtc_timing_parameters *bp_params)
1664 {
1665 struct bios_parser *bp = BP_FROM_DCB(dcb);
1666
1667 if (!bp->cmd_tbl.set_crtc_timing)
1668 return BP_RESULT_FAILURE;
1669
1670 return bp->cmd_tbl.set_crtc_timing(bp, bp_params);
1671 }
1672
bios_parser_enable_crtc(struct dc_bios * dcb,enum controller_id id,bool enable)1673 static enum bp_result bios_parser_enable_crtc(
1674 struct dc_bios *dcb,
1675 enum controller_id id,
1676 bool enable)
1677 {
1678 struct bios_parser *bp = BP_FROM_DCB(dcb);
1679
1680 if (!bp->cmd_tbl.enable_crtc)
1681 return BP_RESULT_FAILURE;
1682
1683 return bp->cmd_tbl.enable_crtc(bp, id, enable);
1684 }
1685
bios_parser_enable_disp_power_gating(struct dc_bios * dcb,enum controller_id controller_id,enum bp_pipe_control_action action)1686 static enum bp_result bios_parser_enable_disp_power_gating(
1687 struct dc_bios *dcb,
1688 enum controller_id controller_id,
1689 enum bp_pipe_control_action action)
1690 {
1691 struct bios_parser *bp = BP_FROM_DCB(dcb);
1692
1693 if (!bp->cmd_tbl.enable_disp_power_gating)
1694 return BP_RESULT_FAILURE;
1695
1696 return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id,
1697 action);
1698 }
1699
bios_parser_enable_lvtma_control(struct dc_bios * dcb,uint8_t uc_pwr_on,uint8_t panel_instance)1700 static enum bp_result bios_parser_enable_lvtma_control(
1701 struct dc_bios *dcb,
1702 uint8_t uc_pwr_on,
1703 uint8_t panel_instance)
1704 {
1705 struct bios_parser *bp = BP_FROM_DCB(dcb);
1706
1707 if (!bp->cmd_tbl.enable_lvtma_control)
1708 return BP_RESULT_FAILURE;
1709
1710 return bp->cmd_tbl.enable_lvtma_control(bp, uc_pwr_on, panel_instance);
1711 }
1712
bios_parser_is_accelerated_mode(struct dc_bios * dcb)1713 static bool bios_parser_is_accelerated_mode(
1714 struct dc_bios *dcb)
1715 {
1716 return bios_is_accelerated_mode(dcb);
1717 }
1718
1719 /**
1720 * bios_parser_set_scratch_critical_state - update critical state bit
1721 * in VBIOS scratch register
1722 *
1723 * @dcb: pointer to the DC BIO
1724 * @state: set or reset state
1725 */
bios_parser_set_scratch_critical_state(struct dc_bios * dcb,bool state)1726 static void bios_parser_set_scratch_critical_state(
1727 struct dc_bios *dcb,
1728 bool state)
1729 {
1730 bios_set_scratch_critical_state(dcb, state);
1731 }
1732
1733 struct atom_dig_transmitter_info_header_v5_3 {
1734 struct atom_common_table_header table_header;
1735 uint16_t dpphy_hdmi_settings_offset;
1736 uint16_t dpphy_dvi_settings_offset;
1737 uint16_t dpphy_dp_setting_table_offset;
1738 uint16_t uniphy_xbar_settings_v2_table_offset;
1739 uint16_t dpphy_internal_reg_overide_offset;
1740 };
1741
bios_parser_get_firmware_info(struct dc_bios * dcb,struct dc_firmware_info * info)1742 static enum bp_result bios_parser_get_firmware_info(
1743 struct dc_bios *dcb,
1744 struct dc_firmware_info *info)
1745 {
1746 struct bios_parser *bp = BP_FROM_DCB(dcb);
1747 static enum bp_result result = BP_RESULT_BADBIOSTABLE;
1748 struct atom_common_table_header *header;
1749
1750 struct atom_data_revision revision;
1751
1752 if (info && DATA_TABLES(firmwareinfo)) {
1753 header = GET_IMAGE(struct atom_common_table_header,
1754 DATA_TABLES(firmwareinfo));
1755 get_atom_data_table_revision(header, &revision);
1756 switch (revision.major) {
1757 case 3:
1758 switch (revision.minor) {
1759 case 1:
1760 result = get_firmware_info_v3_1(bp, info);
1761 break;
1762 case 2:
1763 case 3:
1764 result = get_firmware_info_v3_2(bp, info);
1765 break;
1766 case 4:
1767 result = get_firmware_info_v3_4(bp, info);
1768 break;
1769 default:
1770 break;
1771 }
1772 break;
1773 default:
1774 break;
1775 }
1776 }
1777
1778 return result;
1779 }
1780
get_firmware_info_v3_1(struct bios_parser * bp,struct dc_firmware_info * info)1781 static enum bp_result get_firmware_info_v3_1(
1782 struct bios_parser *bp,
1783 struct dc_firmware_info *info)
1784 {
1785 struct atom_firmware_info_v3_1 *firmware_info;
1786 struct atom_display_controller_info_v4_1 *dce_info = NULL;
1787
1788 if (!info)
1789 return BP_RESULT_BADINPUT;
1790
1791 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1,
1792 DATA_TABLES(firmwareinfo));
1793
1794 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1795 DATA_TABLES(dce_info));
1796
1797 if (!firmware_info || !dce_info)
1798 return BP_RESULT_BADBIOSTABLE;
1799
1800 memset(info, 0, sizeof(*info));
1801
1802 /* Pixel clock pll information. */
1803 /* We need to convert from 10KHz units into KHz units */
1804 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1805 info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10;
1806
1807 /* 27MHz for Vega10: */
1808 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1809
1810 /* Hardcode frequency if BIOS gives no DCE Ref Clk */
1811 if (info->pll_info.crystal_frequency == 0)
1812 info->pll_info.crystal_frequency = 27000;
1813 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
1814 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
1815 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1816
1817 /* Get GPU PLL VCO Clock */
1818
1819 if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1820 /* VBIOS gives in 10KHz */
1821 info->smu_gpu_pll_output_freq =
1822 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1823 }
1824
1825 info->oem_i2c_present = false;
1826
1827 return BP_RESULT_OK;
1828 }
1829
get_firmware_info_v3_2(struct bios_parser * bp,struct dc_firmware_info * info)1830 static enum bp_result get_firmware_info_v3_2(
1831 struct bios_parser *bp,
1832 struct dc_firmware_info *info)
1833 {
1834 struct atom_firmware_info_v3_2 *firmware_info;
1835 struct atom_display_controller_info_v4_1 *dce_info = NULL;
1836 struct atom_common_table_header *header;
1837 struct atom_data_revision revision;
1838 struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL;
1839 struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL;
1840
1841 if (!info)
1842 return BP_RESULT_BADINPUT;
1843
1844 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2,
1845 DATA_TABLES(firmwareinfo));
1846
1847 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1848 DATA_TABLES(dce_info));
1849
1850 if (!firmware_info || !dce_info)
1851 return BP_RESULT_BADBIOSTABLE;
1852
1853 memset(info, 0, sizeof(*info));
1854
1855 header = GET_IMAGE(struct atom_common_table_header,
1856 DATA_TABLES(smu_info));
1857 get_atom_data_table_revision(header, &revision);
1858
1859 if (revision.minor == 2) {
1860 /* Vega12 */
1861 smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2,
1862 DATA_TABLES(smu_info));
1863 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_2->gpuclk_ss_percentage);
1864 if (!smu_info_v3_2)
1865 return BP_RESULT_BADBIOSTABLE;
1866
1867 info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10;
1868 } else if (revision.minor == 3) {
1869 /* Vega20 */
1870 smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3,
1871 DATA_TABLES(smu_info));
1872 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_3->gpuclk_ss_percentage);
1873 if (!smu_info_v3_3)
1874 return BP_RESULT_BADBIOSTABLE;
1875
1876 info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10;
1877 }
1878
1879 // We need to convert from 10KHz units into KHz units.
1880 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1881
1882 /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */
1883 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1884 /* Hardcode frequency if BIOS gives no DCE Ref Clk */
1885 if (info->pll_info.crystal_frequency == 0) {
1886 if (revision.minor == 2)
1887 info->pll_info.crystal_frequency = 27000;
1888 else if (revision.minor == 3)
1889 info->pll_info.crystal_frequency = 100000;
1890 }
1891 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
1892 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
1893 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1894
1895 /* Get GPU PLL VCO Clock */
1896 if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1897 if (revision.minor == 2)
1898 info->smu_gpu_pll_output_freq =
1899 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1900 else if (revision.minor == 3)
1901 info->smu_gpu_pll_output_freq =
1902 bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10;
1903 }
1904
1905 if (firmware_info->board_i2c_feature_id == 0x2) {
1906 info->oem_i2c_present = true;
1907 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id;
1908 } else {
1909 info->oem_i2c_present = false;
1910 }
1911
1912 return BP_RESULT_OK;
1913 }
1914
get_firmware_info_v3_4(struct bios_parser * bp,struct dc_firmware_info * info)1915 static enum bp_result get_firmware_info_v3_4(
1916 struct bios_parser *bp,
1917 struct dc_firmware_info *info)
1918 {
1919 struct atom_firmware_info_v3_4 *firmware_info;
1920 struct atom_common_table_header *header;
1921 struct atom_data_revision revision;
1922 struct atom_display_controller_info_v4_1 *dce_info_v4_1 = NULL;
1923 struct atom_display_controller_info_v4_4 *dce_info_v4_4 = NULL;
1924
1925 struct atom_smu_info_v3_5 *smu_info_v3_5 = NULL;
1926 struct atom_display_controller_info_v4_5 *dce_info_v4_5 = NULL;
1927 struct atom_smu_info_v4_0 *smu_info_v4_0 = NULL;
1928
1929 if (!info)
1930 return BP_RESULT_BADINPUT;
1931
1932 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_4,
1933 DATA_TABLES(firmwareinfo));
1934
1935 if (!firmware_info)
1936 return BP_RESULT_BADBIOSTABLE;
1937
1938 memset(info, 0, sizeof(*info));
1939
1940 header = GET_IMAGE(struct atom_common_table_header,
1941 DATA_TABLES(dce_info));
1942
1943 get_atom_data_table_revision(header, &revision);
1944
1945 switch (revision.major) {
1946 case 4:
1947 switch (revision.minor) {
1948 case 5:
1949 dce_info_v4_5 = GET_IMAGE(struct atom_display_controller_info_v4_5,
1950 DATA_TABLES(dce_info));
1951
1952 if (!dce_info_v4_5)
1953 return BP_RESULT_BADBIOSTABLE;
1954
1955 /* 100MHz expected */
1956 info->pll_info.crystal_frequency = dce_info_v4_5->dce_refclk_10khz * 10;
1957 info->dp_phy_ref_clk = dce_info_v4_5->dpphy_refclk_10khz * 10;
1958 /* 50MHz expected */
1959 info->i2c_engine_ref_clk = dce_info_v4_5->i2c_engine_refclk_10khz * 10;
1960
1961 /* For DCN32/321 Display PLL VCO Frequency from dce_info_v4_5 may not be reliable */
1962 break;
1963
1964 case 4:
1965 dce_info_v4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4,
1966 DATA_TABLES(dce_info));
1967
1968 if (!dce_info_v4_4)
1969 return BP_RESULT_BADBIOSTABLE;
1970
1971 /* 100MHz expected */
1972 info->pll_info.crystal_frequency = dce_info_v4_4->dce_refclk_10khz * 10;
1973 info->dp_phy_ref_clk = dce_info_v4_4->dpphy_refclk_10khz * 10;
1974 /* 50MHz expected */
1975 info->i2c_engine_ref_clk = dce_info_v4_4->i2c_engine_refclk_10khz * 10;
1976
1977 /* Get SMU Display PLL VCO Frequency in KHz*/
1978 info->smu_gpu_pll_output_freq = dce_info_v4_4->dispclk_pll_vco_freq * 10;
1979 break;
1980
1981 default:
1982 /* should not come here, keep as backup, as was before */
1983 dce_info_v4_1 = GET_IMAGE(struct atom_display_controller_info_v4_1,
1984 DATA_TABLES(dce_info));
1985
1986 if (!dce_info_v4_1)
1987 return BP_RESULT_BADBIOSTABLE;
1988
1989 info->pll_info.crystal_frequency = dce_info_v4_1->dce_refclk_10khz * 10;
1990 info->dp_phy_ref_clk = dce_info_v4_1->dpphy_refclk_10khz * 10;
1991 info->i2c_engine_ref_clk = dce_info_v4_1->i2c_engine_refclk_10khz * 10;
1992 break;
1993 }
1994 break;
1995
1996 default:
1997 ASSERT(0);
1998 break;
1999 }
2000
2001 header = GET_IMAGE(struct atom_common_table_header,
2002 DATA_TABLES(smu_info));
2003 get_atom_data_table_revision(header, &revision);
2004
2005 switch (revision.major) {
2006 case 3:
2007 switch (revision.minor) {
2008 case 5:
2009 smu_info_v3_5 = GET_IMAGE(struct atom_smu_info_v3_5,
2010 DATA_TABLES(smu_info));
2011
2012 if (!smu_info_v3_5)
2013 return BP_RESULT_BADBIOSTABLE;
2014 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_5->gpuclk_ss_percentage);
2015 info->default_engine_clk = smu_info_v3_5->bootup_dcefclk_10khz * 10;
2016 break;
2017
2018 default:
2019 break;
2020 }
2021 break;
2022
2023 case 4:
2024 switch (revision.minor) {
2025 case 0:
2026 smu_info_v4_0 = GET_IMAGE(struct atom_smu_info_v4_0,
2027 DATA_TABLES(smu_info));
2028
2029 if (!smu_info_v4_0)
2030 return BP_RESULT_BADBIOSTABLE;
2031
2032 /* For DCN32/321 bootup DCFCLK from smu_info_v4_0 may not be reliable */
2033 break;
2034
2035 default:
2036 break;
2037 }
2038 break;
2039
2040 default:
2041 break;
2042 }
2043
2044 // We need to convert from 10KHz units into KHz units.
2045 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
2046
2047 if (firmware_info->board_i2c_feature_id == 0x2) {
2048 info->oem_i2c_present = true;
2049 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id;
2050 } else {
2051 info->oem_i2c_present = false;
2052 }
2053
2054 return BP_RESULT_OK;
2055 }
2056
bios_parser_get_encoder_cap_info(struct dc_bios * dcb,struct graphics_object_id object_id,struct bp_encoder_cap_info * info)2057 static enum bp_result bios_parser_get_encoder_cap_info(
2058 struct dc_bios *dcb,
2059 struct graphics_object_id object_id,
2060 struct bp_encoder_cap_info *info)
2061 {
2062 struct bios_parser *bp = BP_FROM_DCB(dcb);
2063 struct atom_display_object_path_v2 *object;
2064 struct atom_encoder_caps_record *record = NULL;
2065
2066 if (!info)
2067 return BP_RESULT_BADINPUT;
2068
2069 #if defined(CONFIG_DRM_AMD_DC_DCN)
2070 /* encoder cap record not available in v1_5 */
2071 if (bp->object_info_tbl.revision.minor == 5)
2072 return BP_RESULT_NORECORD;
2073 #endif
2074
2075 object = get_bios_object(bp, object_id);
2076
2077 if (!object)
2078 return BP_RESULT_BADINPUT;
2079
2080 record = get_encoder_cap_record(bp, object);
2081 if (!record)
2082 return BP_RESULT_NORECORD;
2083 DC_LOG_BIOS("record->encodercaps 0x%x for object_id 0x%x", record->encodercaps, object_id.id);
2084
2085 info->DP_HBR2_CAP = (record->encodercaps &
2086 ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0;
2087 info->DP_HBR2_EN = (record->encodercaps &
2088 ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0;
2089 info->DP_HBR3_EN = (record->encodercaps &
2090 ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0;
2091 info->HDMI_6GB_EN = (record->encodercaps &
2092 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0;
2093 info->IS_DP2_CAPABLE = (record->encodercaps &
2094 ATOM_ENCODER_CAP_RECORD_DP2) ? 1 : 0;
2095 info->DP_UHBR10_EN = (record->encodercaps &
2096 ATOM_ENCODER_CAP_RECORD_UHBR10_EN) ? 1 : 0;
2097 info->DP_UHBR13_5_EN = (record->encodercaps &
2098 ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN) ? 1 : 0;
2099 info->DP_UHBR20_EN = (record->encodercaps &
2100 ATOM_ENCODER_CAP_RECORD_UHBR20_EN) ? 1 : 0;
2101 info->DP_IS_USB_C = (record->encodercaps &
2102 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0;
2103 DC_LOG_BIOS("\t info->DP_IS_USB_C %d", info->DP_IS_USB_C);
2104
2105 return BP_RESULT_OK;
2106 }
2107
2108
get_encoder_cap_record(struct bios_parser * bp,struct atom_display_object_path_v2 * object)2109 static struct atom_encoder_caps_record *get_encoder_cap_record(
2110 struct bios_parser *bp,
2111 struct atom_display_object_path_v2 *object)
2112 {
2113 struct atom_common_record_header *header;
2114 uint32_t offset;
2115
2116 if (!object) {
2117 BREAK_TO_DEBUGGER(); /* Invalid object */
2118 return NULL;
2119 }
2120
2121 offset = object->encoder_recordoffset + bp->object_info_tbl_offset;
2122
2123 for (;;) {
2124 header = GET_IMAGE(struct atom_common_record_header, offset);
2125
2126 if (!header)
2127 return NULL;
2128
2129 offset += header->record_size;
2130
2131 if (header->record_type == LAST_RECORD_TYPE ||
2132 !header->record_size)
2133 break;
2134
2135 if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE)
2136 continue;
2137
2138 if (sizeof(struct atom_encoder_caps_record) <=
2139 header->record_size)
2140 return (struct atom_encoder_caps_record *)header;
2141 }
2142
2143 return NULL;
2144 }
2145
get_disp_connector_caps_record(struct bios_parser * bp,struct atom_display_object_path_v2 * object)2146 static struct atom_disp_connector_caps_record *get_disp_connector_caps_record(
2147 struct bios_parser *bp,
2148 struct atom_display_object_path_v2 *object)
2149 {
2150 struct atom_common_record_header *header;
2151 uint32_t offset;
2152
2153 if (!object) {
2154 BREAK_TO_DEBUGGER(); /* Invalid object */
2155 return NULL;
2156 }
2157
2158 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
2159
2160 for (;;) {
2161 header = GET_IMAGE(struct atom_common_record_header, offset);
2162
2163 if (!header)
2164 return NULL;
2165
2166 offset += header->record_size;
2167
2168 if (header->record_type == LAST_RECORD_TYPE ||
2169 !header->record_size)
2170 break;
2171
2172 if (header->record_type != ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE)
2173 continue;
2174
2175 if (sizeof(struct atom_disp_connector_caps_record) <=
2176 header->record_size)
2177 return (struct atom_disp_connector_caps_record *)header;
2178 }
2179
2180 return NULL;
2181 }
2182
get_connector_caps_record(struct bios_parser * bp,struct atom_display_object_path_v3 * object)2183 static struct atom_connector_caps_record *get_connector_caps_record(
2184 struct bios_parser *bp,
2185 struct atom_display_object_path_v3 *object)
2186 {
2187 struct atom_common_record_header *header;
2188 uint32_t offset;
2189
2190 if (!object) {
2191 BREAK_TO_DEBUGGER(); /* Invalid object */
2192 return NULL;
2193 }
2194
2195 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
2196
2197 for (;;) {
2198 header = GET_IMAGE(struct atom_common_record_header, offset);
2199
2200 if (!header)
2201 return NULL;
2202
2203 offset += header->record_size;
2204
2205 if (header->record_type == ATOM_RECORD_END_TYPE ||
2206 !header->record_size)
2207 break;
2208
2209 if (header->record_type != ATOM_CONNECTOR_CAP_RECORD_TYPE)
2210 continue;
2211
2212 if (sizeof(struct atom_connector_caps_record) <= header->record_size)
2213 return (struct atom_connector_caps_record *)header;
2214 }
2215
2216 return NULL;
2217 }
2218
bios_parser_get_disp_connector_caps_info(struct dc_bios * dcb,struct graphics_object_id object_id,struct bp_disp_connector_caps_info * info)2219 static enum bp_result bios_parser_get_disp_connector_caps_info(
2220 struct dc_bios *dcb,
2221 struct graphics_object_id object_id,
2222 struct bp_disp_connector_caps_info *info)
2223 {
2224 struct bios_parser *bp = BP_FROM_DCB(dcb);
2225 struct atom_display_object_path_v2 *object;
2226
2227 struct atom_display_object_path_v3 *object_path_v3;
2228 struct atom_connector_caps_record *record_path_v3;
2229
2230 struct atom_disp_connector_caps_record *record = NULL;
2231
2232 if (!info)
2233 return BP_RESULT_BADINPUT;
2234
2235 switch (bp->object_info_tbl.revision.minor) {
2236 case 4:
2237 default:
2238 object = get_bios_object(bp, object_id);
2239
2240 if (!object)
2241 return BP_RESULT_BADINPUT;
2242
2243 record = get_disp_connector_caps_record(bp, object);
2244 if (!record)
2245 return BP_RESULT_NORECORD;
2246
2247 info->INTERNAL_DISPLAY =
2248 (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) ? 1 : 0;
2249 info->INTERNAL_DISPLAY_BL =
2250 (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) ? 1 : 0;
2251 break;
2252 case 5:
2253 object_path_v3 = get_bios_object_from_path_v3(bp, object_id);
2254
2255 if (!object_path_v3)
2256 return BP_RESULT_BADINPUT;
2257
2258 record_path_v3 = get_connector_caps_record(bp, object_path_v3);
2259 if (!record_path_v3)
2260 return BP_RESULT_NORECORD;
2261
2262 info->INTERNAL_DISPLAY = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY)
2263 ? 1 : 0;
2264 info->INTERNAL_DISPLAY_BL = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL)
2265 ? 1 : 0;
2266 break;
2267 }
2268
2269 return BP_RESULT_OK;
2270 }
2271
get_connector_speed_cap_record(struct bios_parser * bp,struct atom_display_object_path_v3 * object)2272 static struct atom_connector_speed_record *get_connector_speed_cap_record(
2273 struct bios_parser *bp,
2274 struct atom_display_object_path_v3 *object)
2275 {
2276 struct atom_common_record_header *header;
2277 uint32_t offset;
2278
2279 if (!object) {
2280 BREAK_TO_DEBUGGER(); /* Invalid object */
2281 return NULL;
2282 }
2283
2284 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
2285
2286 for (;;) {
2287 header = GET_IMAGE(struct atom_common_record_header, offset);
2288
2289 if (!header)
2290 return NULL;
2291
2292 offset += header->record_size;
2293
2294 if (header->record_type == ATOM_RECORD_END_TYPE ||
2295 !header->record_size)
2296 break;
2297
2298 if (header->record_type != ATOM_CONNECTOR_SPEED_UPTO)
2299 continue;
2300
2301 if (sizeof(struct atom_connector_speed_record) <= header->record_size)
2302 return (struct atom_connector_speed_record *)header;
2303 }
2304
2305 return NULL;
2306 }
2307
bios_parser_get_connector_speed_cap_info(struct dc_bios * dcb,struct graphics_object_id object_id,struct bp_connector_speed_cap_info * info)2308 static enum bp_result bios_parser_get_connector_speed_cap_info(
2309 struct dc_bios *dcb,
2310 struct graphics_object_id object_id,
2311 struct bp_connector_speed_cap_info *info)
2312 {
2313 struct bios_parser *bp = BP_FROM_DCB(dcb);
2314 struct atom_display_object_path_v3 *object_path_v3;
2315 //struct atom_connector_speed_record *record = NULL;
2316 struct atom_connector_speed_record *record;
2317
2318 if (!info)
2319 return BP_RESULT_BADINPUT;
2320
2321 object_path_v3 = get_bios_object_from_path_v3(bp, object_id);
2322
2323 if (!object_path_v3)
2324 return BP_RESULT_BADINPUT;
2325
2326 record = get_connector_speed_cap_record(bp, object_path_v3);
2327 if (!record)
2328 return BP_RESULT_NORECORD;
2329
2330 info->DP_HBR2_EN = (record->connector_max_speed >= 5400) ? 1 : 0;
2331 info->DP_HBR3_EN = (record->connector_max_speed >= 8100) ? 1 : 0;
2332 info->HDMI_6GB_EN = (record->connector_max_speed >= 5940) ? 1 : 0;
2333 info->DP_UHBR10_EN = (record->connector_max_speed >= 10000) ? 1 : 0;
2334 info->DP_UHBR13_5_EN = (record->connector_max_speed >= 13500) ? 1 : 0;
2335 info->DP_UHBR20_EN = (record->connector_max_speed >= 20000) ? 1 : 0;
2336 return BP_RESULT_OK;
2337 }
2338
get_vram_info_v23(struct bios_parser * bp,struct dc_vram_info * info)2339 static enum bp_result get_vram_info_v23(
2340 struct bios_parser *bp,
2341 struct dc_vram_info *info)
2342 {
2343 struct atom_vram_info_header_v2_3 *info_v23;
2344 static enum bp_result result = BP_RESULT_OK;
2345
2346 info_v23 = GET_IMAGE(struct atom_vram_info_header_v2_3,
2347 DATA_TABLES(vram_info));
2348
2349 if (info_v23 == NULL)
2350 return BP_RESULT_BADBIOSTABLE;
2351
2352 info->num_chans = info_v23->vram_module[0].channel_num;
2353 info->dram_channel_width_bytes = (1 << info_v23->vram_module[0].channel_width) / 8;
2354
2355 return result;
2356 }
2357
get_vram_info_v24(struct bios_parser * bp,struct dc_vram_info * info)2358 static enum bp_result get_vram_info_v24(
2359 struct bios_parser *bp,
2360 struct dc_vram_info *info)
2361 {
2362 struct atom_vram_info_header_v2_4 *info_v24;
2363 static enum bp_result result = BP_RESULT_OK;
2364
2365 info_v24 = GET_IMAGE(struct atom_vram_info_header_v2_4,
2366 DATA_TABLES(vram_info));
2367
2368 if (info_v24 == NULL)
2369 return BP_RESULT_BADBIOSTABLE;
2370
2371 info->num_chans = info_v24->vram_module[0].channel_num;
2372 info->dram_channel_width_bytes = (1 << info_v24->vram_module[0].channel_width) / 8;
2373
2374 return result;
2375 }
2376
get_vram_info_v25(struct bios_parser * bp,struct dc_vram_info * info)2377 static enum bp_result get_vram_info_v25(
2378 struct bios_parser *bp,
2379 struct dc_vram_info *info)
2380 {
2381 struct atom_vram_info_header_v2_5 *info_v25;
2382 static enum bp_result result = BP_RESULT_OK;
2383
2384 info_v25 = GET_IMAGE(struct atom_vram_info_header_v2_5,
2385 DATA_TABLES(vram_info));
2386
2387 if (info_v25 == NULL)
2388 return BP_RESULT_BADBIOSTABLE;
2389
2390 info->num_chans = info_v25->vram_module[0].channel_num;
2391 info->dram_channel_width_bytes = (1 << info_v25->vram_module[0].channel_width) / 8;
2392
2393 return result;
2394 }
2395
get_vram_info_v30(struct bios_parser * bp,struct dc_vram_info * info)2396 static enum bp_result get_vram_info_v30(
2397 struct bios_parser *bp,
2398 struct dc_vram_info *info)
2399 {
2400 struct atom_vram_info_header_v3_0 *info_v30;
2401 enum bp_result result = BP_RESULT_OK;
2402
2403 info_v30 = GET_IMAGE(struct atom_vram_info_header_v3_0,
2404 DATA_TABLES(vram_info));
2405
2406 if (info_v30 == NULL)
2407 return BP_RESULT_BADBIOSTABLE;
2408
2409 info->num_chans = info_v30->channel_num;
2410 info->dram_channel_width_bytes = (1 << info_v30->channel_width) / 8;
2411
2412 return result;
2413 }
2414
2415
2416 /*
2417 * get_integrated_info_v11
2418 *
2419 * @brief
2420 * Get V8 integrated BIOS information
2421 *
2422 * @param
2423 * bios_parser *bp - [in]BIOS parser handler to get master data table
2424 * integrated_info *info - [out] store and output integrated info
2425 *
2426 * @return
2427 * static enum bp_result - BP_RESULT_OK if information is available,
2428 * BP_RESULT_BADBIOSTABLE otherwise.
2429 */
get_integrated_info_v11(struct bios_parser * bp,struct integrated_info * info)2430 static enum bp_result get_integrated_info_v11(
2431 struct bios_parser *bp,
2432 struct integrated_info *info)
2433 {
2434 struct atom_integrated_system_info_v1_11 *info_v11;
2435 uint32_t i;
2436
2437 info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11,
2438 DATA_TABLES(integratedsysteminfo));
2439
2440 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v11->gpuclk_ss_percentage);
2441 if (info_v11 == NULL)
2442 return BP_RESULT_BADBIOSTABLE;
2443
2444 info->gpu_cap_info =
2445 le32_to_cpu(info_v11->gpucapinfo);
2446 /*
2447 * system_config: Bit[0] = 0 : PCIE power gating disabled
2448 * = 1 : PCIE power gating enabled
2449 * Bit[1] = 0 : DDR-PLL shut down disabled
2450 * = 1 : DDR-PLL shut down enabled
2451 * Bit[2] = 0 : DDR-PLL power down disabled
2452 * = 1 : DDR-PLL power down enabled
2453 */
2454 info->system_config = le32_to_cpu(info_v11->system_config);
2455 info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo);
2456 info->memory_type = info_v11->memorytype;
2457 info->ma_channel_number = info_v11->umachannelnumber;
2458 info->lvds_ss_percentage =
2459 le16_to_cpu(info_v11->lvds_ss_percentage);
2460 info->dp_ss_control =
2461 le16_to_cpu(info_v11->reserved1);
2462 info->lvds_sspread_rate_in_10hz =
2463 le16_to_cpu(info_v11->lvds_ss_rate_10hz);
2464 info->hdmi_ss_percentage =
2465 le16_to_cpu(info_v11->hdmi_ss_percentage);
2466 info->hdmi_sspread_rate_in_10hz =
2467 le16_to_cpu(info_v11->hdmi_ss_rate_10hz);
2468 info->dvi_ss_percentage =
2469 le16_to_cpu(info_v11->dvi_ss_percentage);
2470 info->dvi_sspread_rate_in_10_hz =
2471 le16_to_cpu(info_v11->dvi_ss_rate_10hz);
2472 info->lvds_misc = info_v11->lvds_misc;
2473 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
2474 info->ext_disp_conn_info.gu_id[i] =
2475 info_v11->extdispconninfo.guid[i];
2476 }
2477
2478 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
2479 info->ext_disp_conn_info.path[i].device_connector_id =
2480 object_id_from_bios_object_id(
2481 le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid));
2482
2483 info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
2484 object_id_from_bios_object_id(
2485 le16_to_cpu(
2486 info_v11->extdispconninfo.path[i].ext_encoder_objid));
2487
2488 info->ext_disp_conn_info.path[i].device_tag =
2489 le16_to_cpu(
2490 info_v11->extdispconninfo.path[i].device_tag);
2491 info->ext_disp_conn_info.path[i].device_acpi_enum =
2492 le16_to_cpu(
2493 info_v11->extdispconninfo.path[i].device_acpi_enum);
2494 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
2495 info_v11->extdispconninfo.path[i].auxddclut_index;
2496 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
2497 info_v11->extdispconninfo.path[i].hpdlut_index;
2498 info->ext_disp_conn_info.path[i].channel_mapping.raw =
2499 info_v11->extdispconninfo.path[i].channelmapping;
2500 info->ext_disp_conn_info.path[i].caps =
2501 le16_to_cpu(info_v11->extdispconninfo.path[i].caps);
2502 }
2503 info->ext_disp_conn_info.checksum =
2504 info_v11->extdispconninfo.checksum;
2505
2506 info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr;
2507 info->dp0_ext_hdmi_reg_num = info_v11->dp0_retimer_set.HdmiRegNum;
2508 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) {
2509 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index =
2510 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2511 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val =
2512 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2513 }
2514 info->dp0_ext_hdmi_6g_reg_num = info_v11->dp0_retimer_set.Hdmi6GRegNum;
2515 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) {
2516 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2517 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2518 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2519 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2520 }
2521
2522 info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr;
2523 info->dp1_ext_hdmi_reg_num = info_v11->dp1_retimer_set.HdmiRegNum;
2524 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) {
2525 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index =
2526 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2527 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val =
2528 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2529 }
2530 info->dp1_ext_hdmi_6g_reg_num = info_v11->dp1_retimer_set.Hdmi6GRegNum;
2531 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) {
2532 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2533 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2534 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2535 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2536 }
2537
2538 info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr;
2539 info->dp2_ext_hdmi_reg_num = info_v11->dp2_retimer_set.HdmiRegNum;
2540 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) {
2541 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index =
2542 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2543 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val =
2544 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2545 }
2546 info->dp2_ext_hdmi_6g_reg_num = info_v11->dp2_retimer_set.Hdmi6GRegNum;
2547 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) {
2548 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2549 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2550 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2551 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2552 }
2553
2554 info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr;
2555 info->dp3_ext_hdmi_reg_num = info_v11->dp3_retimer_set.HdmiRegNum;
2556 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) {
2557 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index =
2558 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2559 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val =
2560 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2561 }
2562 info->dp3_ext_hdmi_6g_reg_num = info_v11->dp3_retimer_set.Hdmi6GRegNum;
2563 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) {
2564 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2565 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2566 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2567 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2568 }
2569
2570
2571 /** TODO - review **/
2572 #if 0
2573 info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock)
2574 * 10;
2575 info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10;
2576 info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10;
2577
2578 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
2579 /* Convert [10KHz] into [KHz] */
2580 info->disp_clk_voltage[i].max_supported_clk =
2581 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].
2582 ulMaximumSupportedCLK) * 10;
2583 info->disp_clk_voltage[i].voltage_index =
2584 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex);
2585 }
2586
2587 info->boot_up_req_display_vector =
2588 le32_to_cpu(info_v11->ulBootUpReqDisplayVector);
2589 info->boot_up_nb_voltage =
2590 le16_to_cpu(info_v11->usBootUpNBVoltage);
2591 info->ext_disp_conn_info_offset =
2592 le16_to_cpu(info_v11->usExtDispConnInfoOffset);
2593 info->gmc_restore_reset_time =
2594 le32_to_cpu(info_v11->ulGMCRestoreResetTime);
2595 info->minimum_n_clk =
2596 le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]);
2597 for (i = 1; i < 4; ++i)
2598 info->minimum_n_clk =
2599 info->minimum_n_clk <
2600 le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ?
2601 info->minimum_n_clk : le32_to_cpu(
2602 info_v11->ulNbpStateNClkFreq[i]);
2603
2604 info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk);
2605 info->ddr_dll_power_up_time =
2606 le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime);
2607 info->ddr_pll_power_up_time =
2608 le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime);
2609 info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType);
2610 info->max_lvds_pclk_freq_in_single_link =
2611 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink);
2612 info->max_lvds_pclk_freq_in_single_link =
2613 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink);
2614 info->lvds_pwr_on_seq_dig_on_to_de_in_4ms =
2615 info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
2616 info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms =
2617 info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
2618 info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms =
2619 info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
2620 info->lvds_pwr_off_seq_vary_bl_to_de_in4ms =
2621 info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
2622 info->lvds_pwr_off_seq_de_to_dig_on_in4ms =
2623 info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
2624 info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms =
2625 info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
2626 info->lvds_off_to_on_delay_in_4ms =
2627 info_v11->ucLVDSOffToOnDelay_in4Ms;
2628 info->lvds_bit_depth_control_val =
2629 le32_to_cpu(info_v11->ulLCDBitDepthControlVal);
2630
2631 for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) {
2632 /* Convert [10KHz] into [KHz] */
2633 info->avail_s_clk[i].supported_s_clk =
2634 le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK)
2635 * 10;
2636 info->avail_s_clk[i].voltage_index =
2637 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex);
2638 info->avail_s_clk[i].voltage_id =
2639 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID);
2640 }
2641 #endif /* TODO*/
2642
2643 return BP_RESULT_OK;
2644 }
2645
get_integrated_info_v2_1(struct bios_parser * bp,struct integrated_info * info)2646 static enum bp_result get_integrated_info_v2_1(
2647 struct bios_parser *bp,
2648 struct integrated_info *info)
2649 {
2650 struct atom_integrated_system_info_v2_1 *info_v2_1;
2651 uint32_t i;
2652
2653 info_v2_1 = GET_IMAGE(struct atom_integrated_system_info_v2_1,
2654 DATA_TABLES(integratedsysteminfo));
2655 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v2_1->gpuclk_ss_percentage);
2656
2657 if (info_v2_1 == NULL)
2658 return BP_RESULT_BADBIOSTABLE;
2659
2660 info->gpu_cap_info =
2661 le32_to_cpu(info_v2_1->gpucapinfo);
2662 /*
2663 * system_config: Bit[0] = 0 : PCIE power gating disabled
2664 * = 1 : PCIE power gating enabled
2665 * Bit[1] = 0 : DDR-PLL shut down disabled
2666 * = 1 : DDR-PLL shut down enabled
2667 * Bit[2] = 0 : DDR-PLL power down disabled
2668 * = 1 : DDR-PLL power down enabled
2669 */
2670 info->system_config = le32_to_cpu(info_v2_1->system_config);
2671 info->cpu_cap_info = le32_to_cpu(info_v2_1->cpucapinfo);
2672 info->memory_type = info_v2_1->memorytype;
2673 info->ma_channel_number = info_v2_1->umachannelnumber;
2674 info->dp_ss_control =
2675 le16_to_cpu(info_v2_1->reserved1);
2676
2677 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
2678 info->ext_disp_conn_info.gu_id[i] =
2679 info_v2_1->extdispconninfo.guid[i];
2680 }
2681
2682 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
2683 info->ext_disp_conn_info.path[i].device_connector_id =
2684 object_id_from_bios_object_id(
2685 le16_to_cpu(info_v2_1->extdispconninfo.path[i].connectorobjid));
2686
2687 info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
2688 object_id_from_bios_object_id(
2689 le16_to_cpu(
2690 info_v2_1->extdispconninfo.path[i].ext_encoder_objid));
2691
2692 info->ext_disp_conn_info.path[i].device_tag =
2693 le16_to_cpu(
2694 info_v2_1->extdispconninfo.path[i].device_tag);
2695 info->ext_disp_conn_info.path[i].device_acpi_enum =
2696 le16_to_cpu(
2697 info_v2_1->extdispconninfo.path[i].device_acpi_enum);
2698 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
2699 info_v2_1->extdispconninfo.path[i].auxddclut_index;
2700 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
2701 info_v2_1->extdispconninfo.path[i].hpdlut_index;
2702 info->ext_disp_conn_info.path[i].channel_mapping.raw =
2703 info_v2_1->extdispconninfo.path[i].channelmapping;
2704 info->ext_disp_conn_info.path[i].caps =
2705 le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps);
2706 }
2707
2708 info->ext_disp_conn_info.checksum =
2709 info_v2_1->extdispconninfo.checksum;
2710 info->dp0_ext_hdmi_slv_addr = info_v2_1->dp0_retimer_set.HdmiSlvAddr;
2711 info->dp0_ext_hdmi_reg_num = info_v2_1->dp0_retimer_set.HdmiRegNum;
2712 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) {
2713 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index =
2714 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2715 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val =
2716 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2717 }
2718 info->dp0_ext_hdmi_6g_reg_num = info_v2_1->dp0_retimer_set.Hdmi6GRegNum;
2719 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) {
2720 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2721 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2722 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2723 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2724 }
2725 info->dp1_ext_hdmi_slv_addr = info_v2_1->dp1_retimer_set.HdmiSlvAddr;
2726 info->dp1_ext_hdmi_reg_num = info_v2_1->dp1_retimer_set.HdmiRegNum;
2727 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) {
2728 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index =
2729 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2730 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val =
2731 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2732 }
2733 info->dp1_ext_hdmi_6g_reg_num = info_v2_1->dp1_retimer_set.Hdmi6GRegNum;
2734 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) {
2735 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2736 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2737 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2738 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2739 }
2740 info->dp2_ext_hdmi_slv_addr = info_v2_1->dp2_retimer_set.HdmiSlvAddr;
2741 info->dp2_ext_hdmi_reg_num = info_v2_1->dp2_retimer_set.HdmiRegNum;
2742 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) {
2743 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index =
2744 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2745 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val =
2746 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2747 }
2748 info->dp2_ext_hdmi_6g_reg_num = info_v2_1->dp2_retimer_set.Hdmi6GRegNum;
2749 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) {
2750 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2751 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2752 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2753 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2754 }
2755 info->dp3_ext_hdmi_slv_addr = info_v2_1->dp3_retimer_set.HdmiSlvAddr;
2756 info->dp3_ext_hdmi_reg_num = info_v2_1->dp3_retimer_set.HdmiRegNum;
2757 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) {
2758 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index =
2759 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2760 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val =
2761 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2762 }
2763 info->dp3_ext_hdmi_6g_reg_num = info_v2_1->dp3_retimer_set.Hdmi6GRegNum;
2764 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) {
2765 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2766 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2767 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2768 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2769 }
2770
2771 info->edp1_info.edp_backlight_pwm_hz =
2772 le16_to_cpu(info_v2_1->edp1_info.edp_backlight_pwm_hz);
2773 info->edp1_info.edp_ss_percentage =
2774 le16_to_cpu(info_v2_1->edp1_info.edp_ss_percentage);
2775 info->edp1_info.edp_ss_rate_10hz =
2776 le16_to_cpu(info_v2_1->edp1_info.edp_ss_rate_10hz);
2777 info->edp1_info.edp_pwr_on_off_delay =
2778 info_v2_1->edp1_info.edp_pwr_on_off_delay;
2779 info->edp1_info.edp_pwr_on_vary_bl_to_blon =
2780 info_v2_1->edp1_info.edp_pwr_on_vary_bl_to_blon;
2781 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff =
2782 info_v2_1->edp1_info.edp_pwr_down_bloff_to_vary_bloff;
2783 info->edp1_info.edp_panel_bpc =
2784 info_v2_1->edp1_info.edp_panel_bpc;
2785 info->edp1_info.edp_bootup_bl_level = info_v2_1->edp1_info.edp_bootup_bl_level;
2786
2787 info->edp2_info.edp_backlight_pwm_hz =
2788 le16_to_cpu(info_v2_1->edp2_info.edp_backlight_pwm_hz);
2789 info->edp2_info.edp_ss_percentage =
2790 le16_to_cpu(info_v2_1->edp2_info.edp_ss_percentage);
2791 info->edp2_info.edp_ss_rate_10hz =
2792 le16_to_cpu(info_v2_1->edp2_info.edp_ss_rate_10hz);
2793 info->edp2_info.edp_pwr_on_off_delay =
2794 info_v2_1->edp2_info.edp_pwr_on_off_delay;
2795 info->edp2_info.edp_pwr_on_vary_bl_to_blon =
2796 info_v2_1->edp2_info.edp_pwr_on_vary_bl_to_blon;
2797 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff =
2798 info_v2_1->edp2_info.edp_pwr_down_bloff_to_vary_bloff;
2799 info->edp2_info.edp_panel_bpc =
2800 info_v2_1->edp2_info.edp_panel_bpc;
2801 info->edp2_info.edp_bootup_bl_level =
2802 info_v2_1->edp2_info.edp_bootup_bl_level;
2803
2804 return BP_RESULT_OK;
2805 }
2806
get_integrated_info_v2_2(struct bios_parser * bp,struct integrated_info * info)2807 static enum bp_result get_integrated_info_v2_2(
2808 struct bios_parser *bp,
2809 struct integrated_info *info)
2810 {
2811 struct atom_integrated_system_info_v2_2 *info_v2_2;
2812 uint32_t i;
2813
2814 info_v2_2 = GET_IMAGE(struct atom_integrated_system_info_v2_2,
2815 DATA_TABLES(integratedsysteminfo));
2816
2817 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v2_2->gpuclk_ss_percentage);
2818
2819 if (info_v2_2 == NULL)
2820 return BP_RESULT_BADBIOSTABLE;
2821
2822 info->gpu_cap_info =
2823 le32_to_cpu(info_v2_2->gpucapinfo);
2824 /*
2825 * system_config: Bit[0] = 0 : PCIE power gating disabled
2826 * = 1 : PCIE power gating enabled
2827 * Bit[1] = 0 : DDR-PLL shut down disabled
2828 * = 1 : DDR-PLL shut down enabled
2829 * Bit[2] = 0 : DDR-PLL power down disabled
2830 * = 1 : DDR-PLL power down enabled
2831 */
2832 info->system_config = le32_to_cpu(info_v2_2->system_config);
2833 info->cpu_cap_info = le32_to_cpu(info_v2_2->cpucapinfo);
2834 info->memory_type = info_v2_2->memorytype;
2835 info->ma_channel_number = info_v2_2->umachannelnumber;
2836 info->dp_ss_control =
2837 le16_to_cpu(info_v2_2->reserved1);
2838
2839 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
2840 info->ext_disp_conn_info.gu_id[i] =
2841 info_v2_2->extdispconninfo.guid[i];
2842 }
2843
2844 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
2845 info->ext_disp_conn_info.path[i].device_connector_id =
2846 object_id_from_bios_object_id(
2847 le16_to_cpu(info_v2_2->extdispconninfo.path[i].connectorobjid));
2848
2849 info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
2850 object_id_from_bios_object_id(
2851 le16_to_cpu(
2852 info_v2_2->extdispconninfo.path[i].ext_encoder_objid));
2853
2854 info->ext_disp_conn_info.path[i].device_tag =
2855 le16_to_cpu(
2856 info_v2_2->extdispconninfo.path[i].device_tag);
2857 info->ext_disp_conn_info.path[i].device_acpi_enum =
2858 le16_to_cpu(
2859 info_v2_2->extdispconninfo.path[i].device_acpi_enum);
2860 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
2861 info_v2_2->extdispconninfo.path[i].auxddclut_index;
2862 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
2863 info_v2_2->extdispconninfo.path[i].hpdlut_index;
2864 info->ext_disp_conn_info.path[i].channel_mapping.raw =
2865 info_v2_2->extdispconninfo.path[i].channelmapping;
2866 info->ext_disp_conn_info.path[i].caps =
2867 le16_to_cpu(info_v2_2->extdispconninfo.path[i].caps);
2868 }
2869
2870 info->ext_disp_conn_info.checksum =
2871 info_v2_2->extdispconninfo.checksum;
2872 info->ext_disp_conn_info.fixdpvoltageswing =
2873 info_v2_2->extdispconninfo.fixdpvoltageswing;
2874
2875 info->edp1_info.edp_backlight_pwm_hz =
2876 le16_to_cpu(info_v2_2->edp1_info.edp_backlight_pwm_hz);
2877 info->edp1_info.edp_ss_percentage =
2878 le16_to_cpu(info_v2_2->edp1_info.edp_ss_percentage);
2879 info->edp1_info.edp_ss_rate_10hz =
2880 le16_to_cpu(info_v2_2->edp1_info.edp_ss_rate_10hz);
2881 info->edp1_info.edp_pwr_on_off_delay =
2882 info_v2_2->edp1_info.edp_pwr_on_off_delay;
2883 info->edp1_info.edp_pwr_on_vary_bl_to_blon =
2884 info_v2_2->edp1_info.edp_pwr_on_vary_bl_to_blon;
2885 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff =
2886 info_v2_2->edp1_info.edp_pwr_down_bloff_to_vary_bloff;
2887 info->edp1_info.edp_panel_bpc =
2888 info_v2_2->edp1_info.edp_panel_bpc;
2889 info->edp1_info.edp_bootup_bl_level =
2890
2891 info->edp2_info.edp_backlight_pwm_hz =
2892 le16_to_cpu(info_v2_2->edp2_info.edp_backlight_pwm_hz);
2893 info->edp2_info.edp_ss_percentage =
2894 le16_to_cpu(info_v2_2->edp2_info.edp_ss_percentage);
2895 info->edp2_info.edp_ss_rate_10hz =
2896 le16_to_cpu(info_v2_2->edp2_info.edp_ss_rate_10hz);
2897 info->edp2_info.edp_pwr_on_off_delay =
2898 info_v2_2->edp2_info.edp_pwr_on_off_delay;
2899 info->edp2_info.edp_pwr_on_vary_bl_to_blon =
2900 info_v2_2->edp2_info.edp_pwr_on_vary_bl_to_blon;
2901 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff =
2902 info_v2_2->edp2_info.edp_pwr_down_bloff_to_vary_bloff;
2903 info->edp2_info.edp_panel_bpc =
2904 info_v2_2->edp2_info.edp_panel_bpc;
2905 info->edp2_info.edp_bootup_bl_level =
2906 info_v2_2->edp2_info.edp_bootup_bl_level;
2907
2908 return BP_RESULT_OK;
2909 }
2910
2911 /*
2912 * construct_integrated_info
2913 *
2914 * @brief
2915 * Get integrated BIOS information based on table revision
2916 *
2917 * @param
2918 * bios_parser *bp - [in]BIOS parser handler to get master data table
2919 * integrated_info *info - [out] store and output integrated info
2920 *
2921 * @return
2922 * static enum bp_result - BP_RESULT_OK if information is available,
2923 * BP_RESULT_BADBIOSTABLE otherwise.
2924 */
construct_integrated_info(struct bios_parser * bp,struct integrated_info * info)2925 static enum bp_result construct_integrated_info(
2926 struct bios_parser *bp,
2927 struct integrated_info *info)
2928 {
2929 static enum bp_result result = BP_RESULT_BADBIOSTABLE;
2930
2931 struct atom_common_table_header *header;
2932 struct atom_data_revision revision;
2933
2934 struct clock_voltage_caps temp = {0, 0};
2935 uint32_t i;
2936 uint32_t j;
2937
2938 if (info && DATA_TABLES(integratedsysteminfo)) {
2939 header = GET_IMAGE(struct atom_common_table_header,
2940 DATA_TABLES(integratedsysteminfo));
2941
2942 get_atom_data_table_revision(header, &revision);
2943
2944 switch (revision.major) {
2945 case 1:
2946 switch (revision.minor) {
2947 case 11:
2948 case 12:
2949 result = get_integrated_info_v11(bp, info);
2950 break;
2951 default:
2952 return result;
2953 }
2954 break;
2955 case 2:
2956 switch (revision.minor) {
2957 case 1:
2958 result = get_integrated_info_v2_1(bp, info);
2959 break;
2960 case 2:
2961 result = get_integrated_info_v2_2(bp, info);
2962 break;
2963 default:
2964 return result;
2965 }
2966 break;
2967 default:
2968 return result;
2969 }
2970 if (result == BP_RESULT_OK) {
2971
2972 DC_LOG_BIOS("edp1:\n"
2973 "\tedp_pwr_on_off_delay = %d\n"
2974 "\tedp_pwr_on_vary_bl_to_blon = %d\n"
2975 "\tedp_pwr_down_bloff_to_vary_bloff = %d\n"
2976 "\tedp_bootup_bl_level = %d\n",
2977 info->edp1_info.edp_pwr_on_off_delay,
2978 info->edp1_info.edp_pwr_on_vary_bl_to_blon,
2979 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff,
2980 info->edp1_info.edp_bootup_bl_level);
2981 DC_LOG_BIOS("edp2:\n"
2982 "\tedp_pwr_on_off_delayv = %d\n"
2983 "\tedp_pwr_on_vary_bl_to_blon = %d\n"
2984 "\tedp_pwr_down_bloff_to_vary_bloff = %d\n"
2985 "\tedp_bootup_bl_level = %d\n",
2986 info->edp2_info.edp_pwr_on_off_delay,
2987 info->edp2_info.edp_pwr_on_vary_bl_to_blon,
2988 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff,
2989 info->edp2_info.edp_bootup_bl_level);
2990 }
2991 }
2992
2993 if (result != BP_RESULT_OK)
2994 return result;
2995 else {
2996 // Log each external path
2997 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
2998 if (info->ext_disp_conn_info.path[i].device_tag != 0)
2999 DC_LOG_BIOS("integrated_info:For EXTERNAL DISPLAY PATH %d --------------\n"
3000 "DEVICE_TAG: 0x%x\n"
3001 "DEVICE_ACPI_ENUM: 0x%x\n"
3002 "DEVICE_CONNECTOR_ID: 0x%x\n"
3003 "EXT_AUX_DDC_LUT_INDEX: %d\n"
3004 "EXT_HPD_PIN_LUT_INDEX: %d\n"
3005 "EXT_ENCODER_OBJ_ID: 0x%x\n"
3006 "Encoder CAPS: 0x%x\n",
3007 i,
3008 info->ext_disp_conn_info.path[i].device_tag,
3009 info->ext_disp_conn_info.path[i].device_acpi_enum,
3010 info->ext_disp_conn_info.path[i].device_connector_id.id,
3011 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index,
3012 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index,
3013 info->ext_disp_conn_info.path[i].ext_encoder_obj_id.id,
3014 info->ext_disp_conn_info.path[i].caps
3015 );
3016 if (info->ext_disp_conn_info.path[i].caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN)
3017 DC_LOG_BIOS("BIOS EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN on path %d\n", i);
3018 else if (bp->base.ctx->dc->config.force_bios_fixed_vs) {
3019 info->ext_disp_conn_info.path[i].caps |= EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN;
3020 DC_LOG_BIOS("driver forced EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN on path %d\n", i);
3021 }
3022 }
3023 // Log the Checksum and Voltage Swing
3024 DC_LOG_BIOS("Integrated info table CHECKSUM: %d\n"
3025 "Integrated info table FIX_DP_VOLTAGE_SWING: %d\n",
3026 info->ext_disp_conn_info.checksum,
3027 info->ext_disp_conn_info.fixdpvoltageswing);
3028 if (bp->base.ctx->dc->config.force_bios_fixed_vs && info->ext_disp_conn_info.fixdpvoltageswing == 0) {
3029 info->ext_disp_conn_info.fixdpvoltageswing = bp->base.ctx->dc->config.force_bios_fixed_vs & 0xF;
3030 DC_LOG_BIOS("driver forced fixdpvoltageswing = %d\n", info->ext_disp_conn_info.fixdpvoltageswing);
3031 }
3032 }
3033 /* Sort voltage table from low to high*/
3034 for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
3035 for (j = i; j > 0; --j) {
3036 if (info->disp_clk_voltage[j].max_supported_clk <
3037 info->disp_clk_voltage[j-1].max_supported_clk
3038 ) {
3039 /* swap j and j - 1*/
3040 temp = info->disp_clk_voltage[j-1];
3041 info->disp_clk_voltage[j-1] =
3042 info->disp_clk_voltage[j];
3043 info->disp_clk_voltage[j] = temp;
3044 }
3045 }
3046 }
3047
3048 return result;
3049 }
3050
bios_parser_get_vram_info(struct dc_bios * dcb,struct dc_vram_info * info)3051 static enum bp_result bios_parser_get_vram_info(
3052 struct dc_bios *dcb,
3053 struct dc_vram_info *info)
3054 {
3055 struct bios_parser *bp = BP_FROM_DCB(dcb);
3056 static enum bp_result result = BP_RESULT_BADBIOSTABLE;
3057 struct atom_common_table_header *header;
3058 struct atom_data_revision revision;
3059
3060 if (info && DATA_TABLES(vram_info)) {
3061 header = GET_IMAGE(struct atom_common_table_header,
3062 DATA_TABLES(vram_info));
3063
3064 get_atom_data_table_revision(header, &revision);
3065
3066 switch (revision.major) {
3067 case 2:
3068 switch (revision.minor) {
3069 case 3:
3070 result = get_vram_info_v23(bp, info);
3071 break;
3072 case 4:
3073 result = get_vram_info_v24(bp, info);
3074 break;
3075 case 5:
3076 result = get_vram_info_v25(bp, info);
3077 break;
3078 default:
3079 break;
3080 }
3081 break;
3082
3083 case 3:
3084 switch (revision.minor) {
3085 case 0:
3086 result = get_vram_info_v30(bp, info);
3087 break;
3088 default:
3089 break;
3090 }
3091 break;
3092
3093 default:
3094 return result;
3095 }
3096
3097 }
3098 return result;
3099 }
3100
bios_parser_create_integrated_info(struct dc_bios * dcb)3101 static struct integrated_info *bios_parser_create_integrated_info(
3102 struct dc_bios *dcb)
3103 {
3104 struct bios_parser *bp = BP_FROM_DCB(dcb);
3105 struct integrated_info *info = NULL;
3106
3107 info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL);
3108
3109 if (info == NULL) {
3110 ASSERT_CRITICAL(0);
3111 return NULL;
3112 }
3113
3114 if (construct_integrated_info(bp, info) == BP_RESULT_OK)
3115 return info;
3116
3117 kfree(info);
3118
3119 return NULL;
3120 }
3121
update_slot_layout_info(struct dc_bios * dcb,unsigned int i,struct slot_layout_info * slot_layout_info)3122 static enum bp_result update_slot_layout_info(
3123 struct dc_bios *dcb,
3124 unsigned int i,
3125 struct slot_layout_info *slot_layout_info)
3126 {
3127 unsigned int record_offset;
3128 unsigned int j;
3129 struct atom_display_object_path_v2 *object;
3130 struct atom_bracket_layout_record *record;
3131 struct atom_common_record_header *record_header;
3132 static enum bp_result result;
3133 struct bios_parser *bp;
3134 struct object_info_table *tbl;
3135 struct display_object_info_table_v1_4 *v1_4;
3136
3137 record = NULL;
3138 record_header = NULL;
3139 result = BP_RESULT_NORECORD;
3140
3141 bp = BP_FROM_DCB(dcb);
3142 tbl = &bp->object_info_tbl;
3143 v1_4 = tbl->v1_4;
3144
3145 object = &v1_4->display_path[i];
3146 record_offset = (unsigned int)
3147 (object->disp_recordoffset) +
3148 (unsigned int)(bp->object_info_tbl_offset);
3149
3150 for (;;) {
3151
3152 record_header = (struct atom_common_record_header *)
3153 GET_IMAGE(struct atom_common_record_header,
3154 record_offset);
3155 if (record_header == NULL) {
3156 result = BP_RESULT_BADBIOSTABLE;
3157 break;
3158 }
3159
3160 /* the end of the list */
3161 if (record_header->record_type == 0xff ||
3162 record_header->record_size == 0) {
3163 break;
3164 }
3165
3166 if (record_header->record_type ==
3167 ATOM_BRACKET_LAYOUT_RECORD_TYPE &&
3168 sizeof(struct atom_bracket_layout_record)
3169 <= record_header->record_size) {
3170 record = (struct atom_bracket_layout_record *)
3171 (record_header);
3172 result = BP_RESULT_OK;
3173 break;
3174 }
3175
3176 record_offset += record_header->record_size;
3177 }
3178
3179 /* return if the record not found */
3180 if (result != BP_RESULT_OK)
3181 return result;
3182
3183 /* get slot sizes */
3184 slot_layout_info->length = record->bracketlen;
3185 slot_layout_info->width = record->bracketwidth;
3186
3187 /* get info for each connector in the slot */
3188 slot_layout_info->num_of_connectors = record->conn_num;
3189 for (j = 0; j < slot_layout_info->num_of_connectors; ++j) {
3190 slot_layout_info->connectors[j].connector_type =
3191 (enum connector_layout_type)
3192 (record->conn_info[j].connector_type);
3193 switch (record->conn_info[j].connector_type) {
3194 case CONNECTOR_TYPE_DVI_D:
3195 slot_layout_info->connectors[j].connector_type =
3196 CONNECTOR_LAYOUT_TYPE_DVI_D;
3197 slot_layout_info->connectors[j].length =
3198 CONNECTOR_SIZE_DVI;
3199 break;
3200
3201 case CONNECTOR_TYPE_HDMI:
3202 slot_layout_info->connectors[j].connector_type =
3203 CONNECTOR_LAYOUT_TYPE_HDMI;
3204 slot_layout_info->connectors[j].length =
3205 CONNECTOR_SIZE_HDMI;
3206 break;
3207
3208 case CONNECTOR_TYPE_DISPLAY_PORT:
3209 slot_layout_info->connectors[j].connector_type =
3210 CONNECTOR_LAYOUT_TYPE_DP;
3211 slot_layout_info->connectors[j].length =
3212 CONNECTOR_SIZE_DP;
3213 break;
3214
3215 case CONNECTOR_TYPE_MINI_DISPLAY_PORT:
3216 slot_layout_info->connectors[j].connector_type =
3217 CONNECTOR_LAYOUT_TYPE_MINI_DP;
3218 slot_layout_info->connectors[j].length =
3219 CONNECTOR_SIZE_MINI_DP;
3220 break;
3221
3222 default:
3223 slot_layout_info->connectors[j].connector_type =
3224 CONNECTOR_LAYOUT_TYPE_UNKNOWN;
3225 slot_layout_info->connectors[j].length =
3226 CONNECTOR_SIZE_UNKNOWN;
3227 }
3228
3229 slot_layout_info->connectors[j].position =
3230 record->conn_info[j].position;
3231 slot_layout_info->connectors[j].connector_id =
3232 object_id_from_bios_object_id(
3233 record->conn_info[j].connectorobjid);
3234 }
3235 return result;
3236 }
3237
update_slot_layout_info_v2(struct dc_bios * dcb,unsigned int i,struct slot_layout_info * slot_layout_info)3238 static enum bp_result update_slot_layout_info_v2(
3239 struct dc_bios *dcb,
3240 unsigned int i,
3241 struct slot_layout_info *slot_layout_info)
3242 {
3243 unsigned int record_offset;
3244 struct atom_display_object_path_v3 *object;
3245 struct atom_bracket_layout_record_v2 *record;
3246 struct atom_common_record_header *record_header;
3247 static enum bp_result result;
3248 struct bios_parser *bp;
3249 struct object_info_table *tbl;
3250 struct display_object_info_table_v1_5 *v1_5;
3251 struct graphics_object_id connector_id;
3252
3253 record = NULL;
3254 record_header = NULL;
3255 result = BP_RESULT_NORECORD;
3256
3257 bp = BP_FROM_DCB(dcb);
3258 tbl = &bp->object_info_tbl;
3259 v1_5 = tbl->v1_5;
3260
3261 object = &v1_5->display_path[i];
3262 record_offset = (unsigned int)
3263 (object->disp_recordoffset) +
3264 (unsigned int)(bp->object_info_tbl_offset);
3265
3266 for (;;) {
3267
3268 record_header = (struct atom_common_record_header *)
3269 GET_IMAGE(struct atom_common_record_header,
3270 record_offset);
3271 if (record_header == NULL) {
3272 result = BP_RESULT_BADBIOSTABLE;
3273 break;
3274 }
3275
3276 /* the end of the list */
3277 if (record_header->record_type == ATOM_RECORD_END_TYPE ||
3278 record_header->record_size == 0) {
3279 break;
3280 }
3281
3282 if (record_header->record_type ==
3283 ATOM_BRACKET_LAYOUT_V2_RECORD_TYPE &&
3284 sizeof(struct atom_bracket_layout_record_v2)
3285 <= record_header->record_size) {
3286 record = (struct atom_bracket_layout_record_v2 *)
3287 (record_header);
3288 result = BP_RESULT_OK;
3289 break;
3290 }
3291
3292 record_offset += record_header->record_size;
3293 }
3294
3295 /* return if the record not found */
3296 if (result != BP_RESULT_OK)
3297 return result;
3298
3299 /* get slot sizes */
3300 connector_id = object_id_from_bios_object_id(object->display_objid);
3301
3302 slot_layout_info->length = record->bracketlen;
3303 slot_layout_info->width = record->bracketwidth;
3304 slot_layout_info->num_of_connectors = v1_5->number_of_path;
3305 slot_layout_info->connectors[i].position = record->conn_num;
3306 slot_layout_info->connectors[i].connector_id = connector_id;
3307
3308 switch (connector_id.id) {
3309 case CONNECTOR_ID_SINGLE_LINK_DVID:
3310 case CONNECTOR_ID_DUAL_LINK_DVID:
3311 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DVI_D;
3312 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DVI;
3313 break;
3314
3315 case CONNECTOR_ID_HDMI_TYPE_A:
3316 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_HDMI;
3317 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_HDMI;
3318 break;
3319
3320 case CONNECTOR_ID_DISPLAY_PORT:
3321 case CONNECTOR_ID_USBC:
3322 if (record->mini_type == MINI_TYPE_NORMAL) {
3323 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DP;
3324 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DP;
3325 } else {
3326 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_MINI_DP;
3327 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_MINI_DP;
3328 }
3329 break;
3330
3331 default:
3332 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_UNKNOWN;
3333 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_UNKNOWN;
3334 }
3335 return result;
3336 }
3337
get_bracket_layout_record(struct dc_bios * dcb,unsigned int bracket_layout_id,struct slot_layout_info * slot_layout_info)3338 static enum bp_result get_bracket_layout_record(
3339 struct dc_bios *dcb,
3340 unsigned int bracket_layout_id,
3341 struct slot_layout_info *slot_layout_info)
3342 {
3343 unsigned int i;
3344 struct bios_parser *bp = BP_FROM_DCB(dcb);
3345 static enum bp_result result;
3346 struct object_info_table *tbl;
3347 struct display_object_info_table_v1_4 *v1_4;
3348 struct display_object_info_table_v1_5 *v1_5;
3349
3350 if (slot_layout_info == NULL) {
3351 DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n");
3352 return BP_RESULT_BADINPUT;
3353 }
3354 tbl = &bp->object_info_tbl;
3355 v1_4 = tbl->v1_4;
3356 v1_5 = tbl->v1_5;
3357
3358 result = BP_RESULT_NORECORD;
3359 switch (bp->object_info_tbl.revision.minor) {
3360 case 4:
3361 default:
3362 for (i = 0; i < v1_4->number_of_path; ++i) {
3363 if (bracket_layout_id ==
3364 v1_4->display_path[i].display_objid) {
3365 result = update_slot_layout_info(dcb, i, slot_layout_info);
3366 break;
3367 }
3368 }
3369 break;
3370 case 5:
3371 for (i = 0; i < v1_5->number_of_path; ++i)
3372 result = update_slot_layout_info_v2(dcb, i, slot_layout_info);
3373 break;
3374 }
3375 return result;
3376 }
3377
bios_get_board_layout_info(struct dc_bios * dcb,struct board_layout_info * board_layout_info)3378 static enum bp_result bios_get_board_layout_info(
3379 struct dc_bios *dcb,
3380 struct board_layout_info *board_layout_info)
3381 {
3382 unsigned int i;
3383
3384 struct bios_parser *bp;
3385
3386 static enum bp_result record_result;
3387 unsigned int max_slots;
3388
3389 const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = {
3390 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1,
3391 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2,
3392 0, 0
3393 };
3394
3395
3396 bp = BP_FROM_DCB(dcb);
3397
3398 if (board_layout_info == NULL) {
3399 DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n");
3400 return BP_RESULT_BADINPUT;
3401 }
3402
3403 board_layout_info->num_of_slots = 0;
3404 max_slots = MAX_BOARD_SLOTS;
3405
3406 // Assume single slot on v1_5
3407 if (bp->object_info_tbl.revision.minor == 5) {
3408 max_slots = 1;
3409 }
3410
3411 for (i = 0; i < max_slots; ++i) {
3412 record_result = get_bracket_layout_record(dcb,
3413 slot_index_to_vbios_id[i],
3414 &board_layout_info->slots[i]);
3415
3416 if (record_result == BP_RESULT_NORECORD && i > 0)
3417 break; /* no more slots present in bios */
3418 else if (record_result != BP_RESULT_OK)
3419 return record_result; /* fail */
3420
3421 ++board_layout_info->num_of_slots;
3422 }
3423
3424 /* all data is valid */
3425 board_layout_info->is_number_of_slots_valid = 1;
3426 board_layout_info->is_slots_size_valid = 1;
3427 board_layout_info->is_connector_offsets_valid = 1;
3428 board_layout_info->is_connector_lengths_valid = 1;
3429
3430 return BP_RESULT_OK;
3431 }
3432
3433
bios_parser_pack_data_tables(struct dc_bios * dcb,void * dst)3434 static uint16_t bios_parser_pack_data_tables(
3435 struct dc_bios *dcb,
3436 void *dst)
3437 {
3438 // TODO: There is data bytes alignment issue, disable it for now.
3439 return 0;
3440 }
3441
bios_get_golden_table(struct bios_parser * bp,uint32_t rev_major,uint32_t rev_minor,uint16_t * dc_golden_table_ver)3442 static struct atom_dc_golden_table_v1 *bios_get_golden_table(
3443 struct bios_parser *bp,
3444 uint32_t rev_major,
3445 uint32_t rev_minor,
3446 uint16_t *dc_golden_table_ver)
3447 {
3448 struct atom_display_controller_info_v4_4 *disp_cntl_tbl_4_4 = NULL;
3449 uint32_t dc_golden_offset = 0;
3450 *dc_golden_table_ver = 0;
3451
3452 if (!DATA_TABLES(dce_info))
3453 return NULL;
3454
3455 /* ver.4.4 or higher */
3456 switch (rev_major) {
3457 case 4:
3458 switch (rev_minor) {
3459 case 4:
3460 disp_cntl_tbl_4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4,
3461 DATA_TABLES(dce_info));
3462 if (!disp_cntl_tbl_4_4)
3463 return NULL;
3464 dc_golden_offset = DATA_TABLES(dce_info) + disp_cntl_tbl_4_4->dc_golden_table_offset;
3465 *dc_golden_table_ver = disp_cntl_tbl_4_4->dc_golden_table_ver;
3466 break;
3467 case 5:
3468 default:
3469 /* For atom_display_controller_info_v4_5 there is no need to get golden table from
3470 * dc_golden_table_offset as all these fields previously in golden table used for AUX
3471 * pre-charge settings are now available directly in atom_display_controller_info_v4_5.
3472 */
3473 break;
3474 }
3475 break;
3476 }
3477
3478 if (!dc_golden_offset)
3479 return NULL;
3480
3481 if (*dc_golden_table_ver != 1)
3482 return NULL;
3483
3484 return GET_IMAGE(struct atom_dc_golden_table_v1,
3485 dc_golden_offset);
3486 }
3487
bios_get_atom_dc_golden_table(struct dc_bios * dcb)3488 static enum bp_result bios_get_atom_dc_golden_table(
3489 struct dc_bios *dcb)
3490 {
3491 struct bios_parser *bp = BP_FROM_DCB(dcb);
3492 enum bp_result result = BP_RESULT_OK;
3493 struct atom_dc_golden_table_v1 *atom_dc_golden_table = NULL;
3494 struct atom_common_table_header *header;
3495 struct atom_data_revision tbl_revision;
3496 uint16_t dc_golden_table_ver = 0;
3497
3498 header = GET_IMAGE(struct atom_common_table_header,
3499 DATA_TABLES(dce_info));
3500 if (!header)
3501 return BP_RESULT_UNSUPPORTED;
3502
3503 get_atom_data_table_revision(header, &tbl_revision);
3504
3505 atom_dc_golden_table = bios_get_golden_table(bp,
3506 tbl_revision.major,
3507 tbl_revision.minor,
3508 &dc_golden_table_ver);
3509
3510 if (!atom_dc_golden_table)
3511 return BP_RESULT_UNSUPPORTED;
3512
3513 dcb->golden_table.dc_golden_table_ver = dc_golden_table_ver;
3514 dcb->golden_table.aux_dphy_rx_control0_val = atom_dc_golden_table->aux_dphy_rx_control0_val;
3515 dcb->golden_table.aux_dphy_rx_control1_val = atom_dc_golden_table->aux_dphy_rx_control1_val;
3516 dcb->golden_table.aux_dphy_tx_control_val = atom_dc_golden_table->aux_dphy_tx_control_val;
3517 dcb->golden_table.dc_gpio_aux_ctrl_0_val = atom_dc_golden_table->dc_gpio_aux_ctrl_0_val;
3518 dcb->golden_table.dc_gpio_aux_ctrl_1_val = atom_dc_golden_table->dc_gpio_aux_ctrl_1_val;
3519 dcb->golden_table.dc_gpio_aux_ctrl_2_val = atom_dc_golden_table->dc_gpio_aux_ctrl_2_val;
3520 dcb->golden_table.dc_gpio_aux_ctrl_3_val = atom_dc_golden_table->dc_gpio_aux_ctrl_3_val;
3521 dcb->golden_table.dc_gpio_aux_ctrl_4_val = atom_dc_golden_table->dc_gpio_aux_ctrl_4_val;
3522 dcb->golden_table.dc_gpio_aux_ctrl_5_val = atom_dc_golden_table->dc_gpio_aux_ctrl_5_val;
3523
3524 return result;
3525 }
3526
3527
3528 static const struct dc_vbios_funcs vbios_funcs = {
3529 .get_connectors_number = bios_parser_get_connectors_number,
3530
3531 .get_connector_id = bios_parser_get_connector_id,
3532
3533 .get_src_obj = bios_parser_get_src_obj,
3534
3535 .get_i2c_info = bios_parser_get_i2c_info,
3536
3537 .get_hpd_info = bios_parser_get_hpd_info,
3538
3539 .get_device_tag = bios_parser_get_device_tag,
3540
3541 .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info,
3542
3543 .get_ss_entry_number = bios_parser_get_ss_entry_number,
3544
3545 .get_embedded_panel_info = bios_parser_get_embedded_panel_info,
3546
3547 .get_gpio_pin_info = bios_parser_get_gpio_pin_info,
3548
3549 .get_encoder_cap_info = bios_parser_get_encoder_cap_info,
3550
3551 .is_device_id_supported = bios_parser_is_device_id_supported,
3552
3553 .is_accelerated_mode = bios_parser_is_accelerated_mode,
3554
3555 .set_scratch_critical_state = bios_parser_set_scratch_critical_state,
3556
3557
3558 /* COMMANDS */
3559 .encoder_control = bios_parser_encoder_control,
3560
3561 .transmitter_control = bios_parser_transmitter_control,
3562
3563 .enable_crtc = bios_parser_enable_crtc,
3564
3565 .set_pixel_clock = bios_parser_set_pixel_clock,
3566
3567 .set_dce_clock = bios_parser_set_dce_clock,
3568
3569 .program_crtc_timing = bios_parser_program_crtc_timing,
3570
3571 .enable_disp_power_gating = bios_parser_enable_disp_power_gating,
3572
3573 .bios_parser_destroy = firmware_parser_destroy,
3574
3575 .get_board_layout_info = bios_get_board_layout_info,
3576 /* TODO: use this fn in hw init?*/
3577 .pack_data_tables = bios_parser_pack_data_tables,
3578
3579 .get_atom_dc_golden_table = bios_get_atom_dc_golden_table,
3580
3581 .enable_lvtma_control = bios_parser_enable_lvtma_control,
3582
3583 .get_soc_bb_info = bios_parser_get_soc_bb_info,
3584
3585 .get_disp_connector_caps_info = bios_parser_get_disp_connector_caps_info,
3586
3587 .get_lttpr_caps = bios_parser_get_lttpr_caps,
3588
3589 .get_lttpr_interop = bios_parser_get_lttpr_interop,
3590
3591 .get_connector_speed_cap_info = bios_parser_get_connector_speed_cap_info,
3592 };
3593
bios_parser2_construct(struct bios_parser * bp,struct bp_init_data * init,enum dce_version dce_version)3594 static bool bios_parser2_construct(
3595 struct bios_parser *bp,
3596 struct bp_init_data *init,
3597 enum dce_version dce_version)
3598 {
3599 uint16_t *rom_header_offset = NULL;
3600 struct atom_rom_header_v2_2 *rom_header = NULL;
3601 struct display_object_info_table_v1_4 *object_info_tbl;
3602 struct atom_data_revision tbl_rev = {0};
3603
3604 if (!init)
3605 return false;
3606
3607 if (!init->bios)
3608 return false;
3609
3610 bp->base.funcs = &vbios_funcs;
3611 bp->base.bios = init->bios;
3612 bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT;
3613
3614 bp->base.ctx = init->ctx;
3615
3616 bp->base.bios_local_image = NULL;
3617
3618 rom_header_offset =
3619 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER);
3620
3621 if (!rom_header_offset)
3622 return false;
3623
3624 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset);
3625
3626 if (!rom_header)
3627 return false;
3628
3629 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev);
3630 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2))
3631 return false;
3632
3633 bp->master_data_tbl =
3634 GET_IMAGE(struct atom_master_data_table_v2_1,
3635 rom_header->masterdatatable_offset);
3636
3637 if (!bp->master_data_tbl)
3638 return false;
3639
3640 bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo);
3641
3642 if (!bp->object_info_tbl_offset)
3643 return false;
3644
3645 object_info_tbl =
3646 GET_IMAGE(struct display_object_info_table_v1_4,
3647 bp->object_info_tbl_offset);
3648
3649 if (!object_info_tbl)
3650 return false;
3651
3652 get_atom_data_table_revision(&object_info_tbl->table_header,
3653 &bp->object_info_tbl.revision);
3654
3655 if (bp->object_info_tbl.revision.major == 1
3656 && bp->object_info_tbl.revision.minor == 4) {
3657 struct display_object_info_table_v1_4 *tbl_v1_4;
3658
3659 tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4,
3660 bp->object_info_tbl_offset);
3661 if (!tbl_v1_4)
3662 return false;
3663
3664 bp->object_info_tbl.v1_4 = tbl_v1_4;
3665 } else if (bp->object_info_tbl.revision.major == 1
3666 && bp->object_info_tbl.revision.minor == 5) {
3667 struct display_object_info_table_v1_5 *tbl_v1_5;
3668
3669 tbl_v1_5 = GET_IMAGE(struct display_object_info_table_v1_5,
3670 bp->object_info_tbl_offset);
3671 if (!tbl_v1_5)
3672 return false;
3673
3674 bp->object_info_tbl.v1_5 = tbl_v1_5;
3675 } else {
3676 ASSERT(0);
3677 return false;
3678 }
3679
3680 dal_firmware_parser_init_cmd_tbl(bp);
3681 dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version);
3682
3683 bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);
3684 bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK;
3685 bios_parser_get_vram_info(&bp->base, &bp->base.vram_info);
3686
3687 return true;
3688 }
3689
firmware_parser_create(struct bp_init_data * init,enum dce_version dce_version)3690 struct dc_bios *firmware_parser_create(
3691 struct bp_init_data *init,
3692 enum dce_version dce_version)
3693 {
3694 struct bios_parser *bp = NULL;
3695
3696 bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL);
3697 if (!bp)
3698 return NULL;
3699
3700 if (bios_parser2_construct(bp, init, dce_version))
3701 return &bp->base;
3702
3703 kfree(bp);
3704 return NULL;
3705 }
3706
3707
3708
