1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/slab.h>
27
28 #include "dm_services.h"
29
30 #include "ObjectID.h"
31 #include "atomfirmware.h"
32
33 #include "dc_bios_types.h"
34 #include "include/grph_object_ctrl_defs.h"
35 #include "include/bios_parser_interface.h"
36 #include "include/i2caux_interface.h"
37 #include "include/logger_interface.h"
38
39 #include "command_table2.h"
40
41 #include "bios_parser_helper.h"
42 #include "command_table_helper2.h"
43 #include "bios_parser2.h"
44 #include "bios_parser_types_internal2.h"
45 #include "bios_parser_interface.h"
46
47 #include "bios_parser_common.h"
48
49 /* Temporarily add in defines until ObjectID.h patch is updated in a few days */
50 #ifndef GENERIC_OBJECT_ID_BRACKET_LAYOUT
51 #define GENERIC_OBJECT_ID_BRACKET_LAYOUT 0x05
52 #endif /* GENERIC_OBJECT_ID_BRACKET_LAYOUT */
53
54 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1
55 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 \
56 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
57 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
58 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT)
59 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 */
60
61 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2
62 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 \
63 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
64 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
65 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT)
66 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 */
67
68 #define DC_LOGGER \
69 bp->base.ctx->logger
70
71 #define LAST_RECORD_TYPE 0xff
72 #define SMU9_SYSPLL0_ID 0
73
74 struct i2c_id_config_access {
75 uint8_t bfI2C_LineMux:4;
76 uint8_t bfHW_EngineID:3;
77 uint8_t bfHW_Capable:1;
78 uint8_t ucAccess;
79 };
80
81 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp,
82 struct atom_i2c_record *record,
83 struct graphics_object_i2c_info *info);
84
85 static enum bp_result bios_parser_get_firmware_info(
86 struct dc_bios *dcb,
87 struct dc_firmware_info *info);
88
89 static enum bp_result bios_parser_get_encoder_cap_info(
90 struct dc_bios *dcb,
91 struct graphics_object_id object_id,
92 struct bp_encoder_cap_info *info);
93
94 static enum bp_result get_firmware_info_v3_1(
95 struct bios_parser *bp,
96 struct dc_firmware_info *info);
97
98 static enum bp_result get_firmware_info_v3_2(
99 struct bios_parser *bp,
100 struct dc_firmware_info *info);
101
102 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp,
103 struct atom_display_object_path_v2 *object);
104
105 static struct atom_encoder_caps_record *get_encoder_cap_record(
106 struct bios_parser *bp,
107 struct atom_display_object_path_v2 *object);
108
109 #define BIOS_IMAGE_SIZE_OFFSET 2
110 #define BIOS_IMAGE_SIZE_UNIT 512
111
112 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table)
113
bios_parser2_destruct(struct bios_parser * bp)114 static void bios_parser2_destruct(struct bios_parser *bp)
115 {
116 kfree(bp->base.bios_local_image);
117 kfree(bp->base.integrated_info);
118 }
119
firmware_parser_destroy(struct dc_bios ** dcb)120 static void firmware_parser_destroy(struct dc_bios **dcb)
121 {
122 struct bios_parser *bp = BP_FROM_DCB(*dcb);
123
124 if (!bp) {
125 BREAK_TO_DEBUGGER();
126 return;
127 }
128
129 bios_parser2_destruct(bp);
130
131 kfree(bp);
132 *dcb = NULL;
133 }
134
get_atom_data_table_revision(struct atom_common_table_header * atom_data_tbl,struct atom_data_revision * tbl_revision)135 static void get_atom_data_table_revision(
136 struct atom_common_table_header *atom_data_tbl,
137 struct atom_data_revision *tbl_revision)
138 {
139 if (!tbl_revision)
140 return;
141
142 /* initialize the revision to 0 which is invalid revision */
143 tbl_revision->major = 0;
144 tbl_revision->minor = 0;
145
146 if (!atom_data_tbl)
147 return;
148
149 tbl_revision->major =
150 (uint32_t) atom_data_tbl->format_revision & 0x3f;
151 tbl_revision->minor =
152 (uint32_t) atom_data_tbl->content_revision & 0x3f;
153 }
154
155 /* BIOS oject table displaypath is per connector.
156 * There is extra path not for connector. BIOS fill its encoderid as 0
157 */
bios_parser_get_connectors_number(struct dc_bios * dcb)158 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb)
159 {
160 struct bios_parser *bp = BP_FROM_DCB(dcb);
161 unsigned int count = 0;
162 unsigned int i;
163
164 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
165 if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0)
166 count++;
167 }
168 return count;
169 }
170
bios_parser_get_connector_id(struct dc_bios * dcb,uint8_t i)171 static struct graphics_object_id bios_parser_get_connector_id(
172 struct dc_bios *dcb,
173 uint8_t i)
174 {
175 struct bios_parser *bp = BP_FROM_DCB(dcb);
176 struct graphics_object_id object_id = dal_graphics_object_id_init(
177 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN);
178 struct object_info_table *tbl = &bp->object_info_tbl;
179 struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4;
180
181 if (v1_4->number_of_path > i) {
182 /* If display_objid is generic object id, the encoderObj
183 * /extencoderobjId should be 0
184 */
185 if (v1_4->display_path[i].encoderobjid != 0 &&
186 v1_4->display_path[i].display_objid != 0)
187 object_id = object_id_from_bios_object_id(
188 v1_4->display_path[i].display_objid);
189 }
190
191 return object_id;
192 }
193
bios_parser_get_src_obj(struct dc_bios * dcb,struct graphics_object_id object_id,uint32_t index,struct graphics_object_id * src_object_id)194 static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb,
195 struct graphics_object_id object_id, uint32_t index,
196 struct graphics_object_id *src_object_id)
197 {
198 struct bios_parser *bp = BP_FROM_DCB(dcb);
199 unsigned int i;
200 enum bp_result bp_result = BP_RESULT_BADINPUT;
201 struct graphics_object_id obj_id = {0};
202 struct object_info_table *tbl = &bp->object_info_tbl;
203
204 if (!src_object_id)
205 return bp_result;
206
207 switch (object_id.type) {
208 /* Encoder's Source is GPU. BIOS does not provide GPU, since all
209 * displaypaths point to same GPU (0x1100). Hardcode GPU object type
210 */
211 case OBJECT_TYPE_ENCODER:
212 /* TODO: since num of src must be less than 2.
213 * If found in for loop, should break.
214 * DAL2 implementation may be changed too
215 */
216 for (i = 0; i < tbl->v1_4->number_of_path; i++) {
217 obj_id = object_id_from_bios_object_id(
218 tbl->v1_4->display_path[i].encoderobjid);
219 if (object_id.type == obj_id.type &&
220 object_id.id == obj_id.id &&
221 object_id.enum_id ==
222 obj_id.enum_id) {
223 *src_object_id =
224 object_id_from_bios_object_id(0x1100);
225 /* break; */
226 }
227 }
228 bp_result = BP_RESULT_OK;
229 break;
230 case OBJECT_TYPE_CONNECTOR:
231 for (i = 0; i < tbl->v1_4->number_of_path; i++) {
232 obj_id = object_id_from_bios_object_id(
233 tbl->v1_4->display_path[i].display_objid);
234
235 if (object_id.type == obj_id.type &&
236 object_id.id == obj_id.id &&
237 object_id.enum_id == obj_id.enum_id) {
238 *src_object_id =
239 object_id_from_bios_object_id(
240 tbl->v1_4->display_path[i].encoderobjid);
241 /* break; */
242 }
243 }
244 bp_result = BP_RESULT_OK;
245 break;
246 default:
247 break;
248 }
249
250 return bp_result;
251 }
252
253 /* from graphics_object_id, find display path which includes the object_id */
get_bios_object(struct bios_parser * bp,struct graphics_object_id id)254 static struct atom_display_object_path_v2 *get_bios_object(
255 struct bios_parser *bp,
256 struct graphics_object_id id)
257 {
258 unsigned int i;
259 struct graphics_object_id obj_id = {0};
260
261 switch (id.type) {
262 case OBJECT_TYPE_ENCODER:
263 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
264 obj_id = object_id_from_bios_object_id(
265 bp->object_info_tbl.v1_4->display_path[i].encoderobjid);
266 if (id.type == obj_id.type && id.id == obj_id.id
267 && id.enum_id == obj_id.enum_id)
268 return &bp->object_info_tbl.v1_4->display_path[i];
269 }
270 fallthrough;
271 case OBJECT_TYPE_CONNECTOR:
272 case OBJECT_TYPE_GENERIC:
273 /* Both Generic and Connector Object ID
274 * will be stored on display_objid
275 */
276 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
277 obj_id = object_id_from_bios_object_id(
278 bp->object_info_tbl.v1_4->display_path[i].display_objid);
279 if (id.type == obj_id.type && id.id == obj_id.id
280 && id.enum_id == obj_id.enum_id)
281 return &bp->object_info_tbl.v1_4->display_path[i];
282 }
283 fallthrough;
284 default:
285 return NULL;
286 }
287 }
288
bios_parser_get_i2c_info(struct dc_bios * dcb,struct graphics_object_id id,struct graphics_object_i2c_info * info)289 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb,
290 struct graphics_object_id id,
291 struct graphics_object_i2c_info *info)
292 {
293 uint32_t offset;
294 struct atom_display_object_path_v2 *object;
295 struct atom_common_record_header *header;
296 struct atom_i2c_record *record;
297 struct atom_i2c_record dummy_record = {0};
298 struct bios_parser *bp = BP_FROM_DCB(dcb);
299
300 if (!info)
301 return BP_RESULT_BADINPUT;
302
303 if (id.type == OBJECT_TYPE_GENERIC) {
304 dummy_record.i2c_id = id.id;
305
306 if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK)
307 return BP_RESULT_OK;
308 else
309 return BP_RESULT_NORECORD;
310 }
311
312 object = get_bios_object(bp, id);
313
314 if (!object)
315 return BP_RESULT_BADINPUT;
316
317 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
318
319 for (;;) {
320 header = GET_IMAGE(struct atom_common_record_header, offset);
321
322 if (!header)
323 return BP_RESULT_BADBIOSTABLE;
324
325 if (header->record_type == LAST_RECORD_TYPE ||
326 !header->record_size)
327 break;
328
329 if (header->record_type == ATOM_I2C_RECORD_TYPE
330 && sizeof(struct atom_i2c_record) <=
331 header->record_size) {
332 /* get the I2C info */
333 record = (struct atom_i2c_record *) header;
334
335 if (get_gpio_i2c_info(bp, record, info) ==
336 BP_RESULT_OK)
337 return BP_RESULT_OK;
338 }
339
340 offset += header->record_size;
341 }
342
343 return BP_RESULT_NORECORD;
344 }
345
get_gpio_i2c_info(struct bios_parser * bp,struct atom_i2c_record * record,struct graphics_object_i2c_info * info)346 static enum bp_result get_gpio_i2c_info(
347 struct bios_parser *bp,
348 struct atom_i2c_record *record,
349 struct graphics_object_i2c_info *info)
350 {
351 struct atom_gpio_pin_lut_v2_1 *header;
352 uint32_t count = 0;
353 unsigned int table_index = 0;
354 bool find_valid = false;
355
356 if (!info)
357 return BP_RESULT_BADINPUT;
358
359 /* get the GPIO_I2C info */
360 if (!DATA_TABLES(gpio_pin_lut))
361 return BP_RESULT_BADBIOSTABLE;
362
363 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1,
364 DATA_TABLES(gpio_pin_lut));
365 if (!header)
366 return BP_RESULT_BADBIOSTABLE;
367
368 if (sizeof(struct atom_common_table_header) +
369 sizeof(struct atom_gpio_pin_assignment) >
370 le16_to_cpu(header->table_header.structuresize))
371 return BP_RESULT_BADBIOSTABLE;
372
373 /* TODO: is version change? */
374 if (header->table_header.content_revision != 1)
375 return BP_RESULT_UNSUPPORTED;
376
377 /* get data count */
378 count = (le16_to_cpu(header->table_header.structuresize)
379 - sizeof(struct atom_common_table_header))
380 / sizeof(struct atom_gpio_pin_assignment);
381
382 for (table_index = 0; table_index < count; table_index++) {
383 if (((record->i2c_id & I2C_HW_CAP) == (
384 header->gpio_pin[table_index].gpio_id &
385 I2C_HW_CAP)) &&
386 ((record->i2c_id & I2C_HW_ENGINE_ID_MASK) ==
387 (header->gpio_pin[table_index].gpio_id &
388 I2C_HW_ENGINE_ID_MASK)) &&
389 ((record->i2c_id & I2C_HW_LANE_MUX) ==
390 (header->gpio_pin[table_index].gpio_id &
391 I2C_HW_LANE_MUX))) {
392 /* still valid */
393 find_valid = true;
394 break;
395 }
396 }
397
398 /* If we don't find the entry that we are looking for then
399 * we will return BP_Result_BadBiosTable.
400 */
401 if (find_valid == false)
402 return BP_RESULT_BADBIOSTABLE;
403
404 /* get the GPIO_I2C_INFO */
405 info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false;
406 info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX;
407 info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4;
408 info->i2c_slave_address = record->i2c_slave_addr;
409
410 /* TODO: check how to get register offset for en, Y, etc. */
411 info->gpio_info.clk_a_register_index =
412 le16_to_cpu(
413 header->gpio_pin[table_index].data_a_reg_index);
414 info->gpio_info.clk_a_shift =
415 header->gpio_pin[table_index].gpio_bitshift;
416
417 return BP_RESULT_OK;
418 }
419
bios_parser_get_hpd_info(struct dc_bios * dcb,struct graphics_object_id id,struct graphics_object_hpd_info * info)420 static enum bp_result bios_parser_get_hpd_info(
421 struct dc_bios *dcb,
422 struct graphics_object_id id,
423 struct graphics_object_hpd_info *info)
424 {
425 struct bios_parser *bp = BP_FROM_DCB(dcb);
426 struct atom_display_object_path_v2 *object;
427 struct atom_hpd_int_record *record = NULL;
428
429 if (!info)
430 return BP_RESULT_BADINPUT;
431
432 object = get_bios_object(bp, id);
433
434 if (!object)
435 return BP_RESULT_BADINPUT;
436
437 record = get_hpd_record(bp, object);
438
439 if (record != NULL) {
440 info->hpd_int_gpio_uid = record->pin_id;
441 info->hpd_active = record->plugin_pin_state;
442 return BP_RESULT_OK;
443 }
444
445 return BP_RESULT_NORECORD;
446 }
447
get_hpd_record(struct bios_parser * bp,struct atom_display_object_path_v2 * object)448 static struct atom_hpd_int_record *get_hpd_record(
449 struct bios_parser *bp,
450 struct atom_display_object_path_v2 *object)
451 {
452 struct atom_common_record_header *header;
453 uint32_t offset;
454
455 if (!object) {
456 BREAK_TO_DEBUGGER(); /* Invalid object */
457 return NULL;
458 }
459
460 offset = le16_to_cpu(object->disp_recordoffset)
461 + bp->object_info_tbl_offset;
462
463 for (;;) {
464 header = GET_IMAGE(struct atom_common_record_header, offset);
465
466 if (!header)
467 return NULL;
468
469 if (header->record_type == LAST_RECORD_TYPE ||
470 !header->record_size)
471 break;
472
473 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE
474 && sizeof(struct atom_hpd_int_record) <=
475 header->record_size)
476 return (struct atom_hpd_int_record *) header;
477
478 offset += header->record_size;
479 }
480
481 return NULL;
482 }
483
484 /**
485 * bios_parser_get_gpio_pin_info
486 * Get GpioPin information of input gpio id
487 *
488 * @param gpio_id, GPIO ID
489 * @param info, GpioPin information structure
490 * @return Bios parser result code
491 * @note
492 * to get the GPIO PIN INFO, we need:
493 * 1. get the GPIO_ID from other object table, see GetHPDInfo()
494 * 2. in DATA_TABLE.GPIO_Pin_LUT, search all records,
495 * to get the registerA offset/mask
496 */
bios_parser_get_gpio_pin_info(struct dc_bios * dcb,uint32_t gpio_id,struct gpio_pin_info * info)497 static enum bp_result bios_parser_get_gpio_pin_info(
498 struct dc_bios *dcb,
499 uint32_t gpio_id,
500 struct gpio_pin_info *info)
501 {
502 struct bios_parser *bp = BP_FROM_DCB(dcb);
503 struct atom_gpio_pin_lut_v2_1 *header;
504 uint32_t count = 0;
505 uint32_t i = 0;
506
507 if (!DATA_TABLES(gpio_pin_lut))
508 return BP_RESULT_BADBIOSTABLE;
509
510 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1,
511 DATA_TABLES(gpio_pin_lut));
512 if (!header)
513 return BP_RESULT_BADBIOSTABLE;
514
515 if (sizeof(struct atom_common_table_header) +
516 sizeof(struct atom_gpio_pin_assignment)
517 > le16_to_cpu(header->table_header.structuresize))
518 return BP_RESULT_BADBIOSTABLE;
519
520 if (header->table_header.content_revision != 1)
521 return BP_RESULT_UNSUPPORTED;
522
523 /* Temporary hard code gpio pin info */
524 #if defined(FOR_SIMNOW_BOOT)
525 {
526 struct atom_gpio_pin_assignment gpio_pin[8] = {
527 {0x5db5, 0, 0, 1, 0},
528 {0x5db5, 8, 8, 2, 0},
529 {0x5db5, 0x10, 0x10, 3, 0},
530 {0x5db5, 0x18, 0x14, 4, 0},
531 {0x5db5, 0x1A, 0x18, 5, 0},
532 {0x5db5, 0x1C, 0x1C, 6, 0},
533 };
534
535 count = 6;
536 memmove(header->gpio_pin, gpio_pin, sizeof(gpio_pin));
537 }
538 #else
539 count = (le16_to_cpu(header->table_header.structuresize)
540 - sizeof(struct atom_common_table_header))
541 / sizeof(struct atom_gpio_pin_assignment);
542 #endif
543 for (i = 0; i < count; ++i) {
544 if (header->gpio_pin[i].gpio_id != gpio_id)
545 continue;
546
547 info->offset =
548 (uint32_t) le16_to_cpu(
549 header->gpio_pin[i].data_a_reg_index);
550 info->offset_y = info->offset + 2;
551 info->offset_en = info->offset + 1;
552 info->offset_mask = info->offset - 1;
553
554 info->mask = (uint32_t) (1 <<
555 header->gpio_pin[i].gpio_bitshift);
556 info->mask_y = info->mask + 2;
557 info->mask_en = info->mask + 1;
558 info->mask_mask = info->mask - 1;
559
560 return BP_RESULT_OK;
561 }
562
563 return BP_RESULT_NORECORD;
564 }
565
device_type_from_device_id(uint16_t device_id)566 static struct device_id device_type_from_device_id(uint16_t device_id)
567 {
568
569 struct device_id result_device_id;
570
571 result_device_id.raw_device_tag = device_id;
572
573 switch (device_id) {
574 case ATOM_DISPLAY_LCD1_SUPPORT:
575 result_device_id.device_type = DEVICE_TYPE_LCD;
576 result_device_id.enum_id = 1;
577 break;
578
579 case ATOM_DISPLAY_DFP1_SUPPORT:
580 result_device_id.device_type = DEVICE_TYPE_DFP;
581 result_device_id.enum_id = 1;
582 break;
583
584 case ATOM_DISPLAY_DFP2_SUPPORT:
585 result_device_id.device_type = DEVICE_TYPE_DFP;
586 result_device_id.enum_id = 2;
587 break;
588
589 case ATOM_DISPLAY_DFP3_SUPPORT:
590 result_device_id.device_type = DEVICE_TYPE_DFP;
591 result_device_id.enum_id = 3;
592 break;
593
594 case ATOM_DISPLAY_DFP4_SUPPORT:
595 result_device_id.device_type = DEVICE_TYPE_DFP;
596 result_device_id.enum_id = 4;
597 break;
598
599 case ATOM_DISPLAY_DFP5_SUPPORT:
600 result_device_id.device_type = DEVICE_TYPE_DFP;
601 result_device_id.enum_id = 5;
602 break;
603
604 case ATOM_DISPLAY_DFP6_SUPPORT:
605 result_device_id.device_type = DEVICE_TYPE_DFP;
606 result_device_id.enum_id = 6;
607 break;
608
609 default:
610 BREAK_TO_DEBUGGER(); /* Invalid device Id */
611 result_device_id.device_type = DEVICE_TYPE_UNKNOWN;
612 result_device_id.enum_id = 0;
613 }
614 return result_device_id;
615 }
616
bios_parser_get_device_tag(struct dc_bios * dcb,struct graphics_object_id connector_object_id,uint32_t device_tag_index,struct connector_device_tag_info * info)617 static enum bp_result bios_parser_get_device_tag(
618 struct dc_bios *dcb,
619 struct graphics_object_id connector_object_id,
620 uint32_t device_tag_index,
621 struct connector_device_tag_info *info)
622 {
623 struct bios_parser *bp = BP_FROM_DCB(dcb);
624 struct atom_display_object_path_v2 *object;
625
626 if (!info)
627 return BP_RESULT_BADINPUT;
628
629 /* getBiosObject will return MXM object */
630 object = get_bios_object(bp, connector_object_id);
631
632 if (!object) {
633 BREAK_TO_DEBUGGER(); /* Invalid object id */
634 return BP_RESULT_BADINPUT;
635 }
636
637 info->acpi_device = 0; /* BIOS no longer provides this */
638 info->dev_id = device_type_from_device_id(object->device_tag);
639
640 return BP_RESULT_OK;
641 }
642
get_ss_info_v4_1(struct bios_parser * bp,uint32_t id,uint32_t index,struct spread_spectrum_info * ss_info)643 static enum bp_result get_ss_info_v4_1(
644 struct bios_parser *bp,
645 uint32_t id,
646 uint32_t index,
647 struct spread_spectrum_info *ss_info)
648 {
649 enum bp_result result = BP_RESULT_OK;
650 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL;
651 struct atom_smu_info_v3_3 *smu_info = NULL;
652
653 if (!ss_info)
654 return BP_RESULT_BADINPUT;
655
656 if (!DATA_TABLES(dce_info))
657 return BP_RESULT_BADBIOSTABLE;
658
659 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1,
660 DATA_TABLES(dce_info));
661 if (!disp_cntl_tbl)
662 return BP_RESULT_BADBIOSTABLE;
663
664
665 ss_info->type.STEP_AND_DELAY_INFO = false;
666 ss_info->spread_percentage_divider = 1000;
667 /* BIOS no longer uses target clock. Always enable for now */
668 ss_info->target_clock_range = 0xffffffff;
669
670 switch (id) {
671 case AS_SIGNAL_TYPE_DVI:
672 ss_info->spread_spectrum_percentage =
673 disp_cntl_tbl->dvi_ss_percentage;
674 ss_info->spread_spectrum_range =
675 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
676 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
677 ss_info->type.CENTER_MODE = true;
678 break;
679 case AS_SIGNAL_TYPE_HDMI:
680 ss_info->spread_spectrum_percentage =
681 disp_cntl_tbl->hdmi_ss_percentage;
682 ss_info->spread_spectrum_range =
683 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
684 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
685 ss_info->type.CENTER_MODE = true;
686 break;
687 /* TODO LVDS not support anymore? */
688 case AS_SIGNAL_TYPE_DISPLAY_PORT:
689 ss_info->spread_spectrum_percentage =
690 disp_cntl_tbl->dp_ss_percentage;
691 ss_info->spread_spectrum_range =
692 disp_cntl_tbl->dp_ss_rate_10hz * 10;
693 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
694 ss_info->type.CENTER_MODE = true;
695 break;
696 case AS_SIGNAL_TYPE_GPU_PLL:
697 /* atom_firmware: DAL only get data from dce_info table.
698 * if data within smu_info is needed for DAL, VBIOS should
699 * copy it into dce_info
700 */
701 result = BP_RESULT_UNSUPPORTED;
702 break;
703 case AS_SIGNAL_TYPE_XGMI:
704 smu_info = GET_IMAGE(struct atom_smu_info_v3_3,
705 DATA_TABLES(smu_info));
706 if (!smu_info)
707 return BP_RESULT_BADBIOSTABLE;
708
709 ss_info->spread_spectrum_percentage =
710 smu_info->waflclk_ss_percentage;
711 ss_info->spread_spectrum_range =
712 smu_info->gpuclk_ss_rate_10hz * 10;
713 if (smu_info->waflclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
714 ss_info->type.CENTER_MODE = true;
715 break;
716 default:
717 result = BP_RESULT_UNSUPPORTED;
718 }
719
720 return result;
721 }
722
get_ss_info_v4_2(struct bios_parser * bp,uint32_t id,uint32_t index,struct spread_spectrum_info * ss_info)723 static enum bp_result get_ss_info_v4_2(
724 struct bios_parser *bp,
725 uint32_t id,
726 uint32_t index,
727 struct spread_spectrum_info *ss_info)
728 {
729 enum bp_result result = BP_RESULT_OK;
730 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL;
731 struct atom_smu_info_v3_1 *smu_info = NULL;
732
733 if (!ss_info)
734 return BP_RESULT_BADINPUT;
735
736 if (!DATA_TABLES(dce_info))
737 return BP_RESULT_BADBIOSTABLE;
738
739 if (!DATA_TABLES(smu_info))
740 return BP_RESULT_BADBIOSTABLE;
741
742 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2,
743 DATA_TABLES(dce_info));
744 if (!disp_cntl_tbl)
745 return BP_RESULT_BADBIOSTABLE;
746
747 smu_info = GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info));
748 if (!smu_info)
749 return BP_RESULT_BADBIOSTABLE;
750
751 ss_info->type.STEP_AND_DELAY_INFO = false;
752 ss_info->spread_percentage_divider = 1000;
753 /* BIOS no longer uses target clock. Always enable for now */
754 ss_info->target_clock_range = 0xffffffff;
755
756 switch (id) {
757 case AS_SIGNAL_TYPE_DVI:
758 ss_info->spread_spectrum_percentage =
759 disp_cntl_tbl->dvi_ss_percentage;
760 ss_info->spread_spectrum_range =
761 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
762 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
763 ss_info->type.CENTER_MODE = true;
764 break;
765 case AS_SIGNAL_TYPE_HDMI:
766 ss_info->spread_spectrum_percentage =
767 disp_cntl_tbl->hdmi_ss_percentage;
768 ss_info->spread_spectrum_range =
769 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
770 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
771 ss_info->type.CENTER_MODE = true;
772 break;
773 /* TODO LVDS not support anymore? */
774 case AS_SIGNAL_TYPE_DISPLAY_PORT:
775 ss_info->spread_spectrum_percentage =
776 smu_info->gpuclk_ss_percentage;
777 ss_info->spread_spectrum_range =
778 smu_info->gpuclk_ss_rate_10hz * 10;
779 if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
780 ss_info->type.CENTER_MODE = true;
781 break;
782 case AS_SIGNAL_TYPE_GPU_PLL:
783 /* atom_firmware: DAL only get data from dce_info table.
784 * if data within smu_info is needed for DAL, VBIOS should
785 * copy it into dce_info
786 */
787 result = BP_RESULT_UNSUPPORTED;
788 break;
789 default:
790 result = BP_RESULT_UNSUPPORTED;
791 }
792
793 return result;
794 }
795
796 /**
797 * bios_parser_get_spread_spectrum_info
798 * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or
799 * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info
800 * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info
801 * ver 3.1,
802 * there is only one entry for each signal /ss id. However, there is
803 * no planning of supporting multiple spread Sprectum entry for EverGreen
804 * @param [in] this
805 * @param [in] signal, ASSignalType to be converted to info index
806 * @param [in] index, number of entries that match the converted info index
807 * @param [out] ss_info, sprectrum information structure,
808 * @return Bios parser result code
809 */
bios_parser_get_spread_spectrum_info(struct dc_bios * dcb,enum as_signal_type signal,uint32_t index,struct spread_spectrum_info * ss_info)810 static enum bp_result bios_parser_get_spread_spectrum_info(
811 struct dc_bios *dcb,
812 enum as_signal_type signal,
813 uint32_t index,
814 struct spread_spectrum_info *ss_info)
815 {
816 struct bios_parser *bp = BP_FROM_DCB(dcb);
817 enum bp_result result = BP_RESULT_UNSUPPORTED;
818 struct atom_common_table_header *header;
819 struct atom_data_revision tbl_revision;
820
821 if (!ss_info) /* check for bad input */
822 return BP_RESULT_BADINPUT;
823
824 if (!DATA_TABLES(dce_info))
825 return BP_RESULT_UNSUPPORTED;
826
827 header = GET_IMAGE(struct atom_common_table_header,
828 DATA_TABLES(dce_info));
829 get_atom_data_table_revision(header, &tbl_revision);
830
831 switch (tbl_revision.major) {
832 case 4:
833 switch (tbl_revision.minor) {
834 case 1:
835 return get_ss_info_v4_1(bp, signal, index, ss_info);
836 case 2:
837 case 3:
838 return get_ss_info_v4_2(bp, signal, index, ss_info);
839 default:
840 break;
841 }
842 break;
843 default:
844 break;
845 }
846 /* there can not be more then one entry for SS Info table */
847 return result;
848 }
849
get_soc_bb_info_v4_4(struct bios_parser * bp,struct bp_soc_bb_info * soc_bb_info)850 static enum bp_result get_soc_bb_info_v4_4(
851 struct bios_parser *bp,
852 struct bp_soc_bb_info *soc_bb_info)
853 {
854 enum bp_result result = BP_RESULT_OK;
855 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL;
856
857 if (!soc_bb_info)
858 return BP_RESULT_BADINPUT;
859
860 if (!DATA_TABLES(dce_info))
861 return BP_RESULT_BADBIOSTABLE;
862
863 if (!DATA_TABLES(smu_info))
864 return BP_RESULT_BADBIOSTABLE;
865
866 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4,
867 DATA_TABLES(dce_info));
868 if (!disp_cntl_tbl)
869 return BP_RESULT_BADBIOSTABLE;
870
871 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat;
872 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat;
873 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat;
874
875 return result;
876 }
877
bios_parser_get_soc_bb_info(struct dc_bios * dcb,struct bp_soc_bb_info * soc_bb_info)878 static enum bp_result bios_parser_get_soc_bb_info(
879 struct dc_bios *dcb,
880 struct bp_soc_bb_info *soc_bb_info)
881 {
882 struct bios_parser *bp = BP_FROM_DCB(dcb);
883 enum bp_result result = BP_RESULT_UNSUPPORTED;
884 struct atom_common_table_header *header;
885 struct atom_data_revision tbl_revision;
886
887 if (!soc_bb_info) /* check for bad input */
888 return BP_RESULT_BADINPUT;
889
890 if (!DATA_TABLES(dce_info))
891 return BP_RESULT_UNSUPPORTED;
892
893 header = GET_IMAGE(struct atom_common_table_header,
894 DATA_TABLES(dce_info));
895 get_atom_data_table_revision(header, &tbl_revision);
896
897 switch (tbl_revision.major) {
898 case 4:
899 switch (tbl_revision.minor) {
900 case 1:
901 case 2:
902 case 3:
903 break;
904 case 4:
905 result = get_soc_bb_info_v4_4(bp, soc_bb_info);
906 default:
907 break;
908 }
909 break;
910 default:
911 break;
912 }
913
914 return result;
915 }
916
get_embedded_panel_info_v2_1(struct bios_parser * bp,struct embedded_panel_info * info)917 static enum bp_result get_embedded_panel_info_v2_1(
918 struct bios_parser *bp,
919 struct embedded_panel_info *info)
920 {
921 struct lcd_info_v2_1 *lvds;
922
923 if (!info)
924 return BP_RESULT_BADINPUT;
925
926 if (!DATA_TABLES(lcd_info))
927 return BP_RESULT_UNSUPPORTED;
928
929 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info));
930
931 if (!lvds)
932 return BP_RESULT_BADBIOSTABLE;
933
934 /* TODO: previous vv1_3, should v2_1 */
935 if (!((lvds->table_header.format_revision == 2)
936 && (lvds->table_header.content_revision >= 1)))
937 return BP_RESULT_UNSUPPORTED;
938
939 memset(info, 0, sizeof(struct embedded_panel_info));
940
941 /* We need to convert from 10KHz units into KHz units */
942 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10;
943 /* usHActive does not include borders, according to VBIOS team */
944 info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active);
945 /* usHBlanking_Time includes borders, so we should really be
946 * subtractingborders duing this translation, but LVDS generally
947 * doesn't have borders, so we should be okay leaving this as is for
948 * now. May need to revisit if we ever have LVDS with borders
949 */
950 info->lcd_timing.horizontal_blanking_time = le16_to_cpu(lvds->lcd_timing.h_blanking_time);
951 /* usVActive does not include borders, according to VBIOS team*/
952 info->lcd_timing.vertical_addressable = le16_to_cpu(lvds->lcd_timing.v_active);
953 /* usVBlanking_Time includes borders, so we should really be
954 * subtracting borders duing this translation, but LVDS generally
955 * doesn't have borders, so we should be okay leaving this as is for
956 * now. May need to revisit if we ever have LVDS with borders
957 */
958 info->lcd_timing.vertical_blanking_time = le16_to_cpu(lvds->lcd_timing.v_blanking_time);
959 info->lcd_timing.horizontal_sync_offset = le16_to_cpu(lvds->lcd_timing.h_sync_offset);
960 info->lcd_timing.horizontal_sync_width = le16_to_cpu(lvds->lcd_timing.h_sync_width);
961 info->lcd_timing.vertical_sync_offset = le16_to_cpu(lvds->lcd_timing.v_sync_offset);
962 info->lcd_timing.vertical_sync_width = le16_to_cpu(lvds->lcd_timing.v_syncwidth);
963 info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border;
964 info->lcd_timing.vertical_border = lvds->lcd_timing.v_border;
965
966 /* not provided by VBIOS */
967 info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0;
968
969 info->lcd_timing.misc_info.H_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo
970 & ATOM_HSYNC_POLARITY);
971 info->lcd_timing.misc_info.V_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo
972 & ATOM_VSYNC_POLARITY);
973
974 /* not provided by VBIOS */
975 info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0;
976
977 info->lcd_timing.misc_info.H_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo
978 & ATOM_H_REPLICATIONBY2);
979 info->lcd_timing.misc_info.V_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo
980 & ATOM_V_REPLICATIONBY2);
981 info->lcd_timing.misc_info.COMPOSITE_SYNC = !!(lvds->lcd_timing.miscinfo
982 & ATOM_COMPOSITESYNC);
983 info->lcd_timing.misc_info.INTERLACE = !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE);
984
985 /* not provided by VBIOS*/
986 info->lcd_timing.misc_info.DOUBLE_CLOCK = 0;
987 /* not provided by VBIOS*/
988 info->ss_id = 0;
989
990 info->realtek_eDPToLVDS = !!(lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID);
991
992 return BP_RESULT_OK;
993 }
994
bios_parser_get_embedded_panel_info(struct dc_bios * dcb,struct embedded_panel_info * info)995 static enum bp_result bios_parser_get_embedded_panel_info(
996 struct dc_bios *dcb,
997 struct embedded_panel_info *info)
998 {
999 struct bios_parser
1000 *bp = BP_FROM_DCB(dcb);
1001 struct atom_common_table_header *header;
1002 struct atom_data_revision tbl_revision;
1003
1004 if (!DATA_TABLES(lcd_info))
1005 return BP_RESULT_FAILURE;
1006
1007 header = GET_IMAGE(struct atom_common_table_header, DATA_TABLES(lcd_info));
1008
1009 if (!header)
1010 return BP_RESULT_BADBIOSTABLE;
1011
1012 get_atom_data_table_revision(header, &tbl_revision);
1013
1014 switch (tbl_revision.major) {
1015 case 2:
1016 switch (tbl_revision.minor) {
1017 case 1:
1018 return get_embedded_panel_info_v2_1(bp, info);
1019 default:
1020 break;
1021 }
1022 default:
1023 break;
1024 }
1025
1026 return BP_RESULT_FAILURE;
1027 }
1028
get_support_mask_for_device_id(struct device_id device_id)1029 static uint32_t get_support_mask_for_device_id(struct device_id device_id)
1030 {
1031 enum dal_device_type device_type = device_id.device_type;
1032 uint32_t enum_id = device_id.enum_id;
1033
1034 switch (device_type) {
1035 case DEVICE_TYPE_LCD:
1036 switch (enum_id) {
1037 case 1:
1038 return ATOM_DISPLAY_LCD1_SUPPORT;
1039 default:
1040 break;
1041 }
1042 break;
1043 case DEVICE_TYPE_DFP:
1044 switch (enum_id) {
1045 case 1:
1046 return ATOM_DISPLAY_DFP1_SUPPORT;
1047 case 2:
1048 return ATOM_DISPLAY_DFP2_SUPPORT;
1049 case 3:
1050 return ATOM_DISPLAY_DFP3_SUPPORT;
1051 case 4:
1052 return ATOM_DISPLAY_DFP4_SUPPORT;
1053 case 5:
1054 return ATOM_DISPLAY_DFP5_SUPPORT;
1055 case 6:
1056 return ATOM_DISPLAY_DFP6_SUPPORT;
1057 default:
1058 break;
1059 }
1060 break;
1061 default:
1062 break;
1063 }
1064
1065 /* Unidentified device ID, return empty support mask. */
1066 return 0;
1067 }
1068
bios_parser_is_device_id_supported(struct dc_bios * dcb,struct device_id id)1069 static bool bios_parser_is_device_id_supported(
1070 struct dc_bios *dcb,
1071 struct device_id id)
1072 {
1073 struct bios_parser *bp = BP_FROM_DCB(dcb);
1074
1075 uint32_t mask = get_support_mask_for_device_id(id);
1076
1077 return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) &
1078 mask) != 0;
1079 }
1080
bios_parser_get_ss_entry_number(struct dc_bios * dcb,enum as_signal_type signal)1081 static uint32_t bios_parser_get_ss_entry_number(
1082 struct dc_bios *dcb,
1083 enum as_signal_type signal)
1084 {
1085 /* TODO: DAL2 atomfirmware implementation does not need this.
1086 * why DAL3 need this?
1087 */
1088 return 1;
1089 }
1090
bios_parser_transmitter_control(struct dc_bios * dcb,struct bp_transmitter_control * cntl)1091 static enum bp_result bios_parser_transmitter_control(
1092 struct dc_bios *dcb,
1093 struct bp_transmitter_control *cntl)
1094 {
1095 struct bios_parser *bp = BP_FROM_DCB(dcb);
1096
1097 if (!bp->cmd_tbl.transmitter_control)
1098 return BP_RESULT_FAILURE;
1099
1100 return bp->cmd_tbl.transmitter_control(bp, cntl);
1101 }
1102
bios_parser_encoder_control(struct dc_bios * dcb,struct bp_encoder_control * cntl)1103 static enum bp_result bios_parser_encoder_control(
1104 struct dc_bios *dcb,
1105 struct bp_encoder_control *cntl)
1106 {
1107 struct bios_parser *bp = BP_FROM_DCB(dcb);
1108
1109 if (!bp->cmd_tbl.dig_encoder_control)
1110 return BP_RESULT_FAILURE;
1111
1112 return bp->cmd_tbl.dig_encoder_control(bp, cntl);
1113 }
1114
bios_parser_set_pixel_clock(struct dc_bios * dcb,struct bp_pixel_clock_parameters * bp_params)1115 static enum bp_result bios_parser_set_pixel_clock(
1116 struct dc_bios *dcb,
1117 struct bp_pixel_clock_parameters *bp_params)
1118 {
1119 struct bios_parser *bp = BP_FROM_DCB(dcb);
1120
1121 if (!bp->cmd_tbl.set_pixel_clock)
1122 return BP_RESULT_FAILURE;
1123
1124 return bp->cmd_tbl.set_pixel_clock(bp, bp_params);
1125 }
1126
bios_parser_set_dce_clock(struct dc_bios * dcb,struct bp_set_dce_clock_parameters * bp_params)1127 static enum bp_result bios_parser_set_dce_clock(
1128 struct dc_bios *dcb,
1129 struct bp_set_dce_clock_parameters *bp_params)
1130 {
1131 struct bios_parser *bp = BP_FROM_DCB(dcb);
1132
1133 if (!bp->cmd_tbl.set_dce_clock)
1134 return BP_RESULT_FAILURE;
1135
1136 return bp->cmd_tbl.set_dce_clock(bp, bp_params);
1137 }
1138
bios_parser_program_crtc_timing(struct dc_bios * dcb,struct bp_hw_crtc_timing_parameters * bp_params)1139 static enum bp_result bios_parser_program_crtc_timing(
1140 struct dc_bios *dcb,
1141 struct bp_hw_crtc_timing_parameters *bp_params)
1142 {
1143 struct bios_parser *bp = BP_FROM_DCB(dcb);
1144
1145 if (!bp->cmd_tbl.set_crtc_timing)
1146 return BP_RESULT_FAILURE;
1147
1148 return bp->cmd_tbl.set_crtc_timing(bp, bp_params);
1149 }
1150
bios_parser_enable_crtc(struct dc_bios * dcb,enum controller_id id,bool enable)1151 static enum bp_result bios_parser_enable_crtc(
1152 struct dc_bios *dcb,
1153 enum controller_id id,
1154 bool enable)
1155 {
1156 struct bios_parser *bp = BP_FROM_DCB(dcb);
1157
1158 if (!bp->cmd_tbl.enable_crtc)
1159 return BP_RESULT_FAILURE;
1160
1161 return bp->cmd_tbl.enable_crtc(bp, id, enable);
1162 }
1163
bios_parser_enable_disp_power_gating(struct dc_bios * dcb,enum controller_id controller_id,enum bp_pipe_control_action action)1164 static enum bp_result bios_parser_enable_disp_power_gating(
1165 struct dc_bios *dcb,
1166 enum controller_id controller_id,
1167 enum bp_pipe_control_action action)
1168 {
1169 struct bios_parser *bp = BP_FROM_DCB(dcb);
1170
1171 if (!bp->cmd_tbl.enable_disp_power_gating)
1172 return BP_RESULT_FAILURE;
1173
1174 return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id,
1175 action);
1176 }
1177
bios_parser_enable_lvtma_control(struct dc_bios * dcb,uint8_t uc_pwr_on)1178 static enum bp_result bios_parser_enable_lvtma_control(
1179 struct dc_bios *dcb,
1180 uint8_t uc_pwr_on)
1181 {
1182 struct bios_parser *bp = BP_FROM_DCB(dcb);
1183
1184 if (!bp->cmd_tbl.enable_lvtma_control)
1185 return BP_RESULT_FAILURE;
1186
1187 return bp->cmd_tbl.enable_lvtma_control(bp, uc_pwr_on);
1188 }
1189
bios_parser_is_accelerated_mode(struct dc_bios * dcb)1190 static bool bios_parser_is_accelerated_mode(
1191 struct dc_bios *dcb)
1192 {
1193 return bios_is_accelerated_mode(dcb);
1194 }
1195
1196 /**
1197 * bios_parser_set_scratch_critical_state
1198 *
1199 * @brief
1200 * update critical state bit in VBIOS scratch register
1201 *
1202 * @param
1203 * bool - to set or reset state
1204 */
bios_parser_set_scratch_critical_state(struct dc_bios * dcb,bool state)1205 static void bios_parser_set_scratch_critical_state(
1206 struct dc_bios *dcb,
1207 bool state)
1208 {
1209 bios_set_scratch_critical_state(dcb, state);
1210 }
1211
bios_parser_get_firmware_info(struct dc_bios * dcb,struct dc_firmware_info * info)1212 static enum bp_result bios_parser_get_firmware_info(
1213 struct dc_bios *dcb,
1214 struct dc_firmware_info *info)
1215 {
1216 struct bios_parser *bp = BP_FROM_DCB(dcb);
1217 enum bp_result result = BP_RESULT_BADBIOSTABLE;
1218 struct atom_common_table_header *header;
1219
1220 struct atom_data_revision revision;
1221
1222 if (info && DATA_TABLES(firmwareinfo)) {
1223 header = GET_IMAGE(struct atom_common_table_header,
1224 DATA_TABLES(firmwareinfo));
1225 get_atom_data_table_revision(header, &revision);
1226 switch (revision.major) {
1227 case 3:
1228 switch (revision.minor) {
1229 case 1:
1230 result = get_firmware_info_v3_1(bp, info);
1231 break;
1232 case 2:
1233 result = get_firmware_info_v3_2(bp, info);
1234 break;
1235 case 3:
1236 #ifdef CONFIG_DRM_AMD_DC_DCN3_0
1237 case 4:
1238 #endif
1239 result = get_firmware_info_v3_2(bp, info);
1240 break;
1241 default:
1242 break;
1243 }
1244 break;
1245 default:
1246 break;
1247 }
1248 }
1249
1250 return result;
1251 }
1252
get_firmware_info_v3_1(struct bios_parser * bp,struct dc_firmware_info * info)1253 static enum bp_result get_firmware_info_v3_1(
1254 struct bios_parser *bp,
1255 struct dc_firmware_info *info)
1256 {
1257 struct atom_firmware_info_v3_1 *firmware_info;
1258 struct atom_display_controller_info_v4_1 *dce_info = NULL;
1259
1260 if (!info)
1261 return BP_RESULT_BADINPUT;
1262
1263 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1,
1264 DATA_TABLES(firmwareinfo));
1265
1266 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1267 DATA_TABLES(dce_info));
1268
1269 if (!firmware_info || !dce_info)
1270 return BP_RESULT_BADBIOSTABLE;
1271
1272 memset(info, 0, sizeof(*info));
1273
1274 /* Pixel clock pll information. */
1275 /* We need to convert from 10KHz units into KHz units */
1276 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1277 info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10;
1278
1279 /* 27MHz for Vega10: */
1280 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1281
1282 /* Hardcode frequency if BIOS gives no DCE Ref Clk */
1283 if (info->pll_info.crystal_frequency == 0)
1284 info->pll_info.crystal_frequency = 27000;
1285 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
1286 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
1287 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1288
1289 /* Get GPU PLL VCO Clock */
1290
1291 if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1292 /* VBIOS gives in 10KHz */
1293 info->smu_gpu_pll_output_freq =
1294 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1295 }
1296
1297 info->oem_i2c_present = false;
1298
1299 return BP_RESULT_OK;
1300 }
1301
get_firmware_info_v3_2(struct bios_parser * bp,struct dc_firmware_info * info)1302 static enum bp_result get_firmware_info_v3_2(
1303 struct bios_parser *bp,
1304 struct dc_firmware_info *info)
1305 {
1306 struct atom_firmware_info_v3_2 *firmware_info;
1307 struct atom_display_controller_info_v4_1 *dce_info = NULL;
1308 struct atom_common_table_header *header;
1309 struct atom_data_revision revision;
1310 struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL;
1311 struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL;
1312
1313 if (!info)
1314 return BP_RESULT_BADINPUT;
1315
1316 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2,
1317 DATA_TABLES(firmwareinfo));
1318
1319 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1320 DATA_TABLES(dce_info));
1321
1322 if (!firmware_info || !dce_info)
1323 return BP_RESULT_BADBIOSTABLE;
1324
1325 memset(info, 0, sizeof(*info));
1326
1327 header = GET_IMAGE(struct atom_common_table_header,
1328 DATA_TABLES(smu_info));
1329 get_atom_data_table_revision(header, &revision);
1330
1331 if (revision.minor == 2) {
1332 /* Vega12 */
1333 smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2,
1334 DATA_TABLES(smu_info));
1335
1336 if (!smu_info_v3_2)
1337 return BP_RESULT_BADBIOSTABLE;
1338
1339 info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10;
1340 } else if (revision.minor == 3) {
1341 /* Vega20 */
1342 smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3,
1343 DATA_TABLES(smu_info));
1344
1345 if (!smu_info_v3_3)
1346 return BP_RESULT_BADBIOSTABLE;
1347
1348 info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10;
1349 }
1350
1351 // We need to convert from 10KHz units into KHz units.
1352 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1353
1354 /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */
1355 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1356 /* Hardcode frequency if BIOS gives no DCE Ref Clk */
1357 if (info->pll_info.crystal_frequency == 0) {
1358 if (revision.minor == 2)
1359 info->pll_info.crystal_frequency = 27000;
1360 else if (revision.minor == 3)
1361 info->pll_info.crystal_frequency = 100000;
1362 }
1363 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
1364 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
1365 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1366
1367 /* Get GPU PLL VCO Clock */
1368 if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1369 if (revision.minor == 2)
1370 info->smu_gpu_pll_output_freq =
1371 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1372 else if (revision.minor == 3)
1373 info->smu_gpu_pll_output_freq =
1374 bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10;
1375 }
1376
1377 if (firmware_info->board_i2c_feature_id == 0x2) {
1378 info->oem_i2c_present = true;
1379 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id;
1380 } else {
1381 info->oem_i2c_present = false;
1382 }
1383
1384 return BP_RESULT_OK;
1385 }
1386
bios_parser_get_encoder_cap_info(struct dc_bios * dcb,struct graphics_object_id object_id,struct bp_encoder_cap_info * info)1387 static enum bp_result bios_parser_get_encoder_cap_info(
1388 struct dc_bios *dcb,
1389 struct graphics_object_id object_id,
1390 struct bp_encoder_cap_info *info)
1391 {
1392 struct bios_parser *bp = BP_FROM_DCB(dcb);
1393 struct atom_display_object_path_v2 *object;
1394 struct atom_encoder_caps_record *record = NULL;
1395
1396 if (!info)
1397 return BP_RESULT_BADINPUT;
1398
1399 object = get_bios_object(bp, object_id);
1400
1401 if (!object)
1402 return BP_RESULT_BADINPUT;
1403
1404 record = get_encoder_cap_record(bp, object);
1405 if (!record)
1406 return BP_RESULT_NORECORD;
1407
1408 info->DP_HBR2_CAP = (record->encodercaps &
1409 ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0;
1410 info->DP_HBR2_EN = (record->encodercaps &
1411 ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0;
1412 info->DP_HBR3_EN = (record->encodercaps &
1413 ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0;
1414 info->HDMI_6GB_EN = (record->encodercaps &
1415 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0;
1416 info->DP_IS_USB_C = (record->encodercaps &
1417 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0;
1418
1419 return BP_RESULT_OK;
1420 }
1421
1422
get_encoder_cap_record(struct bios_parser * bp,struct atom_display_object_path_v2 * object)1423 static struct atom_encoder_caps_record *get_encoder_cap_record(
1424 struct bios_parser *bp,
1425 struct atom_display_object_path_v2 *object)
1426 {
1427 struct atom_common_record_header *header;
1428 uint32_t offset;
1429
1430 if (!object) {
1431 BREAK_TO_DEBUGGER(); /* Invalid object */
1432 return NULL;
1433 }
1434
1435 offset = object->encoder_recordoffset + bp->object_info_tbl_offset;
1436
1437 for (;;) {
1438 header = GET_IMAGE(struct atom_common_record_header, offset);
1439
1440 if (!header)
1441 return NULL;
1442
1443 offset += header->record_size;
1444
1445 if (header->record_type == LAST_RECORD_TYPE ||
1446 !header->record_size)
1447 break;
1448
1449 if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE)
1450 continue;
1451
1452 if (sizeof(struct atom_encoder_caps_record) <=
1453 header->record_size)
1454 return (struct atom_encoder_caps_record *)header;
1455 }
1456
1457 return NULL;
1458 }
1459
get_vram_info_v23(struct bios_parser * bp,struct dc_vram_info * info)1460 static enum bp_result get_vram_info_v23(
1461 struct bios_parser *bp,
1462 struct dc_vram_info *info)
1463 {
1464 struct atom_vram_info_header_v2_3 *info_v23;
1465 enum bp_result result = BP_RESULT_OK;
1466
1467 info_v23 = GET_IMAGE(struct atom_vram_info_header_v2_3,
1468 DATA_TABLES(vram_info));
1469
1470 if (info_v23 == NULL)
1471 return BP_RESULT_BADBIOSTABLE;
1472
1473 info->num_chans = info_v23->vram_module[0].channel_num;
1474 info->dram_channel_width_bytes = (1 << info_v23->vram_module[0].channel_width) / 8;
1475
1476 return result;
1477 }
1478
get_vram_info_v24(struct bios_parser * bp,struct dc_vram_info * info)1479 static enum bp_result get_vram_info_v24(
1480 struct bios_parser *bp,
1481 struct dc_vram_info *info)
1482 {
1483 struct atom_vram_info_header_v2_4 *info_v24;
1484 enum bp_result result = BP_RESULT_OK;
1485
1486 info_v24 = GET_IMAGE(struct atom_vram_info_header_v2_4,
1487 DATA_TABLES(vram_info));
1488
1489 if (info_v24 == NULL)
1490 return BP_RESULT_BADBIOSTABLE;
1491
1492 info->num_chans = info_v24->vram_module[0].channel_num;
1493 info->dram_channel_width_bytes = (1 << info_v24->vram_module[0].channel_width) / 8;
1494
1495 return result;
1496 }
1497
get_vram_info_v25(struct bios_parser * bp,struct dc_vram_info * info)1498 static enum bp_result get_vram_info_v25(
1499 struct bios_parser *bp,
1500 struct dc_vram_info *info)
1501 {
1502 struct atom_vram_info_header_v2_5 *info_v25;
1503 enum bp_result result = BP_RESULT_OK;
1504
1505 info_v25 = GET_IMAGE(struct atom_vram_info_header_v2_5,
1506 DATA_TABLES(vram_info));
1507
1508 if (info_v25 == NULL)
1509 return BP_RESULT_BADBIOSTABLE;
1510
1511 info->num_chans = info_v25->vram_module[0].channel_num;
1512 info->dram_channel_width_bytes = (1 << info_v25->vram_module[0].channel_width) / 8;
1513
1514 return result;
1515 }
1516
1517 /*
1518 * get_integrated_info_v11
1519 *
1520 * @brief
1521 * Get V8 integrated BIOS information
1522 *
1523 * @param
1524 * bios_parser *bp - [in]BIOS parser handler to get master data table
1525 * integrated_info *info - [out] store and output integrated info
1526 *
1527 * @return
1528 * enum bp_result - BP_RESULT_OK if information is available,
1529 * BP_RESULT_BADBIOSTABLE otherwise.
1530 */
get_integrated_info_v11(struct bios_parser * bp,struct integrated_info * info)1531 static enum bp_result get_integrated_info_v11(
1532 struct bios_parser *bp,
1533 struct integrated_info *info)
1534 {
1535 struct atom_integrated_system_info_v1_11 *info_v11;
1536 uint32_t i;
1537
1538 info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11,
1539 DATA_TABLES(integratedsysteminfo));
1540
1541 if (info_v11 == NULL)
1542 return BP_RESULT_BADBIOSTABLE;
1543
1544 info->gpu_cap_info =
1545 le32_to_cpu(info_v11->gpucapinfo);
1546 /*
1547 * system_config: Bit[0] = 0 : PCIE power gating disabled
1548 * = 1 : PCIE power gating enabled
1549 * Bit[1] = 0 : DDR-PLL shut down disabled
1550 * = 1 : DDR-PLL shut down enabled
1551 * Bit[2] = 0 : DDR-PLL power down disabled
1552 * = 1 : DDR-PLL power down enabled
1553 */
1554 info->system_config = le32_to_cpu(info_v11->system_config);
1555 info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo);
1556 info->memory_type = info_v11->memorytype;
1557 info->ma_channel_number = info_v11->umachannelnumber;
1558 info->lvds_ss_percentage =
1559 le16_to_cpu(info_v11->lvds_ss_percentage);
1560 info->dp_ss_control =
1561 le16_to_cpu(info_v11->reserved1);
1562 info->lvds_sspread_rate_in_10hz =
1563 le16_to_cpu(info_v11->lvds_ss_rate_10hz);
1564 info->hdmi_ss_percentage =
1565 le16_to_cpu(info_v11->hdmi_ss_percentage);
1566 info->hdmi_sspread_rate_in_10hz =
1567 le16_to_cpu(info_v11->hdmi_ss_rate_10hz);
1568 info->dvi_ss_percentage =
1569 le16_to_cpu(info_v11->dvi_ss_percentage);
1570 info->dvi_sspread_rate_in_10_hz =
1571 le16_to_cpu(info_v11->dvi_ss_rate_10hz);
1572 info->lvds_misc = info_v11->lvds_misc;
1573 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
1574 info->ext_disp_conn_info.gu_id[i] =
1575 info_v11->extdispconninfo.guid[i];
1576 }
1577
1578 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
1579 info->ext_disp_conn_info.path[i].device_connector_id =
1580 object_id_from_bios_object_id(
1581 le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid));
1582
1583 info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
1584 object_id_from_bios_object_id(
1585 le16_to_cpu(
1586 info_v11->extdispconninfo.path[i].ext_encoder_objid));
1587
1588 info->ext_disp_conn_info.path[i].device_tag =
1589 le16_to_cpu(
1590 info_v11->extdispconninfo.path[i].device_tag);
1591 info->ext_disp_conn_info.path[i].device_acpi_enum =
1592 le16_to_cpu(
1593 info_v11->extdispconninfo.path[i].device_acpi_enum);
1594 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
1595 info_v11->extdispconninfo.path[i].auxddclut_index;
1596 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
1597 info_v11->extdispconninfo.path[i].hpdlut_index;
1598 info->ext_disp_conn_info.path[i].channel_mapping.raw =
1599 info_v11->extdispconninfo.path[i].channelmapping;
1600 info->ext_disp_conn_info.path[i].caps =
1601 le16_to_cpu(info_v11->extdispconninfo.path[i].caps);
1602 }
1603 info->ext_disp_conn_info.checksum =
1604 info_v11->extdispconninfo.checksum;
1605
1606 info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr;
1607 info->dp0_ext_hdmi_reg_num = info_v11->dp0_retimer_set.HdmiRegNum;
1608 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) {
1609 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index =
1610 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1611 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val =
1612 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1613 }
1614 info->dp0_ext_hdmi_6g_reg_num = info_v11->dp0_retimer_set.Hdmi6GRegNum;
1615 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) {
1616 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1617 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1618 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1619 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1620 }
1621
1622 info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr;
1623 info->dp1_ext_hdmi_reg_num = info_v11->dp1_retimer_set.HdmiRegNum;
1624 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) {
1625 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index =
1626 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1627 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val =
1628 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1629 }
1630 info->dp1_ext_hdmi_6g_reg_num = info_v11->dp1_retimer_set.Hdmi6GRegNum;
1631 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) {
1632 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1633 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1634 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1635 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1636 }
1637
1638 info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr;
1639 info->dp2_ext_hdmi_reg_num = info_v11->dp2_retimer_set.HdmiRegNum;
1640 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) {
1641 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index =
1642 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1643 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val =
1644 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1645 }
1646 info->dp2_ext_hdmi_6g_reg_num = info_v11->dp2_retimer_set.Hdmi6GRegNum;
1647 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) {
1648 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1649 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1650 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1651 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1652 }
1653
1654 info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr;
1655 info->dp3_ext_hdmi_reg_num = info_v11->dp3_retimer_set.HdmiRegNum;
1656 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) {
1657 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index =
1658 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1659 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val =
1660 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1661 }
1662 info->dp3_ext_hdmi_6g_reg_num = info_v11->dp3_retimer_set.Hdmi6GRegNum;
1663 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) {
1664 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1665 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1666 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1667 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1668 }
1669
1670
1671 /** TODO - review **/
1672 #if 0
1673 info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock)
1674 * 10;
1675 info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10;
1676 info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10;
1677
1678 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
1679 /* Convert [10KHz] into [KHz] */
1680 info->disp_clk_voltage[i].max_supported_clk =
1681 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].
1682 ulMaximumSupportedCLK) * 10;
1683 info->disp_clk_voltage[i].voltage_index =
1684 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex);
1685 }
1686
1687 info->boot_up_req_display_vector =
1688 le32_to_cpu(info_v11->ulBootUpReqDisplayVector);
1689 info->boot_up_nb_voltage =
1690 le16_to_cpu(info_v11->usBootUpNBVoltage);
1691 info->ext_disp_conn_info_offset =
1692 le16_to_cpu(info_v11->usExtDispConnInfoOffset);
1693 info->gmc_restore_reset_time =
1694 le32_to_cpu(info_v11->ulGMCRestoreResetTime);
1695 info->minimum_n_clk =
1696 le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]);
1697 for (i = 1; i < 4; ++i)
1698 info->minimum_n_clk =
1699 info->minimum_n_clk <
1700 le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ?
1701 info->minimum_n_clk : le32_to_cpu(
1702 info_v11->ulNbpStateNClkFreq[i]);
1703
1704 info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk);
1705 info->ddr_dll_power_up_time =
1706 le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime);
1707 info->ddr_pll_power_up_time =
1708 le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime);
1709 info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType);
1710 info->max_lvds_pclk_freq_in_single_link =
1711 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink);
1712 info->max_lvds_pclk_freq_in_single_link =
1713 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink);
1714 info->lvds_pwr_on_seq_dig_on_to_de_in_4ms =
1715 info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
1716 info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms =
1717 info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
1718 info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms =
1719 info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
1720 info->lvds_pwr_off_seq_vary_bl_to_de_in4ms =
1721 info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
1722 info->lvds_pwr_off_seq_de_to_dig_on_in4ms =
1723 info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
1724 info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms =
1725 info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
1726 info->lvds_off_to_on_delay_in_4ms =
1727 info_v11->ucLVDSOffToOnDelay_in4Ms;
1728 info->lvds_bit_depth_control_val =
1729 le32_to_cpu(info_v11->ulLCDBitDepthControlVal);
1730
1731 for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) {
1732 /* Convert [10KHz] into [KHz] */
1733 info->avail_s_clk[i].supported_s_clk =
1734 le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK)
1735 * 10;
1736 info->avail_s_clk[i].voltage_index =
1737 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex);
1738 info->avail_s_clk[i].voltage_id =
1739 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID);
1740 }
1741 #endif /* TODO*/
1742
1743 return BP_RESULT_OK;
1744 }
1745
1746
1747 /*
1748 * construct_integrated_info
1749 *
1750 * @brief
1751 * Get integrated BIOS information based on table revision
1752 *
1753 * @param
1754 * bios_parser *bp - [in]BIOS parser handler to get master data table
1755 * integrated_info *info - [out] store and output integrated info
1756 *
1757 * @return
1758 * enum bp_result - BP_RESULT_OK if information is available,
1759 * BP_RESULT_BADBIOSTABLE otherwise.
1760 */
construct_integrated_info(struct bios_parser * bp,struct integrated_info * info)1761 static enum bp_result construct_integrated_info(
1762 struct bios_parser *bp,
1763 struct integrated_info *info)
1764 {
1765 enum bp_result result = BP_RESULT_BADBIOSTABLE;
1766
1767 struct atom_common_table_header *header;
1768 struct atom_data_revision revision;
1769 uint32_t i;
1770 uint32_t j;
1771
1772 if (info && DATA_TABLES(integratedsysteminfo)) {
1773 header = GET_IMAGE(struct atom_common_table_header,
1774 DATA_TABLES(integratedsysteminfo));
1775
1776 get_atom_data_table_revision(header, &revision);
1777
1778 /* Don't need to check major revision as they are all 1 */
1779 switch (revision.minor) {
1780 case 11:
1781 case 12:
1782 result = get_integrated_info_v11(bp, info);
1783 break;
1784 default:
1785 return result;
1786 }
1787 }
1788
1789 if (result != BP_RESULT_OK)
1790 return result;
1791
1792 /* Sort voltage table from low to high*/
1793 for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
1794 for (j = i; j > 0; --j) {
1795 if (info->disp_clk_voltage[j].max_supported_clk <
1796 info->disp_clk_voltage[j-1].max_supported_clk
1797 ) {
1798 /* swap j and j - 1*/
1799 swap(info->disp_clk_voltage[j - 1],
1800 info->disp_clk_voltage[j]);
1801 }
1802 }
1803 }
1804
1805 return result;
1806 }
1807
bios_parser_get_vram_info(struct dc_bios * dcb,struct dc_vram_info * info)1808 static enum bp_result bios_parser_get_vram_info(
1809 struct dc_bios *dcb,
1810 struct dc_vram_info *info)
1811 {
1812 struct bios_parser *bp = BP_FROM_DCB(dcb);
1813 enum bp_result result = BP_RESULT_BADBIOSTABLE;
1814 struct atom_common_table_header *header;
1815 struct atom_data_revision revision;
1816
1817 if (info && DATA_TABLES(vram_info)) {
1818 header = GET_IMAGE(struct atom_common_table_header,
1819 DATA_TABLES(vram_info));
1820
1821 get_atom_data_table_revision(header, &revision);
1822
1823 switch (revision.major) {
1824 case 2:
1825 switch (revision.minor) {
1826 case 3:
1827 result = get_vram_info_v23(bp, info);
1828 break;
1829 case 4:
1830 result = get_vram_info_v24(bp, info);
1831 break;
1832 case 5:
1833 result = get_vram_info_v25(bp, info);
1834 break;
1835 default:
1836 break;
1837 }
1838 break;
1839
1840 default:
1841 return result;
1842 }
1843
1844 }
1845 return result;
1846 }
1847
bios_parser_create_integrated_info(struct dc_bios * dcb)1848 static struct integrated_info *bios_parser_create_integrated_info(
1849 struct dc_bios *dcb)
1850 {
1851 struct bios_parser *bp = BP_FROM_DCB(dcb);
1852 struct integrated_info *info = NULL;
1853
1854 info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL);
1855
1856 if (info == NULL) {
1857 ASSERT_CRITICAL(0);
1858 return NULL;
1859 }
1860
1861 if (construct_integrated_info(bp, info) == BP_RESULT_OK)
1862 return info;
1863
1864 kfree(info);
1865
1866 return NULL;
1867 }
1868
update_slot_layout_info(struct dc_bios * dcb,unsigned int i,struct slot_layout_info * slot_layout_info)1869 static enum bp_result update_slot_layout_info(
1870 struct dc_bios *dcb,
1871 unsigned int i,
1872 struct slot_layout_info *slot_layout_info)
1873 {
1874 unsigned int record_offset;
1875 unsigned int j;
1876 struct atom_display_object_path_v2 *object;
1877 struct atom_bracket_layout_record *record;
1878 struct atom_common_record_header *record_header;
1879 enum bp_result result;
1880 struct bios_parser *bp;
1881 struct object_info_table *tbl;
1882 struct display_object_info_table_v1_4 *v1_4;
1883
1884 record = NULL;
1885 record_header = NULL;
1886 result = BP_RESULT_NORECORD;
1887
1888 bp = BP_FROM_DCB(dcb);
1889 tbl = &bp->object_info_tbl;
1890 v1_4 = tbl->v1_4;
1891
1892 object = &v1_4->display_path[i];
1893 record_offset = (unsigned int)
1894 (object->disp_recordoffset) +
1895 (unsigned int)(bp->object_info_tbl_offset);
1896
1897 for (;;) {
1898
1899 record_header = (struct atom_common_record_header *)
1900 GET_IMAGE(struct atom_common_record_header,
1901 record_offset);
1902 if (record_header == NULL) {
1903 result = BP_RESULT_BADBIOSTABLE;
1904 break;
1905 }
1906
1907 /* the end of the list */
1908 if (record_header->record_type == 0xff ||
1909 record_header->record_size == 0) {
1910 break;
1911 }
1912
1913 if (record_header->record_type ==
1914 ATOM_BRACKET_LAYOUT_RECORD_TYPE &&
1915 sizeof(struct atom_bracket_layout_record)
1916 <= record_header->record_size) {
1917 record = (struct atom_bracket_layout_record *)
1918 (record_header);
1919 result = BP_RESULT_OK;
1920 break;
1921 }
1922
1923 record_offset += record_header->record_size;
1924 }
1925
1926 /* return if the record not found */
1927 if (result != BP_RESULT_OK)
1928 return result;
1929
1930 /* get slot sizes */
1931 slot_layout_info->length = record->bracketlen;
1932 slot_layout_info->width = record->bracketwidth;
1933
1934 /* get info for each connector in the slot */
1935 slot_layout_info->num_of_connectors = record->conn_num;
1936 for (j = 0; j < slot_layout_info->num_of_connectors; ++j) {
1937 slot_layout_info->connectors[j].connector_type =
1938 (enum connector_layout_type)
1939 (record->conn_info[j].connector_type);
1940 switch (record->conn_info[j].connector_type) {
1941 case CONNECTOR_TYPE_DVI_D:
1942 slot_layout_info->connectors[j].connector_type =
1943 CONNECTOR_LAYOUT_TYPE_DVI_D;
1944 slot_layout_info->connectors[j].length =
1945 CONNECTOR_SIZE_DVI;
1946 break;
1947
1948 case CONNECTOR_TYPE_HDMI:
1949 slot_layout_info->connectors[j].connector_type =
1950 CONNECTOR_LAYOUT_TYPE_HDMI;
1951 slot_layout_info->connectors[j].length =
1952 CONNECTOR_SIZE_HDMI;
1953 break;
1954
1955 case CONNECTOR_TYPE_DISPLAY_PORT:
1956 slot_layout_info->connectors[j].connector_type =
1957 CONNECTOR_LAYOUT_TYPE_DP;
1958 slot_layout_info->connectors[j].length =
1959 CONNECTOR_SIZE_DP;
1960 break;
1961
1962 case CONNECTOR_TYPE_MINI_DISPLAY_PORT:
1963 slot_layout_info->connectors[j].connector_type =
1964 CONNECTOR_LAYOUT_TYPE_MINI_DP;
1965 slot_layout_info->connectors[j].length =
1966 CONNECTOR_SIZE_MINI_DP;
1967 break;
1968
1969 default:
1970 slot_layout_info->connectors[j].connector_type =
1971 CONNECTOR_LAYOUT_TYPE_UNKNOWN;
1972 slot_layout_info->connectors[j].length =
1973 CONNECTOR_SIZE_UNKNOWN;
1974 }
1975
1976 slot_layout_info->connectors[j].position =
1977 record->conn_info[j].position;
1978 slot_layout_info->connectors[j].connector_id =
1979 object_id_from_bios_object_id(
1980 record->conn_info[j].connectorobjid);
1981 }
1982 return result;
1983 }
1984
1985
get_bracket_layout_record(struct dc_bios * dcb,unsigned int bracket_layout_id,struct slot_layout_info * slot_layout_info)1986 static enum bp_result get_bracket_layout_record(
1987 struct dc_bios *dcb,
1988 unsigned int bracket_layout_id,
1989 struct slot_layout_info *slot_layout_info)
1990 {
1991 unsigned int i;
1992 struct bios_parser *bp = BP_FROM_DCB(dcb);
1993 enum bp_result result;
1994 struct object_info_table *tbl;
1995 struct display_object_info_table_v1_4 *v1_4;
1996
1997 if (slot_layout_info == NULL) {
1998 DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n");
1999 return BP_RESULT_BADINPUT;
2000 }
2001 tbl = &bp->object_info_tbl;
2002 v1_4 = tbl->v1_4;
2003
2004 result = BP_RESULT_NORECORD;
2005 for (i = 0; i < v1_4->number_of_path; ++i) {
2006
2007 if (bracket_layout_id ==
2008 v1_4->display_path[i].display_objid) {
2009 result = update_slot_layout_info(dcb, i,
2010 slot_layout_info);
2011 break;
2012 }
2013 }
2014 return result;
2015 }
2016
bios_get_board_layout_info(struct dc_bios * dcb,struct board_layout_info * board_layout_info)2017 static enum bp_result bios_get_board_layout_info(
2018 struct dc_bios *dcb,
2019 struct board_layout_info *board_layout_info)
2020 {
2021 unsigned int i;
2022 enum bp_result record_result;
2023
2024 const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = {
2025 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1,
2026 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2,
2027 0, 0
2028 };
2029
2030 if (board_layout_info == NULL) {
2031 DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n");
2032 return BP_RESULT_BADINPUT;
2033 }
2034
2035 board_layout_info->num_of_slots = 0;
2036
2037 for (i = 0; i < MAX_BOARD_SLOTS; ++i) {
2038 record_result = get_bracket_layout_record(dcb,
2039 slot_index_to_vbios_id[i],
2040 &board_layout_info->slots[i]);
2041
2042 if (record_result == BP_RESULT_NORECORD && i > 0)
2043 break; /* no more slots present in bios */
2044 else if (record_result != BP_RESULT_OK)
2045 return record_result; /* fail */
2046
2047 ++board_layout_info->num_of_slots;
2048 }
2049
2050 /* all data is valid */
2051 board_layout_info->is_number_of_slots_valid = 1;
2052 board_layout_info->is_slots_size_valid = 1;
2053 board_layout_info->is_connector_offsets_valid = 1;
2054 board_layout_info->is_connector_lengths_valid = 1;
2055
2056 return BP_RESULT_OK;
2057 }
2058
2059
bios_parser_pack_data_tables(struct dc_bios * dcb,void * dst)2060 static uint16_t bios_parser_pack_data_tables(
2061 struct dc_bios *dcb,
2062 void *dst)
2063 {
2064 #ifdef PACK_BIOS_DATA
2065 struct bios_parser *bp = BP_FROM_DCB(dcb);
2066 struct atom_rom_header_v2_2 *rom_header = NULL;
2067 struct atom_rom_header_v2_2 *packed_rom_header = NULL;
2068 struct atom_common_table_header *data_tbl_header = NULL;
2069 struct atom_master_list_of_data_tables_v2_1 *data_tbl_list = NULL;
2070 struct atom_master_data_table_v2_1 *packed_master_data_tbl = NULL;
2071 struct atom_data_revision tbl_rev = {0};
2072 uint16_t *rom_header_offset = NULL;
2073 const uint8_t *bios = bp->base.bios;
2074 uint8_t *bios_dst = (uint8_t *)dst;
2075 uint16_t packed_rom_header_offset;
2076 uint16_t packed_masterdatatable_offset;
2077 uint16_t packed_data_tbl_offset;
2078 uint16_t data_tbl_offset;
2079 unsigned int i;
2080
2081 rom_header_offset =
2082 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER);
2083
2084 if (!rom_header_offset)
2085 return 0;
2086
2087 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset);
2088
2089 if (!rom_header)
2090 return 0;
2091
2092 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev);
2093 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2))
2094 return 0;
2095
2096 get_atom_data_table_revision(&bp->master_data_tbl->table_header, &tbl_rev);
2097 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 1))
2098 return 0;
2099
2100 packed_rom_header_offset =
2101 OFFSET_TO_ATOM_ROM_HEADER_POINTER + sizeof(*rom_header_offset);
2102
2103 packed_masterdatatable_offset =
2104 packed_rom_header_offset + rom_header->table_header.structuresize;
2105
2106 packed_data_tbl_offset =
2107 packed_masterdatatable_offset +
2108 bp->master_data_tbl->table_header.structuresize;
2109
2110 packed_rom_header =
2111 (struct atom_rom_header_v2_2 *)(bios_dst + packed_rom_header_offset);
2112
2113 packed_master_data_tbl =
2114 (struct atom_master_data_table_v2_1 *)(bios_dst +
2115 packed_masterdatatable_offset);
2116
2117 memcpy(bios_dst, bios, OFFSET_TO_ATOM_ROM_HEADER_POINTER);
2118
2119 *((uint16_t *)(bios_dst + OFFSET_TO_ATOM_ROM_HEADER_POINTER)) =
2120 packed_rom_header_offset;
2121
2122 memcpy(bios_dst + packed_rom_header_offset, rom_header,
2123 rom_header->table_header.structuresize);
2124
2125 packed_rom_header->masterdatatable_offset = packed_masterdatatable_offset;
2126
2127 memcpy(&packed_master_data_tbl->table_header,
2128 &bp->master_data_tbl->table_header,
2129 sizeof(bp->master_data_tbl->table_header));
2130
2131 data_tbl_list = &bp->master_data_tbl->listOfdatatables;
2132
2133 /* Each data table offset in data table list is 2 bytes,
2134 * we can use that to iterate through listOfdatatables
2135 * without knowing the name of each member.
2136 */
2137 for (i = 0; i < sizeof(*data_tbl_list)/sizeof(uint16_t); i++) {
2138 data_tbl_offset = *((uint16_t *)data_tbl_list + i);
2139
2140 if (data_tbl_offset) {
2141 data_tbl_header =
2142 (struct atom_common_table_header *)(bios + data_tbl_offset);
2143
2144 memcpy(bios_dst + packed_data_tbl_offset, data_tbl_header,
2145 data_tbl_header->structuresize);
2146
2147 *((uint16_t *)&packed_master_data_tbl->listOfdatatables + i) =
2148 packed_data_tbl_offset;
2149
2150 packed_data_tbl_offset += data_tbl_header->structuresize;
2151 } else {
2152 *((uint16_t *)&packed_master_data_tbl->listOfdatatables + i) = 0;
2153 }
2154 }
2155 return packed_data_tbl_offset;
2156 #endif
2157 // TODO: There is data bytes alignment issue, disable it for now.
2158 return 0;
2159 }
2160
bios_get_golden_table(struct bios_parser * bp,uint32_t rev_major,uint32_t rev_minor,uint16_t * dc_golden_table_ver)2161 static struct atom_dc_golden_table_v1 *bios_get_golden_table(
2162 struct bios_parser *bp,
2163 uint32_t rev_major,
2164 uint32_t rev_minor,
2165 uint16_t *dc_golden_table_ver)
2166 {
2167 struct atom_display_controller_info_v4_4 *disp_cntl_tbl_4_4 = NULL;
2168 uint32_t dc_golden_offset = 0;
2169 *dc_golden_table_ver = 0;
2170
2171 if (!DATA_TABLES(dce_info))
2172 return NULL;
2173
2174 /* ver.4.4 or higher */
2175 switch (rev_major) {
2176 case 4:
2177 switch (rev_minor) {
2178 case 4:
2179 disp_cntl_tbl_4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4,
2180 DATA_TABLES(dce_info));
2181 if (!disp_cntl_tbl_4_4)
2182 return NULL;
2183 dc_golden_offset = DATA_TABLES(dce_info) + disp_cntl_tbl_4_4->dc_golden_table_offset;
2184 *dc_golden_table_ver = disp_cntl_tbl_4_4->dc_golden_table_ver;
2185 break;
2186 }
2187 break;
2188 }
2189
2190 if (!dc_golden_offset)
2191 return NULL;
2192
2193 if (*dc_golden_table_ver != 1)
2194 return NULL;
2195
2196 return GET_IMAGE(struct atom_dc_golden_table_v1,
2197 dc_golden_offset);
2198 }
2199
bios_get_atom_dc_golden_table(struct dc_bios * dcb)2200 static enum bp_result bios_get_atom_dc_golden_table(
2201 struct dc_bios *dcb)
2202 {
2203 struct bios_parser *bp = BP_FROM_DCB(dcb);
2204 enum bp_result result = BP_RESULT_OK;
2205 struct atom_dc_golden_table_v1 *atom_dc_golden_table = NULL;
2206 struct atom_common_table_header *header;
2207 struct atom_data_revision tbl_revision;
2208 uint16_t dc_golden_table_ver = 0;
2209
2210 header = GET_IMAGE(struct atom_common_table_header,
2211 DATA_TABLES(dce_info));
2212 if (!header)
2213 return BP_RESULT_UNSUPPORTED;
2214
2215 get_atom_data_table_revision(header, &tbl_revision);
2216
2217 atom_dc_golden_table = bios_get_golden_table(bp,
2218 tbl_revision.major,
2219 tbl_revision.minor,
2220 &dc_golden_table_ver);
2221
2222 if (!atom_dc_golden_table)
2223 return BP_RESULT_UNSUPPORTED;
2224
2225 dcb->golden_table.dc_golden_table_ver = dc_golden_table_ver;
2226 dcb->golden_table.aux_dphy_rx_control0_val = atom_dc_golden_table->aux_dphy_rx_control0_val;
2227 dcb->golden_table.aux_dphy_rx_control1_val = atom_dc_golden_table->aux_dphy_rx_control1_val;
2228 dcb->golden_table.aux_dphy_tx_control_val = atom_dc_golden_table->aux_dphy_tx_control_val;
2229 dcb->golden_table.dc_gpio_aux_ctrl_0_val = atom_dc_golden_table->dc_gpio_aux_ctrl_0_val;
2230 dcb->golden_table.dc_gpio_aux_ctrl_1_val = atom_dc_golden_table->dc_gpio_aux_ctrl_1_val;
2231 dcb->golden_table.dc_gpio_aux_ctrl_2_val = atom_dc_golden_table->dc_gpio_aux_ctrl_2_val;
2232 dcb->golden_table.dc_gpio_aux_ctrl_3_val = atom_dc_golden_table->dc_gpio_aux_ctrl_3_val;
2233 dcb->golden_table.dc_gpio_aux_ctrl_4_val = atom_dc_golden_table->dc_gpio_aux_ctrl_4_val;
2234 dcb->golden_table.dc_gpio_aux_ctrl_5_val = atom_dc_golden_table->dc_gpio_aux_ctrl_5_val;
2235
2236 return result;
2237 }
2238
2239
2240 static const struct dc_vbios_funcs vbios_funcs = {
2241 .get_connectors_number = bios_parser_get_connectors_number,
2242
2243 .get_connector_id = bios_parser_get_connector_id,
2244
2245 .get_src_obj = bios_parser_get_src_obj,
2246
2247 .get_i2c_info = bios_parser_get_i2c_info,
2248
2249 .get_hpd_info = bios_parser_get_hpd_info,
2250
2251 .get_device_tag = bios_parser_get_device_tag,
2252
2253 .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info,
2254
2255 .get_ss_entry_number = bios_parser_get_ss_entry_number,
2256
2257 .get_embedded_panel_info = bios_parser_get_embedded_panel_info,
2258
2259 .get_gpio_pin_info = bios_parser_get_gpio_pin_info,
2260
2261 .get_encoder_cap_info = bios_parser_get_encoder_cap_info,
2262
2263 .is_device_id_supported = bios_parser_is_device_id_supported,
2264
2265 .is_accelerated_mode = bios_parser_is_accelerated_mode,
2266
2267 .set_scratch_critical_state = bios_parser_set_scratch_critical_state,
2268
2269
2270 /* COMMANDS */
2271 .encoder_control = bios_parser_encoder_control,
2272
2273 .transmitter_control = bios_parser_transmitter_control,
2274
2275 .enable_crtc = bios_parser_enable_crtc,
2276
2277 .set_pixel_clock = bios_parser_set_pixel_clock,
2278
2279 .set_dce_clock = bios_parser_set_dce_clock,
2280
2281 .program_crtc_timing = bios_parser_program_crtc_timing,
2282
2283 .enable_disp_power_gating = bios_parser_enable_disp_power_gating,
2284
2285 .bios_parser_destroy = firmware_parser_destroy,
2286
2287 .get_board_layout_info = bios_get_board_layout_info,
2288 .pack_data_tables = bios_parser_pack_data_tables,
2289
2290 .get_atom_dc_golden_table = bios_get_atom_dc_golden_table,
2291
2292 .enable_lvtma_control = bios_parser_enable_lvtma_control,
2293
2294 .get_soc_bb_info = bios_parser_get_soc_bb_info,
2295 };
2296
bios_parser2_construct(struct bios_parser * bp,struct bp_init_data * init,enum dce_version dce_version)2297 static bool bios_parser2_construct(
2298 struct bios_parser *bp,
2299 struct bp_init_data *init,
2300 enum dce_version dce_version)
2301 {
2302 uint16_t *rom_header_offset = NULL;
2303 struct atom_rom_header_v2_2 *rom_header = NULL;
2304 struct display_object_info_table_v1_4 *object_info_tbl;
2305 struct atom_data_revision tbl_rev = {0};
2306
2307 if (!init)
2308 return false;
2309
2310 if (!init->bios)
2311 return false;
2312
2313 bp->base.funcs = &vbios_funcs;
2314 bp->base.bios = init->bios;
2315 bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT;
2316
2317 bp->base.ctx = init->ctx;
2318
2319 bp->base.bios_local_image = NULL;
2320
2321 rom_header_offset =
2322 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER);
2323
2324 if (!rom_header_offset)
2325 return false;
2326
2327 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset);
2328
2329 if (!rom_header)
2330 return false;
2331
2332 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev);
2333 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2))
2334 return false;
2335
2336 bp->master_data_tbl =
2337 GET_IMAGE(struct atom_master_data_table_v2_1,
2338 rom_header->masterdatatable_offset);
2339
2340 if (!bp->master_data_tbl)
2341 return false;
2342
2343 bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo);
2344
2345 if (!bp->object_info_tbl_offset)
2346 return false;
2347
2348 object_info_tbl =
2349 GET_IMAGE(struct display_object_info_table_v1_4,
2350 bp->object_info_tbl_offset);
2351
2352 if (!object_info_tbl)
2353 return false;
2354
2355 get_atom_data_table_revision(&object_info_tbl->table_header,
2356 &bp->object_info_tbl.revision);
2357
2358 if (bp->object_info_tbl.revision.major == 1
2359 && bp->object_info_tbl.revision.minor >= 4) {
2360 struct display_object_info_table_v1_4 *tbl_v1_4;
2361
2362 tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4,
2363 bp->object_info_tbl_offset);
2364 if (!tbl_v1_4)
2365 return false;
2366
2367 bp->object_info_tbl.v1_4 = tbl_v1_4;
2368 } else
2369 return false;
2370
2371 dal_firmware_parser_init_cmd_tbl(bp);
2372 dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version);
2373
2374 bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);
2375 bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK;
2376 bios_parser_get_vram_info(&bp->base, &bp->base.vram_info);
2377
2378 return true;
2379 }
2380
firmware_parser_create(struct bp_init_data * init,enum dce_version dce_version)2381 struct dc_bios *firmware_parser_create(
2382 struct bp_init_data *init,
2383 enum dce_version dce_version)
2384 {
2385 struct bios_parser *bp = NULL;
2386
2387 bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL);
2388 if (!bp)
2389 return NULL;
2390
2391 if (bios_parser2_construct(bp, init, dce_version))
2392 return &bp->base;
2393
2394 kfree(bp);
2395 return NULL;
2396 }
2397
2398
2399
