1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
7 *
8 * MMU support
9 *
10 * Copyright (C) 2006 Qumranet, Inc.
11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 *
13 * Authors:
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
16 */
17
18 /*
19 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
20 * so the code in this file is compiled twice, once per pte size.
21 */
22
23 #if PTTYPE == 64
24 #define pt_element_t u64
25 #define guest_walker guest_walker64
26 #define FNAME(name) paging##64_##name
27 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
28 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
29 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
30 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
31 #define PT_LEVEL_BITS PT64_LEVEL_BITS
32 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
33 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
34 #define PT_HAVE_ACCESSED_DIRTY(mmu) true
35 #ifdef CONFIG_X86_64
36 #define PT_MAX_FULL_LEVELS PT64_ROOT_MAX_LEVEL
37 #define CMPXCHG cmpxchg
38 #else
39 #define CMPXCHG cmpxchg64
40 #define PT_MAX_FULL_LEVELS 2
41 #endif
42 #elif PTTYPE == 32
43 #define pt_element_t u32
44 #define guest_walker guest_walker32
45 #define FNAME(name) paging##32_##name
46 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
47 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
48 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
49 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
50 #define PT_LEVEL_BITS PT32_LEVEL_BITS
51 #define PT_MAX_FULL_LEVELS 2
52 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
53 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
54 #define PT_HAVE_ACCESSED_DIRTY(mmu) true
55 #define CMPXCHG cmpxchg
56 #elif PTTYPE == PTTYPE_EPT
57 #define pt_element_t u64
58 #define guest_walker guest_walkerEPT
59 #define FNAME(name) ept_##name
60 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
61 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
62 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
63 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
64 #define PT_LEVEL_BITS PT64_LEVEL_BITS
65 #define PT_GUEST_DIRTY_SHIFT 9
66 #define PT_GUEST_ACCESSED_SHIFT 8
67 #define PT_HAVE_ACCESSED_DIRTY(mmu) ((mmu)->ept_ad)
68 #define CMPXCHG cmpxchg64
69 #define PT_MAX_FULL_LEVELS PT64_ROOT_MAX_LEVEL
70 #else
71 #error Invalid PTTYPE value
72 #endif
73
74 #define PT_GUEST_DIRTY_MASK (1 << PT_GUEST_DIRTY_SHIFT)
75 #define PT_GUEST_ACCESSED_MASK (1 << PT_GUEST_ACCESSED_SHIFT)
76
77 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
78 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PG_LEVEL_4K)
79
80 /*
81 * The guest_walker structure emulates the behavior of the hardware page
82 * table walker.
83 */
84 struct guest_walker {
85 int level;
86 unsigned max_level;
87 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
88 pt_element_t ptes[PT_MAX_FULL_LEVELS];
89 pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
90 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
91 pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS];
92 bool pte_writable[PT_MAX_FULL_LEVELS];
93 unsigned pt_access;
94 unsigned pte_access;
95 gfn_t gfn;
96 struct x86_exception fault;
97 };
98
gpte_to_gfn_lvl(pt_element_t gpte,int lvl)99 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
100 {
101 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
102 }
103
FNAME(protect_clean_gpte)104 static inline void FNAME(protect_clean_gpte)(struct kvm_mmu *mmu, unsigned *access,
105 unsigned gpte)
106 {
107 unsigned mask;
108
109 /* dirty bit is not supported, so no need to track it */
110 if (!PT_HAVE_ACCESSED_DIRTY(mmu))
111 return;
112
113 BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK);
114
115 mask = (unsigned)~ACC_WRITE_MASK;
116 /* Allow write access to dirty gptes */
117 mask |= (gpte >> (PT_GUEST_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) &
118 PT_WRITABLE_MASK;
119 *access &= mask;
120 }
121
FNAME(is_present_gpte)122 static inline int FNAME(is_present_gpte)(unsigned long pte)
123 {
124 #if PTTYPE != PTTYPE_EPT
125 return pte & PT_PRESENT_MASK;
126 #else
127 return pte & 7;
128 #endif
129 }
130
FNAME(is_bad_mt_xwr)131 static bool FNAME(is_bad_mt_xwr)(struct rsvd_bits_validate *rsvd_check, u64 gpte)
132 {
133 #if PTTYPE != PTTYPE_EPT
134 return false;
135 #else
136 return __is_bad_mt_xwr(rsvd_check, gpte);
137 #endif
138 }
139
FNAME(is_rsvd_bits_set)140 static bool FNAME(is_rsvd_bits_set)(struct kvm_mmu *mmu, u64 gpte, int level)
141 {
142 return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level) ||
143 FNAME(is_bad_mt_xwr)(&mmu->guest_rsvd_check, gpte);
144 }
145
FNAME(cmpxchg_gpte)146 static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
147 pt_element_t __user *ptep_user, unsigned index,
148 pt_element_t orig_pte, pt_element_t new_pte)
149 {
150 int npages;
151 pt_element_t ret;
152 pt_element_t *table;
153 struct page *page;
154
155 npages = get_user_pages_fast((unsigned long)ptep_user, 1, FOLL_WRITE, &page);
156 if (likely(npages == 1)) {
157 table = kmap_atomic(page);
158 ret = CMPXCHG(&table[index], orig_pte, new_pte);
159 kunmap_atomic(table);
160
161 kvm_release_page_dirty(page);
162 } else {
163 struct vm_area_struct *vma;
164 unsigned long vaddr = (unsigned long)ptep_user & PAGE_MASK;
165 unsigned long pfn;
166 unsigned long paddr;
167
168 mmap_read_lock(current->mm);
169 vma = find_vma_intersection(current->mm, vaddr, vaddr + PAGE_SIZE);
170 if (!vma || !(vma->vm_flags & VM_PFNMAP)) {
171 mmap_read_unlock(current->mm);
172 return -EFAULT;
173 }
174 pfn = ((vaddr - vma->vm_start) >> PAGE_SHIFT) + vma->vm_pgoff;
175 paddr = pfn << PAGE_SHIFT;
176 table = memremap(paddr, PAGE_SIZE, MEMREMAP_WB);
177 if (!table) {
178 mmap_read_unlock(current->mm);
179 return -EFAULT;
180 }
181 ret = CMPXCHG(&table[index], orig_pte, new_pte);
182 memunmap(table);
183 mmap_read_unlock(current->mm);
184 }
185
186 return (ret != orig_pte);
187 }
188
FNAME(prefetch_invalid_gpte)189 static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu,
190 struct kvm_mmu_page *sp, u64 *spte,
191 u64 gpte)
192 {
193 if (!FNAME(is_present_gpte)(gpte))
194 goto no_present;
195
196 /* if accessed bit is not supported prefetch non accessed gpte */
197 if (PT_HAVE_ACCESSED_DIRTY(vcpu->arch.mmu) &&
198 !(gpte & PT_GUEST_ACCESSED_MASK))
199 goto no_present;
200
201 if (FNAME(is_rsvd_bits_set)(vcpu->arch.mmu, gpte, PG_LEVEL_4K))
202 goto no_present;
203
204 return false;
205
206 no_present:
207 drop_spte(vcpu->kvm, spte);
208 return true;
209 }
210
211 /*
212 * For PTTYPE_EPT, a page table can be executable but not readable
213 * on supported processors. Therefore, set_spte does not automatically
214 * set bit 0 if execute only is supported. Here, we repurpose ACC_USER_MASK
215 * to signify readability since it isn't used in the EPT case
216 */
FNAME(gpte_access)217 static inline unsigned FNAME(gpte_access)(u64 gpte)
218 {
219 unsigned access;
220 #if PTTYPE == PTTYPE_EPT
221 access = ((gpte & VMX_EPT_WRITABLE_MASK) ? ACC_WRITE_MASK : 0) |
222 ((gpte & VMX_EPT_EXECUTABLE_MASK) ? ACC_EXEC_MASK : 0) |
223 ((gpte & VMX_EPT_READABLE_MASK) ? ACC_USER_MASK : 0);
224 #else
225 BUILD_BUG_ON(ACC_EXEC_MASK != PT_PRESENT_MASK);
226 BUILD_BUG_ON(ACC_EXEC_MASK != 1);
227 access = gpte & (PT_WRITABLE_MASK | PT_USER_MASK | PT_PRESENT_MASK);
228 /* Combine NX with P (which is set here) to get ACC_EXEC_MASK. */
229 access ^= (gpte >> PT64_NX_SHIFT);
230 #endif
231
232 return access;
233 }
234
FNAME(update_accessed_dirty_bits)235 static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu,
236 struct kvm_mmu *mmu,
237 struct guest_walker *walker,
238 gpa_t addr, int write_fault)
239 {
240 unsigned level, index;
241 pt_element_t pte, orig_pte;
242 pt_element_t __user *ptep_user;
243 gfn_t table_gfn;
244 int ret;
245
246 /* dirty/accessed bits are not supported, so no need to update them */
247 if (!PT_HAVE_ACCESSED_DIRTY(mmu))
248 return 0;
249
250 for (level = walker->max_level; level >= walker->level; --level) {
251 pte = orig_pte = walker->ptes[level - 1];
252 table_gfn = walker->table_gfn[level - 1];
253 ptep_user = walker->ptep_user[level - 1];
254 index = offset_in_page(ptep_user) / sizeof(pt_element_t);
255 if (!(pte & PT_GUEST_ACCESSED_MASK)) {
256 trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte));
257 pte |= PT_GUEST_ACCESSED_MASK;
258 }
259 if (level == walker->level && write_fault &&
260 !(pte & PT_GUEST_DIRTY_MASK)) {
261 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
262 #if PTTYPE == PTTYPE_EPT
263 if (kvm_x86_ops.nested_ops->write_log_dirty(vcpu, addr))
264 return -EINVAL;
265 #endif
266 pte |= PT_GUEST_DIRTY_MASK;
267 }
268 if (pte == orig_pte)
269 continue;
270
271 /*
272 * If the slot is read-only, simply do not process the accessed
273 * and dirty bits. This is the correct thing to do if the slot
274 * is ROM, and page tables in read-as-ROM/write-as-MMIO slots
275 * are only supported if the accessed and dirty bits are already
276 * set in the ROM (so that MMIO writes are never needed).
277 *
278 * Note that NPT does not allow this at all and faults, since
279 * it always wants nested page table entries for the guest
280 * page tables to be writable. And EPT works but will simply
281 * overwrite the read-only memory to set the accessed and dirty
282 * bits.
283 */
284 if (unlikely(!walker->pte_writable[level - 1]))
285 continue;
286
287 ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte);
288 if (ret)
289 return ret;
290
291 kvm_vcpu_mark_page_dirty(vcpu, table_gfn);
292 walker->ptes[level - 1] = pte;
293 }
294 return 0;
295 }
296
FNAME(gpte_pkeys)297 static inline unsigned FNAME(gpte_pkeys)(struct kvm_vcpu *vcpu, u64 gpte)
298 {
299 unsigned pkeys = 0;
300 #if PTTYPE == 64
301 pte_t pte = {.pte = gpte};
302
303 pkeys = pte_flags_pkey(pte_flags(pte));
304 #endif
305 return pkeys;
306 }
307
308 /*
309 * Fetch a guest pte for a guest virtual address, or for an L2's GPA.
310 */
FNAME(walk_addr_generic)311 static int FNAME(walk_addr_generic)(struct guest_walker *walker,
312 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
313 gpa_t addr, u32 access)
314 {
315 int ret;
316 pt_element_t pte;
317 pt_element_t __user *ptep_user;
318 gfn_t table_gfn;
319 u64 pt_access, pte_access;
320 unsigned index, accessed_dirty, pte_pkey;
321 unsigned nested_access;
322 gpa_t pte_gpa;
323 bool have_ad;
324 int offset;
325 u64 walk_nx_mask = 0;
326 const int write_fault = access & PFERR_WRITE_MASK;
327 const int user_fault = access & PFERR_USER_MASK;
328 const int fetch_fault = access & PFERR_FETCH_MASK;
329 u16 errcode = 0;
330 gpa_t real_gpa;
331 gfn_t gfn;
332
333 trace_kvm_mmu_pagetable_walk(addr, access);
334 retry_walk:
335 walker->level = mmu->root_level;
336 pte = mmu->get_guest_pgd(vcpu);
337 have_ad = PT_HAVE_ACCESSED_DIRTY(mmu);
338
339 #if PTTYPE == 64
340 walk_nx_mask = 1ULL << PT64_NX_SHIFT;
341 if (walker->level == PT32E_ROOT_LEVEL) {
342 pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3);
343 trace_kvm_mmu_paging_element(pte, walker->level);
344 if (!FNAME(is_present_gpte)(pte))
345 goto error;
346 --walker->level;
347 }
348 #endif
349 walker->max_level = walker->level;
350 ASSERT(!(is_long_mode(vcpu) && !is_pae(vcpu)));
351
352 /*
353 * FIXME: on Intel processors, loads of the PDPTE registers for PAE paging
354 * by the MOV to CR instruction are treated as reads and do not cause the
355 * processor to set the dirty flag in any EPT paging-structure entry.
356 */
357 nested_access = (have_ad ? PFERR_WRITE_MASK : 0) | PFERR_USER_MASK;
358
359 pte_access = ~0;
360 ++walker->level;
361
362 do {
363 unsigned long host_addr;
364
365 pt_access = pte_access;
366 --walker->level;
367
368 index = PT_INDEX(addr, walker->level);
369 table_gfn = gpte_to_gfn(pte);
370 offset = index * sizeof(pt_element_t);
371 pte_gpa = gfn_to_gpa(table_gfn) + offset;
372
373 BUG_ON(walker->level < 1);
374 walker->table_gfn[walker->level - 1] = table_gfn;
375 walker->pte_gpa[walker->level - 1] = pte_gpa;
376
377 real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn),
378 nested_access,
379 &walker->fault);
380
381 /*
382 * FIXME: This can happen if emulation (for of an INS/OUTS
383 * instruction) triggers a nested page fault. The exit
384 * qualification / exit info field will incorrectly have
385 * "guest page access" as the nested page fault's cause,
386 * instead of "guest page structure access". To fix this,
387 * the x86_exception struct should be augmented with enough
388 * information to fix the exit_qualification or exit_info_1
389 * fields.
390 */
391 if (unlikely(real_gpa == UNMAPPED_GVA))
392 return 0;
393
394 host_addr = kvm_vcpu_gfn_to_hva_prot(vcpu, gpa_to_gfn(real_gpa),
395 &walker->pte_writable[walker->level - 1]);
396 if (unlikely(kvm_is_error_hva(host_addr)))
397 goto error;
398
399 ptep_user = (pt_element_t __user *)((void *)host_addr + offset);
400 if (unlikely(__get_user(pte, ptep_user)))
401 goto error;
402 walker->ptep_user[walker->level - 1] = ptep_user;
403
404 trace_kvm_mmu_paging_element(pte, walker->level);
405
406 /*
407 * Inverting the NX it lets us AND it like other
408 * permission bits.
409 */
410 pte_access = pt_access & (pte ^ walk_nx_mask);
411
412 if (unlikely(!FNAME(is_present_gpte)(pte)))
413 goto error;
414
415 if (unlikely(FNAME(is_rsvd_bits_set)(mmu, pte, walker->level))) {
416 errcode = PFERR_RSVD_MASK | PFERR_PRESENT_MASK;
417 goto error;
418 }
419
420 walker->ptes[walker->level - 1] = pte;
421 } while (!is_last_gpte(mmu, walker->level, pte));
422
423 pte_pkey = FNAME(gpte_pkeys)(vcpu, pte);
424 accessed_dirty = have_ad ? pte_access & PT_GUEST_ACCESSED_MASK : 0;
425
426 /* Convert to ACC_*_MASK flags for struct guest_walker. */
427 walker->pt_access = FNAME(gpte_access)(pt_access ^ walk_nx_mask);
428 walker->pte_access = FNAME(gpte_access)(pte_access ^ walk_nx_mask);
429 errcode = permission_fault(vcpu, mmu, walker->pte_access, pte_pkey, access);
430 if (unlikely(errcode))
431 goto error;
432
433 gfn = gpte_to_gfn_lvl(pte, walker->level);
434 gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT;
435
436 if (PTTYPE == 32 && walker->level > PG_LEVEL_4K && is_cpuid_PSE36())
437 gfn += pse36_gfn_delta(pte);
438
439 real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access, &walker->fault);
440 if (real_gpa == UNMAPPED_GVA)
441 return 0;
442
443 walker->gfn = real_gpa >> PAGE_SHIFT;
444
445 if (!write_fault)
446 FNAME(protect_clean_gpte)(mmu, &walker->pte_access, pte);
447 else
448 /*
449 * On a write fault, fold the dirty bit into accessed_dirty.
450 * For modes without A/D bits support accessed_dirty will be
451 * always clear.
452 */
453 accessed_dirty &= pte >>
454 (PT_GUEST_DIRTY_SHIFT - PT_GUEST_ACCESSED_SHIFT);
455
456 if (unlikely(!accessed_dirty)) {
457 ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker,
458 addr, write_fault);
459 if (unlikely(ret < 0))
460 goto error;
461 else if (ret)
462 goto retry_walk;
463 }
464
465 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
466 __func__, (u64)pte, walker->pte_access, walker->pt_access);
467 return 1;
468
469 error:
470 errcode |= write_fault | user_fault;
471 if (fetch_fault && (mmu->nx ||
472 kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)))
473 errcode |= PFERR_FETCH_MASK;
474
475 walker->fault.vector = PF_VECTOR;
476 walker->fault.error_code_valid = true;
477 walker->fault.error_code = errcode;
478
479 #if PTTYPE == PTTYPE_EPT
480 /*
481 * Use PFERR_RSVD_MASK in error_code to to tell if EPT
482 * misconfiguration requires to be injected. The detection is
483 * done by is_rsvd_bits_set() above.
484 *
485 * We set up the value of exit_qualification to inject:
486 * [2:0] - Derive from the access bits. The exit_qualification might be
487 * out of date if it is serving an EPT misconfiguration.
488 * [5:3] - Calculated by the page walk of the guest EPT page tables
489 * [7:8] - Derived from [7:8] of real exit_qualification
490 *
491 * The other bits are set to 0.
492 */
493 if (!(errcode & PFERR_RSVD_MASK)) {
494 vcpu->arch.exit_qualification &= 0x180;
495 if (write_fault)
496 vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_WRITE;
497 if (user_fault)
498 vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_READ;
499 if (fetch_fault)
500 vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_INSTR;
501 vcpu->arch.exit_qualification |= (pte_access & 0x7) << 3;
502 }
503 #endif
504 walker->fault.address = addr;
505 walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu;
506
507 trace_kvm_mmu_walker_error(walker->fault.error_code);
508 return 0;
509 }
510
FNAME(walk_addr)511 static int FNAME(walk_addr)(struct guest_walker *walker,
512 struct kvm_vcpu *vcpu, gpa_t addr, u32 access)
513 {
514 return FNAME(walk_addr_generic)(walker, vcpu, vcpu->arch.mmu, addr,
515 access);
516 }
517
518 #if PTTYPE != PTTYPE_EPT
FNAME(walk_addr_nested)519 static int FNAME(walk_addr_nested)(struct guest_walker *walker,
520 struct kvm_vcpu *vcpu, gva_t addr,
521 u32 access)
522 {
523 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu,
524 addr, access);
525 }
526 #endif
527
528 static bool
FNAME(prefetch_gpte)529 FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
530 u64 *spte, pt_element_t gpte, bool no_dirty_log)
531 {
532 unsigned pte_access;
533 gfn_t gfn;
534 kvm_pfn_t pfn;
535
536 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
537 return false;
538
539 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
540
541 gfn = gpte_to_gfn(gpte);
542 pte_access = sp->role.access & FNAME(gpte_access)(gpte);
543 FNAME(protect_clean_gpte)(vcpu->arch.mmu, &pte_access, gpte);
544 pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
545 no_dirty_log && (pte_access & ACC_WRITE_MASK));
546 if (is_error_pfn(pfn))
547 return false;
548
549 /*
550 * we call mmu_set_spte() with host_writable = true because
551 * pte_prefetch_gfn_to_pfn always gets a writable pfn.
552 */
553 mmu_set_spte(vcpu, spte, pte_access, false, PG_LEVEL_4K, gfn, pfn,
554 true, true);
555
556 kvm_release_pfn_clean(pfn);
557 return true;
558 }
559
FNAME(update_pte)560 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
561 u64 *spte, const void *pte)
562 {
563 pt_element_t gpte = *(const pt_element_t *)pte;
564
565 FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false);
566 }
567
FNAME(gpte_changed)568 static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
569 struct guest_walker *gw, int level)
570 {
571 pt_element_t curr_pte;
572 gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
573 u64 mask;
574 int r, index;
575
576 if (level == PG_LEVEL_4K) {
577 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
578 base_gpa = pte_gpa & ~mask;
579 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
580
581 r = kvm_vcpu_read_guest_atomic(vcpu, base_gpa,
582 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
583 curr_pte = gw->prefetch_ptes[index];
584 } else
585 r = kvm_vcpu_read_guest_atomic(vcpu, pte_gpa,
586 &curr_pte, sizeof(curr_pte));
587
588 return r || curr_pte != gw->ptes[level - 1];
589 }
590
FNAME(pte_prefetch)591 static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
592 u64 *sptep)
593 {
594 struct kvm_mmu_page *sp;
595 pt_element_t *gptep = gw->prefetch_ptes;
596 u64 *spte;
597 int i;
598
599 sp = sptep_to_sp(sptep);
600
601 if (sp->role.level > PG_LEVEL_4K)
602 return;
603
604 if (sp->role.direct)
605 return __direct_pte_prefetch(vcpu, sp, sptep);
606
607 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
608 spte = sp->spt + i;
609
610 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
611 if (spte == sptep)
612 continue;
613
614 if (is_shadow_present_pte(*spte))
615 continue;
616
617 if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true))
618 break;
619 }
620 }
621
622 /*
623 * Fetch a shadow pte for a specific level in the paging hierarchy.
624 * If the guest tries to write a write-protected page, we need to
625 * emulate this operation, return 1 to indicate this case.
626 */
FNAME(fetch)627 static int FNAME(fetch)(struct kvm_vcpu *vcpu, gpa_t addr,
628 struct guest_walker *gw, u32 error_code,
629 int max_level, kvm_pfn_t pfn, bool map_writable,
630 bool prefault)
631 {
632 bool nx_huge_page_workaround_enabled = is_nx_huge_page_enabled();
633 bool write_fault = error_code & PFERR_WRITE_MASK;
634 bool exec = error_code & PFERR_FETCH_MASK;
635 bool huge_page_disallowed = exec && nx_huge_page_workaround_enabled;
636 struct kvm_mmu_page *sp = NULL;
637 struct kvm_shadow_walk_iterator it;
638 unsigned direct_access, access = gw->pt_access;
639 int top_level, level, req_level, ret;
640 gfn_t base_gfn = gw->gfn;
641
642 direct_access = gw->pte_access;
643
644 top_level = vcpu->arch.mmu->root_level;
645 if (top_level == PT32E_ROOT_LEVEL)
646 top_level = PT32_ROOT_LEVEL;
647 /*
648 * Verify that the top-level gpte is still there. Since the page
649 * is a root page, it is either write protected (and cannot be
650 * changed from now on) or it is invalid (in which case, we don't
651 * really care if it changes underneath us after this point).
652 */
653 if (FNAME(gpte_changed)(vcpu, gw, top_level))
654 goto out_gpte_changed;
655
656 if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)))
657 goto out_gpte_changed;
658
659 for (shadow_walk_init(&it, vcpu, addr);
660 shadow_walk_okay(&it) && it.level > gw->level;
661 shadow_walk_next(&it)) {
662 gfn_t table_gfn;
663
664 clear_sp_write_flooding_count(it.sptep);
665 drop_large_spte(vcpu, it.sptep);
666
667 sp = NULL;
668 if (!is_shadow_present_pte(*it.sptep)) {
669 table_gfn = gw->table_gfn[it.level - 2];
670 sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
671 false, access);
672 }
673
674 /*
675 * Verify that the gpte in the page we've just write
676 * protected is still there.
677 */
678 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
679 goto out_gpte_changed;
680
681 if (sp)
682 link_shadow_page(vcpu, it.sptep, sp);
683 }
684
685 level = kvm_mmu_hugepage_adjust(vcpu, gw->gfn, max_level, &pfn,
686 huge_page_disallowed, &req_level);
687
688 trace_kvm_mmu_spte_requested(addr, gw->level, pfn);
689
690 for (; shadow_walk_okay(&it); shadow_walk_next(&it)) {
691 clear_sp_write_flooding_count(it.sptep);
692
693 /*
694 * We cannot overwrite existing page tables with an NX
695 * large page, as the leaf could be executable.
696 */
697 if (nx_huge_page_workaround_enabled)
698 disallowed_hugepage_adjust(*it.sptep, gw->gfn, it.level,
699 &pfn, &level);
700
701 base_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
702 if (it.level == level)
703 break;
704
705 validate_direct_spte(vcpu, it.sptep, direct_access);
706
707 drop_large_spte(vcpu, it.sptep);
708
709 if (!is_shadow_present_pte(*it.sptep)) {
710 sp = kvm_mmu_get_page(vcpu, base_gfn, addr,
711 it.level - 1, true, direct_access);
712 link_shadow_page(vcpu, it.sptep, sp);
713 if (huge_page_disallowed && req_level >= it.level)
714 account_huge_nx_page(vcpu->kvm, sp);
715 }
716 }
717
718 ret = mmu_set_spte(vcpu, it.sptep, gw->pte_access, write_fault,
719 it.level, base_gfn, pfn, prefault, map_writable);
720 if (ret == RET_PF_SPURIOUS)
721 return ret;
722
723 FNAME(pte_prefetch)(vcpu, gw, it.sptep);
724 ++vcpu->stat.pf_fixed;
725 return ret;
726
727 out_gpte_changed:
728 return RET_PF_RETRY;
729 }
730
731 /*
732 * To see whether the mapped gfn can write its page table in the current
733 * mapping.
734 *
735 * It is the helper function of FNAME(page_fault). When guest uses large page
736 * size to map the writable gfn which is used as current page table, we should
737 * force kvm to use small page size to map it because new shadow page will be
738 * created when kvm establishes shadow page table that stop kvm using large
739 * page size. Do it early can avoid unnecessary #PF and emulation.
740 *
741 * @write_fault_to_shadow_pgtable will return true if the fault gfn is
742 * currently used as its page table.
743 *
744 * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok
745 * since the PDPT is always shadowed, that means, we can not use large page
746 * size to map the gfn which is used as PDPT.
747 */
748 static bool
FNAME(is_self_change_mapping)749 FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu,
750 struct guest_walker *walker, bool user_fault,
751 bool *write_fault_to_shadow_pgtable)
752 {
753 int level;
754 gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1);
755 bool self_changed = false;
756
757 if (!(walker->pte_access & ACC_WRITE_MASK ||
758 (!is_write_protection(vcpu) && !user_fault)))
759 return false;
760
761 for (level = walker->level; level <= walker->max_level; level++) {
762 gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1];
763
764 self_changed |= !(gfn & mask);
765 *write_fault_to_shadow_pgtable |= !gfn;
766 }
767
768 return self_changed;
769 }
770
771 /*
772 * Page fault handler. There are several causes for a page fault:
773 * - there is no shadow pte for the guest pte
774 * - write access through a shadow pte marked read only so that we can set
775 * the dirty bit
776 * - write access to a shadow pte marked read only so we can update the page
777 * dirty bitmap, when userspace requests it
778 * - mmio access; in this case we will never install a present shadow pte
779 * - normal guest page fault due to the guest pte marked not present, not
780 * writable, or not executable
781 *
782 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
783 * a negative value on error.
784 */
FNAME(page_fault)785 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gpa_t addr, u32 error_code,
786 bool prefault)
787 {
788 bool write_fault = error_code & PFERR_WRITE_MASK;
789 bool user_fault = error_code & PFERR_USER_MASK;
790 struct guest_walker walker;
791 int r;
792 kvm_pfn_t pfn;
793 unsigned long mmu_seq;
794 bool map_writable, is_self_change_mapping;
795 int max_level;
796
797 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
798
799 /*
800 * If PFEC.RSVD is set, this is a shadow page fault.
801 * The bit needs to be cleared before walking guest page tables.
802 */
803 error_code &= ~PFERR_RSVD_MASK;
804
805 /*
806 * Look up the guest pte for the faulting address.
807 */
808 r = FNAME(walk_addr)(&walker, vcpu, addr, error_code);
809
810 /*
811 * The page is not mapped by the guest. Let the guest handle it.
812 */
813 if (!r) {
814 pgprintk("%s: guest page fault\n", __func__);
815 if (!prefault)
816 kvm_inject_emulated_page_fault(vcpu, &walker.fault);
817
818 return RET_PF_RETRY;
819 }
820
821 if (page_fault_handle_page_track(vcpu, error_code, walker.gfn)) {
822 shadow_page_table_clear_flood(vcpu, addr);
823 return RET_PF_EMULATE;
824 }
825
826 r = mmu_topup_memory_caches(vcpu, true);
827 if (r)
828 return r;
829
830 vcpu->arch.write_fault_to_shadow_pgtable = false;
831
832 is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu,
833 &walker, user_fault, &vcpu->arch.write_fault_to_shadow_pgtable);
834
835 if (is_self_change_mapping)
836 max_level = PG_LEVEL_4K;
837 else
838 max_level = walker.level;
839
840 mmu_seq = vcpu->kvm->mmu_notifier_seq;
841 smp_rmb();
842
843 if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault,
844 &map_writable))
845 return RET_PF_RETRY;
846
847 if (handle_abnormal_pfn(vcpu, addr, walker.gfn, pfn, walker.pte_access, &r))
848 return r;
849
850 /*
851 * Do not change pte_access if the pfn is a mmio page, otherwise
852 * we will cache the incorrect access into mmio spte.
853 */
854 if (write_fault && !(walker.pte_access & ACC_WRITE_MASK) &&
855 !is_write_protection(vcpu) && !user_fault &&
856 !is_noslot_pfn(pfn)) {
857 walker.pte_access |= ACC_WRITE_MASK;
858 walker.pte_access &= ~ACC_USER_MASK;
859
860 /*
861 * If we converted a user page to a kernel page,
862 * so that the kernel can write to it when cr0.wp=0,
863 * then we should prevent the kernel from executing it
864 * if SMEP is enabled.
865 */
866 if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
867 walker.pte_access &= ~ACC_EXEC_MASK;
868 }
869
870 r = RET_PF_RETRY;
871 spin_lock(&vcpu->kvm->mmu_lock);
872 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
873 goto out_unlock;
874
875 kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
876 r = make_mmu_pages_available(vcpu);
877 if (r)
878 goto out_unlock;
879 r = FNAME(fetch)(vcpu, addr, &walker, error_code, max_level, pfn,
880 map_writable, prefault);
881 kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
882
883 out_unlock:
884 spin_unlock(&vcpu->kvm->mmu_lock);
885 kvm_release_pfn_clean(pfn);
886 return r;
887 }
888
FNAME(get_level1_sp_gpa)889 static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp)
890 {
891 int offset = 0;
892
893 WARN_ON(sp->role.level != PG_LEVEL_4K);
894
895 if (PTTYPE == 32)
896 offset = sp->role.quadrant << PT64_LEVEL_BITS;
897
898 return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
899 }
900
FNAME(invlpg)901 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root_hpa)
902 {
903 struct kvm_shadow_walk_iterator iterator;
904 struct kvm_mmu_page *sp;
905 u64 old_spte;
906 int level;
907 u64 *sptep;
908
909 vcpu_clear_mmio_info(vcpu, gva);
910
911 /*
912 * No need to check return value here, rmap_can_add() can
913 * help us to skip pte prefetch later.
914 */
915 mmu_topup_memory_caches(vcpu, true);
916
917 if (!VALID_PAGE(root_hpa)) {
918 WARN_ON(1);
919 return;
920 }
921
922 spin_lock(&vcpu->kvm->mmu_lock);
923 for_each_shadow_entry_using_root(vcpu, root_hpa, gva, iterator) {
924 level = iterator.level;
925 sptep = iterator.sptep;
926
927 sp = sptep_to_sp(sptep);
928 old_spte = *sptep;
929 if (is_last_spte(old_spte, level)) {
930 pt_element_t gpte;
931 gpa_t pte_gpa;
932
933 if (!sp->unsync)
934 break;
935
936 pte_gpa = FNAME(get_level1_sp_gpa)(sp);
937 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
938
939 mmu_page_zap_pte(vcpu->kvm, sp, sptep, NULL);
940 if (is_shadow_present_pte(old_spte))
941 kvm_flush_remote_tlbs_with_address(vcpu->kvm,
942 sp->gfn, KVM_PAGES_PER_HPAGE(sp->role.level));
943
944 if (!rmap_can_add(vcpu))
945 break;
946
947 if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte,
948 sizeof(pt_element_t)))
949 break;
950
951 FNAME(update_pte)(vcpu, sp, sptep, &gpte);
952 }
953
954 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
955 break;
956 }
957 spin_unlock(&vcpu->kvm->mmu_lock);
958 }
959
960 /* Note, @addr is a GPA when gva_to_gpa() translates an L2 GPA to an L1 GPA. */
FNAME(gva_to_gpa)961 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gpa_t addr, u32 access,
962 struct x86_exception *exception)
963 {
964 struct guest_walker walker;
965 gpa_t gpa = UNMAPPED_GVA;
966 int r;
967
968 r = FNAME(walk_addr)(&walker, vcpu, addr, access);
969
970 if (r) {
971 gpa = gfn_to_gpa(walker.gfn);
972 gpa |= addr & ~PAGE_MASK;
973 } else if (exception)
974 *exception = walker.fault;
975
976 return gpa;
977 }
978
979 #if PTTYPE != PTTYPE_EPT
980 /* Note, gva_to_gpa_nested() is only used to translate L2 GVAs. */
FNAME(gva_to_gpa_nested)981 static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gpa_t vaddr,
982 u32 access,
983 struct x86_exception *exception)
984 {
985 struct guest_walker walker;
986 gpa_t gpa = UNMAPPED_GVA;
987 int r;
988
989 #ifndef CONFIG_X86_64
990 /* A 64-bit GVA should be impossible on 32-bit KVM. */
991 WARN_ON_ONCE(vaddr >> 32);
992 #endif
993
994 r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access);
995
996 if (r) {
997 gpa = gfn_to_gpa(walker.gfn);
998 gpa |= vaddr & ~PAGE_MASK;
999 } else if (exception)
1000 *exception = walker.fault;
1001
1002 return gpa;
1003 }
1004 #endif
1005
1006 /*
1007 * Using the cached information from sp->gfns is safe because:
1008 * - The spte has a reference to the struct page, so the pfn for a given gfn
1009 * can't change unless all sptes pointing to it are nuked first.
1010 *
1011 * Note:
1012 * We should flush all tlbs if spte is dropped even though guest is
1013 * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page
1014 * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't
1015 * used by guest then tlbs are not flushed, so guest is allowed to access the
1016 * freed pages.
1017 * And we increase kvm->tlbs_dirty to delay tlbs flush in this case.
1018 */
FNAME(sync_page)1019 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1020 {
1021 int i, nr_present = 0;
1022 bool host_writable;
1023 gpa_t first_pte_gpa;
1024 int set_spte_ret = 0;
1025
1026 /* direct kvm_mmu_page can not be unsync. */
1027 BUG_ON(sp->role.direct);
1028
1029 first_pte_gpa = FNAME(get_level1_sp_gpa)(sp);
1030
1031 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
1032 unsigned pte_access;
1033 pt_element_t gpte;
1034 gpa_t pte_gpa;
1035 gfn_t gfn;
1036
1037 if (!sp->spt[i])
1038 continue;
1039
1040 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
1041
1042 if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte,
1043 sizeof(pt_element_t)))
1044 return 0;
1045
1046 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) {
1047 /*
1048 * Update spte before increasing tlbs_dirty to make
1049 * sure no tlb flush is lost after spte is zapped; see
1050 * the comments in kvm_flush_remote_tlbs().
1051 */
1052 smp_wmb();
1053 vcpu->kvm->tlbs_dirty++;
1054 continue;
1055 }
1056
1057 gfn = gpte_to_gfn(gpte);
1058 pte_access = sp->role.access;
1059 pte_access &= FNAME(gpte_access)(gpte);
1060 FNAME(protect_clean_gpte)(vcpu->arch.mmu, &pte_access, gpte);
1061
1062 if (sync_mmio_spte(vcpu, &sp->spt[i], gfn, pte_access,
1063 &nr_present))
1064 continue;
1065
1066 if (gfn != sp->gfns[i]) {
1067 drop_spte(vcpu->kvm, &sp->spt[i]);
1068 /*
1069 * The same as above where we are doing
1070 * prefetch_invalid_gpte().
1071 */
1072 smp_wmb();
1073 vcpu->kvm->tlbs_dirty++;
1074 continue;
1075 }
1076
1077 nr_present++;
1078
1079 host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE;
1080
1081 set_spte_ret |= set_spte(vcpu, &sp->spt[i],
1082 pte_access, PG_LEVEL_4K,
1083 gfn, spte_to_pfn(sp->spt[i]),
1084 true, false, host_writable);
1085 }
1086
1087 if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH)
1088 kvm_flush_remote_tlbs(vcpu->kvm);
1089
1090 return nr_present;
1091 }
1092
1093 #undef pt_element_t
1094 #undef guest_walker
1095 #undef FNAME
1096 #undef PT_BASE_ADDR_MASK
1097 #undef PT_INDEX
1098 #undef PT_LVL_ADDR_MASK
1099 #undef PT_LVL_OFFSET_MASK
1100 #undef PT_LEVEL_BITS
1101 #undef PT_MAX_FULL_LEVELS
1102 #undef gpte_to_gfn
1103 #undef gpte_to_gfn_lvl
1104 #undef CMPXCHG
1105 #undef PT_GUEST_ACCESSED_MASK
1106 #undef PT_GUEST_DIRTY_MASK
1107 #undef PT_GUEST_DIRTY_SHIFT
1108 #undef PT_GUEST_ACCESSED_SHIFT
1109 #undef PT_HAVE_ACCESSED_DIRTY
1110
