1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/kernel.h>
7 #include <linux/moduleparam.h>
8 #include <linux/init.h>
9 #include <linux/types.h>
10 #include <linux/device.h>
11 #include <linux/io.h>
12 #include <linux/err.h>
13 #include <linux/fs.h>
14 #include <linux/slab.h>
15 #include <linux/delay.h>
16 #include <linux/smp.h>
17 #include <linux/sysfs.h>
18 #include <linux/stat.h>
19 #include <linux/clk.h>
20 #include <linux/cpu.h>
21 #include <linux/coresight.h>
22 #include <linux/coresight-pmu.h>
23 #include <linux/pm_wakeup.h>
24 #include <linux/amba/bus.h>
25 #include <linux/seq_file.h>
26 #include <linux/uaccess.h>
27 #include <linux/perf_event.h>
28 #include <linux/pm_runtime.h>
29 #include <asm/sections.h>
30 #include <asm/local.h>
31
32 #include "coresight-etm4x.h"
33 #include "coresight-etm-perf.h"
34
35 static int boot_enable;
36 module_param_named(boot_enable, boot_enable, int, S_IRUGO);
37
38 /* The number of ETMv4 currently registered */
39 static int etm4_count;
40 static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
41 static void etm4_set_default_config(struct etmv4_config *config);
42 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
43 struct perf_event *event);
44
45 static enum cpuhp_state hp_online;
46
etm4_os_unlock(struct etmv4_drvdata * drvdata)47 static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
48 {
49 /* Writing any value to ETMOSLAR unlocks the trace registers */
50 writel_relaxed(0x0, drvdata->base + TRCOSLAR);
51 drvdata->os_unlock = true;
52 isb();
53 }
54
etm4_arch_supported(u8 arch)55 static bool etm4_arch_supported(u8 arch)
56 {
57 switch (arch) {
58 case ETM_ARCH_V4:
59 break;
60 default:
61 return false;
62 }
63 return true;
64 }
65
etm4_cpu_id(struct coresight_device * csdev)66 static int etm4_cpu_id(struct coresight_device *csdev)
67 {
68 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
69
70 return drvdata->cpu;
71 }
72
etm4_trace_id(struct coresight_device * csdev)73 static int etm4_trace_id(struct coresight_device *csdev)
74 {
75 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
76
77 return drvdata->trcid;
78 }
79
etm4_enable_hw(void * info)80 static void etm4_enable_hw(void *info)
81 {
82 int i;
83 struct etmv4_drvdata *drvdata = info;
84 struct etmv4_config *config = &drvdata->config;
85
86 CS_UNLOCK(drvdata->base);
87
88 etm4_os_unlock(drvdata);
89
90 /* Disable the trace unit before programming trace registers */
91 writel_relaxed(0, drvdata->base + TRCPRGCTLR);
92
93 /* wait for TRCSTATR.IDLE to go up */
94 if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
95 dev_err(drvdata->dev,
96 "timeout while waiting for Idle Trace Status\n");
97
98 writel_relaxed(config->pe_sel, drvdata->base + TRCPROCSELR);
99 writel_relaxed(config->cfg, drvdata->base + TRCCONFIGR);
100 /* nothing specific implemented */
101 writel_relaxed(0x0, drvdata->base + TRCAUXCTLR);
102 writel_relaxed(config->eventctrl0, drvdata->base + TRCEVENTCTL0R);
103 writel_relaxed(config->eventctrl1, drvdata->base + TRCEVENTCTL1R);
104 writel_relaxed(config->stall_ctrl, drvdata->base + TRCSTALLCTLR);
105 writel_relaxed(config->ts_ctrl, drvdata->base + TRCTSCTLR);
106 writel_relaxed(config->syncfreq, drvdata->base + TRCSYNCPR);
107 writel_relaxed(config->ccctlr, drvdata->base + TRCCCCTLR);
108 writel_relaxed(config->bb_ctrl, drvdata->base + TRCBBCTLR);
109 writel_relaxed(drvdata->trcid, drvdata->base + TRCTRACEIDR);
110 writel_relaxed(config->vinst_ctrl, drvdata->base + TRCVICTLR);
111 writel_relaxed(config->viiectlr, drvdata->base + TRCVIIECTLR);
112 writel_relaxed(config->vissctlr,
113 drvdata->base + TRCVISSCTLR);
114 writel_relaxed(config->vipcssctlr,
115 drvdata->base + TRCVIPCSSCTLR);
116 for (i = 0; i < drvdata->nrseqstate - 1; i++)
117 writel_relaxed(config->seq_ctrl[i],
118 drvdata->base + TRCSEQEVRn(i));
119 writel_relaxed(config->seq_rst, drvdata->base + TRCSEQRSTEVR);
120 writel_relaxed(config->seq_state, drvdata->base + TRCSEQSTR);
121 writel_relaxed(config->ext_inp, drvdata->base + TRCEXTINSELR);
122 for (i = 0; i < drvdata->nr_cntr; i++) {
123 writel_relaxed(config->cntrldvr[i],
124 drvdata->base + TRCCNTRLDVRn(i));
125 writel_relaxed(config->cntr_ctrl[i],
126 drvdata->base + TRCCNTCTLRn(i));
127 writel_relaxed(config->cntr_val[i],
128 drvdata->base + TRCCNTVRn(i));
129 }
130
131 /* Resource selector pair 0 is always implemented and reserved */
132 for (i = 0; i < drvdata->nr_resource * 2; i++)
133 writel_relaxed(config->res_ctrl[i],
134 drvdata->base + TRCRSCTLRn(i));
135
136 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
137 writel_relaxed(config->ss_ctrl[i],
138 drvdata->base + TRCSSCCRn(i));
139 writel_relaxed(config->ss_status[i],
140 drvdata->base + TRCSSCSRn(i));
141 writel_relaxed(config->ss_pe_cmp[i],
142 drvdata->base + TRCSSPCICRn(i));
143 }
144 for (i = 0; i < drvdata->nr_addr_cmp; i++) {
145 writeq_relaxed(config->addr_val[i],
146 drvdata->base + TRCACVRn(i));
147 writeq_relaxed(config->addr_acc[i],
148 drvdata->base + TRCACATRn(i));
149 }
150 for (i = 0; i < drvdata->numcidc; i++)
151 writeq_relaxed(config->ctxid_pid[i],
152 drvdata->base + TRCCIDCVRn(i));
153 writel_relaxed(config->ctxid_mask0, drvdata->base + TRCCIDCCTLR0);
154 writel_relaxed(config->ctxid_mask1, drvdata->base + TRCCIDCCTLR1);
155
156 for (i = 0; i < drvdata->numvmidc; i++)
157 writeq_relaxed(config->vmid_val[i],
158 drvdata->base + TRCVMIDCVRn(i));
159 writel_relaxed(config->vmid_mask0, drvdata->base + TRCVMIDCCTLR0);
160 writel_relaxed(config->vmid_mask1, drvdata->base + TRCVMIDCCTLR1);
161
162 /*
163 * Request to keep the trace unit powered and also
164 * emulation of powerdown
165 */
166 writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR) | TRCPDCR_PU,
167 drvdata->base + TRCPDCR);
168
169 /* Enable the trace unit */
170 writel_relaxed(1, drvdata->base + TRCPRGCTLR);
171
172 /* wait for TRCSTATR.IDLE to go back down to '0' */
173 if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
174 dev_err(drvdata->dev,
175 "timeout while waiting for Idle Trace Status\n");
176
177 CS_LOCK(drvdata->base);
178
179 dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
180 }
181
etm4_parse_event_config(struct etmv4_drvdata * drvdata,struct perf_event * event)182 static int etm4_parse_event_config(struct etmv4_drvdata *drvdata,
183 struct perf_event *event)
184 {
185 int ret = 0;
186 struct etmv4_config *config = &drvdata->config;
187 struct perf_event_attr *attr = &event->attr;
188
189 if (!attr) {
190 ret = -EINVAL;
191 goto out;
192 }
193
194 /* Clear configuration from previous run */
195 memset(config, 0, sizeof(struct etmv4_config));
196
197 if (attr->exclude_kernel)
198 config->mode = ETM_MODE_EXCL_KERN;
199
200 if (attr->exclude_user)
201 config->mode = ETM_MODE_EXCL_USER;
202
203 /* Always start from the default config */
204 etm4_set_default_config(config);
205
206 /* Configure filters specified on the perf cmd line, if any. */
207 ret = etm4_set_event_filters(drvdata, event);
208 if (ret)
209 goto out;
210
211 /* Go from generic option to ETMv4 specifics */
212 if (attr->config & BIT(ETM_OPT_CYCACC)) {
213 config->cfg |= BIT(4);
214 /* TRM: Must program this for cycacc to work */
215 config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;
216 }
217 if (attr->config & BIT(ETM_OPT_TS))
218 /* bit[11], Global timestamp tracing bit */
219 config->cfg |= BIT(11);
220 /* return stack - enable if selected and supported */
221 if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack)
222 /* bit[12], Return stack enable bit */
223 config->cfg |= BIT(12);
224
225 out:
226 return ret;
227 }
228
etm4_enable_perf(struct coresight_device * csdev,struct perf_event * event)229 static int etm4_enable_perf(struct coresight_device *csdev,
230 struct perf_event *event)
231 {
232 int ret = 0;
233 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
234
235 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
236 ret = -EINVAL;
237 goto out;
238 }
239
240 /* Configure the tracer based on the session's specifics */
241 ret = etm4_parse_event_config(drvdata, event);
242 if (ret)
243 goto out;
244 /* And enable it */
245 etm4_enable_hw(drvdata);
246
247 out:
248 return ret;
249 }
250
etm4_enable_sysfs(struct coresight_device * csdev)251 static int etm4_enable_sysfs(struct coresight_device *csdev)
252 {
253 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
254 int ret;
255
256 spin_lock(&drvdata->spinlock);
257
258 /*
259 * Executing etm4_enable_hw on the cpu whose ETM is being enabled
260 * ensures that register writes occur when cpu is powered.
261 */
262 ret = smp_call_function_single(drvdata->cpu,
263 etm4_enable_hw, drvdata, 1);
264 if (ret)
265 goto err;
266
267 drvdata->sticky_enable = true;
268 spin_unlock(&drvdata->spinlock);
269
270 dev_info(drvdata->dev, "ETM tracing enabled\n");
271 return 0;
272
273 err:
274 spin_unlock(&drvdata->spinlock);
275 return ret;
276 }
277
etm4_enable(struct coresight_device * csdev,struct perf_event * event,u32 mode)278 static int etm4_enable(struct coresight_device *csdev,
279 struct perf_event *event, u32 mode)
280 {
281 int ret;
282 u32 val;
283 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
284
285 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
286
287 /* Someone is already using the tracer */
288 if (val)
289 return -EBUSY;
290
291 switch (mode) {
292 case CS_MODE_SYSFS:
293 ret = etm4_enable_sysfs(csdev);
294 break;
295 case CS_MODE_PERF:
296 ret = etm4_enable_perf(csdev, event);
297 break;
298 default:
299 ret = -EINVAL;
300 }
301
302 /* The tracer didn't start */
303 if (ret)
304 local_set(&drvdata->mode, CS_MODE_DISABLED);
305
306 return ret;
307 }
308
etm4_disable_hw(void * info)309 static void etm4_disable_hw(void *info)
310 {
311 u32 control;
312 struct etmv4_drvdata *drvdata = info;
313
314 CS_UNLOCK(drvdata->base);
315
316 /* power can be removed from the trace unit now */
317 control = readl_relaxed(drvdata->base + TRCPDCR);
318 control &= ~TRCPDCR_PU;
319 writel_relaxed(control, drvdata->base + TRCPDCR);
320
321 control = readl_relaxed(drvdata->base + TRCPRGCTLR);
322
323 /* EN, bit[0] Trace unit enable bit */
324 control &= ~0x1;
325
326 /* make sure everything completes before disabling */
327 mb();
328 isb();
329 writel_relaxed(control, drvdata->base + TRCPRGCTLR);
330
331 CS_LOCK(drvdata->base);
332
333 dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
334 }
335
etm4_disable_perf(struct coresight_device * csdev,struct perf_event * event)336 static int etm4_disable_perf(struct coresight_device *csdev,
337 struct perf_event *event)
338 {
339 u32 control;
340 struct etm_filters *filters = event->hw.addr_filters;
341 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
342
343 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
344 return -EINVAL;
345
346 etm4_disable_hw(drvdata);
347
348 /*
349 * Check if the start/stop logic was active when the unit was stopped.
350 * That way we can re-enable the start/stop logic when the process is
351 * scheduled again. Configuration of the start/stop logic happens in
352 * function etm4_set_event_filters().
353 */
354 control = readl_relaxed(drvdata->base + TRCVICTLR);
355 /* TRCVICTLR::SSSTATUS, bit[9] */
356 filters->ssstatus = (control & BIT(9));
357
358 return 0;
359 }
360
etm4_disable_sysfs(struct coresight_device * csdev)361 static void etm4_disable_sysfs(struct coresight_device *csdev)
362 {
363 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
364
365 /*
366 * Taking hotplug lock here protects from clocks getting disabled
367 * with tracing being left on (crash scenario) if user disable occurs
368 * after cpu online mask indicates the cpu is offline but before the
369 * DYING hotplug callback is serviced by the ETM driver.
370 */
371 cpus_read_lock();
372 spin_lock(&drvdata->spinlock);
373
374 /*
375 * Executing etm4_disable_hw on the cpu whose ETM is being disabled
376 * ensures that register writes occur when cpu is powered.
377 */
378 smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
379
380 spin_unlock(&drvdata->spinlock);
381 cpus_read_unlock();
382
383 dev_info(drvdata->dev, "ETM tracing disabled\n");
384 }
385
etm4_disable(struct coresight_device * csdev,struct perf_event * event)386 static void etm4_disable(struct coresight_device *csdev,
387 struct perf_event *event)
388 {
389 u32 mode;
390 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
391
392 /*
393 * For as long as the tracer isn't disabled another entity can't
394 * change its status. As such we can read the status here without
395 * fearing it will change under us.
396 */
397 mode = local_read(&drvdata->mode);
398
399 switch (mode) {
400 case CS_MODE_DISABLED:
401 break;
402 case CS_MODE_SYSFS:
403 etm4_disable_sysfs(csdev);
404 break;
405 case CS_MODE_PERF:
406 etm4_disable_perf(csdev, event);
407 break;
408 }
409
410 if (mode)
411 local_set(&drvdata->mode, CS_MODE_DISABLED);
412 }
413
414 static const struct coresight_ops_source etm4_source_ops = {
415 .cpu_id = etm4_cpu_id,
416 .trace_id = etm4_trace_id,
417 .enable = etm4_enable,
418 .disable = etm4_disable,
419 };
420
421 static const struct coresight_ops etm4_cs_ops = {
422 .source_ops = &etm4_source_ops,
423 };
424
etm4_init_arch_data(void * info)425 static void etm4_init_arch_data(void *info)
426 {
427 u32 etmidr0;
428 u32 etmidr1;
429 u32 etmidr2;
430 u32 etmidr3;
431 u32 etmidr4;
432 u32 etmidr5;
433 struct etmv4_drvdata *drvdata = info;
434
435 /* Make sure all registers are accessible */
436 etm4_os_unlock(drvdata);
437
438 CS_UNLOCK(drvdata->base);
439
440 /* find all capabilities of the tracing unit */
441 etmidr0 = readl_relaxed(drvdata->base + TRCIDR0);
442
443 /* INSTP0, bits[2:1] P0 tracing support field */
444 if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2))
445 drvdata->instrp0 = true;
446 else
447 drvdata->instrp0 = false;
448
449 /* TRCBB, bit[5] Branch broadcast tracing support bit */
450 if (BMVAL(etmidr0, 5, 5))
451 drvdata->trcbb = true;
452 else
453 drvdata->trcbb = false;
454
455 /* TRCCOND, bit[6] Conditional instruction tracing support bit */
456 if (BMVAL(etmidr0, 6, 6))
457 drvdata->trccond = true;
458 else
459 drvdata->trccond = false;
460
461 /* TRCCCI, bit[7] Cycle counting instruction bit */
462 if (BMVAL(etmidr0, 7, 7))
463 drvdata->trccci = true;
464 else
465 drvdata->trccci = false;
466
467 /* RETSTACK, bit[9] Return stack bit */
468 if (BMVAL(etmidr0, 9, 9))
469 drvdata->retstack = true;
470 else
471 drvdata->retstack = false;
472
473 /* NUMEVENT, bits[11:10] Number of events field */
474 drvdata->nr_event = BMVAL(etmidr0, 10, 11);
475 /* QSUPP, bits[16:15] Q element support field */
476 drvdata->q_support = BMVAL(etmidr0, 15, 16);
477 /* TSSIZE, bits[28:24] Global timestamp size field */
478 drvdata->ts_size = BMVAL(etmidr0, 24, 28);
479
480 /* base architecture of trace unit */
481 etmidr1 = readl_relaxed(drvdata->base + TRCIDR1);
482 /*
483 * TRCARCHMIN, bits[7:4] architecture the minor version number
484 * TRCARCHMAJ, bits[11:8] architecture major versin number
485 */
486 drvdata->arch = BMVAL(etmidr1, 4, 11);
487
488 /* maximum size of resources */
489 etmidr2 = readl_relaxed(drvdata->base + TRCIDR2);
490 /* CIDSIZE, bits[9:5] Indicates the Context ID size */
491 drvdata->ctxid_size = BMVAL(etmidr2, 5, 9);
492 /* VMIDSIZE, bits[14:10] Indicates the VMID size */
493 drvdata->vmid_size = BMVAL(etmidr2, 10, 14);
494 /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
495 drvdata->ccsize = BMVAL(etmidr2, 25, 28);
496
497 etmidr3 = readl_relaxed(drvdata->base + TRCIDR3);
498 /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
499 drvdata->ccitmin = BMVAL(etmidr3, 0, 11);
500 /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
501 drvdata->s_ex_level = BMVAL(etmidr3, 16, 19);
502 /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
503 drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23);
504
505 /*
506 * TRCERR, bit[24] whether a trace unit can trace a
507 * system error exception.
508 */
509 if (BMVAL(etmidr3, 24, 24))
510 drvdata->trc_error = true;
511 else
512 drvdata->trc_error = false;
513
514 /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
515 if (BMVAL(etmidr3, 25, 25))
516 drvdata->syncpr = true;
517 else
518 drvdata->syncpr = false;
519
520 /* STALLCTL, bit[26] is stall control implemented? */
521 if (BMVAL(etmidr3, 26, 26))
522 drvdata->stallctl = true;
523 else
524 drvdata->stallctl = false;
525
526 /* SYSSTALL, bit[27] implementation can support stall control? */
527 if (BMVAL(etmidr3, 27, 27))
528 drvdata->sysstall = true;
529 else
530 drvdata->sysstall = false;
531
532 /* NUMPROC, bits[30:28] the number of PEs available for tracing */
533 drvdata->nr_pe = BMVAL(etmidr3, 28, 30);
534
535 /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
536 if (BMVAL(etmidr3, 31, 31))
537 drvdata->nooverflow = true;
538 else
539 drvdata->nooverflow = false;
540
541 /* number of resources trace unit supports */
542 etmidr4 = readl_relaxed(drvdata->base + TRCIDR4);
543 /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
544 drvdata->nr_addr_cmp = BMVAL(etmidr4, 0, 3);
545 /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
546 drvdata->nr_pe_cmp = BMVAL(etmidr4, 12, 15);
547 /*
548 * NUMRSPAIR, bits[19:16]
549 * The number of resource pairs conveyed by the HW starts at 0, i.e a
550 * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on.
551 * As such add 1 to the value of NUMRSPAIR for a better representation.
552 */
553 drvdata->nr_resource = BMVAL(etmidr4, 16, 19) + 1;
554 /*
555 * NUMSSCC, bits[23:20] the number of single-shot
556 * comparator control for tracing
557 */
558 drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
559 /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
560 drvdata->numcidc = BMVAL(etmidr4, 24, 27);
561 /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
562 drvdata->numvmidc = BMVAL(etmidr4, 28, 31);
563
564 etmidr5 = readl_relaxed(drvdata->base + TRCIDR5);
565 /* NUMEXTIN, bits[8:0] number of external inputs implemented */
566 drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8);
567 /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
568 drvdata->trcid_size = BMVAL(etmidr5, 16, 21);
569 /* ATBTRIG, bit[22] implementation can support ATB triggers? */
570 if (BMVAL(etmidr5, 22, 22))
571 drvdata->atbtrig = true;
572 else
573 drvdata->atbtrig = false;
574 /*
575 * LPOVERRIDE, bit[23] implementation supports
576 * low-power state override
577 */
578 if (BMVAL(etmidr5, 23, 23))
579 drvdata->lpoverride = true;
580 else
581 drvdata->lpoverride = false;
582 /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
583 drvdata->nrseqstate = BMVAL(etmidr5, 25, 27);
584 /* NUMCNTR, bits[30:28] number of counters available for tracing */
585 drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
586 CS_LOCK(drvdata->base);
587 }
588
etm4_set_default_config(struct etmv4_config * config)589 static void etm4_set_default_config(struct etmv4_config *config)
590 {
591 /* disable all events tracing */
592 config->eventctrl0 = 0x0;
593 config->eventctrl1 = 0x0;
594
595 /* disable stalling */
596 config->stall_ctrl = 0x0;
597
598 /* enable trace synchronization every 4096 bytes, if available */
599 config->syncfreq = 0xC;
600
601 /* disable timestamp event */
602 config->ts_ctrl = 0x0;
603
604 /* TRCVICTLR::EVENT = 0x01, select the always on logic */
605 config->vinst_ctrl |= BIT(0);
606 }
607
etm4_get_access_type(struct etmv4_config * config)608 static u64 etm4_get_access_type(struct etmv4_config *config)
609 {
610 u64 access_type = 0;
611
612 /*
613 * EXLEVEL_NS, bits[15:12]
614 * The Exception levels are:
615 * Bit[12] Exception level 0 - Application
616 * Bit[13] Exception level 1 - OS
617 * Bit[14] Exception level 2 - Hypervisor
618 * Bit[15] Never implemented
619 *
620 * Always stay away from hypervisor mode.
621 */
622 access_type = ETM_EXLEVEL_NS_HYP;
623
624 if (config->mode & ETM_MODE_EXCL_KERN)
625 access_type |= ETM_EXLEVEL_NS_OS;
626
627 if (config->mode & ETM_MODE_EXCL_USER)
628 access_type |= ETM_EXLEVEL_NS_APP;
629
630 /*
631 * EXLEVEL_S, bits[11:8], don't trace anything happening
632 * in secure state.
633 */
634 access_type |= (ETM_EXLEVEL_S_APP |
635 ETM_EXLEVEL_S_OS |
636 ETM_EXLEVEL_S_HYP);
637
638 return access_type;
639 }
640
etm4_set_comparator_filter(struct etmv4_config * config,u64 start,u64 stop,int comparator)641 static void etm4_set_comparator_filter(struct etmv4_config *config,
642 u64 start, u64 stop, int comparator)
643 {
644 u64 access_type = etm4_get_access_type(config);
645
646 /* First half of default address comparator */
647 config->addr_val[comparator] = start;
648 config->addr_acc[comparator] = access_type;
649 config->addr_type[comparator] = ETM_ADDR_TYPE_RANGE;
650
651 /* Second half of default address comparator */
652 config->addr_val[comparator + 1] = stop;
653 config->addr_acc[comparator + 1] = access_type;
654 config->addr_type[comparator + 1] = ETM_ADDR_TYPE_RANGE;
655
656 /*
657 * Configure the ViewInst function to include this address range
658 * comparator.
659 *
660 * @comparator is divided by two since it is the index in the
661 * etmv4_config::addr_val array but register TRCVIIECTLR deals with
662 * address range comparator _pairs_.
663 *
664 * Therefore:
665 * index 0 -> compatator pair 0
666 * index 2 -> comparator pair 1
667 * index 4 -> comparator pair 2
668 * ...
669 * index 14 -> comparator pair 7
670 */
671 config->viiectlr |= BIT(comparator / 2);
672 }
673
etm4_set_start_stop_filter(struct etmv4_config * config,u64 address,int comparator,enum etm_addr_type type)674 static void etm4_set_start_stop_filter(struct etmv4_config *config,
675 u64 address, int comparator,
676 enum etm_addr_type type)
677 {
678 int shift;
679 u64 access_type = etm4_get_access_type(config);
680
681 /* Configure the comparator */
682 config->addr_val[comparator] = address;
683 config->addr_acc[comparator] = access_type;
684 config->addr_type[comparator] = type;
685
686 /*
687 * Configure ViewInst Start-Stop control register.
688 * Addresses configured to start tracing go from bit 0 to n-1,
689 * while those configured to stop tracing from 16 to 16 + n-1.
690 */
691 shift = (type == ETM_ADDR_TYPE_START ? 0 : 16);
692 config->vissctlr |= BIT(shift + comparator);
693 }
694
etm4_set_default_filter(struct etmv4_config * config)695 static void etm4_set_default_filter(struct etmv4_config *config)
696 {
697 u64 start, stop;
698
699 /*
700 * Configure address range comparator '0' to encompass all
701 * possible addresses.
702 */
703 start = 0x0;
704 stop = ~0x0;
705
706 etm4_set_comparator_filter(config, start, stop,
707 ETM_DEFAULT_ADDR_COMP);
708
709 /*
710 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
711 * in the started state
712 */
713 config->vinst_ctrl |= BIT(9);
714
715 /* No start-stop filtering for ViewInst */
716 config->vissctlr = 0x0;
717 }
718
etm4_set_default(struct etmv4_config * config)719 static void etm4_set_default(struct etmv4_config *config)
720 {
721 if (WARN_ON_ONCE(!config))
722 return;
723
724 /*
725 * Make default initialisation trace everything
726 *
727 * Select the "always true" resource selector on the
728 * "Enablign Event" line and configure address range comparator
729 * '0' to trace all the possible address range. From there
730 * configure the "include/exclude" engine to include address
731 * range comparator '0'.
732 */
733 etm4_set_default_config(config);
734 etm4_set_default_filter(config);
735 }
736
etm4_get_next_comparator(struct etmv4_drvdata * drvdata,u32 type)737 static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type)
738 {
739 int nr_comparator, index = 0;
740 struct etmv4_config *config = &drvdata->config;
741
742 /*
743 * nr_addr_cmp holds the number of comparator _pair_, so time 2
744 * for the total number of comparators.
745 */
746 nr_comparator = drvdata->nr_addr_cmp * 2;
747
748 /* Go through the tally of comparators looking for a free one. */
749 while (index < nr_comparator) {
750 switch (type) {
751 case ETM_ADDR_TYPE_RANGE:
752 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE &&
753 config->addr_type[index + 1] == ETM_ADDR_TYPE_NONE)
754 return index;
755
756 /* Address range comparators go in pairs */
757 index += 2;
758 break;
759 case ETM_ADDR_TYPE_START:
760 case ETM_ADDR_TYPE_STOP:
761 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE)
762 return index;
763
764 /* Start/stop address can have odd indexes */
765 index += 1;
766 break;
767 default:
768 return -EINVAL;
769 }
770 }
771
772 /* If we are here all the comparators have been used. */
773 return -ENOSPC;
774 }
775
etm4_set_event_filters(struct etmv4_drvdata * drvdata,struct perf_event * event)776 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
777 struct perf_event *event)
778 {
779 int i, comparator, ret = 0;
780 u64 address;
781 struct etmv4_config *config = &drvdata->config;
782 struct etm_filters *filters = event->hw.addr_filters;
783
784 if (!filters)
785 goto default_filter;
786
787 /* Sync events with what Perf got */
788 perf_event_addr_filters_sync(event);
789
790 /*
791 * If there are no filters to deal with simply go ahead with
792 * the default filter, i.e the entire address range.
793 */
794 if (!filters->nr_filters)
795 goto default_filter;
796
797 for (i = 0; i < filters->nr_filters; i++) {
798 struct etm_filter *filter = &filters->etm_filter[i];
799 enum etm_addr_type type = filter->type;
800
801 /* See if a comparator is free. */
802 comparator = etm4_get_next_comparator(drvdata, type);
803 if (comparator < 0) {
804 ret = comparator;
805 goto out;
806 }
807
808 switch (type) {
809 case ETM_ADDR_TYPE_RANGE:
810 etm4_set_comparator_filter(config,
811 filter->start_addr,
812 filter->stop_addr,
813 comparator);
814 /*
815 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
816 * in the started state
817 */
818 config->vinst_ctrl |= BIT(9);
819
820 /* No start-stop filtering for ViewInst */
821 config->vissctlr = 0x0;
822 break;
823 case ETM_ADDR_TYPE_START:
824 case ETM_ADDR_TYPE_STOP:
825 /* Get the right start or stop address */
826 address = (type == ETM_ADDR_TYPE_START ?
827 filter->start_addr :
828 filter->stop_addr);
829
830 /* Configure comparator */
831 etm4_set_start_stop_filter(config, address,
832 comparator, type);
833
834 /*
835 * If filters::ssstatus == 1, trace acquisition was
836 * started but the process was yanked away before the
837 * the stop address was hit. As such the start/stop
838 * logic needs to be re-started so that tracing can
839 * resume where it left.
840 *
841 * The start/stop logic status when a process is
842 * scheduled out is checked in function
843 * etm4_disable_perf().
844 */
845 if (filters->ssstatus)
846 config->vinst_ctrl |= BIT(9);
847
848 /* No include/exclude filtering for ViewInst */
849 config->viiectlr = 0x0;
850 break;
851 default:
852 ret = -EINVAL;
853 goto out;
854 }
855 }
856
857 goto out;
858
859
860 default_filter:
861 etm4_set_default_filter(config);
862
863 out:
864 return ret;
865 }
866
etm4_config_trace_mode(struct etmv4_config * config)867 void etm4_config_trace_mode(struct etmv4_config *config)
868 {
869 u32 addr_acc, mode;
870
871 mode = config->mode;
872 mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
873
874 /* excluding kernel AND user space doesn't make sense */
875 WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER));
876
877 /* nothing to do if neither flags are set */
878 if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
879 return;
880
881 addr_acc = config->addr_acc[ETM_DEFAULT_ADDR_COMP];
882 /* clear default config */
883 addr_acc &= ~(ETM_EXLEVEL_NS_APP | ETM_EXLEVEL_NS_OS);
884
885 /*
886 * EXLEVEL_NS, bits[15:12]
887 * The Exception levels are:
888 * Bit[12] Exception level 0 - Application
889 * Bit[13] Exception level 1 - OS
890 * Bit[14] Exception level 2 - Hypervisor
891 * Bit[15] Never implemented
892 */
893 if (mode & ETM_MODE_EXCL_KERN)
894 addr_acc |= ETM_EXLEVEL_NS_OS;
895 else
896 addr_acc |= ETM_EXLEVEL_NS_APP;
897
898 config->addr_acc[ETM_DEFAULT_ADDR_COMP] = addr_acc;
899 config->addr_acc[ETM_DEFAULT_ADDR_COMP + 1] = addr_acc;
900 }
901
etm4_online_cpu(unsigned int cpu)902 static int etm4_online_cpu(unsigned int cpu)
903 {
904 if (!etmdrvdata[cpu])
905 return 0;
906
907 if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
908 coresight_enable(etmdrvdata[cpu]->csdev);
909 return 0;
910 }
911
etm4_starting_cpu(unsigned int cpu)912 static int etm4_starting_cpu(unsigned int cpu)
913 {
914 if (!etmdrvdata[cpu])
915 return 0;
916
917 spin_lock(&etmdrvdata[cpu]->spinlock);
918 if (!etmdrvdata[cpu]->os_unlock) {
919 etm4_os_unlock(etmdrvdata[cpu]);
920 etmdrvdata[cpu]->os_unlock = true;
921 }
922
923 if (local_read(&etmdrvdata[cpu]->mode))
924 etm4_enable_hw(etmdrvdata[cpu]);
925 spin_unlock(&etmdrvdata[cpu]->spinlock);
926 return 0;
927 }
928
etm4_dying_cpu(unsigned int cpu)929 static int etm4_dying_cpu(unsigned int cpu)
930 {
931 if (!etmdrvdata[cpu])
932 return 0;
933
934 spin_lock(&etmdrvdata[cpu]->spinlock);
935 if (local_read(&etmdrvdata[cpu]->mode))
936 etm4_disable_hw(etmdrvdata[cpu]);
937 spin_unlock(&etmdrvdata[cpu]->spinlock);
938 return 0;
939 }
940
etm4_init_trace_id(struct etmv4_drvdata * drvdata)941 static void etm4_init_trace_id(struct etmv4_drvdata *drvdata)
942 {
943 drvdata->trcid = coresight_get_trace_id(drvdata->cpu);
944 }
945
etm4_probe(struct amba_device * adev,const struct amba_id * id)946 static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
947 {
948 int ret;
949 void __iomem *base;
950 struct device *dev = &adev->dev;
951 struct coresight_platform_data *pdata = NULL;
952 struct etmv4_drvdata *drvdata;
953 struct resource *res = &adev->res;
954 struct coresight_desc desc = { 0 };
955 struct device_node *np = adev->dev.of_node;
956
957 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
958 if (!drvdata)
959 return -ENOMEM;
960
961 if (np) {
962 pdata = of_get_coresight_platform_data(dev, np);
963 if (IS_ERR(pdata))
964 return PTR_ERR(pdata);
965 adev->dev.platform_data = pdata;
966 }
967
968 drvdata->dev = &adev->dev;
969 dev_set_drvdata(dev, drvdata);
970
971 /* Validity for the resource is already checked by the AMBA core */
972 base = devm_ioremap_resource(dev, res);
973 if (IS_ERR(base))
974 return PTR_ERR(base);
975
976 drvdata->base = base;
977
978 spin_lock_init(&drvdata->spinlock);
979
980 drvdata->cpu = pdata ? pdata->cpu : 0;
981
982 cpus_read_lock();
983 etmdrvdata[drvdata->cpu] = drvdata;
984
985 if (smp_call_function_single(drvdata->cpu,
986 etm4_init_arch_data, drvdata, 1))
987 dev_err(dev, "ETM arch init failed\n");
988
989 if (!etm4_count++) {
990 cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ARM_CORESIGHT_STARTING,
991 "arm/coresight4:starting",
992 etm4_starting_cpu, etm4_dying_cpu);
993 ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ONLINE_DYN,
994 "arm/coresight4:online",
995 etm4_online_cpu, NULL);
996 if (ret < 0)
997 goto err_arch_supported;
998 hp_online = ret;
999 }
1000
1001 cpus_read_unlock();
1002
1003 if (etm4_arch_supported(drvdata->arch) == false) {
1004 ret = -EINVAL;
1005 goto err_arch_supported;
1006 }
1007
1008 etm4_init_trace_id(drvdata);
1009 etm4_set_default(&drvdata->config);
1010
1011 desc.type = CORESIGHT_DEV_TYPE_SOURCE;
1012 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
1013 desc.ops = &etm4_cs_ops;
1014 desc.pdata = pdata;
1015 desc.dev = dev;
1016 desc.groups = coresight_etmv4_groups;
1017 drvdata->csdev = coresight_register(&desc);
1018 if (IS_ERR(drvdata->csdev)) {
1019 ret = PTR_ERR(drvdata->csdev);
1020 goto err_arch_supported;
1021 }
1022
1023 ret = etm_perf_symlink(drvdata->csdev, true);
1024 if (ret) {
1025 coresight_unregister(drvdata->csdev);
1026 goto err_arch_supported;
1027 }
1028
1029 pm_runtime_put(&adev->dev);
1030 dev_info(dev, "CPU%d: ETM v%d.%d initialized\n",
1031 drvdata->cpu, drvdata->arch >> 4, drvdata->arch & 0xf);
1032
1033 if (boot_enable) {
1034 coresight_enable(drvdata->csdev);
1035 drvdata->boot_enable = true;
1036 }
1037
1038 return 0;
1039
1040 err_arch_supported:
1041 if (--etm4_count == 0) {
1042 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1043 if (hp_online)
1044 cpuhp_remove_state_nocalls(hp_online);
1045 }
1046 return ret;
1047 }
1048
1049 #define ETM4x_AMBA_ID(pid) \
1050 { \
1051 .id = pid, \
1052 .mask = 0x000fffff, \
1053 }
1054
1055 static const struct amba_id etm4_ids[] = {
1056 ETM4x_AMBA_ID(0x000bb95d), /* Cortex-A53 */
1057 ETM4x_AMBA_ID(0x000bb95e), /* Cortex-A57 */
1058 ETM4x_AMBA_ID(0x000bb95a), /* Cortex-A72 */
1059 ETM4x_AMBA_ID(0x000bb959), /* Cortex-A73 */
1060 ETM4x_AMBA_ID(0x000bb9da), /* Cortex-A35 */
1061 {},
1062 };
1063
1064 static struct amba_driver etm4x_driver = {
1065 .drv = {
1066 .name = "coresight-etm4x",
1067 .suppress_bind_attrs = true,
1068 },
1069 .probe = etm4_probe,
1070 .id_table = etm4_ids,
1071 };
1072 builtin_amba_driver(etm4x_driver);
1073
