1 /*
2 * Copyright (C) 2012,2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * Derived from arch/arm/include/asm/kvm_host.h:
6 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
7 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #ifndef __ARM64_KVM_HOST_H__
23 #define __ARM64_KVM_HOST_H__
24
25 #include <linux/types.h>
26 #include <linux/kvm_types.h>
27 #include <asm/cpufeature.h>
28 #include <asm/daifflags.h>
29 #include <asm/fpsimd.h>
30 #include <asm/kvm.h>
31 #include <asm/kvm_asm.h>
32 #include <asm/kvm_mmio.h>
33 #include <asm/thread_info.h>
34
35 #define __KVM_HAVE_ARCH_INTC_INITIALIZED
36
37 #define KVM_USER_MEM_SLOTS 512
38 #define KVM_HALT_POLL_NS_DEFAULT 500000
39
40 #include <kvm/arm_vgic.h>
41 #include <kvm/arm_arch_timer.h>
42 #include <kvm/arm_pmu.h>
43
44 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
45
46 #define KVM_VCPU_MAX_FEATURES 4
47
48 #define KVM_REQ_SLEEP \
49 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
50 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1)
51
52 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use);
53
54 int __attribute_const__ kvm_target_cpu(void);
55 int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
56 int kvm_arch_dev_ioctl_check_extension(struct kvm *kvm, long ext);
57 void __extended_idmap_trampoline(phys_addr_t boot_pgd, phys_addr_t idmap_start);
58
59 struct kvm_arch {
60 /* The VMID generation used for the virt. memory system */
61 u64 vmid_gen;
62 u32 vmid;
63
64 /* 1-level 2nd stage table, protected by kvm->mmu_lock */
65 pgd_t *pgd;
66
67 /* VTTBR value associated with above pgd and vmid */
68 u64 vttbr;
69
70 /* The last vcpu id that ran on each physical CPU */
71 int __percpu *last_vcpu_ran;
72
73 /* The maximum number of vCPUs depends on the used GIC model */
74 int max_vcpus;
75
76 /* Interrupt controller */
77 struct vgic_dist vgic;
78
79 /* Mandated version of PSCI */
80 u32 psci_version;
81 };
82
83 #define KVM_NR_MEM_OBJS 40
84
85 /*
86 * We don't want allocation failures within the mmu code, so we preallocate
87 * enough memory for a single page fault in a cache.
88 */
89 struct kvm_mmu_memory_cache {
90 int nobjs;
91 void *objects[KVM_NR_MEM_OBJS];
92 };
93
94 struct kvm_vcpu_fault_info {
95 u32 esr_el2; /* Hyp Syndrom Register */
96 u64 far_el2; /* Hyp Fault Address Register */
97 u64 hpfar_el2; /* Hyp IPA Fault Address Register */
98 u64 disr_el1; /* Deferred [SError] Status Register */
99 };
100
101 /*
102 * 0 is reserved as an invalid value.
103 * Order should be kept in sync with the save/restore code.
104 */
105 enum vcpu_sysreg {
106 __INVALID_SYSREG__,
107 MPIDR_EL1, /* MultiProcessor Affinity Register */
108 CSSELR_EL1, /* Cache Size Selection Register */
109 SCTLR_EL1, /* System Control Register */
110 ACTLR_EL1, /* Auxiliary Control Register */
111 CPACR_EL1, /* Coprocessor Access Control */
112 TTBR0_EL1, /* Translation Table Base Register 0 */
113 TTBR1_EL1, /* Translation Table Base Register 1 */
114 TCR_EL1, /* Translation Control Register */
115 ESR_EL1, /* Exception Syndrome Register */
116 AFSR0_EL1, /* Auxiliary Fault Status Register 0 */
117 AFSR1_EL1, /* Auxiliary Fault Status Register 1 */
118 FAR_EL1, /* Fault Address Register */
119 MAIR_EL1, /* Memory Attribute Indirection Register */
120 VBAR_EL1, /* Vector Base Address Register */
121 CONTEXTIDR_EL1, /* Context ID Register */
122 TPIDR_EL0, /* Thread ID, User R/W */
123 TPIDRRO_EL0, /* Thread ID, User R/O */
124 TPIDR_EL1, /* Thread ID, Privileged */
125 AMAIR_EL1, /* Aux Memory Attribute Indirection Register */
126 CNTKCTL_EL1, /* Timer Control Register (EL1) */
127 PAR_EL1, /* Physical Address Register */
128 MDSCR_EL1, /* Monitor Debug System Control Register */
129 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */
130 DISR_EL1, /* Deferred Interrupt Status Register */
131
132 /* Performance Monitors Registers */
133 PMCR_EL0, /* Control Register */
134 PMSELR_EL0, /* Event Counter Selection Register */
135 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */
136 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
137 PMCCNTR_EL0, /* Cycle Counter Register */
138 PMEVTYPER0_EL0, /* Event Type Register (0-30) */
139 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
140 PMCCFILTR_EL0, /* Cycle Count Filter Register */
141 PMCNTENSET_EL0, /* Count Enable Set Register */
142 PMINTENSET_EL1, /* Interrupt Enable Set Register */
143 PMOVSSET_EL0, /* Overflow Flag Status Set Register */
144 PMSWINC_EL0, /* Software Increment Register */
145 PMUSERENR_EL0, /* User Enable Register */
146
147 /* 32bit specific registers. Keep them at the end of the range */
148 DACR32_EL2, /* Domain Access Control Register */
149 IFSR32_EL2, /* Instruction Fault Status Register */
150 FPEXC32_EL2, /* Floating-Point Exception Control Register */
151 DBGVCR32_EL2, /* Debug Vector Catch Register */
152
153 NR_SYS_REGS /* Nothing after this line! */
154 };
155
156 /* 32bit mapping */
157 #define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */
158 #define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */
159 #define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */
160 #define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */
161 #define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */
162 #define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */
163 #define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */
164 #define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */
165 #define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */
166 #define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */
167 #define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */
168 #define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */
169 #define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */
170 #define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */
171 #define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */
172 #define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */
173 #define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */
174 #define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */
175 #define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */
176 #define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */
177 #define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */
178 #define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */
179 #define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */
180 #define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */
181 #define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */
182 #define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */
183 #define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */
184 #define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */
185 #define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */
186
187 #define cp14_DBGDSCRext (MDSCR_EL1 * 2)
188 #define cp14_DBGBCR0 (DBGBCR0_EL1 * 2)
189 #define cp14_DBGBVR0 (DBGBVR0_EL1 * 2)
190 #define cp14_DBGBXVR0 (cp14_DBGBVR0 + 1)
191 #define cp14_DBGWCR0 (DBGWCR0_EL1 * 2)
192 #define cp14_DBGWVR0 (DBGWVR0_EL1 * 2)
193 #define cp14_DBGDCCINT (MDCCINT_EL1 * 2)
194
195 #define NR_COPRO_REGS (NR_SYS_REGS * 2)
196
197 struct kvm_cpu_context {
198 struct kvm_regs gp_regs;
199 union {
200 u64 sys_regs[NR_SYS_REGS];
201 u32 copro[NR_COPRO_REGS];
202 };
203
204 struct kvm_vcpu *__hyp_running_vcpu;
205 };
206
207 typedef struct kvm_cpu_context kvm_cpu_context_t;
208
209 struct kvm_vcpu_arch {
210 struct kvm_cpu_context ctxt;
211
212 /* HYP configuration */
213 u64 hcr_el2;
214 u32 mdcr_el2;
215
216 /* Exception Information */
217 struct kvm_vcpu_fault_info fault;
218
219 /* State of various workarounds, see kvm_asm.h for bit assignment */
220 u64 workaround_flags;
221
222 /* Miscellaneous vcpu state flags */
223 u64 flags;
224
225 /*
226 * We maintain more than a single set of debug registers to support
227 * debugging the guest from the host and to maintain separate host and
228 * guest state during world switches. vcpu_debug_state are the debug
229 * registers of the vcpu as the guest sees them. host_debug_state are
230 * the host registers which are saved and restored during
231 * world switches. external_debug_state contains the debug
232 * values we want to debug the guest. This is set via the
233 * KVM_SET_GUEST_DEBUG ioctl.
234 *
235 * debug_ptr points to the set of debug registers that should be loaded
236 * onto the hardware when running the guest.
237 */
238 struct kvm_guest_debug_arch *debug_ptr;
239 struct kvm_guest_debug_arch vcpu_debug_state;
240 struct kvm_guest_debug_arch external_debug_state;
241
242 /* Pointer to host CPU context */
243 kvm_cpu_context_t *host_cpu_context;
244
245 struct thread_info *host_thread_info; /* hyp VA */
246 struct user_fpsimd_state *host_fpsimd_state; /* hyp VA */
247
248 struct {
249 /* {Break,watch}point registers */
250 struct kvm_guest_debug_arch regs;
251 /* Statistical profiling extension */
252 u64 pmscr_el1;
253 } host_debug_state;
254
255 /* VGIC state */
256 struct vgic_cpu vgic_cpu;
257 struct arch_timer_cpu timer_cpu;
258 struct kvm_pmu pmu;
259
260 /*
261 * Anything that is not used directly from assembly code goes
262 * here.
263 */
264
265 /*
266 * Guest registers we preserve during guest debugging.
267 *
268 * These shadow registers are updated by the kvm_handle_sys_reg
269 * trap handler if the guest accesses or updates them while we
270 * are using guest debug.
271 */
272 struct {
273 u32 mdscr_el1;
274 } guest_debug_preserved;
275
276 /* vcpu power-off state */
277 bool power_off;
278
279 /* Don't run the guest (internal implementation need) */
280 bool pause;
281
282 /* IO related fields */
283 struct kvm_decode mmio_decode;
284
285 /* Cache some mmu pages needed inside spinlock regions */
286 struct kvm_mmu_memory_cache mmu_page_cache;
287
288 /* Target CPU and feature flags */
289 int target;
290 DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
291
292 /* Detect first run of a vcpu */
293 bool has_run_once;
294
295 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */
296 u64 vsesr_el2;
297
298 /* True when deferrable sysregs are loaded on the physical CPU,
299 * see kvm_vcpu_load_sysregs and kvm_vcpu_put_sysregs. */
300 bool sysregs_loaded_on_cpu;
301 };
302
303 /* vcpu_arch flags field values: */
304 #define KVM_ARM64_DEBUG_DIRTY (1 << 0)
305 #define KVM_ARM64_FP_ENABLED (1 << 1) /* guest FP regs loaded */
306 #define KVM_ARM64_FP_HOST (1 << 2) /* host FP regs loaded */
307 #define KVM_ARM64_HOST_SVE_IN_USE (1 << 3) /* backup for host TIF_SVE */
308 #define KVM_ARM64_HOST_SVE_ENABLED (1 << 4) /* SVE enabled for EL0 */
309
310 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.gp_regs)
311
312 /*
313 * Only use __vcpu_sys_reg if you know you want the memory backed version of a
314 * register, and not the one most recently accessed by a running VCPU. For
315 * example, for userspace access or for system registers that are never context
316 * switched, but only emulated.
317 */
318 #define __vcpu_sys_reg(v,r) ((v)->arch.ctxt.sys_regs[(r)])
319
320 u64 vcpu_read_sys_reg(struct kvm_vcpu *vcpu, int reg);
321 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg);
322
323 /*
324 * CP14 and CP15 live in the same array, as they are backed by the
325 * same system registers.
326 */
327 #define vcpu_cp14(v,r) ((v)->arch.ctxt.copro[(r)])
328 #define vcpu_cp15(v,r) ((v)->arch.ctxt.copro[(r)])
329
330 struct kvm_vm_stat {
331 ulong remote_tlb_flush;
332 };
333
334 struct kvm_vcpu_stat {
335 u64 halt_successful_poll;
336 u64 halt_attempted_poll;
337 u64 halt_poll_invalid;
338 u64 halt_wakeup;
339 u64 hvc_exit_stat;
340 u64 wfe_exit_stat;
341 u64 wfi_exit_stat;
342 u64 mmio_exit_user;
343 u64 mmio_exit_kernel;
344 u64 exits;
345 };
346
347 int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init);
348 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
349 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
350 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
351 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
352 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
353 struct kvm_vcpu_events *events);
354
355 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu,
356 struct kvm_vcpu_events *events);
357
358 #define KVM_ARCH_WANT_MMU_NOTIFIER
359 int kvm_unmap_hva_range(struct kvm *kvm,
360 unsigned long start, unsigned long end);
361 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
362 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
363 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
364
365 struct kvm_vcpu *kvm_arm_get_running_vcpu(void);
366 struct kvm_vcpu * __percpu *kvm_get_running_vcpus(void);
367 void kvm_arm_halt_guest(struct kvm *kvm);
368 void kvm_arm_resume_guest(struct kvm *kvm);
369
370 u64 __kvm_call_hyp(void *hypfn, ...);
371 #define kvm_call_hyp(f, ...) __kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__)
372
373 void force_vm_exit(const cpumask_t *mask);
374 void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot);
375
376 int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
377 int exception_index);
378 void handle_exit_early(struct kvm_vcpu *vcpu, struct kvm_run *run,
379 int exception_index);
380
381 int kvm_perf_init(void);
382 int kvm_perf_teardown(void);
383
384 void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome);
385
386 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
387
388 DECLARE_PER_CPU(kvm_cpu_context_t, kvm_host_cpu_state);
389
__cpu_init_hyp_mode(phys_addr_t pgd_ptr,unsigned long hyp_stack_ptr,unsigned long vector_ptr)390 static inline void __cpu_init_hyp_mode(phys_addr_t pgd_ptr,
391 unsigned long hyp_stack_ptr,
392 unsigned long vector_ptr)
393 {
394 /*
395 * Calculate the raw per-cpu offset without a translation from the
396 * kernel's mapping to the linear mapping, and store it in tpidr_el2
397 * so that we can use adr_l to access per-cpu variables in EL2.
398 */
399 u64 tpidr_el2 = ((u64)this_cpu_ptr(&kvm_host_cpu_state) -
400 (u64)kvm_ksym_ref(kvm_host_cpu_state));
401
402 /*
403 * Call initialization code, and switch to the full blown HYP code.
404 * If the cpucaps haven't been finalized yet, something has gone very
405 * wrong, and hyp will crash and burn when it uses any
406 * cpus_have_const_cap() wrapper.
407 */
408 BUG_ON(!static_branch_likely(&arm64_const_caps_ready));
409 __kvm_call_hyp((void *)pgd_ptr, hyp_stack_ptr, vector_ptr, tpidr_el2);
410 }
411
kvm_arch_check_sve_has_vhe(void)412 static inline bool kvm_arch_check_sve_has_vhe(void)
413 {
414 /*
415 * The Arm architecture specifies that implementation of SVE
416 * requires VHE also to be implemented. The KVM code for arm64
417 * relies on this when SVE is present:
418 */
419 if (system_supports_sve())
420 return has_vhe();
421 else
422 return true;
423 }
424
kvm_arch_hardware_unsetup(void)425 static inline void kvm_arch_hardware_unsetup(void) {}
kvm_arch_sync_events(struct kvm * kvm)426 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
kvm_arch_vcpu_uninit(struct kvm_vcpu * vcpu)427 static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
kvm_arch_sched_in(struct kvm_vcpu * vcpu,int cpu)428 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
kvm_arch_vcpu_block_finish(struct kvm_vcpu * vcpu)429 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
430
431 void kvm_arm_init_debug(void);
432 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu);
433 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu);
434 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu);
435 bool kvm_arm_handle_step_debug(struct kvm_vcpu *vcpu, struct kvm_run *run);
436 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
437 struct kvm_device_attr *attr);
438 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
439 struct kvm_device_attr *attr);
440 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
441 struct kvm_device_attr *attr);
442
__cpu_init_stage2(void)443 static inline void __cpu_init_stage2(void)
444 {
445 u32 parange = kvm_call_hyp(__init_stage2_translation);
446
447 WARN_ONCE(parange < 40,
448 "PARange is %d bits, unsupported configuration!", parange);
449 }
450
451 /* Guest/host FPSIMD coordination helpers */
452 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu);
453 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu);
454 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu);
455 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu);
456
457 #ifdef CONFIG_KVM /* Avoid conflicts with core headers if CONFIG_KVM=n */
kvm_arch_vcpu_run_pid_change(struct kvm_vcpu * vcpu)458 static inline int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu)
459 {
460 return kvm_arch_vcpu_run_map_fp(vcpu);
461 }
462 #endif
463
kvm_arm_vhe_guest_enter(void)464 static inline void kvm_arm_vhe_guest_enter(void)
465 {
466 local_daif_mask();
467 }
468
kvm_arm_vhe_guest_exit(void)469 static inline void kvm_arm_vhe_guest_exit(void)
470 {
471 local_daif_restore(DAIF_PROCCTX_NOIRQ);
472
473 /*
474 * When we exit from the guest we change a number of CPU configuration
475 * parameters, such as traps. Make sure these changes take effect
476 * before running the host or additional guests.
477 */
478 isb();
479 }
480
kvm_arm_harden_branch_predictor(void)481 static inline bool kvm_arm_harden_branch_predictor(void)
482 {
483 return cpus_have_const_cap(ARM64_HARDEN_BRANCH_PREDICTOR);
484 }
485
486 #define KVM_SSBD_UNKNOWN -1
487 #define KVM_SSBD_FORCE_DISABLE 0
488 #define KVM_SSBD_KERNEL 1
489 #define KVM_SSBD_FORCE_ENABLE 2
490 #define KVM_SSBD_MITIGATED 3
491
kvm_arm_have_ssbd(void)492 static inline int kvm_arm_have_ssbd(void)
493 {
494 switch (arm64_get_ssbd_state()) {
495 case ARM64_SSBD_FORCE_DISABLE:
496 return KVM_SSBD_FORCE_DISABLE;
497 case ARM64_SSBD_KERNEL:
498 return KVM_SSBD_KERNEL;
499 case ARM64_SSBD_FORCE_ENABLE:
500 return KVM_SSBD_FORCE_ENABLE;
501 case ARM64_SSBD_MITIGATED:
502 return KVM_SSBD_MITIGATED;
503 case ARM64_SSBD_UNKNOWN:
504 default:
505 return KVM_SSBD_UNKNOWN;
506 }
507 }
508
509 void kvm_vcpu_load_sysregs(struct kvm_vcpu *vcpu);
510 void kvm_vcpu_put_sysregs(struct kvm_vcpu *vcpu);
511
512 #define __KVM_HAVE_ARCH_VM_ALLOC
513 struct kvm *kvm_arch_alloc_vm(void);
514 void kvm_arch_free_vm(struct kvm *kvm);
515
516 #endif /* __ARM64_KVM_HOST_H__ */
517
