1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 *
5 * Copyright (C) 2002 - 2011 Paul Mundt
6 * Copyright (C) 2015 Glider bvba
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 */
18 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19 #define SUPPORT_SYSRQ
20 #endif
21
22 #undef DEBUG
23
24 #include <linux/clk.h>
25 #include <linux/console.h>
26 #include <linux/ctype.h>
27 #include <linux/cpufreq.h>
28 #include <linux/delay.h>
29 #include <linux/dmaengine.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/err.h>
32 #include <linux/errno.h>
33 #include <linux/init.h>
34 #include <linux/interrupt.h>
35 #include <linux/ioport.h>
36 #include <linux/ktime.h>
37 #include <linux/major.h>
38 #include <linux/module.h>
39 #include <linux/mm.h>
40 #include <linux/of.h>
41 #include <linux/of_device.h>
42 #include <linux/platform_device.h>
43 #include <linux/pm_runtime.h>
44 #include <linux/scatterlist.h>
45 #include <linux/serial.h>
46 #include <linux/serial_sci.h>
47 #include <linux/sh_dma.h>
48 #include <linux/slab.h>
49 #include <linux/string.h>
50 #include <linux/sysrq.h>
51 #include <linux/timer.h>
52 #include <linux/tty.h>
53 #include <linux/tty_flip.h>
54
55 #ifdef CONFIG_SUPERH
56 #include <asm/sh_bios.h>
57 #endif
58
59 #include "serial_mctrl_gpio.h"
60 #include "sh-sci.h"
61
62 /* Offsets into the sci_port->irqs array */
63 enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_DRI_IRQ,
69 SCIx_TEI_IRQ,
70 SCIx_NR_IRQS,
71
72 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
73 };
74
75 #define SCIx_IRQ_IS_MUXED(port) \
76 ((port)->irqs[SCIx_ERI_IRQ] == \
77 (port)->irqs[SCIx_RXI_IRQ]) || \
78 ((port)->irqs[SCIx_ERI_IRQ] && \
79 ((port)->irqs[SCIx_RXI_IRQ] < 0))
80
81 enum SCI_CLKS {
82 SCI_FCK, /* Functional Clock */
83 SCI_SCK, /* Optional External Clock */
84 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
85 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
86 SCI_NUM_CLKS
87 };
88
89 /* Bit x set means sampling rate x + 1 is supported */
90 #define SCI_SR(x) BIT((x) - 1)
91 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
92
93 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
94 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
95 SCI_SR(19) | SCI_SR(27)
96
97 #define min_sr(_port) ffs((_port)->sampling_rate_mask)
98 #define max_sr(_port) fls((_port)->sampling_rate_mask)
99
100 /* Iterate over all supported sampling rates, from high to low */
101 #define for_each_sr(_sr, _port) \
102 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
103 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
104
105 struct plat_sci_reg {
106 u8 offset, size;
107 };
108
109 struct sci_port_params {
110 const struct plat_sci_reg regs[SCIx_NR_REGS];
111 unsigned int fifosize;
112 unsigned int overrun_reg;
113 unsigned int overrun_mask;
114 unsigned int sampling_rate_mask;
115 unsigned int error_mask;
116 unsigned int error_clear;
117 };
118
119 struct sci_port {
120 struct uart_port port;
121
122 /* Platform configuration */
123 const struct sci_port_params *params;
124 const struct plat_sci_port *cfg;
125 unsigned int sampling_rate_mask;
126 resource_size_t reg_size;
127 struct mctrl_gpios *gpios;
128
129 /* Clocks */
130 struct clk *clks[SCI_NUM_CLKS];
131 unsigned long clk_rates[SCI_NUM_CLKS];
132
133 int irqs[SCIx_NR_IRQS];
134 char *irqstr[SCIx_NR_IRQS];
135
136 struct dma_chan *chan_tx;
137 struct dma_chan *chan_rx;
138
139 #ifdef CONFIG_SERIAL_SH_SCI_DMA
140 struct dma_chan *chan_tx_saved;
141 struct dma_chan *chan_rx_saved;
142 dma_cookie_t cookie_tx;
143 dma_cookie_t cookie_rx[2];
144 dma_cookie_t active_rx;
145 dma_addr_t tx_dma_addr;
146 unsigned int tx_dma_len;
147 struct scatterlist sg_rx[2];
148 void *rx_buf[2];
149 size_t buf_len_rx;
150 struct work_struct work_tx;
151 struct hrtimer rx_timer;
152 unsigned int rx_timeout; /* microseconds */
153 #endif
154 unsigned int rx_frame;
155 int rx_trigger;
156 struct timer_list rx_fifo_timer;
157 int rx_fifo_timeout;
158 u16 hscif_tot;
159
160 bool has_rtscts;
161 bool autorts;
162 };
163
164 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
165
166 static struct sci_port sci_ports[SCI_NPORTS];
167 static unsigned long sci_ports_in_use;
168 static struct uart_driver sci_uart_driver;
169
170 static inline struct sci_port *
to_sci_port(struct uart_port * uart)171 to_sci_port(struct uart_port *uart)
172 {
173 return container_of(uart, struct sci_port, port);
174 }
175
176 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
177 /*
178 * Common SCI definitions, dependent on the port's regshift
179 * value.
180 */
181 [SCIx_SCI_REGTYPE] = {
182 .regs = {
183 [SCSMR] = { 0x00, 8 },
184 [SCBRR] = { 0x01, 8 },
185 [SCSCR] = { 0x02, 8 },
186 [SCxTDR] = { 0x03, 8 },
187 [SCxSR] = { 0x04, 8 },
188 [SCxRDR] = { 0x05, 8 },
189 },
190 .fifosize = 1,
191 .overrun_reg = SCxSR,
192 .overrun_mask = SCI_ORER,
193 .sampling_rate_mask = SCI_SR(32),
194 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
195 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
196 },
197
198 /*
199 * Common definitions for legacy IrDA ports.
200 */
201 [SCIx_IRDA_REGTYPE] = {
202 .regs = {
203 [SCSMR] = { 0x00, 8 },
204 [SCBRR] = { 0x02, 8 },
205 [SCSCR] = { 0x04, 8 },
206 [SCxTDR] = { 0x06, 8 },
207 [SCxSR] = { 0x08, 16 },
208 [SCxRDR] = { 0x0a, 8 },
209 [SCFCR] = { 0x0c, 8 },
210 [SCFDR] = { 0x0e, 16 },
211 },
212 .fifosize = 1,
213 .overrun_reg = SCxSR,
214 .overrun_mask = SCI_ORER,
215 .sampling_rate_mask = SCI_SR(32),
216 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
217 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
218 },
219
220 /*
221 * Common SCIFA definitions.
222 */
223 [SCIx_SCIFA_REGTYPE] = {
224 .regs = {
225 [SCSMR] = { 0x00, 16 },
226 [SCBRR] = { 0x04, 8 },
227 [SCSCR] = { 0x08, 16 },
228 [SCxTDR] = { 0x20, 8 },
229 [SCxSR] = { 0x14, 16 },
230 [SCxRDR] = { 0x24, 8 },
231 [SCFCR] = { 0x18, 16 },
232 [SCFDR] = { 0x1c, 16 },
233 [SCPCR] = { 0x30, 16 },
234 [SCPDR] = { 0x34, 16 },
235 },
236 .fifosize = 64,
237 .overrun_reg = SCxSR,
238 .overrun_mask = SCIFA_ORER,
239 .sampling_rate_mask = SCI_SR_SCIFAB,
240 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
241 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
242 },
243
244 /*
245 * Common SCIFB definitions.
246 */
247 [SCIx_SCIFB_REGTYPE] = {
248 .regs = {
249 [SCSMR] = { 0x00, 16 },
250 [SCBRR] = { 0x04, 8 },
251 [SCSCR] = { 0x08, 16 },
252 [SCxTDR] = { 0x40, 8 },
253 [SCxSR] = { 0x14, 16 },
254 [SCxRDR] = { 0x60, 8 },
255 [SCFCR] = { 0x18, 16 },
256 [SCTFDR] = { 0x38, 16 },
257 [SCRFDR] = { 0x3c, 16 },
258 [SCPCR] = { 0x30, 16 },
259 [SCPDR] = { 0x34, 16 },
260 },
261 .fifosize = 256,
262 .overrun_reg = SCxSR,
263 .overrun_mask = SCIFA_ORER,
264 .sampling_rate_mask = SCI_SR_SCIFAB,
265 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
266 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
267 },
268
269 /*
270 * Common SH-2(A) SCIF definitions for ports with FIFO data
271 * count registers.
272 */
273 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
274 .regs = {
275 [SCSMR] = { 0x00, 16 },
276 [SCBRR] = { 0x04, 8 },
277 [SCSCR] = { 0x08, 16 },
278 [SCxTDR] = { 0x0c, 8 },
279 [SCxSR] = { 0x10, 16 },
280 [SCxRDR] = { 0x14, 8 },
281 [SCFCR] = { 0x18, 16 },
282 [SCFDR] = { 0x1c, 16 },
283 [SCSPTR] = { 0x20, 16 },
284 [SCLSR] = { 0x24, 16 },
285 },
286 .fifosize = 16,
287 .overrun_reg = SCLSR,
288 .overrun_mask = SCLSR_ORER,
289 .sampling_rate_mask = SCI_SR(32),
290 .error_mask = SCIF_DEFAULT_ERROR_MASK,
291 .error_clear = SCIF_ERROR_CLEAR,
292 },
293
294 /*
295 * The "SCIFA" that is in RZ/T and RZ/A2.
296 * It looks like a normal SCIF with FIFO data, but with a
297 * compressed address space. Also, the break out of interrupts
298 * are different: ERI/BRI, RXI, TXI, TEI, DRI.
299 */
300 [SCIx_RZ_SCIFA_REGTYPE] = {
301 .regs = {
302 [SCSMR] = { 0x00, 16 },
303 [SCBRR] = { 0x02, 8 },
304 [SCSCR] = { 0x04, 16 },
305 [SCxTDR] = { 0x06, 8 },
306 [SCxSR] = { 0x08, 16 },
307 [SCxRDR] = { 0x0A, 8 },
308 [SCFCR] = { 0x0C, 16 },
309 [SCFDR] = { 0x0E, 16 },
310 [SCSPTR] = { 0x10, 16 },
311 [SCLSR] = { 0x12, 16 },
312 },
313 .fifosize = 16,
314 .overrun_reg = SCLSR,
315 .overrun_mask = SCLSR_ORER,
316 .sampling_rate_mask = SCI_SR(32),
317 .error_mask = SCIF_DEFAULT_ERROR_MASK,
318 .error_clear = SCIF_ERROR_CLEAR,
319 },
320
321 /*
322 * Common SH-3 SCIF definitions.
323 */
324 [SCIx_SH3_SCIF_REGTYPE] = {
325 .regs = {
326 [SCSMR] = { 0x00, 8 },
327 [SCBRR] = { 0x02, 8 },
328 [SCSCR] = { 0x04, 8 },
329 [SCxTDR] = { 0x06, 8 },
330 [SCxSR] = { 0x08, 16 },
331 [SCxRDR] = { 0x0a, 8 },
332 [SCFCR] = { 0x0c, 8 },
333 [SCFDR] = { 0x0e, 16 },
334 },
335 .fifosize = 16,
336 .overrun_reg = SCLSR,
337 .overrun_mask = SCLSR_ORER,
338 .sampling_rate_mask = SCI_SR(32),
339 .error_mask = SCIF_DEFAULT_ERROR_MASK,
340 .error_clear = SCIF_ERROR_CLEAR,
341 },
342
343 /*
344 * Common SH-4(A) SCIF(B) definitions.
345 */
346 [SCIx_SH4_SCIF_REGTYPE] = {
347 .regs = {
348 [SCSMR] = { 0x00, 16 },
349 [SCBRR] = { 0x04, 8 },
350 [SCSCR] = { 0x08, 16 },
351 [SCxTDR] = { 0x0c, 8 },
352 [SCxSR] = { 0x10, 16 },
353 [SCxRDR] = { 0x14, 8 },
354 [SCFCR] = { 0x18, 16 },
355 [SCFDR] = { 0x1c, 16 },
356 [SCSPTR] = { 0x20, 16 },
357 [SCLSR] = { 0x24, 16 },
358 },
359 .fifosize = 16,
360 .overrun_reg = SCLSR,
361 .overrun_mask = SCLSR_ORER,
362 .sampling_rate_mask = SCI_SR(32),
363 .error_mask = SCIF_DEFAULT_ERROR_MASK,
364 .error_clear = SCIF_ERROR_CLEAR,
365 },
366
367 /*
368 * Common SCIF definitions for ports with a Baud Rate Generator for
369 * External Clock (BRG).
370 */
371 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
372 .regs = {
373 [SCSMR] = { 0x00, 16 },
374 [SCBRR] = { 0x04, 8 },
375 [SCSCR] = { 0x08, 16 },
376 [SCxTDR] = { 0x0c, 8 },
377 [SCxSR] = { 0x10, 16 },
378 [SCxRDR] = { 0x14, 8 },
379 [SCFCR] = { 0x18, 16 },
380 [SCFDR] = { 0x1c, 16 },
381 [SCSPTR] = { 0x20, 16 },
382 [SCLSR] = { 0x24, 16 },
383 [SCDL] = { 0x30, 16 },
384 [SCCKS] = { 0x34, 16 },
385 },
386 .fifosize = 16,
387 .overrun_reg = SCLSR,
388 .overrun_mask = SCLSR_ORER,
389 .sampling_rate_mask = SCI_SR(32),
390 .error_mask = SCIF_DEFAULT_ERROR_MASK,
391 .error_clear = SCIF_ERROR_CLEAR,
392 },
393
394 /*
395 * Common HSCIF definitions.
396 */
397 [SCIx_HSCIF_REGTYPE] = {
398 .regs = {
399 [SCSMR] = { 0x00, 16 },
400 [SCBRR] = { 0x04, 8 },
401 [SCSCR] = { 0x08, 16 },
402 [SCxTDR] = { 0x0c, 8 },
403 [SCxSR] = { 0x10, 16 },
404 [SCxRDR] = { 0x14, 8 },
405 [SCFCR] = { 0x18, 16 },
406 [SCFDR] = { 0x1c, 16 },
407 [SCSPTR] = { 0x20, 16 },
408 [SCLSR] = { 0x24, 16 },
409 [HSSRR] = { 0x40, 16 },
410 [SCDL] = { 0x30, 16 },
411 [SCCKS] = { 0x34, 16 },
412 [HSRTRGR] = { 0x54, 16 },
413 [HSTTRGR] = { 0x58, 16 },
414 },
415 .fifosize = 128,
416 .overrun_reg = SCLSR,
417 .overrun_mask = SCLSR_ORER,
418 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
419 .error_mask = SCIF_DEFAULT_ERROR_MASK,
420 .error_clear = SCIF_ERROR_CLEAR,
421 },
422
423 /*
424 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
425 * register.
426 */
427 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
428 .regs = {
429 [SCSMR] = { 0x00, 16 },
430 [SCBRR] = { 0x04, 8 },
431 [SCSCR] = { 0x08, 16 },
432 [SCxTDR] = { 0x0c, 8 },
433 [SCxSR] = { 0x10, 16 },
434 [SCxRDR] = { 0x14, 8 },
435 [SCFCR] = { 0x18, 16 },
436 [SCFDR] = { 0x1c, 16 },
437 [SCLSR] = { 0x24, 16 },
438 },
439 .fifosize = 16,
440 .overrun_reg = SCLSR,
441 .overrun_mask = SCLSR_ORER,
442 .sampling_rate_mask = SCI_SR(32),
443 .error_mask = SCIF_DEFAULT_ERROR_MASK,
444 .error_clear = SCIF_ERROR_CLEAR,
445 },
446
447 /*
448 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
449 * count registers.
450 */
451 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
452 .regs = {
453 [SCSMR] = { 0x00, 16 },
454 [SCBRR] = { 0x04, 8 },
455 [SCSCR] = { 0x08, 16 },
456 [SCxTDR] = { 0x0c, 8 },
457 [SCxSR] = { 0x10, 16 },
458 [SCxRDR] = { 0x14, 8 },
459 [SCFCR] = { 0x18, 16 },
460 [SCFDR] = { 0x1c, 16 },
461 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
462 [SCRFDR] = { 0x20, 16 },
463 [SCSPTR] = { 0x24, 16 },
464 [SCLSR] = { 0x28, 16 },
465 },
466 .fifosize = 16,
467 .overrun_reg = SCLSR,
468 .overrun_mask = SCLSR_ORER,
469 .sampling_rate_mask = SCI_SR(32),
470 .error_mask = SCIF_DEFAULT_ERROR_MASK,
471 .error_clear = SCIF_ERROR_CLEAR,
472 },
473
474 /*
475 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
476 * registers.
477 */
478 [SCIx_SH7705_SCIF_REGTYPE] = {
479 .regs = {
480 [SCSMR] = { 0x00, 16 },
481 [SCBRR] = { 0x04, 8 },
482 [SCSCR] = { 0x08, 16 },
483 [SCxTDR] = { 0x20, 8 },
484 [SCxSR] = { 0x14, 16 },
485 [SCxRDR] = { 0x24, 8 },
486 [SCFCR] = { 0x18, 16 },
487 [SCFDR] = { 0x1c, 16 },
488 },
489 .fifosize = 64,
490 .overrun_reg = SCxSR,
491 .overrun_mask = SCIFA_ORER,
492 .sampling_rate_mask = SCI_SR(16),
493 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
494 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
495 },
496 };
497
498 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
499
500 /*
501 * The "offset" here is rather misleading, in that it refers to an enum
502 * value relative to the port mapping rather than the fixed offset
503 * itself, which needs to be manually retrieved from the platform's
504 * register map for the given port.
505 */
sci_serial_in(struct uart_port * p,int offset)506 static unsigned int sci_serial_in(struct uart_port *p, int offset)
507 {
508 const struct plat_sci_reg *reg = sci_getreg(p, offset);
509
510 if (reg->size == 8)
511 return ioread8(p->membase + (reg->offset << p->regshift));
512 else if (reg->size == 16)
513 return ioread16(p->membase + (reg->offset << p->regshift));
514 else
515 WARN(1, "Invalid register access\n");
516
517 return 0;
518 }
519
sci_serial_out(struct uart_port * p,int offset,int value)520 static void sci_serial_out(struct uart_port *p, int offset, int value)
521 {
522 const struct plat_sci_reg *reg = sci_getreg(p, offset);
523
524 if (reg->size == 8)
525 iowrite8(value, p->membase + (reg->offset << p->regshift));
526 else if (reg->size == 16)
527 iowrite16(value, p->membase + (reg->offset << p->regshift));
528 else
529 WARN(1, "Invalid register access\n");
530 }
531
sci_port_enable(struct sci_port * sci_port)532 static void sci_port_enable(struct sci_port *sci_port)
533 {
534 unsigned int i;
535
536 if (!sci_port->port.dev)
537 return;
538
539 pm_runtime_get_sync(sci_port->port.dev);
540
541 for (i = 0; i < SCI_NUM_CLKS; i++) {
542 clk_prepare_enable(sci_port->clks[i]);
543 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
544 }
545 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
546 }
547
sci_port_disable(struct sci_port * sci_port)548 static void sci_port_disable(struct sci_port *sci_port)
549 {
550 unsigned int i;
551
552 if (!sci_port->port.dev)
553 return;
554
555 for (i = SCI_NUM_CLKS; i-- > 0; )
556 clk_disable_unprepare(sci_port->clks[i]);
557
558 pm_runtime_put_sync(sci_port->port.dev);
559 }
560
port_rx_irq_mask(struct uart_port * port)561 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
562 {
563 /*
564 * Not all ports (such as SCIFA) will support REIE. Rather than
565 * special-casing the port type, we check the port initialization
566 * IRQ enable mask to see whether the IRQ is desired at all. If
567 * it's unset, it's logically inferred that there's no point in
568 * testing for it.
569 */
570 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
571 }
572
sci_start_tx(struct uart_port * port)573 static void sci_start_tx(struct uart_port *port)
574 {
575 struct sci_port *s = to_sci_port(port);
576 unsigned short ctrl;
577
578 #ifdef CONFIG_SERIAL_SH_SCI_DMA
579 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
580 u16 new, scr = serial_port_in(port, SCSCR);
581 if (s->chan_tx)
582 new = scr | SCSCR_TDRQE;
583 else
584 new = scr & ~SCSCR_TDRQE;
585 if (new != scr)
586 serial_port_out(port, SCSCR, new);
587 }
588
589 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
590 dma_submit_error(s->cookie_tx)) {
591 s->cookie_tx = 0;
592 schedule_work(&s->work_tx);
593 }
594 #endif
595
596 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
597 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
598 ctrl = serial_port_in(port, SCSCR);
599 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
600 }
601 }
602
sci_stop_tx(struct uart_port * port)603 static void sci_stop_tx(struct uart_port *port)
604 {
605 unsigned short ctrl;
606
607 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
608 ctrl = serial_port_in(port, SCSCR);
609
610 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
611 ctrl &= ~SCSCR_TDRQE;
612
613 ctrl &= ~SCSCR_TIE;
614
615 serial_port_out(port, SCSCR, ctrl);
616 }
617
sci_start_rx(struct uart_port * port)618 static void sci_start_rx(struct uart_port *port)
619 {
620 unsigned short ctrl;
621
622 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
623
624 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
625 ctrl &= ~SCSCR_RDRQE;
626
627 serial_port_out(port, SCSCR, ctrl);
628 }
629
sci_stop_rx(struct uart_port * port)630 static void sci_stop_rx(struct uart_port *port)
631 {
632 unsigned short ctrl;
633
634 ctrl = serial_port_in(port, SCSCR);
635
636 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
637 ctrl &= ~SCSCR_RDRQE;
638
639 ctrl &= ~port_rx_irq_mask(port);
640
641 serial_port_out(port, SCSCR, ctrl);
642 }
643
sci_clear_SCxSR(struct uart_port * port,unsigned int mask)644 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
645 {
646 if (port->type == PORT_SCI) {
647 /* Just store the mask */
648 serial_port_out(port, SCxSR, mask);
649 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
650 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
651 /* Only clear the status bits we want to clear */
652 serial_port_out(port, SCxSR,
653 serial_port_in(port, SCxSR) & mask);
654 } else {
655 /* Store the mask, clear parity/framing errors */
656 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
657 }
658 }
659
660 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
661 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
662
663 #ifdef CONFIG_CONSOLE_POLL
sci_poll_get_char(struct uart_port * port)664 static int sci_poll_get_char(struct uart_port *port)
665 {
666 unsigned short status;
667 int c;
668
669 do {
670 status = serial_port_in(port, SCxSR);
671 if (status & SCxSR_ERRORS(port)) {
672 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
673 continue;
674 }
675 break;
676 } while (1);
677
678 if (!(status & SCxSR_RDxF(port)))
679 return NO_POLL_CHAR;
680
681 c = serial_port_in(port, SCxRDR);
682
683 /* Dummy read */
684 serial_port_in(port, SCxSR);
685 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
686
687 return c;
688 }
689 #endif
690
sci_poll_put_char(struct uart_port * port,unsigned char c)691 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
692 {
693 unsigned short status;
694
695 do {
696 status = serial_port_in(port, SCxSR);
697 } while (!(status & SCxSR_TDxE(port)));
698
699 serial_port_out(port, SCxTDR, c);
700 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
701 }
702 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
703 CONFIG_SERIAL_SH_SCI_EARLYCON */
704
sci_init_pins(struct uart_port * port,unsigned int cflag)705 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
706 {
707 struct sci_port *s = to_sci_port(port);
708
709 /*
710 * Use port-specific handler if provided.
711 */
712 if (s->cfg->ops && s->cfg->ops->init_pins) {
713 s->cfg->ops->init_pins(port, cflag);
714 return;
715 }
716
717 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
718 u16 data = serial_port_in(port, SCPDR);
719 u16 ctrl = serial_port_in(port, SCPCR);
720
721 /* Enable RXD and TXD pin functions */
722 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
723 if (to_sci_port(port)->has_rtscts) {
724 /* RTS# is output, active low, unless autorts */
725 if (!(port->mctrl & TIOCM_RTS)) {
726 ctrl |= SCPCR_RTSC;
727 data |= SCPDR_RTSD;
728 } else if (!s->autorts) {
729 ctrl |= SCPCR_RTSC;
730 data &= ~SCPDR_RTSD;
731 } else {
732 /* Enable RTS# pin function */
733 ctrl &= ~SCPCR_RTSC;
734 }
735 /* Enable CTS# pin function */
736 ctrl &= ~SCPCR_CTSC;
737 }
738 serial_port_out(port, SCPDR, data);
739 serial_port_out(port, SCPCR, ctrl);
740 } else if (sci_getreg(port, SCSPTR)->size) {
741 u16 status = serial_port_in(port, SCSPTR);
742
743 /* RTS# is always output; and active low, unless autorts */
744 status |= SCSPTR_RTSIO;
745 if (!(port->mctrl & TIOCM_RTS))
746 status |= SCSPTR_RTSDT;
747 else if (!s->autorts)
748 status &= ~SCSPTR_RTSDT;
749 /* CTS# and SCK are inputs */
750 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
751 serial_port_out(port, SCSPTR, status);
752 }
753 }
754
sci_txfill(struct uart_port * port)755 static int sci_txfill(struct uart_port *port)
756 {
757 struct sci_port *s = to_sci_port(port);
758 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
759 const struct plat_sci_reg *reg;
760
761 reg = sci_getreg(port, SCTFDR);
762 if (reg->size)
763 return serial_port_in(port, SCTFDR) & fifo_mask;
764
765 reg = sci_getreg(port, SCFDR);
766 if (reg->size)
767 return serial_port_in(port, SCFDR) >> 8;
768
769 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
770 }
771
sci_txroom(struct uart_port * port)772 static int sci_txroom(struct uart_port *port)
773 {
774 return port->fifosize - sci_txfill(port);
775 }
776
sci_rxfill(struct uart_port * port)777 static int sci_rxfill(struct uart_port *port)
778 {
779 struct sci_port *s = to_sci_port(port);
780 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
781 const struct plat_sci_reg *reg;
782
783 reg = sci_getreg(port, SCRFDR);
784 if (reg->size)
785 return serial_port_in(port, SCRFDR) & fifo_mask;
786
787 reg = sci_getreg(port, SCFDR);
788 if (reg->size)
789 return serial_port_in(port, SCFDR) & fifo_mask;
790
791 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
792 }
793
794 /* ********************************************************************** *
795 * the interrupt related routines *
796 * ********************************************************************** */
797
sci_transmit_chars(struct uart_port * port)798 static void sci_transmit_chars(struct uart_port *port)
799 {
800 struct circ_buf *xmit = &port->state->xmit;
801 unsigned int stopped = uart_tx_stopped(port);
802 unsigned short status;
803 unsigned short ctrl;
804 int count;
805
806 status = serial_port_in(port, SCxSR);
807 if (!(status & SCxSR_TDxE(port))) {
808 ctrl = serial_port_in(port, SCSCR);
809 if (uart_circ_empty(xmit))
810 ctrl &= ~SCSCR_TIE;
811 else
812 ctrl |= SCSCR_TIE;
813 serial_port_out(port, SCSCR, ctrl);
814 return;
815 }
816
817 count = sci_txroom(port);
818
819 do {
820 unsigned char c;
821
822 if (port->x_char) {
823 c = port->x_char;
824 port->x_char = 0;
825 } else if (!uart_circ_empty(xmit) && !stopped) {
826 c = xmit->buf[xmit->tail];
827 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
828 } else {
829 break;
830 }
831
832 serial_port_out(port, SCxTDR, c);
833
834 port->icount.tx++;
835 } while (--count > 0);
836
837 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
838
839 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
840 uart_write_wakeup(port);
841 if (uart_circ_empty(xmit)) {
842 sci_stop_tx(port);
843 } else {
844 ctrl = serial_port_in(port, SCSCR);
845
846 if (port->type != PORT_SCI) {
847 serial_port_in(port, SCxSR); /* Dummy read */
848 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
849 }
850
851 ctrl |= SCSCR_TIE;
852 serial_port_out(port, SCSCR, ctrl);
853 }
854 }
855
856 /* On SH3, SCIF may read end-of-break as a space->mark char */
857 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
858
sci_receive_chars(struct uart_port * port)859 static void sci_receive_chars(struct uart_port *port)
860 {
861 struct tty_port *tport = &port->state->port;
862 int i, count, copied = 0;
863 unsigned short status;
864 unsigned char flag;
865
866 status = serial_port_in(port, SCxSR);
867 if (!(status & SCxSR_RDxF(port)))
868 return;
869
870 while (1) {
871 /* Don't copy more bytes than there is room for in the buffer */
872 count = tty_buffer_request_room(tport, sci_rxfill(port));
873
874 /* If for any reason we can't copy more data, we're done! */
875 if (count == 0)
876 break;
877
878 if (port->type == PORT_SCI) {
879 char c = serial_port_in(port, SCxRDR);
880 if (uart_handle_sysrq_char(port, c))
881 count = 0;
882 else
883 tty_insert_flip_char(tport, c, TTY_NORMAL);
884 } else {
885 for (i = 0; i < count; i++) {
886 char c = serial_port_in(port, SCxRDR);
887
888 status = serial_port_in(port, SCxSR);
889 if (uart_handle_sysrq_char(port, c)) {
890 count--; i--;
891 continue;
892 }
893
894 /* Store data and status */
895 if (status & SCxSR_FER(port)) {
896 flag = TTY_FRAME;
897 port->icount.frame++;
898 dev_notice(port->dev, "frame error\n");
899 } else if (status & SCxSR_PER(port)) {
900 flag = TTY_PARITY;
901 port->icount.parity++;
902 dev_notice(port->dev, "parity error\n");
903 } else
904 flag = TTY_NORMAL;
905
906 tty_insert_flip_char(tport, c, flag);
907 }
908 }
909
910 serial_port_in(port, SCxSR); /* dummy read */
911 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
912
913 copied += count;
914 port->icount.rx += count;
915 }
916
917 if (copied) {
918 /* Tell the rest of the system the news. New characters! */
919 tty_flip_buffer_push(tport);
920 } else {
921 /* TTY buffers full; read from RX reg to prevent lockup */
922 serial_port_in(port, SCxRDR);
923 serial_port_in(port, SCxSR); /* dummy read */
924 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
925 }
926 }
927
sci_handle_errors(struct uart_port * port)928 static int sci_handle_errors(struct uart_port *port)
929 {
930 int copied = 0;
931 unsigned short status = serial_port_in(port, SCxSR);
932 struct tty_port *tport = &port->state->port;
933 struct sci_port *s = to_sci_port(port);
934
935 /* Handle overruns */
936 if (status & s->params->overrun_mask) {
937 port->icount.overrun++;
938
939 /* overrun error */
940 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
941 copied++;
942
943 dev_notice(port->dev, "overrun error\n");
944 }
945
946 if (status & SCxSR_FER(port)) {
947 /* frame error */
948 port->icount.frame++;
949
950 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
951 copied++;
952
953 dev_notice(port->dev, "frame error\n");
954 }
955
956 if (status & SCxSR_PER(port)) {
957 /* parity error */
958 port->icount.parity++;
959
960 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
961 copied++;
962
963 dev_notice(port->dev, "parity error\n");
964 }
965
966 if (copied)
967 tty_flip_buffer_push(tport);
968
969 return copied;
970 }
971
sci_handle_fifo_overrun(struct uart_port * port)972 static int sci_handle_fifo_overrun(struct uart_port *port)
973 {
974 struct tty_port *tport = &port->state->port;
975 struct sci_port *s = to_sci_port(port);
976 const struct plat_sci_reg *reg;
977 int copied = 0;
978 u16 status;
979
980 reg = sci_getreg(port, s->params->overrun_reg);
981 if (!reg->size)
982 return 0;
983
984 status = serial_port_in(port, s->params->overrun_reg);
985 if (status & s->params->overrun_mask) {
986 status &= ~s->params->overrun_mask;
987 serial_port_out(port, s->params->overrun_reg, status);
988
989 port->icount.overrun++;
990
991 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
992 tty_flip_buffer_push(tport);
993
994 dev_dbg(port->dev, "overrun error\n");
995 copied++;
996 }
997
998 return copied;
999 }
1000
sci_handle_breaks(struct uart_port * port)1001 static int sci_handle_breaks(struct uart_port *port)
1002 {
1003 int copied = 0;
1004 unsigned short status = serial_port_in(port, SCxSR);
1005 struct tty_port *tport = &port->state->port;
1006
1007 if (uart_handle_break(port))
1008 return 0;
1009
1010 if (status & SCxSR_BRK(port)) {
1011 port->icount.brk++;
1012
1013 /* Notify of BREAK */
1014 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1015 copied++;
1016
1017 dev_dbg(port->dev, "BREAK detected\n");
1018 }
1019
1020 if (copied)
1021 tty_flip_buffer_push(tport);
1022
1023 copied += sci_handle_fifo_overrun(port);
1024
1025 return copied;
1026 }
1027
scif_set_rtrg(struct uart_port * port,int rx_trig)1028 static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1029 {
1030 unsigned int bits;
1031
1032 if (rx_trig < 1)
1033 rx_trig = 1;
1034 if (rx_trig >= port->fifosize)
1035 rx_trig = port->fifosize;
1036
1037 /* HSCIF can be set to an arbitrary level. */
1038 if (sci_getreg(port, HSRTRGR)->size) {
1039 serial_port_out(port, HSRTRGR, rx_trig);
1040 return rx_trig;
1041 }
1042
1043 switch (port->type) {
1044 case PORT_SCIF:
1045 if (rx_trig < 4) {
1046 bits = 0;
1047 rx_trig = 1;
1048 } else if (rx_trig < 8) {
1049 bits = SCFCR_RTRG0;
1050 rx_trig = 4;
1051 } else if (rx_trig < 14) {
1052 bits = SCFCR_RTRG1;
1053 rx_trig = 8;
1054 } else {
1055 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1056 rx_trig = 14;
1057 }
1058 break;
1059 case PORT_SCIFA:
1060 case PORT_SCIFB:
1061 if (rx_trig < 16) {
1062 bits = 0;
1063 rx_trig = 1;
1064 } else if (rx_trig < 32) {
1065 bits = SCFCR_RTRG0;
1066 rx_trig = 16;
1067 } else if (rx_trig < 48) {
1068 bits = SCFCR_RTRG1;
1069 rx_trig = 32;
1070 } else {
1071 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1072 rx_trig = 48;
1073 }
1074 break;
1075 default:
1076 WARN(1, "unknown FIFO configuration");
1077 return 1;
1078 }
1079
1080 serial_port_out(port, SCFCR,
1081 (serial_port_in(port, SCFCR) &
1082 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1083
1084 return rx_trig;
1085 }
1086
scif_rtrg_enabled(struct uart_port * port)1087 static int scif_rtrg_enabled(struct uart_port *port)
1088 {
1089 if (sci_getreg(port, HSRTRGR)->size)
1090 return serial_port_in(port, HSRTRGR) != 0;
1091 else
1092 return (serial_port_in(port, SCFCR) &
1093 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1094 }
1095
rx_fifo_timer_fn(struct timer_list * t)1096 static void rx_fifo_timer_fn(struct timer_list *t)
1097 {
1098 struct sci_port *s = from_timer(s, t, rx_fifo_timer);
1099 struct uart_port *port = &s->port;
1100
1101 dev_dbg(port->dev, "Rx timed out\n");
1102 scif_set_rtrg(port, 1);
1103 }
1104
rx_trigger_show(struct device * dev,struct device_attribute * attr,char * buf)1105 static ssize_t rx_trigger_show(struct device *dev,
1106 struct device_attribute *attr,
1107 char *buf)
1108 {
1109 struct uart_port *port = dev_get_drvdata(dev);
1110 struct sci_port *sci = to_sci_port(port);
1111
1112 return sprintf(buf, "%d\n", sci->rx_trigger);
1113 }
1114
rx_trigger_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1115 static ssize_t rx_trigger_store(struct device *dev,
1116 struct device_attribute *attr,
1117 const char *buf,
1118 size_t count)
1119 {
1120 struct uart_port *port = dev_get_drvdata(dev);
1121 struct sci_port *sci = to_sci_port(port);
1122 int ret;
1123 long r;
1124
1125 ret = kstrtol(buf, 0, &r);
1126 if (ret)
1127 return ret;
1128
1129 sci->rx_trigger = scif_set_rtrg(port, r);
1130 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1131 scif_set_rtrg(port, 1);
1132
1133 return count;
1134 }
1135
1136 static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store);
1137
rx_fifo_timeout_show(struct device * dev,struct device_attribute * attr,char * buf)1138 static ssize_t rx_fifo_timeout_show(struct device *dev,
1139 struct device_attribute *attr,
1140 char *buf)
1141 {
1142 struct uart_port *port = dev_get_drvdata(dev);
1143 struct sci_port *sci = to_sci_port(port);
1144 int v;
1145
1146 if (port->type == PORT_HSCIF)
1147 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1148 else
1149 v = sci->rx_fifo_timeout;
1150
1151 return sprintf(buf, "%d\n", v);
1152 }
1153
rx_fifo_timeout_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1154 static ssize_t rx_fifo_timeout_store(struct device *dev,
1155 struct device_attribute *attr,
1156 const char *buf,
1157 size_t count)
1158 {
1159 struct uart_port *port = dev_get_drvdata(dev);
1160 struct sci_port *sci = to_sci_port(port);
1161 int ret;
1162 long r;
1163
1164 ret = kstrtol(buf, 0, &r);
1165 if (ret)
1166 return ret;
1167
1168 if (port->type == PORT_HSCIF) {
1169 if (r < 0 || r > 3)
1170 return -EINVAL;
1171 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1172 } else {
1173 sci->rx_fifo_timeout = r;
1174 scif_set_rtrg(port, 1);
1175 if (r > 0)
1176 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1177 }
1178
1179 return count;
1180 }
1181
1182 static DEVICE_ATTR_RW(rx_fifo_timeout);
1183
1184
1185 #ifdef CONFIG_SERIAL_SH_SCI_DMA
sci_dma_tx_complete(void * arg)1186 static void sci_dma_tx_complete(void *arg)
1187 {
1188 struct sci_port *s = arg;
1189 struct uart_port *port = &s->port;
1190 struct circ_buf *xmit = &port->state->xmit;
1191 unsigned long flags;
1192
1193 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1194
1195 spin_lock_irqsave(&port->lock, flags);
1196
1197 xmit->tail += s->tx_dma_len;
1198 xmit->tail &= UART_XMIT_SIZE - 1;
1199
1200 port->icount.tx += s->tx_dma_len;
1201
1202 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1203 uart_write_wakeup(port);
1204
1205 if (!uart_circ_empty(xmit)) {
1206 s->cookie_tx = 0;
1207 schedule_work(&s->work_tx);
1208 } else {
1209 s->cookie_tx = -EINVAL;
1210 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1211 u16 ctrl = serial_port_in(port, SCSCR);
1212 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1213 }
1214 }
1215
1216 spin_unlock_irqrestore(&port->lock, flags);
1217 }
1218
1219 /* Locking: called with port lock held */
sci_dma_rx_push(struct sci_port * s,void * buf,size_t count)1220 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1221 {
1222 struct uart_port *port = &s->port;
1223 struct tty_port *tport = &port->state->port;
1224 int copied;
1225
1226 copied = tty_insert_flip_string(tport, buf, count);
1227 if (copied < count)
1228 port->icount.buf_overrun++;
1229
1230 port->icount.rx += copied;
1231
1232 return copied;
1233 }
1234
sci_dma_rx_find_active(struct sci_port * s)1235 static int sci_dma_rx_find_active(struct sci_port *s)
1236 {
1237 unsigned int i;
1238
1239 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1240 if (s->active_rx == s->cookie_rx[i])
1241 return i;
1242
1243 return -1;
1244 }
1245
sci_rx_dma_release(struct sci_port * s)1246 static void sci_rx_dma_release(struct sci_port *s)
1247 {
1248 struct dma_chan *chan = s->chan_rx_saved;
1249
1250 s->chan_rx_saved = s->chan_rx = NULL;
1251 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1252 dmaengine_terminate_sync(chan);
1253 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1254 sg_dma_address(&s->sg_rx[0]));
1255 dma_release_channel(chan);
1256 }
1257
start_hrtimer_us(struct hrtimer * hrt,unsigned long usec)1258 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1259 {
1260 long sec = usec / 1000000;
1261 long nsec = (usec % 1000000) * 1000;
1262 ktime_t t = ktime_set(sec, nsec);
1263
1264 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1265 }
1266
sci_dma_rx_complete(void * arg)1267 static void sci_dma_rx_complete(void *arg)
1268 {
1269 struct sci_port *s = arg;
1270 struct dma_chan *chan = s->chan_rx;
1271 struct uart_port *port = &s->port;
1272 struct dma_async_tx_descriptor *desc;
1273 unsigned long flags;
1274 int active, count = 0;
1275
1276 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1277 s->active_rx);
1278
1279 spin_lock_irqsave(&port->lock, flags);
1280
1281 active = sci_dma_rx_find_active(s);
1282 if (active >= 0)
1283 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1284
1285 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1286
1287 if (count)
1288 tty_flip_buffer_push(&port->state->port);
1289
1290 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1291 DMA_DEV_TO_MEM,
1292 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1293 if (!desc)
1294 goto fail;
1295
1296 desc->callback = sci_dma_rx_complete;
1297 desc->callback_param = s;
1298 s->cookie_rx[active] = dmaengine_submit(desc);
1299 if (dma_submit_error(s->cookie_rx[active]))
1300 goto fail;
1301
1302 s->active_rx = s->cookie_rx[!active];
1303
1304 dma_async_issue_pending(chan);
1305
1306 spin_unlock_irqrestore(&port->lock, flags);
1307 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1308 __func__, s->cookie_rx[active], active, s->active_rx);
1309 return;
1310
1311 fail:
1312 spin_unlock_irqrestore(&port->lock, flags);
1313 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1314 /* Switch to PIO */
1315 spin_lock_irqsave(&port->lock, flags);
1316 s->chan_rx = NULL;
1317 sci_start_rx(port);
1318 spin_unlock_irqrestore(&port->lock, flags);
1319 }
1320
sci_tx_dma_release(struct sci_port * s)1321 static void sci_tx_dma_release(struct sci_port *s)
1322 {
1323 struct dma_chan *chan = s->chan_tx_saved;
1324
1325 cancel_work_sync(&s->work_tx);
1326 s->chan_tx_saved = s->chan_tx = NULL;
1327 s->cookie_tx = -EINVAL;
1328 dmaengine_terminate_sync(chan);
1329 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1330 DMA_TO_DEVICE);
1331 dma_release_channel(chan);
1332 }
1333
sci_submit_rx(struct sci_port * s)1334 static void sci_submit_rx(struct sci_port *s)
1335 {
1336 struct dma_chan *chan = s->chan_rx;
1337 struct uart_port *port = &s->port;
1338 unsigned long flags;
1339 int i;
1340
1341 for (i = 0; i < 2; i++) {
1342 struct scatterlist *sg = &s->sg_rx[i];
1343 struct dma_async_tx_descriptor *desc;
1344
1345 desc = dmaengine_prep_slave_sg(chan,
1346 sg, 1, DMA_DEV_TO_MEM,
1347 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1348 if (!desc)
1349 goto fail;
1350
1351 desc->callback = sci_dma_rx_complete;
1352 desc->callback_param = s;
1353 s->cookie_rx[i] = dmaengine_submit(desc);
1354 if (dma_submit_error(s->cookie_rx[i]))
1355 goto fail;
1356
1357 }
1358
1359 s->active_rx = s->cookie_rx[0];
1360
1361 dma_async_issue_pending(chan);
1362 return;
1363
1364 fail:
1365 if (i)
1366 dmaengine_terminate_async(chan);
1367 for (i = 0; i < 2; i++)
1368 s->cookie_rx[i] = -EINVAL;
1369 s->active_rx = -EINVAL;
1370 /* Switch to PIO */
1371 spin_lock_irqsave(&port->lock, flags);
1372 s->chan_rx = NULL;
1373 sci_start_rx(port);
1374 spin_unlock_irqrestore(&port->lock, flags);
1375 }
1376
work_fn_tx(struct work_struct * work)1377 static void work_fn_tx(struct work_struct *work)
1378 {
1379 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1380 struct dma_async_tx_descriptor *desc;
1381 struct dma_chan *chan = s->chan_tx;
1382 struct uart_port *port = &s->port;
1383 struct circ_buf *xmit = &port->state->xmit;
1384 unsigned long flags;
1385 dma_addr_t buf;
1386
1387 /*
1388 * DMA is idle now.
1389 * Port xmit buffer is already mapped, and it is one page... Just adjust
1390 * offsets and lengths. Since it is a circular buffer, we have to
1391 * transmit till the end, and then the rest. Take the port lock to get a
1392 * consistent xmit buffer state.
1393 */
1394 spin_lock_irq(&port->lock);
1395 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1396 s->tx_dma_len = min_t(unsigned int,
1397 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1398 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1399 spin_unlock_irq(&port->lock);
1400
1401 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1402 DMA_MEM_TO_DEV,
1403 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1404 if (!desc) {
1405 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1406 goto switch_to_pio;
1407 }
1408
1409 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1410 DMA_TO_DEVICE);
1411
1412 spin_lock_irq(&port->lock);
1413 desc->callback = sci_dma_tx_complete;
1414 desc->callback_param = s;
1415 spin_unlock_irq(&port->lock);
1416 s->cookie_tx = dmaengine_submit(desc);
1417 if (dma_submit_error(s->cookie_tx)) {
1418 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1419 goto switch_to_pio;
1420 }
1421
1422 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1423 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1424
1425 dma_async_issue_pending(chan);
1426 return;
1427
1428 switch_to_pio:
1429 spin_lock_irqsave(&port->lock, flags);
1430 s->chan_tx = NULL;
1431 sci_start_tx(port);
1432 spin_unlock_irqrestore(&port->lock, flags);
1433 return;
1434 }
1435
rx_timer_fn(struct hrtimer * t)1436 static enum hrtimer_restart rx_timer_fn(struct hrtimer *t)
1437 {
1438 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
1439 struct dma_chan *chan = s->chan_rx;
1440 struct uart_port *port = &s->port;
1441 struct dma_tx_state state;
1442 enum dma_status status;
1443 unsigned long flags;
1444 unsigned int read;
1445 int active, count;
1446 u16 scr;
1447
1448 dev_dbg(port->dev, "DMA Rx timed out\n");
1449
1450 spin_lock_irqsave(&port->lock, flags);
1451
1452 active = sci_dma_rx_find_active(s);
1453 if (active < 0) {
1454 spin_unlock_irqrestore(&port->lock, flags);
1455 return HRTIMER_NORESTART;
1456 }
1457
1458 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1459 if (status == DMA_COMPLETE) {
1460 spin_unlock_irqrestore(&port->lock, flags);
1461 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1462 s->active_rx, active);
1463
1464 /* Let packet complete handler take care of the packet */
1465 return HRTIMER_NORESTART;
1466 }
1467
1468 dmaengine_pause(chan);
1469
1470 /*
1471 * sometimes DMA transfer doesn't stop even if it is stopped and
1472 * data keeps on coming until transaction is complete so check
1473 * for DMA_COMPLETE again
1474 * Let packet complete handler take care of the packet
1475 */
1476 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1477 if (status == DMA_COMPLETE) {
1478 spin_unlock_irqrestore(&port->lock, flags);
1479 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1480 return HRTIMER_NORESTART;
1481 }
1482
1483 /* Handle incomplete DMA receive */
1484 dmaengine_terminate_async(s->chan_rx);
1485 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1486
1487 if (read) {
1488 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1489 if (count)
1490 tty_flip_buffer_push(&port->state->port);
1491 }
1492
1493 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1494 sci_submit_rx(s);
1495
1496 /* Direct new serial port interrupts back to CPU */
1497 scr = serial_port_in(port, SCSCR);
1498 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1499 scr &= ~SCSCR_RDRQE;
1500 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1501 }
1502 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1503
1504 spin_unlock_irqrestore(&port->lock, flags);
1505
1506 return HRTIMER_NORESTART;
1507 }
1508
sci_request_dma_chan(struct uart_port * port,enum dma_transfer_direction dir)1509 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1510 enum dma_transfer_direction dir)
1511 {
1512 struct dma_chan *chan;
1513 struct dma_slave_config cfg;
1514 int ret;
1515
1516 chan = dma_request_slave_channel(port->dev,
1517 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1518 if (!chan) {
1519 dev_warn(port->dev, "dma_request_slave_channel failed\n");
1520 return NULL;
1521 }
1522
1523 memset(&cfg, 0, sizeof(cfg));
1524 cfg.direction = dir;
1525 if (dir == DMA_MEM_TO_DEV) {
1526 cfg.dst_addr = port->mapbase +
1527 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1528 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1529 } else {
1530 cfg.src_addr = port->mapbase +
1531 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1532 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1533 }
1534
1535 ret = dmaengine_slave_config(chan, &cfg);
1536 if (ret) {
1537 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1538 dma_release_channel(chan);
1539 return NULL;
1540 }
1541
1542 return chan;
1543 }
1544
sci_request_dma(struct uart_port * port)1545 static void sci_request_dma(struct uart_port *port)
1546 {
1547 struct sci_port *s = to_sci_port(port);
1548 struct dma_chan *chan;
1549
1550 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1551
1552 if (!port->dev->of_node)
1553 return;
1554
1555 s->cookie_tx = -EINVAL;
1556
1557 /*
1558 * Don't request a dma channel if no channel was specified
1559 * in the device tree.
1560 */
1561 if (!of_find_property(port->dev->of_node, "dmas", NULL))
1562 return;
1563
1564 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1565 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1566 if (chan) {
1567 /* UART circular tx buffer is an aligned page. */
1568 s->tx_dma_addr = dma_map_single(chan->device->dev,
1569 port->state->xmit.buf,
1570 UART_XMIT_SIZE,
1571 DMA_TO_DEVICE);
1572 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1573 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1574 dma_release_channel(chan);
1575 } else {
1576 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1577 __func__, UART_XMIT_SIZE,
1578 port->state->xmit.buf, &s->tx_dma_addr);
1579
1580 INIT_WORK(&s->work_tx, work_fn_tx);
1581 s->chan_tx_saved = s->chan_tx = chan;
1582 }
1583 }
1584
1585 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1586 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1587 if (chan) {
1588 unsigned int i;
1589 dma_addr_t dma;
1590 void *buf;
1591
1592 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1593 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1594 &dma, GFP_KERNEL);
1595 if (!buf) {
1596 dev_warn(port->dev,
1597 "Failed to allocate Rx dma buffer, using PIO\n");
1598 dma_release_channel(chan);
1599 return;
1600 }
1601
1602 for (i = 0; i < 2; i++) {
1603 struct scatterlist *sg = &s->sg_rx[i];
1604
1605 sg_init_table(sg, 1);
1606 s->rx_buf[i] = buf;
1607 sg_dma_address(sg) = dma;
1608 sg_dma_len(sg) = s->buf_len_rx;
1609
1610 buf += s->buf_len_rx;
1611 dma += s->buf_len_rx;
1612 }
1613
1614 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1615 s->rx_timer.function = rx_timer_fn;
1616
1617 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1618 sci_submit_rx(s);
1619
1620 s->chan_rx_saved = s->chan_rx = chan;
1621 }
1622 }
1623
sci_free_dma(struct uart_port * port)1624 static void sci_free_dma(struct uart_port *port)
1625 {
1626 struct sci_port *s = to_sci_port(port);
1627
1628 if (s->chan_tx_saved)
1629 sci_tx_dma_release(s);
1630 if (s->chan_rx_saved)
1631 sci_rx_dma_release(s);
1632 }
1633
sci_flush_buffer(struct uart_port * port)1634 static void sci_flush_buffer(struct uart_port *port)
1635 {
1636 /*
1637 * In uart_flush_buffer(), the xmit circular buffer has just been
1638 * cleared, so we have to reset tx_dma_len accordingly.
1639 */
1640 to_sci_port(port)->tx_dma_len = 0;
1641 }
1642 #else /* !CONFIG_SERIAL_SH_SCI_DMA */
sci_request_dma(struct uart_port * port)1643 static inline void sci_request_dma(struct uart_port *port)
1644 {
1645 }
1646
sci_free_dma(struct uart_port * port)1647 static inline void sci_free_dma(struct uart_port *port)
1648 {
1649 }
1650
1651 #define sci_flush_buffer NULL
1652 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1653
sci_rx_interrupt(int irq,void * ptr)1654 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1655 {
1656 struct uart_port *port = ptr;
1657 struct sci_port *s = to_sci_port(port);
1658
1659 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1660 if (s->chan_rx) {
1661 u16 scr = serial_port_in(port, SCSCR);
1662 u16 ssr = serial_port_in(port, SCxSR);
1663
1664 /* Disable future Rx interrupts */
1665 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1666 disable_irq_nosync(irq);
1667 scr |= SCSCR_RDRQE;
1668 } else {
1669 scr &= ~SCSCR_RIE;
1670 sci_submit_rx(s);
1671 }
1672 serial_port_out(port, SCSCR, scr);
1673 /* Clear current interrupt */
1674 serial_port_out(port, SCxSR,
1675 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1676 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1677 jiffies, s->rx_timeout);
1678 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1679
1680 return IRQ_HANDLED;
1681 }
1682 #endif
1683
1684 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1685 if (!scif_rtrg_enabled(port))
1686 scif_set_rtrg(port, s->rx_trigger);
1687
1688 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1689 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
1690 }
1691
1692 /* I think sci_receive_chars has to be called irrespective
1693 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1694 * to be disabled?
1695 */
1696 sci_receive_chars(ptr);
1697
1698 return IRQ_HANDLED;
1699 }
1700
sci_tx_interrupt(int irq,void * ptr)1701 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1702 {
1703 struct uart_port *port = ptr;
1704 unsigned long flags;
1705
1706 spin_lock_irqsave(&port->lock, flags);
1707 sci_transmit_chars(port);
1708 spin_unlock_irqrestore(&port->lock, flags);
1709
1710 return IRQ_HANDLED;
1711 }
1712
sci_br_interrupt(int irq,void * ptr)1713 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1714 {
1715 struct uart_port *port = ptr;
1716
1717 /* Handle BREAKs */
1718 sci_handle_breaks(port);
1719 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1720
1721 return IRQ_HANDLED;
1722 }
1723
sci_er_interrupt(int irq,void * ptr)1724 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1725 {
1726 struct uart_port *port = ptr;
1727 struct sci_port *s = to_sci_port(port);
1728
1729 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
1730 /* Break and Error interrupts are muxed */
1731 unsigned short ssr_status = serial_port_in(port, SCxSR);
1732
1733 /* Break Interrupt */
1734 if (ssr_status & SCxSR_BRK(port))
1735 sci_br_interrupt(irq, ptr);
1736
1737 /* Break only? */
1738 if (!(ssr_status & SCxSR_ERRORS(port)))
1739 return IRQ_HANDLED;
1740 }
1741
1742 /* Handle errors */
1743 if (port->type == PORT_SCI) {
1744 if (sci_handle_errors(port)) {
1745 /* discard character in rx buffer */
1746 serial_port_in(port, SCxSR);
1747 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1748 }
1749 } else {
1750 sci_handle_fifo_overrun(port);
1751 if (!s->chan_rx)
1752 sci_receive_chars(ptr);
1753 }
1754
1755 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1756
1757 /* Kick the transmission */
1758 if (!s->chan_tx)
1759 sci_tx_interrupt(irq, ptr);
1760
1761 return IRQ_HANDLED;
1762 }
1763
sci_mpxed_interrupt(int irq,void * ptr)1764 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1765 {
1766 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1767 struct uart_port *port = ptr;
1768 struct sci_port *s = to_sci_port(port);
1769 irqreturn_t ret = IRQ_NONE;
1770
1771 ssr_status = serial_port_in(port, SCxSR);
1772 scr_status = serial_port_in(port, SCSCR);
1773 if (s->params->overrun_reg == SCxSR)
1774 orer_status = ssr_status;
1775 else if (sci_getreg(port, s->params->overrun_reg)->size)
1776 orer_status = serial_port_in(port, s->params->overrun_reg);
1777
1778 err_enabled = scr_status & port_rx_irq_mask(port);
1779
1780 /* Tx Interrupt */
1781 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1782 !s->chan_tx)
1783 ret = sci_tx_interrupt(irq, ptr);
1784
1785 /*
1786 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1787 * DR flags
1788 */
1789 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1790 (scr_status & SCSCR_RIE))
1791 ret = sci_rx_interrupt(irq, ptr);
1792
1793 /* Error Interrupt */
1794 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1795 ret = sci_er_interrupt(irq, ptr);
1796
1797 /* Break Interrupt */
1798 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1799 ret = sci_br_interrupt(irq, ptr);
1800
1801 /* Overrun Interrupt */
1802 if (orer_status & s->params->overrun_mask) {
1803 sci_handle_fifo_overrun(port);
1804 ret = IRQ_HANDLED;
1805 }
1806
1807 return ret;
1808 }
1809
1810 static const struct sci_irq_desc {
1811 const char *desc;
1812 irq_handler_t handler;
1813 } sci_irq_desc[] = {
1814 /*
1815 * Split out handlers, the default case.
1816 */
1817 [SCIx_ERI_IRQ] = {
1818 .desc = "rx err",
1819 .handler = sci_er_interrupt,
1820 },
1821
1822 [SCIx_RXI_IRQ] = {
1823 .desc = "rx full",
1824 .handler = sci_rx_interrupt,
1825 },
1826
1827 [SCIx_TXI_IRQ] = {
1828 .desc = "tx empty",
1829 .handler = sci_tx_interrupt,
1830 },
1831
1832 [SCIx_BRI_IRQ] = {
1833 .desc = "break",
1834 .handler = sci_br_interrupt,
1835 },
1836
1837 [SCIx_DRI_IRQ] = {
1838 .desc = "rx ready",
1839 .handler = sci_rx_interrupt,
1840 },
1841
1842 [SCIx_TEI_IRQ] = {
1843 .desc = "tx end",
1844 .handler = sci_tx_interrupt,
1845 },
1846
1847 /*
1848 * Special muxed handler.
1849 */
1850 [SCIx_MUX_IRQ] = {
1851 .desc = "mux",
1852 .handler = sci_mpxed_interrupt,
1853 },
1854 };
1855
sci_request_irq(struct sci_port * port)1856 static int sci_request_irq(struct sci_port *port)
1857 {
1858 struct uart_port *up = &port->port;
1859 int i, j, w, ret = 0;
1860
1861 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1862 const struct sci_irq_desc *desc;
1863 int irq;
1864
1865 /* Check if already registered (muxed) */
1866 for (w = 0; w < i; w++)
1867 if (port->irqs[w] == port->irqs[i])
1868 w = i + 1;
1869 if (w > i)
1870 continue;
1871
1872 if (SCIx_IRQ_IS_MUXED(port)) {
1873 i = SCIx_MUX_IRQ;
1874 irq = up->irq;
1875 } else {
1876 irq = port->irqs[i];
1877
1878 /*
1879 * Certain port types won't support all of the
1880 * available interrupt sources.
1881 */
1882 if (unlikely(irq < 0))
1883 continue;
1884 }
1885
1886 desc = sci_irq_desc + i;
1887 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1888 dev_name(up->dev), desc->desc);
1889 if (!port->irqstr[j]) {
1890 ret = -ENOMEM;
1891 goto out_nomem;
1892 }
1893
1894 ret = request_irq(irq, desc->handler, up->irqflags,
1895 port->irqstr[j], port);
1896 if (unlikely(ret)) {
1897 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1898 goto out_noirq;
1899 }
1900 }
1901
1902 return 0;
1903
1904 out_noirq:
1905 while (--i >= 0)
1906 free_irq(port->irqs[i], port);
1907
1908 out_nomem:
1909 while (--j >= 0)
1910 kfree(port->irqstr[j]);
1911
1912 return ret;
1913 }
1914
sci_free_irq(struct sci_port * port)1915 static void sci_free_irq(struct sci_port *port)
1916 {
1917 int i;
1918
1919 /*
1920 * Intentionally in reverse order so we iterate over the muxed
1921 * IRQ first.
1922 */
1923 for (i = 0; i < SCIx_NR_IRQS; i++) {
1924 int irq = port->irqs[i];
1925
1926 /*
1927 * Certain port types won't support all of the available
1928 * interrupt sources.
1929 */
1930 if (unlikely(irq < 0))
1931 continue;
1932
1933 free_irq(port->irqs[i], port);
1934 kfree(port->irqstr[i]);
1935
1936 if (SCIx_IRQ_IS_MUXED(port)) {
1937 /* If there's only one IRQ, we're done. */
1938 return;
1939 }
1940 }
1941 }
1942
sci_tx_empty(struct uart_port * port)1943 static unsigned int sci_tx_empty(struct uart_port *port)
1944 {
1945 unsigned short status = serial_port_in(port, SCxSR);
1946 unsigned short in_tx_fifo = sci_txfill(port);
1947
1948 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1949 }
1950
sci_set_rts(struct uart_port * port,bool state)1951 static void sci_set_rts(struct uart_port *port, bool state)
1952 {
1953 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1954 u16 data = serial_port_in(port, SCPDR);
1955
1956 /* Active low */
1957 if (state)
1958 data &= ~SCPDR_RTSD;
1959 else
1960 data |= SCPDR_RTSD;
1961 serial_port_out(port, SCPDR, data);
1962
1963 /* RTS# is output */
1964 serial_port_out(port, SCPCR,
1965 serial_port_in(port, SCPCR) | SCPCR_RTSC);
1966 } else if (sci_getreg(port, SCSPTR)->size) {
1967 u16 ctrl = serial_port_in(port, SCSPTR);
1968
1969 /* Active low */
1970 if (state)
1971 ctrl &= ~SCSPTR_RTSDT;
1972 else
1973 ctrl |= SCSPTR_RTSDT;
1974 serial_port_out(port, SCSPTR, ctrl);
1975 }
1976 }
1977
sci_get_cts(struct uart_port * port)1978 static bool sci_get_cts(struct uart_port *port)
1979 {
1980 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1981 /* Active low */
1982 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
1983 } else if (sci_getreg(port, SCSPTR)->size) {
1984 /* Active low */
1985 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
1986 }
1987
1988 return true;
1989 }
1990
1991 /*
1992 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1993 * CTS/RTS is supported in hardware by at least one port and controlled
1994 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1995 * handled via the ->init_pins() op, which is a bit of a one-way street,
1996 * lacking any ability to defer pin control -- this will later be
1997 * converted over to the GPIO framework).
1998 *
1999 * Other modes (such as loopback) are supported generically on certain
2000 * port types, but not others. For these it's sufficient to test for the
2001 * existence of the support register and simply ignore the port type.
2002 */
sci_set_mctrl(struct uart_port * port,unsigned int mctrl)2003 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
2004 {
2005 struct sci_port *s = to_sci_port(port);
2006
2007 if (mctrl & TIOCM_LOOP) {
2008 const struct plat_sci_reg *reg;
2009
2010 /*
2011 * Standard loopback mode for SCFCR ports.
2012 */
2013 reg = sci_getreg(port, SCFCR);
2014 if (reg->size)
2015 serial_port_out(port, SCFCR,
2016 serial_port_in(port, SCFCR) |
2017 SCFCR_LOOP);
2018 }
2019
2020 mctrl_gpio_set(s->gpios, mctrl);
2021
2022 if (!s->has_rtscts)
2023 return;
2024
2025 if (!(mctrl & TIOCM_RTS)) {
2026 /* Disable Auto RTS */
2027 serial_port_out(port, SCFCR,
2028 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
2029
2030 /* Clear RTS */
2031 sci_set_rts(port, 0);
2032 } else if (s->autorts) {
2033 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2034 /* Enable RTS# pin function */
2035 serial_port_out(port, SCPCR,
2036 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
2037 }
2038
2039 /* Enable Auto RTS */
2040 serial_port_out(port, SCFCR,
2041 serial_port_in(port, SCFCR) | SCFCR_MCE);
2042 } else {
2043 /* Set RTS */
2044 sci_set_rts(port, 1);
2045 }
2046 }
2047
sci_get_mctrl(struct uart_port * port)2048 static unsigned int sci_get_mctrl(struct uart_port *port)
2049 {
2050 struct sci_port *s = to_sci_port(port);
2051 struct mctrl_gpios *gpios = s->gpios;
2052 unsigned int mctrl = 0;
2053
2054 mctrl_gpio_get(gpios, &mctrl);
2055
2056 /*
2057 * CTS/RTS is handled in hardware when supported, while nothing
2058 * else is wired up.
2059 */
2060 if (s->autorts) {
2061 if (sci_get_cts(port))
2062 mctrl |= TIOCM_CTS;
2063 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) {
2064 mctrl |= TIOCM_CTS;
2065 }
2066 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
2067 mctrl |= TIOCM_DSR;
2068 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
2069 mctrl |= TIOCM_CAR;
2070
2071 return mctrl;
2072 }
2073
sci_enable_ms(struct uart_port * port)2074 static void sci_enable_ms(struct uart_port *port)
2075 {
2076 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2077 }
2078
sci_break_ctl(struct uart_port * port,int break_state)2079 static void sci_break_ctl(struct uart_port *port, int break_state)
2080 {
2081 unsigned short scscr, scsptr;
2082 unsigned long flags;
2083
2084 /* check wheter the port has SCSPTR */
2085 if (!sci_getreg(port, SCSPTR)->size) {
2086 /*
2087 * Not supported by hardware. Most parts couple break and rx
2088 * interrupts together, with break detection always enabled.
2089 */
2090 return;
2091 }
2092
2093 spin_lock_irqsave(&port->lock, flags);
2094 scsptr = serial_port_in(port, SCSPTR);
2095 scscr = serial_port_in(port, SCSCR);
2096
2097 if (break_state == -1) {
2098 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2099 scscr &= ~SCSCR_TE;
2100 } else {
2101 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2102 scscr |= SCSCR_TE;
2103 }
2104
2105 serial_port_out(port, SCSPTR, scsptr);
2106 serial_port_out(port, SCSCR, scscr);
2107 spin_unlock_irqrestore(&port->lock, flags);
2108 }
2109
sci_startup(struct uart_port * port)2110 static int sci_startup(struct uart_port *port)
2111 {
2112 struct sci_port *s = to_sci_port(port);
2113 int ret;
2114
2115 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2116
2117 sci_request_dma(port);
2118
2119 ret = sci_request_irq(s);
2120 if (unlikely(ret < 0)) {
2121 sci_free_dma(port);
2122 return ret;
2123 }
2124
2125 return 0;
2126 }
2127
sci_shutdown(struct uart_port * port)2128 static void sci_shutdown(struct uart_port *port)
2129 {
2130 struct sci_port *s = to_sci_port(port);
2131 unsigned long flags;
2132 u16 scr;
2133
2134 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2135
2136 s->autorts = false;
2137 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2138
2139 spin_lock_irqsave(&port->lock, flags);
2140 sci_stop_rx(port);
2141 sci_stop_tx(port);
2142 /*
2143 * Stop RX and TX, disable related interrupts, keep clock source
2144 * and HSCIF TOT bits
2145 */
2146 scr = serial_port_in(port, SCSCR);
2147 serial_port_out(port, SCSCR, scr &
2148 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2149 spin_unlock_irqrestore(&port->lock, flags);
2150
2151 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2152 if (s->chan_rx_saved) {
2153 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2154 port->line);
2155 hrtimer_cancel(&s->rx_timer);
2156 }
2157 #endif
2158
2159 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2160 del_timer_sync(&s->rx_fifo_timer);
2161 sci_free_irq(s);
2162 sci_free_dma(port);
2163 }
2164
sci_sck_calc(struct sci_port * s,unsigned int bps,unsigned int * srr)2165 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2166 unsigned int *srr)
2167 {
2168 unsigned long freq = s->clk_rates[SCI_SCK];
2169 int err, min_err = INT_MAX;
2170 unsigned int sr;
2171
2172 if (s->port.type != PORT_HSCIF)
2173 freq *= 2;
2174
2175 for_each_sr(sr, s) {
2176 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2177 if (abs(err) >= abs(min_err))
2178 continue;
2179
2180 min_err = err;
2181 *srr = sr - 1;
2182
2183 if (!err)
2184 break;
2185 }
2186
2187 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2188 *srr + 1);
2189 return min_err;
2190 }
2191
sci_brg_calc(struct sci_port * s,unsigned int bps,unsigned long freq,unsigned int * dlr,unsigned int * srr)2192 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2193 unsigned long freq, unsigned int *dlr,
2194 unsigned int *srr)
2195 {
2196 int err, min_err = INT_MAX;
2197 unsigned int sr, dl;
2198
2199 if (s->port.type != PORT_HSCIF)
2200 freq *= 2;
2201
2202 for_each_sr(sr, s) {
2203 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2204 dl = clamp(dl, 1U, 65535U);
2205
2206 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2207 if (abs(err) >= abs(min_err))
2208 continue;
2209
2210 min_err = err;
2211 *dlr = dl;
2212 *srr = sr - 1;
2213
2214 if (!err)
2215 break;
2216 }
2217
2218 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2219 min_err, *dlr, *srr + 1);
2220 return min_err;
2221 }
2222
2223 /* calculate sample rate, BRR, and clock select */
sci_scbrr_calc(struct sci_port * s,unsigned int bps,unsigned int * brr,unsigned int * srr,unsigned int * cks)2224 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2225 unsigned int *brr, unsigned int *srr,
2226 unsigned int *cks)
2227 {
2228 unsigned long freq = s->clk_rates[SCI_FCK];
2229 unsigned int sr, br, prediv, scrate, c;
2230 int err, min_err = INT_MAX;
2231
2232 if (s->port.type != PORT_HSCIF)
2233 freq *= 2;
2234
2235 /*
2236 * Find the combination of sample rate and clock select with the
2237 * smallest deviation from the desired baud rate.
2238 * Prefer high sample rates to maximise the receive margin.
2239 *
2240 * M: Receive margin (%)
2241 * N: Ratio of bit rate to clock (N = sampling rate)
2242 * D: Clock duty (D = 0 to 1.0)
2243 * L: Frame length (L = 9 to 12)
2244 * F: Absolute value of clock frequency deviation
2245 *
2246 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2247 * (|D - 0.5| / N * (1 + F))|
2248 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2249 */
2250 for_each_sr(sr, s) {
2251 for (c = 0; c <= 3; c++) {
2252 /* integerized formulas from HSCIF documentation */
2253 prediv = sr * (1 << (2 * c + 1));
2254
2255 /*
2256 * We need to calculate:
2257 *
2258 * br = freq / (prediv * bps) clamped to [1..256]
2259 * err = freq / (br * prediv) - bps
2260 *
2261 * Watch out for overflow when calculating the desired
2262 * sampling clock rate!
2263 */
2264 if (bps > UINT_MAX / prediv)
2265 break;
2266
2267 scrate = prediv * bps;
2268 br = DIV_ROUND_CLOSEST(freq, scrate);
2269 br = clamp(br, 1U, 256U);
2270
2271 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2272 if (abs(err) >= abs(min_err))
2273 continue;
2274
2275 min_err = err;
2276 *brr = br - 1;
2277 *srr = sr - 1;
2278 *cks = c;
2279
2280 if (!err)
2281 goto found;
2282 }
2283 }
2284
2285 found:
2286 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2287 min_err, *brr, *srr + 1, *cks);
2288 return min_err;
2289 }
2290
sci_reset(struct uart_port * port)2291 static void sci_reset(struct uart_port *port)
2292 {
2293 const struct plat_sci_reg *reg;
2294 unsigned int status;
2295 struct sci_port *s = to_sci_port(port);
2296
2297 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
2298
2299 reg = sci_getreg(port, SCFCR);
2300 if (reg->size)
2301 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2302
2303 sci_clear_SCxSR(port,
2304 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2305 SCxSR_BREAK_CLEAR(port));
2306 if (sci_getreg(port, SCLSR)->size) {
2307 status = serial_port_in(port, SCLSR);
2308 status &= ~(SCLSR_TO | SCLSR_ORER);
2309 serial_port_out(port, SCLSR, status);
2310 }
2311
2312 if (s->rx_trigger > 1) {
2313 if (s->rx_fifo_timeout) {
2314 scif_set_rtrg(port, 1);
2315 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2316 } else {
2317 if (port->type == PORT_SCIFA ||
2318 port->type == PORT_SCIFB)
2319 scif_set_rtrg(port, 1);
2320 else
2321 scif_set_rtrg(port, s->rx_trigger);
2322 }
2323 }
2324 }
2325
sci_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)2326 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2327 struct ktermios *old)
2328 {
2329 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2330 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2331 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2332 struct sci_port *s = to_sci_port(port);
2333 const struct plat_sci_reg *reg;
2334 int min_err = INT_MAX, err;
2335 unsigned long max_freq = 0;
2336 int best_clk = -1;
2337 unsigned long flags;
2338
2339 if ((termios->c_cflag & CSIZE) == CS7)
2340 smr_val |= SCSMR_CHR;
2341 if (termios->c_cflag & PARENB)
2342 smr_val |= SCSMR_PE;
2343 if (termios->c_cflag & PARODD)
2344 smr_val |= SCSMR_PE | SCSMR_ODD;
2345 if (termios->c_cflag & CSTOPB)
2346 smr_val |= SCSMR_STOP;
2347
2348 /*
2349 * earlyprintk comes here early on with port->uartclk set to zero.
2350 * the clock framework is not up and running at this point so here
2351 * we assume that 115200 is the maximum baud rate. please note that
2352 * the baud rate is not programmed during earlyprintk - it is assumed
2353 * that the previous boot loader has enabled required clocks and
2354 * setup the baud rate generator hardware for us already.
2355 */
2356 if (!port->uartclk) {
2357 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2358 goto done;
2359 }
2360
2361 for (i = 0; i < SCI_NUM_CLKS; i++)
2362 max_freq = max(max_freq, s->clk_rates[i]);
2363
2364 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2365 if (!baud)
2366 goto done;
2367
2368 /*
2369 * There can be multiple sources for the sampling clock. Find the one
2370 * that gives us the smallest deviation from the desired baud rate.
2371 */
2372
2373 /* Optional Undivided External Clock */
2374 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2375 port->type != PORT_SCIFB) {
2376 err = sci_sck_calc(s, baud, &srr1);
2377 if (abs(err) < abs(min_err)) {
2378 best_clk = SCI_SCK;
2379 scr_val = SCSCR_CKE1;
2380 sccks = SCCKS_CKS;
2381 min_err = err;
2382 srr = srr1;
2383 if (!err)
2384 goto done;
2385 }
2386 }
2387
2388 /* Optional BRG Frequency Divided External Clock */
2389 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2390 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2391 &srr1);
2392 if (abs(err) < abs(min_err)) {
2393 best_clk = SCI_SCIF_CLK;
2394 scr_val = SCSCR_CKE1;
2395 sccks = 0;
2396 min_err = err;
2397 dl = dl1;
2398 srr = srr1;
2399 if (!err)
2400 goto done;
2401 }
2402 }
2403
2404 /* Optional BRG Frequency Divided Internal Clock */
2405 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2406 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2407 &srr1);
2408 if (abs(err) < abs(min_err)) {
2409 best_clk = SCI_BRG_INT;
2410 scr_val = SCSCR_CKE1;
2411 sccks = SCCKS_XIN;
2412 min_err = err;
2413 dl = dl1;
2414 srr = srr1;
2415 if (!min_err)
2416 goto done;
2417 }
2418 }
2419
2420 /* Divided Functional Clock using standard Bit Rate Register */
2421 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2422 if (abs(err) < abs(min_err)) {
2423 best_clk = SCI_FCK;
2424 scr_val = 0;
2425 min_err = err;
2426 brr = brr1;
2427 srr = srr1;
2428 cks = cks1;
2429 }
2430
2431 done:
2432 if (best_clk >= 0)
2433 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2434 s->clks[best_clk], baud, min_err);
2435
2436 sci_port_enable(s);
2437
2438 /*
2439 * Program the optional External Baud Rate Generator (BRG) first.
2440 * It controls the mux to select (H)SCK or frequency divided clock.
2441 */
2442 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2443 serial_port_out(port, SCDL, dl);
2444 serial_port_out(port, SCCKS, sccks);
2445 }
2446
2447 spin_lock_irqsave(&port->lock, flags);
2448
2449 sci_reset(port);
2450
2451 uart_update_timeout(port, termios->c_cflag, baud);
2452
2453 /* byte size and parity */
2454 switch (termios->c_cflag & CSIZE) {
2455 case CS5:
2456 bits = 7;
2457 break;
2458 case CS6:
2459 bits = 8;
2460 break;
2461 case CS7:
2462 bits = 9;
2463 break;
2464 default:
2465 bits = 10;
2466 break;
2467 }
2468
2469 if (termios->c_cflag & CSTOPB)
2470 bits++;
2471 if (termios->c_cflag & PARENB)
2472 bits++;
2473
2474 if (best_clk >= 0) {
2475 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2476 switch (srr + 1) {
2477 case 5: smr_val |= SCSMR_SRC_5; break;
2478 case 7: smr_val |= SCSMR_SRC_7; break;
2479 case 11: smr_val |= SCSMR_SRC_11; break;
2480 case 13: smr_val |= SCSMR_SRC_13; break;
2481 case 16: smr_val |= SCSMR_SRC_16; break;
2482 case 17: smr_val |= SCSMR_SRC_17; break;
2483 case 19: smr_val |= SCSMR_SRC_19; break;
2484 case 27: smr_val |= SCSMR_SRC_27; break;
2485 }
2486 smr_val |= cks;
2487 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2488 serial_port_out(port, SCSMR, smr_val);
2489 serial_port_out(port, SCBRR, brr);
2490 if (sci_getreg(port, HSSRR)->size) {
2491 unsigned int hssrr = srr | HSCIF_SRE;
2492 /* Calculate deviation from intended rate at the
2493 * center of the last stop bit in sampling clocks.
2494 */
2495 int last_stop = bits * 2 - 1;
2496 int deviation = min_err * srr * last_stop / 2 / baud;
2497
2498 if (abs(deviation) >= 2) {
2499 /* At least two sampling clocks off at the
2500 * last stop bit; we can increase the error
2501 * margin by shifting the sampling point.
2502 */
2503 int shift = min(-8, max(7, deviation / 2));
2504
2505 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2506 HSCIF_SRHP_MASK;
2507 hssrr |= HSCIF_SRDE;
2508 }
2509 serial_port_out(port, HSSRR, hssrr);
2510 }
2511
2512 /* Wait one bit interval */
2513 udelay((1000000 + (baud - 1)) / baud);
2514 } else {
2515 /* Don't touch the bit rate configuration */
2516 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2517 smr_val |= serial_port_in(port, SCSMR) &
2518 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2519 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2520 serial_port_out(port, SCSMR, smr_val);
2521 }
2522
2523 sci_init_pins(port, termios->c_cflag);
2524
2525 port->status &= ~UPSTAT_AUTOCTS;
2526 s->autorts = false;
2527 reg = sci_getreg(port, SCFCR);
2528 if (reg->size) {
2529 unsigned short ctrl = serial_port_in(port, SCFCR);
2530
2531 if ((port->flags & UPF_HARD_FLOW) &&
2532 (termios->c_cflag & CRTSCTS)) {
2533 /* There is no CTS interrupt to restart the hardware */
2534 port->status |= UPSTAT_AUTOCTS;
2535 /* MCE is enabled when RTS is raised */
2536 s->autorts = true;
2537 }
2538
2539 /*
2540 * As we've done a sci_reset() above, ensure we don't
2541 * interfere with the FIFOs while toggling MCE. As the
2542 * reset values could still be set, simply mask them out.
2543 */
2544 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2545
2546 serial_port_out(port, SCFCR, ctrl);
2547 }
2548 if (port->flags & UPF_HARD_FLOW) {
2549 /* Refresh (Auto) RTS */
2550 sci_set_mctrl(port, port->mctrl);
2551 }
2552
2553 scr_val |= SCSCR_RE | SCSCR_TE |
2554 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2555 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2556 if ((srr + 1 == 5) &&
2557 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2558 /*
2559 * In asynchronous mode, when the sampling rate is 1/5, first
2560 * received data may become invalid on some SCIFA and SCIFB.
2561 * To avoid this problem wait more than 1 serial data time (1
2562 * bit time x serial data number) after setting SCSCR.RE = 1.
2563 */
2564 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2565 }
2566
2567 /*
2568 * Calculate delay for 2 DMA buffers (4 FIFO).
2569 * See serial_core.c::uart_update_timeout().
2570 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2571 * function calculates 1 jiffie for the data plus 5 jiffies for the
2572 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2573 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2574 * value obtained by this formula is too small. Therefore, if the value
2575 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2576 */
2577 s->rx_frame = (10000 * bits) / (baud / 100);
2578 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2579 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2580 if (s->rx_timeout < 20)
2581 s->rx_timeout = 20;
2582 #endif
2583
2584 if ((termios->c_cflag & CREAD) != 0)
2585 sci_start_rx(port);
2586
2587 spin_unlock_irqrestore(&port->lock, flags);
2588
2589 sci_port_disable(s);
2590
2591 if (UART_ENABLE_MS(port, termios->c_cflag))
2592 sci_enable_ms(port);
2593 }
2594
sci_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)2595 static void sci_pm(struct uart_port *port, unsigned int state,
2596 unsigned int oldstate)
2597 {
2598 struct sci_port *sci_port = to_sci_port(port);
2599
2600 switch (state) {
2601 case UART_PM_STATE_OFF:
2602 sci_port_disable(sci_port);
2603 break;
2604 default:
2605 sci_port_enable(sci_port);
2606 break;
2607 }
2608 }
2609
sci_type(struct uart_port * port)2610 static const char *sci_type(struct uart_port *port)
2611 {
2612 switch (port->type) {
2613 case PORT_IRDA:
2614 return "irda";
2615 case PORT_SCI:
2616 return "sci";
2617 case PORT_SCIF:
2618 return "scif";
2619 case PORT_SCIFA:
2620 return "scifa";
2621 case PORT_SCIFB:
2622 return "scifb";
2623 case PORT_HSCIF:
2624 return "hscif";
2625 }
2626
2627 return NULL;
2628 }
2629
sci_remap_port(struct uart_port * port)2630 static int sci_remap_port(struct uart_port *port)
2631 {
2632 struct sci_port *sport = to_sci_port(port);
2633
2634 /*
2635 * Nothing to do if there's already an established membase.
2636 */
2637 if (port->membase)
2638 return 0;
2639
2640 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2641 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2642 if (unlikely(!port->membase)) {
2643 dev_err(port->dev, "can't remap port#%d\n", port->line);
2644 return -ENXIO;
2645 }
2646 } else {
2647 /*
2648 * For the simple (and majority of) cases where we don't
2649 * need to do any remapping, just cast the cookie
2650 * directly.
2651 */
2652 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2653 }
2654
2655 return 0;
2656 }
2657
sci_release_port(struct uart_port * port)2658 static void sci_release_port(struct uart_port *port)
2659 {
2660 struct sci_port *sport = to_sci_port(port);
2661
2662 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2663 iounmap(port->membase);
2664 port->membase = NULL;
2665 }
2666
2667 release_mem_region(port->mapbase, sport->reg_size);
2668 }
2669
sci_request_port(struct uart_port * port)2670 static int sci_request_port(struct uart_port *port)
2671 {
2672 struct resource *res;
2673 struct sci_port *sport = to_sci_port(port);
2674 int ret;
2675
2676 res = request_mem_region(port->mapbase, sport->reg_size,
2677 dev_name(port->dev));
2678 if (unlikely(res == NULL)) {
2679 dev_err(port->dev, "request_mem_region failed.");
2680 return -EBUSY;
2681 }
2682
2683 ret = sci_remap_port(port);
2684 if (unlikely(ret != 0)) {
2685 release_resource(res);
2686 return ret;
2687 }
2688
2689 return 0;
2690 }
2691
sci_config_port(struct uart_port * port,int flags)2692 static void sci_config_port(struct uart_port *port, int flags)
2693 {
2694 if (flags & UART_CONFIG_TYPE) {
2695 struct sci_port *sport = to_sci_port(port);
2696
2697 port->type = sport->cfg->type;
2698 sci_request_port(port);
2699 }
2700 }
2701
sci_verify_port(struct uart_port * port,struct serial_struct * ser)2702 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2703 {
2704 if (ser->baud_base < 2400)
2705 /* No paper tape reader for Mitch.. */
2706 return -EINVAL;
2707
2708 return 0;
2709 }
2710
2711 static const struct uart_ops sci_uart_ops = {
2712 .tx_empty = sci_tx_empty,
2713 .set_mctrl = sci_set_mctrl,
2714 .get_mctrl = sci_get_mctrl,
2715 .start_tx = sci_start_tx,
2716 .stop_tx = sci_stop_tx,
2717 .stop_rx = sci_stop_rx,
2718 .enable_ms = sci_enable_ms,
2719 .break_ctl = sci_break_ctl,
2720 .startup = sci_startup,
2721 .shutdown = sci_shutdown,
2722 .flush_buffer = sci_flush_buffer,
2723 .set_termios = sci_set_termios,
2724 .pm = sci_pm,
2725 .type = sci_type,
2726 .release_port = sci_release_port,
2727 .request_port = sci_request_port,
2728 .config_port = sci_config_port,
2729 .verify_port = sci_verify_port,
2730 #ifdef CONFIG_CONSOLE_POLL
2731 .poll_get_char = sci_poll_get_char,
2732 .poll_put_char = sci_poll_put_char,
2733 #endif
2734 };
2735
sci_init_clocks(struct sci_port * sci_port,struct device * dev)2736 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2737 {
2738 const char *clk_names[] = {
2739 [SCI_FCK] = "fck",
2740 [SCI_SCK] = "sck",
2741 [SCI_BRG_INT] = "brg_int",
2742 [SCI_SCIF_CLK] = "scif_clk",
2743 };
2744 struct clk *clk;
2745 unsigned int i;
2746
2747 if (sci_port->cfg->type == PORT_HSCIF)
2748 clk_names[SCI_SCK] = "hsck";
2749
2750 for (i = 0; i < SCI_NUM_CLKS; i++) {
2751 clk = devm_clk_get(dev, clk_names[i]);
2752 if (PTR_ERR(clk) == -EPROBE_DEFER)
2753 return -EPROBE_DEFER;
2754
2755 if (IS_ERR(clk) && i == SCI_FCK) {
2756 /*
2757 * "fck" used to be called "sci_ick", and we need to
2758 * maintain DT backward compatibility.
2759 */
2760 clk = devm_clk_get(dev, "sci_ick");
2761 if (PTR_ERR(clk) == -EPROBE_DEFER)
2762 return -EPROBE_DEFER;
2763
2764 if (!IS_ERR(clk))
2765 goto found;
2766
2767 /*
2768 * Not all SH platforms declare a clock lookup entry
2769 * for SCI devices, in which case we need to get the
2770 * global "peripheral_clk" clock.
2771 */
2772 clk = devm_clk_get(dev, "peripheral_clk");
2773 if (!IS_ERR(clk))
2774 goto found;
2775
2776 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2777 PTR_ERR(clk));
2778 return PTR_ERR(clk);
2779 }
2780
2781 found:
2782 if (IS_ERR(clk))
2783 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2784 PTR_ERR(clk));
2785 else
2786 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2787 clk, clk_get_rate(clk));
2788 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2789 }
2790 return 0;
2791 }
2792
2793 static const struct sci_port_params *
sci_probe_regmap(const struct plat_sci_port * cfg)2794 sci_probe_regmap(const struct plat_sci_port *cfg)
2795 {
2796 unsigned int regtype;
2797
2798 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2799 return &sci_port_params[cfg->regtype];
2800
2801 switch (cfg->type) {
2802 case PORT_SCI:
2803 regtype = SCIx_SCI_REGTYPE;
2804 break;
2805 case PORT_IRDA:
2806 regtype = SCIx_IRDA_REGTYPE;
2807 break;
2808 case PORT_SCIFA:
2809 regtype = SCIx_SCIFA_REGTYPE;
2810 break;
2811 case PORT_SCIFB:
2812 regtype = SCIx_SCIFB_REGTYPE;
2813 break;
2814 case PORT_SCIF:
2815 /*
2816 * The SH-4 is a bit of a misnomer here, although that's
2817 * where this particular port layout originated. This
2818 * configuration (or some slight variation thereof)
2819 * remains the dominant model for all SCIFs.
2820 */
2821 regtype = SCIx_SH4_SCIF_REGTYPE;
2822 break;
2823 case PORT_HSCIF:
2824 regtype = SCIx_HSCIF_REGTYPE;
2825 break;
2826 default:
2827 pr_err("Can't probe register map for given port\n");
2828 return NULL;
2829 }
2830
2831 return &sci_port_params[regtype];
2832 }
2833
sci_init_single(struct platform_device * dev,struct sci_port * sci_port,unsigned int index,const struct plat_sci_port * p,bool early)2834 static int sci_init_single(struct platform_device *dev,
2835 struct sci_port *sci_port, unsigned int index,
2836 const struct plat_sci_port *p, bool early)
2837 {
2838 struct uart_port *port = &sci_port->port;
2839 const struct resource *res;
2840 unsigned int i;
2841 int ret;
2842
2843 sci_port->cfg = p;
2844
2845 port->ops = &sci_uart_ops;
2846 port->iotype = UPIO_MEM;
2847 port->line = index;
2848
2849 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2850 if (res == NULL)
2851 return -ENOMEM;
2852
2853 port->mapbase = res->start;
2854 sci_port->reg_size = resource_size(res);
2855
2856 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2857 sci_port->irqs[i] = platform_get_irq(dev, i);
2858
2859 /* The SCI generates several interrupts. They can be muxed together or
2860 * connected to different interrupt lines. In the muxed case only one
2861 * interrupt resource is specified as there is only one interrupt ID.
2862 * In the non-muxed case, up to 6 interrupt signals might be generated
2863 * from the SCI, however those signals might have their own individual
2864 * interrupt ID numbers, or muxed together with another interrupt.
2865 */
2866 if (sci_port->irqs[0] < 0)
2867 return -ENXIO;
2868
2869 if (sci_port->irqs[1] < 0)
2870 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
2871 sci_port->irqs[i] = sci_port->irqs[0];
2872
2873 sci_port->params = sci_probe_regmap(p);
2874 if (unlikely(sci_port->params == NULL))
2875 return -EINVAL;
2876
2877 switch (p->type) {
2878 case PORT_SCIFB:
2879 sci_port->rx_trigger = 48;
2880 break;
2881 case PORT_HSCIF:
2882 sci_port->rx_trigger = 64;
2883 break;
2884 case PORT_SCIFA:
2885 sci_port->rx_trigger = 32;
2886 break;
2887 case PORT_SCIF:
2888 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2889 /* RX triggering not implemented for this IP */
2890 sci_port->rx_trigger = 1;
2891 else
2892 sci_port->rx_trigger = 8;
2893 break;
2894 default:
2895 sci_port->rx_trigger = 1;
2896 break;
2897 }
2898
2899 sci_port->rx_fifo_timeout = 0;
2900 sci_port->hscif_tot = 0;
2901
2902 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2903 * match the SoC datasheet, this should be investigated. Let platform
2904 * data override the sampling rate for now.
2905 */
2906 sci_port->sampling_rate_mask = p->sampling_rate
2907 ? SCI_SR(p->sampling_rate)
2908 : sci_port->params->sampling_rate_mask;
2909
2910 if (!early) {
2911 ret = sci_init_clocks(sci_port, &dev->dev);
2912 if (ret < 0)
2913 return ret;
2914
2915 port->dev = &dev->dev;
2916
2917 pm_runtime_enable(&dev->dev);
2918 }
2919
2920 port->type = p->type;
2921 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
2922 port->fifosize = sci_port->params->fifosize;
2923
2924 if (port->type == PORT_SCI) {
2925 if (sci_port->reg_size >= 0x20)
2926 port->regshift = 2;
2927 else
2928 port->regshift = 1;
2929 }
2930
2931 /*
2932 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2933 * for the multi-IRQ ports, which is where we are primarily
2934 * concerned with the shutdown path synchronization.
2935 *
2936 * For the muxed case there's nothing more to do.
2937 */
2938 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2939 port->irqflags = 0;
2940
2941 port->serial_in = sci_serial_in;
2942 port->serial_out = sci_serial_out;
2943
2944 return 0;
2945 }
2946
sci_cleanup_single(struct sci_port * port)2947 static void sci_cleanup_single(struct sci_port *port)
2948 {
2949 pm_runtime_disable(port->port.dev);
2950 }
2951
2952 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2953 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
serial_console_putchar(struct uart_port * port,int ch)2954 static void serial_console_putchar(struct uart_port *port, int ch)
2955 {
2956 sci_poll_put_char(port, ch);
2957 }
2958
2959 /*
2960 * Print a string to the serial port trying not to disturb
2961 * any possible real use of the port...
2962 */
serial_console_write(struct console * co,const char * s,unsigned count)2963 static void serial_console_write(struct console *co, const char *s,
2964 unsigned count)
2965 {
2966 struct sci_port *sci_port = &sci_ports[co->index];
2967 struct uart_port *port = &sci_port->port;
2968 unsigned short bits, ctrl, ctrl_temp;
2969 unsigned long flags;
2970 int locked = 1;
2971
2972 #if defined(SUPPORT_SYSRQ)
2973 if (port->sysrq)
2974 locked = 0;
2975 else
2976 #endif
2977 if (oops_in_progress)
2978 locked = spin_trylock_irqsave(&port->lock, flags);
2979 else
2980 spin_lock_irqsave(&port->lock, flags);
2981
2982 /* first save SCSCR then disable interrupts, keep clock source */
2983 ctrl = serial_port_in(port, SCSCR);
2984 ctrl_temp = SCSCR_RE | SCSCR_TE |
2985 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2986 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
2987 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
2988
2989 uart_console_write(port, s, count, serial_console_putchar);
2990
2991 /* wait until fifo is empty and last bit has been transmitted */
2992 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2993 while ((serial_port_in(port, SCxSR) & bits) != bits)
2994 cpu_relax();
2995
2996 /* restore the SCSCR */
2997 serial_port_out(port, SCSCR, ctrl);
2998
2999 if (locked)
3000 spin_unlock_irqrestore(&port->lock, flags);
3001 }
3002
serial_console_setup(struct console * co,char * options)3003 static int serial_console_setup(struct console *co, char *options)
3004 {
3005 struct sci_port *sci_port;
3006 struct uart_port *port;
3007 int baud = 115200;
3008 int bits = 8;
3009 int parity = 'n';
3010 int flow = 'n';
3011 int ret;
3012
3013 /*
3014 * Refuse to handle any bogus ports.
3015 */
3016 if (co->index < 0 || co->index >= SCI_NPORTS)
3017 return -ENODEV;
3018
3019 sci_port = &sci_ports[co->index];
3020 port = &sci_port->port;
3021
3022 /*
3023 * Refuse to handle uninitialized ports.
3024 */
3025 if (!port->ops)
3026 return -ENODEV;
3027
3028 ret = sci_remap_port(port);
3029 if (unlikely(ret != 0))
3030 return ret;
3031
3032 if (options)
3033 uart_parse_options(options, &baud, &parity, &bits, &flow);
3034
3035 return uart_set_options(port, co, baud, parity, bits, flow);
3036 }
3037
3038 static struct console serial_console = {
3039 .name = "ttySC",
3040 .device = uart_console_device,
3041 .write = serial_console_write,
3042 .setup = serial_console_setup,
3043 .flags = CON_PRINTBUFFER,
3044 .index = -1,
3045 .data = &sci_uart_driver,
3046 };
3047
3048 static struct console early_serial_console = {
3049 .name = "early_ttySC",
3050 .write = serial_console_write,
3051 .flags = CON_PRINTBUFFER,
3052 .index = -1,
3053 };
3054
3055 static char early_serial_buf[32];
3056
sci_probe_earlyprintk(struct platform_device * pdev)3057 static int sci_probe_earlyprintk(struct platform_device *pdev)
3058 {
3059 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
3060
3061 if (early_serial_console.data)
3062 return -EEXIST;
3063
3064 early_serial_console.index = pdev->id;
3065
3066 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
3067
3068 serial_console_setup(&early_serial_console, early_serial_buf);
3069
3070 if (!strstr(early_serial_buf, "keep"))
3071 early_serial_console.flags |= CON_BOOT;
3072
3073 register_console(&early_serial_console);
3074 return 0;
3075 }
3076
3077 #define SCI_CONSOLE (&serial_console)
3078
3079 #else
sci_probe_earlyprintk(struct platform_device * pdev)3080 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3081 {
3082 return -EINVAL;
3083 }
3084
3085 #define SCI_CONSOLE NULL
3086
3087 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
3088
3089 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3090
3091 static DEFINE_MUTEX(sci_uart_registration_lock);
3092 static struct uart_driver sci_uart_driver = {
3093 .owner = THIS_MODULE,
3094 .driver_name = "sci",
3095 .dev_name = "ttySC",
3096 .major = SCI_MAJOR,
3097 .minor = SCI_MINOR_START,
3098 .nr = SCI_NPORTS,
3099 .cons = SCI_CONSOLE,
3100 };
3101
sci_remove(struct platform_device * dev)3102 static int sci_remove(struct platform_device *dev)
3103 {
3104 struct sci_port *port = platform_get_drvdata(dev);
3105
3106 sci_ports_in_use &= ~BIT(port->port.line);
3107 uart_remove_one_port(&sci_uart_driver, &port->port);
3108
3109 sci_cleanup_single(port);
3110
3111 if (port->port.fifosize > 1) {
3112 sysfs_remove_file(&dev->dev.kobj,
3113 &dev_attr_rx_fifo_trigger.attr);
3114 }
3115 if (port->port.type == PORT_SCIFA || port->port.type == PORT_SCIFB ||
3116 port->port.type == PORT_HSCIF) {
3117 sysfs_remove_file(&dev->dev.kobj,
3118 &dev_attr_rx_fifo_timeout.attr);
3119 }
3120
3121 return 0;
3122 }
3123
3124
3125 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3126 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3127 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
3128
3129 static const struct of_device_id of_sci_match[] = {
3130 /* SoC-specific types */
3131 {
3132 .compatible = "renesas,scif-r7s72100",
3133 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3134 },
3135 {
3136 .compatible = "renesas,scif-r7s9210",
3137 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3138 },
3139 /* Family-specific types */
3140 {
3141 .compatible = "renesas,rcar-gen1-scif",
3142 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3143 }, {
3144 .compatible = "renesas,rcar-gen2-scif",
3145 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3146 }, {
3147 .compatible = "renesas,rcar-gen3-scif",
3148 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3149 },
3150 /* Generic types */
3151 {
3152 .compatible = "renesas,scif",
3153 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
3154 }, {
3155 .compatible = "renesas,scifa",
3156 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
3157 }, {
3158 .compatible = "renesas,scifb",
3159 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
3160 }, {
3161 .compatible = "renesas,hscif",
3162 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
3163 }, {
3164 .compatible = "renesas,sci",
3165 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
3166 }, {
3167 /* Terminator */
3168 },
3169 };
3170 MODULE_DEVICE_TABLE(of, of_sci_match);
3171
sci_parse_dt(struct platform_device * pdev,unsigned int * dev_id)3172 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3173 unsigned int *dev_id)
3174 {
3175 struct device_node *np = pdev->dev.of_node;
3176 struct plat_sci_port *p;
3177 struct sci_port *sp;
3178 const void *data;
3179 int id;
3180
3181 if (!IS_ENABLED(CONFIG_OF) || !np)
3182 return NULL;
3183
3184 data = of_device_get_match_data(&pdev->dev);
3185
3186 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3187 if (!p)
3188 return NULL;
3189
3190 /* Get the line number from the aliases node. */
3191 id = of_alias_get_id(np, "serial");
3192 if (id < 0 && ~sci_ports_in_use)
3193 id = ffz(sci_ports_in_use);
3194 if (id < 0) {
3195 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3196 return NULL;
3197 }
3198 if (id >= ARRAY_SIZE(sci_ports)) {
3199 dev_err(&pdev->dev, "serial%d out of range\n", id);
3200 return NULL;
3201 }
3202
3203 sp = &sci_ports[id];
3204 *dev_id = id;
3205
3206 p->type = SCI_OF_TYPE(data);
3207 p->regtype = SCI_OF_REGTYPE(data);
3208
3209 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3210
3211 return p;
3212 }
3213
sci_probe_single(struct platform_device * dev,unsigned int index,struct plat_sci_port * p,struct sci_port * sciport)3214 static int sci_probe_single(struct platform_device *dev,
3215 unsigned int index,
3216 struct plat_sci_port *p,
3217 struct sci_port *sciport)
3218 {
3219 int ret;
3220
3221 /* Sanity check */
3222 if (unlikely(index >= SCI_NPORTS)) {
3223 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3224 index+1, SCI_NPORTS);
3225 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3226 return -EINVAL;
3227 }
3228 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3229 if (sci_ports_in_use & BIT(index))
3230 return -EBUSY;
3231
3232 mutex_lock(&sci_uart_registration_lock);
3233 if (!sci_uart_driver.state) {
3234 ret = uart_register_driver(&sci_uart_driver);
3235 if (ret) {
3236 mutex_unlock(&sci_uart_registration_lock);
3237 return ret;
3238 }
3239 }
3240 mutex_unlock(&sci_uart_registration_lock);
3241
3242 ret = sci_init_single(dev, sciport, index, p, false);
3243 if (ret)
3244 return ret;
3245
3246 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3247 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
3248 return PTR_ERR(sciport->gpios);
3249
3250 if (sciport->has_rtscts) {
3251 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3252 UART_GPIO_CTS)) ||
3253 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3254 UART_GPIO_RTS))) {
3255 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3256 return -EINVAL;
3257 }
3258 sciport->port.flags |= UPF_HARD_FLOW;
3259 }
3260
3261 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3262 if (ret) {
3263 sci_cleanup_single(sciport);
3264 return ret;
3265 }
3266
3267 return 0;
3268 }
3269
sci_probe(struct platform_device * dev)3270 static int sci_probe(struct platform_device *dev)
3271 {
3272 struct plat_sci_port *p;
3273 struct sci_port *sp;
3274 unsigned int dev_id;
3275 int ret;
3276
3277 /*
3278 * If we've come here via earlyprintk initialization, head off to
3279 * the special early probe. We don't have sufficient device state
3280 * to make it beyond this yet.
3281 */
3282 if (is_early_platform_device(dev))
3283 return sci_probe_earlyprintk(dev);
3284
3285 if (dev->dev.of_node) {
3286 p = sci_parse_dt(dev, &dev_id);
3287 if (p == NULL)
3288 return -EINVAL;
3289 } else {
3290 p = dev->dev.platform_data;
3291 if (p == NULL) {
3292 dev_err(&dev->dev, "no platform data supplied\n");
3293 return -EINVAL;
3294 }
3295
3296 dev_id = dev->id;
3297 }
3298
3299 sp = &sci_ports[dev_id];
3300 platform_set_drvdata(dev, sp);
3301
3302 ret = sci_probe_single(dev, dev_id, p, sp);
3303 if (ret)
3304 return ret;
3305
3306 if (sp->port.fifosize > 1) {
3307 ret = sysfs_create_file(&dev->dev.kobj,
3308 &dev_attr_rx_fifo_trigger.attr);
3309 if (ret)
3310 return ret;
3311 }
3312 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3313 sp->port.type == PORT_HSCIF) {
3314 ret = sysfs_create_file(&dev->dev.kobj,
3315 &dev_attr_rx_fifo_timeout.attr);
3316 if (ret) {
3317 if (sp->port.fifosize > 1) {
3318 sysfs_remove_file(&dev->dev.kobj,
3319 &dev_attr_rx_fifo_trigger.attr);
3320 }
3321 return ret;
3322 }
3323 }
3324
3325 #ifdef CONFIG_SH_STANDARD_BIOS
3326 sh_bios_gdb_detach();
3327 #endif
3328
3329 sci_ports_in_use |= BIT(dev_id);
3330 return 0;
3331 }
3332
sci_suspend(struct device * dev)3333 static __maybe_unused int sci_suspend(struct device *dev)
3334 {
3335 struct sci_port *sport = dev_get_drvdata(dev);
3336
3337 if (sport)
3338 uart_suspend_port(&sci_uart_driver, &sport->port);
3339
3340 return 0;
3341 }
3342
sci_resume(struct device * dev)3343 static __maybe_unused int sci_resume(struct device *dev)
3344 {
3345 struct sci_port *sport = dev_get_drvdata(dev);
3346
3347 if (sport)
3348 uart_resume_port(&sci_uart_driver, &sport->port);
3349
3350 return 0;
3351 }
3352
3353 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3354
3355 static struct platform_driver sci_driver = {
3356 .probe = sci_probe,
3357 .remove = sci_remove,
3358 .driver = {
3359 .name = "sh-sci",
3360 .pm = &sci_dev_pm_ops,
3361 .of_match_table = of_match_ptr(of_sci_match),
3362 },
3363 };
3364
sci_init(void)3365 static int __init sci_init(void)
3366 {
3367 pr_info("%s\n", banner);
3368
3369 return platform_driver_register(&sci_driver);
3370 }
3371
sci_exit(void)3372 static void __exit sci_exit(void)
3373 {
3374 platform_driver_unregister(&sci_driver);
3375
3376 if (sci_uart_driver.state)
3377 uart_unregister_driver(&sci_uart_driver);
3378 }
3379
3380 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3381 early_platform_init_buffer("earlyprintk", &sci_driver,
3382 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3383 #endif
3384 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3385 static struct plat_sci_port port_cfg __initdata;
3386
early_console_setup(struct earlycon_device * device,int type)3387 static int __init early_console_setup(struct earlycon_device *device,
3388 int type)
3389 {
3390 if (!device->port.membase)
3391 return -ENODEV;
3392
3393 device->port.serial_in = sci_serial_in;
3394 device->port.serial_out = sci_serial_out;
3395 device->port.type = type;
3396 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3397 port_cfg.type = type;
3398 sci_ports[0].cfg = &port_cfg;
3399 sci_ports[0].params = sci_probe_regmap(&port_cfg);
3400 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3401 sci_serial_out(&sci_ports[0].port, SCSCR,
3402 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3403
3404 device->con->write = serial_console_write;
3405 return 0;
3406 }
sci_early_console_setup(struct earlycon_device * device,const char * opt)3407 static int __init sci_early_console_setup(struct earlycon_device *device,
3408 const char *opt)
3409 {
3410 return early_console_setup(device, PORT_SCI);
3411 }
scif_early_console_setup(struct earlycon_device * device,const char * opt)3412 static int __init scif_early_console_setup(struct earlycon_device *device,
3413 const char *opt)
3414 {
3415 return early_console_setup(device, PORT_SCIF);
3416 }
scifa_early_console_setup(struct earlycon_device * device,const char * opt)3417 static int __init scifa_early_console_setup(struct earlycon_device *device,
3418 const char *opt)
3419 {
3420 return early_console_setup(device, PORT_SCIFA);
3421 }
scifb_early_console_setup(struct earlycon_device * device,const char * opt)3422 static int __init scifb_early_console_setup(struct earlycon_device *device,
3423 const char *opt)
3424 {
3425 return early_console_setup(device, PORT_SCIFB);
3426 }
hscif_early_console_setup(struct earlycon_device * device,const char * opt)3427 static int __init hscif_early_console_setup(struct earlycon_device *device,
3428 const char *opt)
3429 {
3430 return early_console_setup(device, PORT_HSCIF);
3431 }
3432
3433 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3434 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3435 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3436 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3437 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3438 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3439
3440 module_init(sci_init);
3441 module_exit(sci_exit);
3442
3443 MODULE_LICENSE("GPL");
3444 MODULE_ALIAS("platform:sh-sci");
3445 MODULE_AUTHOR("Paul Mundt");
3446 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
3447
