1 /*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include "en.h"
34
35 /* mlx5e global resources should be placed in this file.
36 * Global resources are common to all the netdevices created on the same nic.
37 */
38
mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev * mdev,void * mkc)39 void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc)
40 {
41 bool ro_pci_enable = pcie_relaxed_ordering_enabled(mdev->pdev);
42 bool ro_write = MLX5_CAP_GEN(mdev, relaxed_ordering_write);
43 bool ro_read = MLX5_CAP_GEN(mdev, relaxed_ordering_read);
44
45 MLX5_SET(mkc, mkc, relaxed_ordering_read, ro_pci_enable && ro_read);
46 MLX5_SET(mkc, mkc, relaxed_ordering_write, ro_pci_enable && ro_write);
47 }
48
mlx5e_create_mkey(struct mlx5_core_dev * mdev,u32 pdn,struct mlx5_core_mkey * mkey)49 static int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn,
50 struct mlx5_core_mkey *mkey)
51 {
52 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
53 void *mkc;
54 u32 *in;
55 int err;
56
57 in = kvzalloc(inlen, GFP_KERNEL);
58 if (!in)
59 return -ENOMEM;
60
61 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
62 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_PA);
63 MLX5_SET(mkc, mkc, lw, 1);
64 MLX5_SET(mkc, mkc, lr, 1);
65 mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
66 MLX5_SET(mkc, mkc, pd, pdn);
67 MLX5_SET(mkc, mkc, length64, 1);
68 MLX5_SET(mkc, mkc, qpn, 0xffffff);
69
70 err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
71
72 kvfree(in);
73 return err;
74 }
75
mlx5e_create_mdev_resources(struct mlx5_core_dev * mdev)76 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev)
77 {
78 struct mlx5e_hw_objs *res = &mdev->mlx5e_res.hw_objs;
79 int err;
80
81 err = mlx5_core_alloc_pd(mdev, &res->pdn);
82 if (err) {
83 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
84 return err;
85 }
86
87 err = mlx5_core_alloc_transport_domain(mdev, &res->td.tdn);
88 if (err) {
89 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
90 goto err_dealloc_pd;
91 }
92
93 err = mlx5e_create_mkey(mdev, res->pdn, &res->mkey);
94 if (err) {
95 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
96 goto err_dealloc_transport_domain;
97 }
98
99 err = mlx5_alloc_bfreg(mdev, &res->bfreg, false, false);
100 if (err) {
101 mlx5_core_err(mdev, "alloc bfreg failed, %d\n", err);
102 goto err_destroy_mkey;
103 }
104
105 INIT_LIST_HEAD(&res->td.tirs_list);
106 mutex_init(&res->td.list_lock);
107
108 return 0;
109
110 err_destroy_mkey:
111 mlx5_core_destroy_mkey(mdev, &res->mkey);
112 err_dealloc_transport_domain:
113 mlx5_core_dealloc_transport_domain(mdev, res->td.tdn);
114 err_dealloc_pd:
115 mlx5_core_dealloc_pd(mdev, res->pdn);
116 return err;
117 }
118
mlx5e_destroy_mdev_resources(struct mlx5_core_dev * mdev)119 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev)
120 {
121 struct mlx5e_hw_objs *res = &mdev->mlx5e_res.hw_objs;
122
123 mlx5_free_bfreg(mdev, &res->bfreg);
124 mlx5_core_destroy_mkey(mdev, &res->mkey);
125 mlx5_core_dealloc_transport_domain(mdev, res->td.tdn);
126 mlx5_core_dealloc_pd(mdev, res->pdn);
127 memset(res, 0, sizeof(*res));
128 }
129
mlx5e_refresh_tirs(struct mlx5e_priv * priv,bool enable_uc_lb,bool enable_mc_lb)130 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb,
131 bool enable_mc_lb)
132 {
133 struct mlx5_core_dev *mdev = priv->mdev;
134 struct mlx5e_tir *tir;
135 u8 lb_flags = 0;
136 int err = 0;
137 u32 tirn = 0;
138 int inlen;
139 void *in;
140
141 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
142 in = kvzalloc(inlen, GFP_KERNEL);
143 if (!in) {
144 err = -ENOMEM;
145 goto out;
146 }
147
148 if (enable_uc_lb)
149 lb_flags = MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
150
151 if (enable_mc_lb)
152 lb_flags |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
153
154 if (lb_flags)
155 MLX5_SET(modify_tir_in, in, ctx.self_lb_block, lb_flags);
156
157 MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
158
159 mutex_lock(&mdev->mlx5e_res.hw_objs.td.list_lock);
160 list_for_each_entry(tir, &mdev->mlx5e_res.hw_objs.td.tirs_list, list) {
161 tirn = tir->tirn;
162 err = mlx5_core_modify_tir(mdev, tirn, in);
163 if (err)
164 goto out;
165 }
166
167 out:
168 kvfree(in);
169 if (err)
170 netdev_err(priv->netdev, "refresh tir(0x%x) failed, %d\n", tirn, err);
171 mutex_unlock(&mdev->mlx5e_res.hw_objs.td.list_lock);
172
173 return err;
174 }
175
