1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2013 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11 #ifndef EFX_IO_H
12 #define EFX_IO_H
13
14 #include <linux/io.h>
15 #include <linux/spinlock.h>
16
17 /**************************************************************************
18 *
19 * NIC register I/O
20 *
21 **************************************************************************
22 *
23 * Notes on locking strategy for the Falcon architecture:
24 *
25 * Many CSRs are very wide and cannot be read or written atomically.
26 * Writes from the host are buffered by the Bus Interface Unit (BIU)
27 * up to 128 bits. Whenever the host writes part of such a register,
28 * the BIU collects the written value and does not write to the
29 * underlying register until all 4 dwords have been written. A
30 * similar buffering scheme applies to host access to the NIC's 64-bit
31 * SRAM.
32 *
33 * Writes to different CSRs and 64-bit SRAM words must be serialised,
34 * since interleaved access can result in lost writes. We use
35 * efx_nic::biu_lock for this.
36 *
37 * We also serialise reads from 128-bit CSRs and SRAM with the same
38 * spinlock. This may not be necessary, but it doesn't really matter
39 * as there are no such reads on the fast path.
40 *
41 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
42 * 128-bit but are special-cased in the BIU to avoid the need for
43 * locking in the host:
44 *
45 * - They are write-only.
46 * - The semantics of writing to these registers are such that
47 * replacing the low 96 bits with zero does not affect functionality.
48 * - If the host writes to the last dword address of such a register
49 * (i.e. the high 32 bits) the underlying register will always be
50 * written. If the collector and the current write together do not
51 * provide values for all 128 bits of the register, the low 96 bits
52 * will be written as zero.
53 * - If the host writes to the address of any other part of such a
54 * register while the collector already holds values for some other
55 * register, the write is discarded and the collector maintains its
56 * current state.
57 *
58 * The EF10 architecture exposes very few registers to the host and
59 * most of them are only 32 bits wide. The only exceptions are the MC
60 * doorbell register pair, which has its own latching, and
61 * TX_DESC_UPD, which works in a similar way to the Falcon
62 * architecture.
63 */
64
65 #if BITS_PER_LONG == 64
66 #define EFX_USE_QWORD_IO 1
67 #endif
68
69 /* Hardware issue requires that only 64-bit naturally aligned writes
70 * are seen by hardware. Its not strictly necessary to restrict to
71 * x86_64 arch, but done for safety since unusual write combining behaviour
72 * can break PIO.
73 */
74 #ifdef CONFIG_X86_64
75 /* PIO is a win only if write-combining is possible */
76 #ifdef ARCH_HAS_IOREMAP_WC
77 #define EFX_USE_PIO 1
78 #endif
79 #endif
80
81 #ifdef EFX_USE_QWORD_IO
_efx_writeq(struct efx_nic * efx,__le64 value,unsigned int reg)82 static inline void _efx_writeq(struct efx_nic *efx, __le64 value,
83 unsigned int reg)
84 {
85 __raw_writeq((__force u64)value, efx->membase + reg);
86 }
_efx_readq(struct efx_nic * efx,unsigned int reg)87 static inline __le64 _efx_readq(struct efx_nic *efx, unsigned int reg)
88 {
89 return (__force __le64)__raw_readq(efx->membase + reg);
90 }
91 #endif
92
_efx_writed(struct efx_nic * efx,__le32 value,unsigned int reg)93 static inline void _efx_writed(struct efx_nic *efx, __le32 value,
94 unsigned int reg)
95 {
96 __raw_writel((__force u32)value, efx->membase + reg);
97 }
_efx_readd(struct efx_nic * efx,unsigned int reg)98 static inline __le32 _efx_readd(struct efx_nic *efx, unsigned int reg)
99 {
100 return (__force __le32)__raw_readl(efx->membase + reg);
101 }
102
103 /* Write a normal 128-bit CSR, locking as appropriate. */
efx_writeo(struct efx_nic * efx,const efx_oword_t * value,unsigned int reg)104 static inline void efx_writeo(struct efx_nic *efx, const efx_oword_t *value,
105 unsigned int reg)
106 {
107 unsigned long flags __attribute__ ((unused));
108
109 netif_vdbg(efx, hw, efx->net_dev,
110 "writing register %x with " EFX_OWORD_FMT "\n", reg,
111 EFX_OWORD_VAL(*value));
112
113 spin_lock_irqsave(&efx->biu_lock, flags);
114 #ifdef EFX_USE_QWORD_IO
115 _efx_writeq(efx, value->u64[0], reg + 0);
116 _efx_writeq(efx, value->u64[1], reg + 8);
117 #else
118 _efx_writed(efx, value->u32[0], reg + 0);
119 _efx_writed(efx, value->u32[1], reg + 4);
120 _efx_writed(efx, value->u32[2], reg + 8);
121 _efx_writed(efx, value->u32[3], reg + 12);
122 #endif
123 mmiowb();
124 spin_unlock_irqrestore(&efx->biu_lock, flags);
125 }
126
127 /* Write 64-bit SRAM through the supplied mapping, locking as appropriate. */
efx_sram_writeq(struct efx_nic * efx,void __iomem * membase,const efx_qword_t * value,unsigned int index)128 static inline void efx_sram_writeq(struct efx_nic *efx, void __iomem *membase,
129 const efx_qword_t *value, unsigned int index)
130 {
131 unsigned int addr = index * sizeof(*value);
132 unsigned long flags __attribute__ ((unused));
133
134 netif_vdbg(efx, hw, efx->net_dev,
135 "writing SRAM address %x with " EFX_QWORD_FMT "\n",
136 addr, EFX_QWORD_VAL(*value));
137
138 spin_lock_irqsave(&efx->biu_lock, flags);
139 #ifdef EFX_USE_QWORD_IO
140 __raw_writeq((__force u64)value->u64[0], membase + addr);
141 #else
142 __raw_writel((__force u32)value->u32[0], membase + addr);
143 __raw_writel((__force u32)value->u32[1], membase + addr + 4);
144 #endif
145 mmiowb();
146 spin_unlock_irqrestore(&efx->biu_lock, flags);
147 }
148
149 /* Write a 32-bit CSR or the last dword of a special 128-bit CSR */
efx_writed(struct efx_nic * efx,const efx_dword_t * value,unsigned int reg)150 static inline void efx_writed(struct efx_nic *efx, const efx_dword_t *value,
151 unsigned int reg)
152 {
153 netif_vdbg(efx, hw, efx->net_dev,
154 "writing register %x with "EFX_DWORD_FMT"\n",
155 reg, EFX_DWORD_VAL(*value));
156
157 /* No lock required */
158 _efx_writed(efx, value->u32[0], reg);
159 }
160
161 /* Read a 128-bit CSR, locking as appropriate. */
efx_reado(struct efx_nic * efx,efx_oword_t * value,unsigned int reg)162 static inline void efx_reado(struct efx_nic *efx, efx_oword_t *value,
163 unsigned int reg)
164 {
165 unsigned long flags __attribute__ ((unused));
166
167 spin_lock_irqsave(&efx->biu_lock, flags);
168 value->u32[0] = _efx_readd(efx, reg + 0);
169 value->u32[1] = _efx_readd(efx, reg + 4);
170 value->u32[2] = _efx_readd(efx, reg + 8);
171 value->u32[3] = _efx_readd(efx, reg + 12);
172 spin_unlock_irqrestore(&efx->biu_lock, flags);
173
174 netif_vdbg(efx, hw, efx->net_dev,
175 "read from register %x, got " EFX_OWORD_FMT "\n", reg,
176 EFX_OWORD_VAL(*value));
177 }
178
179 /* Read 64-bit SRAM through the supplied mapping, locking as appropriate. */
efx_sram_readq(struct efx_nic * efx,void __iomem * membase,efx_qword_t * value,unsigned int index)180 static inline void efx_sram_readq(struct efx_nic *efx, void __iomem *membase,
181 efx_qword_t *value, unsigned int index)
182 {
183 unsigned int addr = index * sizeof(*value);
184 unsigned long flags __attribute__ ((unused));
185
186 spin_lock_irqsave(&efx->biu_lock, flags);
187 #ifdef EFX_USE_QWORD_IO
188 value->u64[0] = (__force __le64)__raw_readq(membase + addr);
189 #else
190 value->u32[0] = (__force __le32)__raw_readl(membase + addr);
191 value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4);
192 #endif
193 spin_unlock_irqrestore(&efx->biu_lock, flags);
194
195 netif_vdbg(efx, hw, efx->net_dev,
196 "read from SRAM address %x, got "EFX_QWORD_FMT"\n",
197 addr, EFX_QWORD_VAL(*value));
198 }
199
200 /* Read a 32-bit CSR or SRAM */
efx_readd(struct efx_nic * efx,efx_dword_t * value,unsigned int reg)201 static inline void efx_readd(struct efx_nic *efx, efx_dword_t *value,
202 unsigned int reg)
203 {
204 value->u32[0] = _efx_readd(efx, reg);
205 netif_vdbg(efx, hw, efx->net_dev,
206 "read from register %x, got "EFX_DWORD_FMT"\n",
207 reg, EFX_DWORD_VAL(*value));
208 }
209
210 /* Write a 128-bit CSR forming part of a table */
211 static inline void
efx_writeo_table(struct efx_nic * efx,const efx_oword_t * value,unsigned int reg,unsigned int index)212 efx_writeo_table(struct efx_nic *efx, const efx_oword_t *value,
213 unsigned int reg, unsigned int index)
214 {
215 efx_writeo(efx, value, reg + index * sizeof(efx_oword_t));
216 }
217
218 /* Read a 128-bit CSR forming part of a table */
efx_reado_table(struct efx_nic * efx,efx_oword_t * value,unsigned int reg,unsigned int index)219 static inline void efx_reado_table(struct efx_nic *efx, efx_oword_t *value,
220 unsigned int reg, unsigned int index)
221 {
222 efx_reado(efx, value, reg + index * sizeof(efx_oword_t));
223 }
224
225 /* default VI stride (step between per-VI registers) is 8K */
226 #define EFX_DEFAULT_VI_STRIDE 0x2000
227
228 /* Calculate offset to page-mapped register */
efx_paged_reg(struct efx_nic * efx,unsigned int page,unsigned int reg)229 static inline unsigned int efx_paged_reg(struct efx_nic *efx, unsigned int page,
230 unsigned int reg)
231 {
232 return page * efx->vi_stride + reg;
233 }
234
235 /* Write the whole of RX_DESC_UPD or TX_DESC_UPD */
_efx_writeo_page(struct efx_nic * efx,efx_oword_t * value,unsigned int reg,unsigned int page)236 static inline void _efx_writeo_page(struct efx_nic *efx, efx_oword_t *value,
237 unsigned int reg, unsigned int page)
238 {
239 reg = efx_paged_reg(efx, page, reg);
240
241 netif_vdbg(efx, hw, efx->net_dev,
242 "writing register %x with " EFX_OWORD_FMT "\n", reg,
243 EFX_OWORD_VAL(*value));
244
245 #ifdef EFX_USE_QWORD_IO
246 _efx_writeq(efx, value->u64[0], reg + 0);
247 _efx_writeq(efx, value->u64[1], reg + 8);
248 #else
249 _efx_writed(efx, value->u32[0], reg + 0);
250 _efx_writed(efx, value->u32[1], reg + 4);
251 _efx_writed(efx, value->u32[2], reg + 8);
252 _efx_writed(efx, value->u32[3], reg + 12);
253 #endif
254 }
255 #define efx_writeo_page(efx, value, reg, page) \
256 _efx_writeo_page(efx, value, \
257 reg + \
258 BUILD_BUG_ON_ZERO((reg) != 0x830 && (reg) != 0xa10), \
259 page)
260
261 /* Write a page-mapped 32-bit CSR (EVQ_RPTR, EVQ_TMR (EF10), or the
262 * high bits of RX_DESC_UPD or TX_DESC_UPD)
263 */
264 static inline void
_efx_writed_page(struct efx_nic * efx,const efx_dword_t * value,unsigned int reg,unsigned int page)265 _efx_writed_page(struct efx_nic *efx, const efx_dword_t *value,
266 unsigned int reg, unsigned int page)
267 {
268 efx_writed(efx, value, efx_paged_reg(efx, page, reg));
269 }
270 #define efx_writed_page(efx, value, reg, page) \
271 _efx_writed_page(efx, value, \
272 reg + \
273 BUILD_BUG_ON_ZERO((reg) != 0x400 && \
274 (reg) != 0x420 && \
275 (reg) != 0x830 && \
276 (reg) != 0x83c && \
277 (reg) != 0xa18 && \
278 (reg) != 0xa1c), \
279 page)
280
281 /* Write TIMER_COMMAND. This is a page-mapped 32-bit CSR, but a bug
282 * in the BIU means that writes to TIMER_COMMAND[0] invalidate the
283 * collector register.
284 */
_efx_writed_page_locked(struct efx_nic * efx,const efx_dword_t * value,unsigned int reg,unsigned int page)285 static inline void _efx_writed_page_locked(struct efx_nic *efx,
286 const efx_dword_t *value,
287 unsigned int reg,
288 unsigned int page)
289 {
290 unsigned long flags __attribute__ ((unused));
291
292 if (page == 0) {
293 spin_lock_irqsave(&efx->biu_lock, flags);
294 efx_writed(efx, value, efx_paged_reg(efx, page, reg));
295 spin_unlock_irqrestore(&efx->biu_lock, flags);
296 } else {
297 efx_writed(efx, value, efx_paged_reg(efx, page, reg));
298 }
299 }
300 #define efx_writed_page_locked(efx, value, reg, page) \
301 _efx_writed_page_locked(efx, value, \
302 reg + BUILD_BUG_ON_ZERO((reg) != 0x420), \
303 page)
304
305 #endif /* EFX_IO_H */
306
