1 /*
2 * The file intends to implement PE based on the information from
3 * platforms. Basically, there have 3 types of PEs: PHB/Bus/Device.
4 * All the PEs should be organized as hierarchy tree. The first level
5 * of the tree will be associated to existing PHBs since the particular
6 * PE is only meaningful in one PHB domain.
7 *
8 * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2012.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24
25 #include <linux/delay.h>
26 #include <linux/export.h>
27 #include <linux/gfp.h>
28 #include <linux/kernel.h>
29 #include <linux/pci.h>
30 #include <linux/string.h>
31
32 #include <asm/pci-bridge.h>
33 #include <asm/ppc-pci.h>
34
35 static int eeh_pe_aux_size = 0;
36 static LIST_HEAD(eeh_phb_pe);
37
38 /**
39 * eeh_set_pe_aux_size - Set PE auxillary data size
40 * @size: PE auxillary data size
41 *
42 * Set PE auxillary data size
43 */
eeh_set_pe_aux_size(int size)44 void eeh_set_pe_aux_size(int size)
45 {
46 if (size < 0)
47 return;
48
49 eeh_pe_aux_size = size;
50 }
51
52 /**
53 * eeh_pe_alloc - Allocate PE
54 * @phb: PCI controller
55 * @type: PE type
56 *
57 * Allocate PE instance dynamically.
58 */
eeh_pe_alloc(struct pci_controller * phb,int type)59 static struct eeh_pe *eeh_pe_alloc(struct pci_controller *phb, int type)
60 {
61 struct eeh_pe *pe;
62 size_t alloc_size;
63
64 alloc_size = sizeof(struct eeh_pe);
65 if (eeh_pe_aux_size) {
66 alloc_size = ALIGN(alloc_size, cache_line_size());
67 alloc_size += eeh_pe_aux_size;
68 }
69
70 /* Allocate PHB PE */
71 pe = kzalloc(alloc_size, GFP_KERNEL);
72 if (!pe) return NULL;
73
74 /* Initialize PHB PE */
75 pe->type = type;
76 pe->phb = phb;
77 INIT_LIST_HEAD(&pe->child_list);
78 INIT_LIST_HEAD(&pe->child);
79 INIT_LIST_HEAD(&pe->edevs);
80
81 pe->data = (void *)pe + ALIGN(sizeof(struct eeh_pe),
82 cache_line_size());
83 return pe;
84 }
85
86 /**
87 * eeh_phb_pe_create - Create PHB PE
88 * @phb: PCI controller
89 *
90 * The function should be called while the PHB is detected during
91 * system boot or PCI hotplug in order to create PHB PE.
92 */
eeh_phb_pe_create(struct pci_controller * phb)93 int eeh_phb_pe_create(struct pci_controller *phb)
94 {
95 struct eeh_pe *pe;
96
97 /* Allocate PHB PE */
98 pe = eeh_pe_alloc(phb, EEH_PE_PHB);
99 if (!pe) {
100 pr_err("%s: out of memory!\n", __func__);
101 return -ENOMEM;
102 }
103
104 /* Put it into the list */
105 list_add_tail(&pe->child, &eeh_phb_pe);
106
107 pr_debug("EEH: Add PE for PHB#%x\n", phb->global_number);
108
109 return 0;
110 }
111
112 /**
113 * eeh_phb_pe_get - Retrieve PHB PE based on the given PHB
114 * @phb: PCI controller
115 *
116 * The overall PEs form hierarchy tree. The first layer of the
117 * hierarchy tree is composed of PHB PEs. The function is used
118 * to retrieve the corresponding PHB PE according to the given PHB.
119 */
eeh_phb_pe_get(struct pci_controller * phb)120 struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb)
121 {
122 struct eeh_pe *pe;
123
124 list_for_each_entry(pe, &eeh_phb_pe, child) {
125 /*
126 * Actually, we needn't check the type since
127 * the PE for PHB has been determined when that
128 * was created.
129 */
130 if ((pe->type & EEH_PE_PHB) && pe->phb == phb)
131 return pe;
132 }
133
134 return NULL;
135 }
136
137 /**
138 * eeh_pe_next - Retrieve the next PE in the tree
139 * @pe: current PE
140 * @root: root PE
141 *
142 * The function is used to retrieve the next PE in the
143 * hierarchy PE tree.
144 */
eeh_pe_next(struct eeh_pe * pe,struct eeh_pe * root)145 struct eeh_pe *eeh_pe_next(struct eeh_pe *pe, struct eeh_pe *root)
146 {
147 struct list_head *next = pe->child_list.next;
148
149 if (next == &pe->child_list) {
150 while (1) {
151 if (pe == root)
152 return NULL;
153 next = pe->child.next;
154 if (next != &pe->parent->child_list)
155 break;
156 pe = pe->parent;
157 }
158 }
159
160 return list_entry(next, struct eeh_pe, child);
161 }
162
163 /**
164 * eeh_pe_traverse - Traverse PEs in the specified PHB
165 * @root: root PE
166 * @fn: callback
167 * @flag: extra parameter to callback
168 *
169 * The function is used to traverse the specified PE and its
170 * child PEs. The traversing is to be terminated once the
171 * callback returns something other than NULL, or no more PEs
172 * to be traversed.
173 */
eeh_pe_traverse(struct eeh_pe * root,eeh_pe_traverse_func fn,void * flag)174 void *eeh_pe_traverse(struct eeh_pe *root,
175 eeh_pe_traverse_func fn, void *flag)
176 {
177 struct eeh_pe *pe;
178 void *ret;
179
180 eeh_for_each_pe(root, pe) {
181 ret = fn(pe, flag);
182 if (ret) return ret;
183 }
184
185 return NULL;
186 }
187
188 /**
189 * eeh_pe_dev_traverse - Traverse the devices from the PE
190 * @root: EEH PE
191 * @fn: function callback
192 * @flag: extra parameter to callback
193 *
194 * The function is used to traverse the devices of the specified
195 * PE and its child PEs.
196 */
eeh_pe_dev_traverse(struct eeh_pe * root,eeh_edev_traverse_func fn,void * flag)197 void *eeh_pe_dev_traverse(struct eeh_pe *root,
198 eeh_edev_traverse_func fn, void *flag)
199 {
200 struct eeh_pe *pe;
201 struct eeh_dev *edev, *tmp;
202 void *ret;
203
204 if (!root) {
205 pr_warn("%s: Invalid PE %p\n",
206 __func__, root);
207 return NULL;
208 }
209
210 /* Traverse root PE */
211 eeh_for_each_pe(root, pe) {
212 eeh_pe_for_each_dev(pe, edev, tmp) {
213 ret = fn(edev, flag);
214 if (ret)
215 return ret;
216 }
217 }
218
219 return NULL;
220 }
221
222 /**
223 * __eeh_pe_get - Check the PE address
224 * @data: EEH PE
225 * @flag: EEH device
226 *
227 * For one particular PE, it can be identified by PE address
228 * or tranditional BDF address. BDF address is composed of
229 * Bus/Device/Function number. The extra data referred by flag
230 * indicates which type of address should be used.
231 */
232 struct eeh_pe_get_flag {
233 int pe_no;
234 int config_addr;
235 };
236
__eeh_pe_get(struct eeh_pe * pe,void * flag)237 static void *__eeh_pe_get(struct eeh_pe *pe, void *flag)
238 {
239 struct eeh_pe_get_flag *tmp = (struct eeh_pe_get_flag *) flag;
240
241 /* Unexpected PHB PE */
242 if (pe->type & EEH_PE_PHB)
243 return NULL;
244
245 /*
246 * We prefer PE address. For most cases, we should
247 * have non-zero PE address
248 */
249 if (eeh_has_flag(EEH_VALID_PE_ZERO)) {
250 if (tmp->pe_no == pe->addr)
251 return pe;
252 } else {
253 if (tmp->pe_no &&
254 (tmp->pe_no == pe->addr))
255 return pe;
256 }
257
258 /* Try BDF address */
259 if (tmp->config_addr &&
260 (tmp->config_addr == pe->config_addr))
261 return pe;
262
263 return NULL;
264 }
265
266 /**
267 * eeh_pe_get - Search PE based on the given address
268 * @phb: PCI controller
269 * @pe_no: PE number
270 * @config_addr: Config address
271 *
272 * Search the corresponding PE based on the specified address which
273 * is included in the eeh device. The function is used to check if
274 * the associated PE has been created against the PE address. It's
275 * notable that the PE address has 2 format: traditional PE address
276 * which is composed of PCI bus/device/function number, or unified
277 * PE address.
278 */
eeh_pe_get(struct pci_controller * phb,int pe_no,int config_addr)279 struct eeh_pe *eeh_pe_get(struct pci_controller *phb,
280 int pe_no, int config_addr)
281 {
282 struct eeh_pe *root = eeh_phb_pe_get(phb);
283 struct eeh_pe_get_flag tmp = { pe_no, config_addr };
284 struct eeh_pe *pe;
285
286 pe = eeh_pe_traverse(root, __eeh_pe_get, &tmp);
287
288 return pe;
289 }
290
291 /**
292 * eeh_pe_get_parent - Retrieve the parent PE
293 * @edev: EEH device
294 *
295 * The whole PEs existing in the system are organized as hierarchy
296 * tree. The function is used to retrieve the parent PE according
297 * to the parent EEH device.
298 */
eeh_pe_get_parent(struct eeh_dev * edev)299 static struct eeh_pe *eeh_pe_get_parent(struct eeh_dev *edev)
300 {
301 struct eeh_dev *parent;
302 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
303
304 /*
305 * It might have the case for the indirect parent
306 * EEH device already having associated PE, but
307 * the direct parent EEH device doesn't have yet.
308 */
309 if (edev->physfn)
310 pdn = pci_get_pdn(edev->physfn);
311 else
312 pdn = pdn ? pdn->parent : NULL;
313 while (pdn) {
314 /* We're poking out of PCI territory */
315 parent = pdn_to_eeh_dev(pdn);
316 if (!parent)
317 return NULL;
318
319 if (parent->pe)
320 return parent->pe;
321
322 pdn = pdn->parent;
323 }
324
325 return NULL;
326 }
327
328 /**
329 * eeh_add_to_parent_pe - Add EEH device to parent PE
330 * @edev: EEH device
331 *
332 * Add EEH device to the parent PE. If the parent PE already
333 * exists, the PE type will be changed to EEH_PE_BUS. Otherwise,
334 * we have to create new PE to hold the EEH device and the new
335 * PE will be linked to its parent PE as well.
336 */
eeh_add_to_parent_pe(struct eeh_dev * edev)337 int eeh_add_to_parent_pe(struct eeh_dev *edev)
338 {
339 struct eeh_pe *pe, *parent;
340 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
341 int config_addr = (pdn->busno << 8) | (pdn->devfn);
342
343 /* Check if the PE number is valid */
344 if (!eeh_has_flag(EEH_VALID_PE_ZERO) && !edev->pe_config_addr) {
345 pr_err("%s: Invalid PE#0 for edev 0x%x on PHB#%x\n",
346 __func__, config_addr, pdn->phb->global_number);
347 return -EINVAL;
348 }
349
350 /*
351 * Search the PE has been existing or not according
352 * to the PE address. If that has been existing, the
353 * PE should be composed of PCI bus and its subordinate
354 * components.
355 */
356 pe = eeh_pe_get(pdn->phb, edev->pe_config_addr, config_addr);
357 if (pe && !(pe->type & EEH_PE_INVALID)) {
358 /* Mark the PE as type of PCI bus */
359 pe->type = EEH_PE_BUS;
360 edev->pe = pe;
361
362 /* Put the edev to PE */
363 list_add_tail(&edev->list, &pe->edevs);
364 pr_debug("EEH: Add %04x:%02x:%02x.%01x to Bus PE#%x\n",
365 pdn->phb->global_number,
366 pdn->busno,
367 PCI_SLOT(pdn->devfn),
368 PCI_FUNC(pdn->devfn),
369 pe->addr);
370 return 0;
371 } else if (pe && (pe->type & EEH_PE_INVALID)) {
372 list_add_tail(&edev->list, &pe->edevs);
373 edev->pe = pe;
374 /*
375 * We're running to here because of PCI hotplug caused by
376 * EEH recovery. We need clear EEH_PE_INVALID until the top.
377 */
378 parent = pe;
379 while (parent) {
380 if (!(parent->type & EEH_PE_INVALID))
381 break;
382 parent->type &= ~(EEH_PE_INVALID | EEH_PE_KEEP);
383 parent = parent->parent;
384 }
385
386 pr_debug("EEH: Add %04x:%02x:%02x.%01x to Device "
387 "PE#%x, Parent PE#%x\n",
388 pdn->phb->global_number,
389 pdn->busno,
390 PCI_SLOT(pdn->devfn),
391 PCI_FUNC(pdn->devfn),
392 pe->addr, pe->parent->addr);
393 return 0;
394 }
395
396 /* Create a new EEH PE */
397 if (edev->physfn)
398 pe = eeh_pe_alloc(pdn->phb, EEH_PE_VF);
399 else
400 pe = eeh_pe_alloc(pdn->phb, EEH_PE_DEVICE);
401 if (!pe) {
402 pr_err("%s: out of memory!\n", __func__);
403 return -ENOMEM;
404 }
405 pe->addr = edev->pe_config_addr;
406 pe->config_addr = config_addr;
407
408 /*
409 * Put the new EEH PE into hierarchy tree. If the parent
410 * can't be found, the newly created PE will be attached
411 * to PHB directly. Otherwise, we have to associate the
412 * PE with its parent.
413 */
414 parent = eeh_pe_get_parent(edev);
415 if (!parent) {
416 parent = eeh_phb_pe_get(pdn->phb);
417 if (!parent) {
418 pr_err("%s: No PHB PE is found (PHB Domain=%d)\n",
419 __func__, pdn->phb->global_number);
420 edev->pe = NULL;
421 kfree(pe);
422 return -EEXIST;
423 }
424 }
425 pe->parent = parent;
426
427 /*
428 * Put the newly created PE into the child list and
429 * link the EEH device accordingly.
430 */
431 list_add_tail(&pe->child, &parent->child_list);
432 list_add_tail(&edev->list, &pe->edevs);
433 edev->pe = pe;
434 pr_debug("EEH: Add %04x:%02x:%02x.%01x to "
435 "Device PE#%x, Parent PE#%x\n",
436 pdn->phb->global_number,
437 pdn->busno,
438 PCI_SLOT(pdn->devfn),
439 PCI_FUNC(pdn->devfn),
440 pe->addr, pe->parent->addr);
441
442 return 0;
443 }
444
445 /**
446 * eeh_rmv_from_parent_pe - Remove one EEH device from the associated PE
447 * @edev: EEH device
448 *
449 * The PE hierarchy tree might be changed when doing PCI hotplug.
450 * Also, the PCI devices or buses could be removed from the system
451 * during EEH recovery. So we have to call the function remove the
452 * corresponding PE accordingly if necessary.
453 */
eeh_rmv_from_parent_pe(struct eeh_dev * edev)454 int eeh_rmv_from_parent_pe(struct eeh_dev *edev)
455 {
456 struct eeh_pe *pe, *parent, *child;
457 int cnt;
458 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
459
460 if (!edev->pe) {
461 pr_debug("%s: No PE found for device %04x:%02x:%02x.%01x\n",
462 __func__, pdn->phb->global_number,
463 pdn->busno,
464 PCI_SLOT(pdn->devfn),
465 PCI_FUNC(pdn->devfn));
466 return -EEXIST;
467 }
468
469 /* Remove the EEH device */
470 pe = eeh_dev_to_pe(edev);
471 edev->pe = NULL;
472 list_del(&edev->list);
473
474 /*
475 * Check if the parent PE includes any EEH devices.
476 * If not, we should delete that. Also, we should
477 * delete the parent PE if it doesn't have associated
478 * child PEs and EEH devices.
479 */
480 while (1) {
481 parent = pe->parent;
482 if (pe->type & EEH_PE_PHB)
483 break;
484
485 if (!(pe->state & EEH_PE_KEEP)) {
486 if (list_empty(&pe->edevs) &&
487 list_empty(&pe->child_list)) {
488 list_del(&pe->child);
489 kfree(pe);
490 } else {
491 break;
492 }
493 } else {
494 if (list_empty(&pe->edevs)) {
495 cnt = 0;
496 list_for_each_entry(child, &pe->child_list, child) {
497 if (!(child->type & EEH_PE_INVALID)) {
498 cnt++;
499 break;
500 }
501 }
502
503 if (!cnt)
504 pe->type |= EEH_PE_INVALID;
505 else
506 break;
507 }
508 }
509
510 pe = parent;
511 }
512
513 return 0;
514 }
515
516 /**
517 * eeh_pe_update_time_stamp - Update PE's frozen time stamp
518 * @pe: EEH PE
519 *
520 * We have time stamp for each PE to trace its time of getting
521 * frozen in last hour. The function should be called to update
522 * the time stamp on first error of the specific PE. On the other
523 * handle, we needn't account for errors happened in last hour.
524 */
eeh_pe_update_time_stamp(struct eeh_pe * pe)525 void eeh_pe_update_time_stamp(struct eeh_pe *pe)
526 {
527 time64_t tstamp;
528
529 if (!pe) return;
530
531 if (pe->freeze_count <= 0) {
532 pe->freeze_count = 0;
533 pe->tstamp = ktime_get_seconds();
534 } else {
535 tstamp = ktime_get_seconds();
536 if (tstamp - pe->tstamp > 3600) {
537 pe->tstamp = tstamp;
538 pe->freeze_count = 0;
539 }
540 }
541 }
542
543 /**
544 * __eeh_pe_state_mark - Mark the state for the PE
545 * @data: EEH PE
546 * @flag: state
547 *
548 * The function is used to mark the indicated state for the given
549 * PE. Also, the associated PCI devices will be put into IO frozen
550 * state as well.
551 */
__eeh_pe_state_mark(struct eeh_pe * pe,void * flag)552 static void *__eeh_pe_state_mark(struct eeh_pe *pe, void *flag)
553 {
554 int state = *((int *)flag);
555 struct eeh_dev *edev, *tmp;
556 struct pci_dev *pdev;
557
558 /* Keep the state of permanently removed PE intact */
559 if (pe->state & EEH_PE_REMOVED)
560 return NULL;
561
562 pe->state |= state;
563
564 /* Offline PCI devices if applicable */
565 if (!(state & EEH_PE_ISOLATED))
566 return NULL;
567
568 eeh_pe_for_each_dev(pe, edev, tmp) {
569 pdev = eeh_dev_to_pci_dev(edev);
570 if (pdev)
571 pdev->error_state = pci_channel_io_frozen;
572 }
573
574 /* Block PCI config access if required */
575 if (pe->state & EEH_PE_CFG_RESTRICTED)
576 pe->state |= EEH_PE_CFG_BLOCKED;
577
578 return NULL;
579 }
580
581 /**
582 * eeh_pe_state_mark - Mark specified state for PE and its associated device
583 * @pe: EEH PE
584 *
585 * EEH error affects the current PE and its child PEs. The function
586 * is used to mark appropriate state for the affected PEs and the
587 * associated devices.
588 */
eeh_pe_state_mark(struct eeh_pe * pe,int state)589 void eeh_pe_state_mark(struct eeh_pe *pe, int state)
590 {
591 eeh_pe_traverse(pe, __eeh_pe_state_mark, &state);
592 }
593 EXPORT_SYMBOL_GPL(eeh_pe_state_mark);
594
__eeh_pe_dev_mode_mark(struct eeh_dev * edev,void * flag)595 static void *__eeh_pe_dev_mode_mark(struct eeh_dev *edev, void *flag)
596 {
597 int mode = *((int *)flag);
598
599 edev->mode |= mode;
600
601 return NULL;
602 }
603
604 /**
605 * eeh_pe_dev_state_mark - Mark state for all device under the PE
606 * @pe: EEH PE
607 *
608 * Mark specific state for all child devices of the PE.
609 */
eeh_pe_dev_mode_mark(struct eeh_pe * pe,int mode)610 void eeh_pe_dev_mode_mark(struct eeh_pe *pe, int mode)
611 {
612 eeh_pe_dev_traverse(pe, __eeh_pe_dev_mode_mark, &mode);
613 }
614
615 /**
616 * __eeh_pe_state_clear - Clear state for the PE
617 * @data: EEH PE
618 * @flag: state
619 *
620 * The function is used to clear the indicated state from the
621 * given PE. Besides, we also clear the check count of the PE
622 * as well.
623 */
__eeh_pe_state_clear(struct eeh_pe * pe,void * flag)624 static void *__eeh_pe_state_clear(struct eeh_pe *pe, void *flag)
625 {
626 int state = *((int *)flag);
627 struct eeh_dev *edev, *tmp;
628 struct pci_dev *pdev;
629
630 /* Keep the state of permanently removed PE intact */
631 if (pe->state & EEH_PE_REMOVED)
632 return NULL;
633
634 pe->state &= ~state;
635
636 /*
637 * Special treatment on clearing isolated state. Clear
638 * check count since last isolation and put all affected
639 * devices to normal state.
640 */
641 if (!(state & EEH_PE_ISOLATED))
642 return NULL;
643
644 pe->check_count = 0;
645 eeh_pe_for_each_dev(pe, edev, tmp) {
646 pdev = eeh_dev_to_pci_dev(edev);
647 if (!pdev)
648 continue;
649
650 pdev->error_state = pci_channel_io_normal;
651 }
652
653 /* Unblock PCI config access if required */
654 if (pe->state & EEH_PE_CFG_RESTRICTED)
655 pe->state &= ~EEH_PE_CFG_BLOCKED;
656
657 return NULL;
658 }
659
660 /**
661 * eeh_pe_state_clear - Clear state for the PE and its children
662 * @pe: PE
663 * @state: state to be cleared
664 *
665 * When the PE and its children has been recovered from error,
666 * we need clear the error state for that. The function is used
667 * for the purpose.
668 */
eeh_pe_state_clear(struct eeh_pe * pe,int state)669 void eeh_pe_state_clear(struct eeh_pe *pe, int state)
670 {
671 eeh_pe_traverse(pe, __eeh_pe_state_clear, &state);
672 }
673
674 /**
675 * eeh_pe_state_mark_with_cfg - Mark PE state with unblocked config space
676 * @pe: PE
677 * @state: PE state to be set
678 *
679 * Set specified flag to PE and its child PEs. The PCI config space
680 * of some PEs is blocked automatically when EEH_PE_ISOLATED is set,
681 * which isn't needed in some situations. The function allows to set
682 * the specified flag to indicated PEs without blocking their PCI
683 * config space.
684 */
eeh_pe_state_mark_with_cfg(struct eeh_pe * pe,int state)685 void eeh_pe_state_mark_with_cfg(struct eeh_pe *pe, int state)
686 {
687 eeh_pe_traverse(pe, __eeh_pe_state_mark, &state);
688 if (!(state & EEH_PE_ISOLATED))
689 return;
690
691 /* Clear EEH_PE_CFG_BLOCKED, which might be set just now */
692 state = EEH_PE_CFG_BLOCKED;
693 eeh_pe_traverse(pe, __eeh_pe_state_clear, &state);
694 }
695
696 /*
697 * Some PCI bridges (e.g. PLX bridges) have primary/secondary
698 * buses assigned explicitly by firmware, and we probably have
699 * lost that after reset. So we have to delay the check until
700 * the PCI-CFG registers have been restored for the parent
701 * bridge.
702 *
703 * Don't use normal PCI-CFG accessors, which probably has been
704 * blocked on normal path during the stage. So we need utilize
705 * eeh operations, which is always permitted.
706 */
eeh_bridge_check_link(struct eeh_dev * edev)707 static void eeh_bridge_check_link(struct eeh_dev *edev)
708 {
709 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
710 int cap;
711 uint32_t val;
712 int timeout = 0;
713
714 /*
715 * We only check root port and downstream ports of
716 * PCIe switches
717 */
718 if (!(edev->mode & (EEH_DEV_ROOT_PORT | EEH_DEV_DS_PORT)))
719 return;
720
721 pr_debug("%s: Check PCIe link for %04x:%02x:%02x.%01x ...\n",
722 __func__, pdn->phb->global_number,
723 pdn->busno,
724 PCI_SLOT(pdn->devfn),
725 PCI_FUNC(pdn->devfn));
726
727 /* Check slot status */
728 cap = edev->pcie_cap;
729 eeh_ops->read_config(pdn, cap + PCI_EXP_SLTSTA, 2, &val);
730 if (!(val & PCI_EXP_SLTSTA_PDS)) {
731 pr_debug(" No card in the slot (0x%04x) !\n", val);
732 return;
733 }
734
735 /* Check power status if we have the capability */
736 eeh_ops->read_config(pdn, cap + PCI_EXP_SLTCAP, 2, &val);
737 if (val & PCI_EXP_SLTCAP_PCP) {
738 eeh_ops->read_config(pdn, cap + PCI_EXP_SLTCTL, 2, &val);
739 if (val & PCI_EXP_SLTCTL_PCC) {
740 pr_debug(" In power-off state, power it on ...\n");
741 val &= ~(PCI_EXP_SLTCTL_PCC | PCI_EXP_SLTCTL_PIC);
742 val |= (0x0100 & PCI_EXP_SLTCTL_PIC);
743 eeh_ops->write_config(pdn, cap + PCI_EXP_SLTCTL, 2, val);
744 msleep(2 * 1000);
745 }
746 }
747
748 /* Enable link */
749 eeh_ops->read_config(pdn, cap + PCI_EXP_LNKCTL, 2, &val);
750 val &= ~PCI_EXP_LNKCTL_LD;
751 eeh_ops->write_config(pdn, cap + PCI_EXP_LNKCTL, 2, val);
752
753 /* Check link */
754 eeh_ops->read_config(pdn, cap + PCI_EXP_LNKCAP, 4, &val);
755 if (!(val & PCI_EXP_LNKCAP_DLLLARC)) {
756 pr_debug(" No link reporting capability (0x%08x) \n", val);
757 msleep(1000);
758 return;
759 }
760
761 /* Wait the link is up until timeout (5s) */
762 timeout = 0;
763 while (timeout < 5000) {
764 msleep(20);
765 timeout += 20;
766
767 eeh_ops->read_config(pdn, cap + PCI_EXP_LNKSTA, 2, &val);
768 if (val & PCI_EXP_LNKSTA_DLLLA)
769 break;
770 }
771
772 if (val & PCI_EXP_LNKSTA_DLLLA)
773 pr_debug(" Link up (%s)\n",
774 (val & PCI_EXP_LNKSTA_CLS_2_5GB) ? "2.5GB" : "5GB");
775 else
776 pr_debug(" Link not ready (0x%04x)\n", val);
777 }
778
779 #define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
780 #define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)])
781
eeh_restore_bridge_bars(struct eeh_dev * edev)782 static void eeh_restore_bridge_bars(struct eeh_dev *edev)
783 {
784 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
785 int i;
786
787 /*
788 * Device BARs: 0x10 - 0x18
789 * Bus numbers and windows: 0x18 - 0x30
790 */
791 for (i = 4; i < 13; i++)
792 eeh_ops->write_config(pdn, i*4, 4, edev->config_space[i]);
793 /* Rom: 0x38 */
794 eeh_ops->write_config(pdn, 14*4, 4, edev->config_space[14]);
795
796 /* Cache line & Latency timer: 0xC 0xD */
797 eeh_ops->write_config(pdn, PCI_CACHE_LINE_SIZE, 1,
798 SAVED_BYTE(PCI_CACHE_LINE_SIZE));
799 eeh_ops->write_config(pdn, PCI_LATENCY_TIMER, 1,
800 SAVED_BYTE(PCI_LATENCY_TIMER));
801 /* Max latency, min grant, interrupt ping and line: 0x3C */
802 eeh_ops->write_config(pdn, 15*4, 4, edev->config_space[15]);
803
804 /* PCI Command: 0x4 */
805 eeh_ops->write_config(pdn, PCI_COMMAND, 4, edev->config_space[1] |
806 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
807
808 /* Check the PCIe link is ready */
809 eeh_bridge_check_link(edev);
810 }
811
eeh_restore_device_bars(struct eeh_dev * edev)812 static void eeh_restore_device_bars(struct eeh_dev *edev)
813 {
814 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
815 int i;
816 u32 cmd;
817
818 for (i = 4; i < 10; i++)
819 eeh_ops->write_config(pdn, i*4, 4, edev->config_space[i]);
820 /* 12 == Expansion ROM Address */
821 eeh_ops->write_config(pdn, 12*4, 4, edev->config_space[12]);
822
823 eeh_ops->write_config(pdn, PCI_CACHE_LINE_SIZE, 1,
824 SAVED_BYTE(PCI_CACHE_LINE_SIZE));
825 eeh_ops->write_config(pdn, PCI_LATENCY_TIMER, 1,
826 SAVED_BYTE(PCI_LATENCY_TIMER));
827
828 /* max latency, min grant, interrupt pin and line */
829 eeh_ops->write_config(pdn, 15*4, 4, edev->config_space[15]);
830
831 /*
832 * Restore PERR & SERR bits, some devices require it,
833 * don't touch the other command bits
834 */
835 eeh_ops->read_config(pdn, PCI_COMMAND, 4, &cmd);
836 if (edev->config_space[1] & PCI_COMMAND_PARITY)
837 cmd |= PCI_COMMAND_PARITY;
838 else
839 cmd &= ~PCI_COMMAND_PARITY;
840 if (edev->config_space[1] & PCI_COMMAND_SERR)
841 cmd |= PCI_COMMAND_SERR;
842 else
843 cmd &= ~PCI_COMMAND_SERR;
844 eeh_ops->write_config(pdn, PCI_COMMAND, 4, cmd);
845 }
846
847 /**
848 * eeh_restore_one_device_bars - Restore the Base Address Registers for one device
849 * @data: EEH device
850 * @flag: Unused
851 *
852 * Loads the PCI configuration space base address registers,
853 * the expansion ROM base address, the latency timer, and etc.
854 * from the saved values in the device node.
855 */
eeh_restore_one_device_bars(struct eeh_dev * edev,void * flag)856 static void *eeh_restore_one_device_bars(struct eeh_dev *edev, void *flag)
857 {
858 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
859
860 /* Do special restore for bridges */
861 if (edev->mode & EEH_DEV_BRIDGE)
862 eeh_restore_bridge_bars(edev);
863 else
864 eeh_restore_device_bars(edev);
865
866 if (eeh_ops->restore_config && pdn)
867 eeh_ops->restore_config(pdn);
868
869 return NULL;
870 }
871
872 /**
873 * eeh_pe_restore_bars - Restore the PCI config space info
874 * @pe: EEH PE
875 *
876 * This routine performs a recursive walk to the children
877 * of this device as well.
878 */
eeh_pe_restore_bars(struct eeh_pe * pe)879 void eeh_pe_restore_bars(struct eeh_pe *pe)
880 {
881 /*
882 * We needn't take the EEH lock since eeh_pe_dev_traverse()
883 * will take that.
884 */
885 eeh_pe_dev_traverse(pe, eeh_restore_one_device_bars, NULL);
886 }
887
888 /**
889 * eeh_pe_loc_get - Retrieve location code binding to the given PE
890 * @pe: EEH PE
891 *
892 * Retrieve the location code of the given PE. If the primary PE bus
893 * is root bus, we will grab location code from PHB device tree node
894 * or root port. Otherwise, the upstream bridge's device tree node
895 * of the primary PE bus will be checked for the location code.
896 */
eeh_pe_loc_get(struct eeh_pe * pe)897 const char *eeh_pe_loc_get(struct eeh_pe *pe)
898 {
899 struct pci_bus *bus = eeh_pe_bus_get(pe);
900 struct device_node *dn;
901 const char *loc = NULL;
902
903 while (bus) {
904 dn = pci_bus_to_OF_node(bus);
905 if (!dn) {
906 bus = bus->parent;
907 continue;
908 }
909
910 if (pci_is_root_bus(bus))
911 loc = of_get_property(dn, "ibm,io-base-loc-code", NULL);
912 else
913 loc = of_get_property(dn, "ibm,slot-location-code",
914 NULL);
915
916 if (loc)
917 return loc;
918
919 bus = bus->parent;
920 }
921
922 return "N/A";
923 }
924
925 /**
926 * eeh_pe_bus_get - Retrieve PCI bus according to the given PE
927 * @pe: EEH PE
928 *
929 * Retrieve the PCI bus according to the given PE. Basically,
930 * there're 3 types of PEs: PHB/Bus/Device. For PHB PE, the
931 * primary PCI bus will be retrieved. The parent bus will be
932 * returned for BUS PE. However, we don't have associated PCI
933 * bus for DEVICE PE.
934 */
eeh_pe_bus_get(struct eeh_pe * pe)935 struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe)
936 {
937 struct eeh_dev *edev;
938 struct pci_dev *pdev;
939
940 if (pe->type & EEH_PE_PHB)
941 return pe->phb->bus;
942
943 /* The primary bus might be cached during probe time */
944 if (pe->state & EEH_PE_PRI_BUS)
945 return pe->bus;
946
947 /* Retrieve the parent PCI bus of first (top) PCI device */
948 edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, list);
949 pdev = eeh_dev_to_pci_dev(edev);
950 if (pdev)
951 return pdev->bus;
952
953 return NULL;
954 }
955
