1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4 #include "e1000.h"
5
6 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
7 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
8 u16 *data, bool read, bool page_set);
9 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
10 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
11 u16 *data, bool read);
12
13 /* Cable length tables */
14 static const u16 e1000_m88_cable_length_table[] = {
15 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED
16 };
17
18 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
19 ARRAY_SIZE(e1000_m88_cable_length_table)
20
21 static const u16 e1000_igp_2_cable_length_table[] = {
22 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
23 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
24 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
25 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
26 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
27 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
28 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
29 124
30 };
31
32 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
33 ARRAY_SIZE(e1000_igp_2_cable_length_table)
34
35 /**
36 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
37 * @hw: pointer to the HW structure
38 *
39 * Read the PHY management control register and check whether a PHY reset
40 * is blocked. If a reset is not blocked return 0, otherwise
41 * return E1000_BLK_PHY_RESET (12).
42 **/
e1000e_check_reset_block_generic(struct e1000_hw * hw)43 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
44 {
45 u32 manc;
46
47 manc = er32(MANC);
48
49 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0;
50 }
51
52 /**
53 * e1000e_get_phy_id - Retrieve the PHY ID and revision
54 * @hw: pointer to the HW structure
55 *
56 * Reads the PHY registers and stores the PHY ID and possibly the PHY
57 * revision in the hardware structure.
58 **/
e1000e_get_phy_id(struct e1000_hw * hw)59 s32 e1000e_get_phy_id(struct e1000_hw *hw)
60 {
61 struct e1000_phy_info *phy = &hw->phy;
62 s32 ret_val = 0;
63 u16 phy_id;
64 u16 retry_count = 0;
65
66 if (!phy->ops.read_reg)
67 return 0;
68
69 while (retry_count < 2) {
70 ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id);
71 if (ret_val)
72 return ret_val;
73
74 phy->id = (u32)(phy_id << 16);
75 usleep_range(20, 40);
76 ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id);
77 if (ret_val)
78 return ret_val;
79
80 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
81 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
82
83 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
84 return 0;
85
86 retry_count++;
87 }
88
89 return 0;
90 }
91
92 /**
93 * e1000e_phy_reset_dsp - Reset PHY DSP
94 * @hw: pointer to the HW structure
95 *
96 * Reset the digital signal processor.
97 **/
e1000e_phy_reset_dsp(struct e1000_hw * hw)98 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
99 {
100 s32 ret_val;
101
102 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
103 if (ret_val)
104 return ret_val;
105
106 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
107 }
108
109 /**
110 * e1000e_read_phy_reg_mdic - Read MDI control register
111 * @hw: pointer to the HW structure
112 * @offset: register offset to be read
113 * @data: pointer to the read data
114 *
115 * Reads the MDI control register in the PHY at offset and stores the
116 * information read to data.
117 **/
e1000e_read_phy_reg_mdic(struct e1000_hw * hw,u32 offset,u16 * data)118 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
119 {
120 struct e1000_phy_info *phy = &hw->phy;
121 u32 i, mdic = 0;
122
123 if (offset > MAX_PHY_REG_ADDRESS) {
124 e_dbg("PHY Address %d is out of range\n", offset);
125 return -E1000_ERR_PARAM;
126 }
127
128 /* Set up Op-code, Phy Address, and register offset in the MDI
129 * Control register. The MAC will take care of interfacing with the
130 * PHY to retrieve the desired data.
131 */
132 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
133 (phy->addr << E1000_MDIC_PHY_SHIFT) |
134 (E1000_MDIC_OP_READ));
135
136 ew32(MDIC, mdic);
137
138 /* Poll the ready bit to see if the MDI read completed
139 * Increasing the time out as testing showed failures with
140 * the lower time out
141 */
142 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
143 udelay(50);
144 mdic = er32(MDIC);
145 if (mdic & E1000_MDIC_READY)
146 break;
147 }
148 if (!(mdic & E1000_MDIC_READY)) {
149 e_dbg("MDI Read did not complete\n");
150 return -E1000_ERR_PHY;
151 }
152 if (mdic & E1000_MDIC_ERROR) {
153 e_dbg("MDI Error\n");
154 return -E1000_ERR_PHY;
155 }
156 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
157 e_dbg("MDI Read offset error - requested %d, returned %d\n",
158 offset,
159 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
160 return -E1000_ERR_PHY;
161 }
162 *data = (u16)mdic;
163
164 /* Allow some time after each MDIC transaction to avoid
165 * reading duplicate data in the next MDIC transaction.
166 */
167 if (hw->mac.type == e1000_pch2lan)
168 udelay(100);
169
170 return 0;
171 }
172
173 /**
174 * e1000e_write_phy_reg_mdic - Write MDI control register
175 * @hw: pointer to the HW structure
176 * @offset: register offset to write to
177 * @data: data to write to register at offset
178 *
179 * Writes data to MDI control register in the PHY at offset.
180 **/
e1000e_write_phy_reg_mdic(struct e1000_hw * hw,u32 offset,u16 data)181 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
182 {
183 struct e1000_phy_info *phy = &hw->phy;
184 u32 i, mdic = 0;
185
186 if (offset > MAX_PHY_REG_ADDRESS) {
187 e_dbg("PHY Address %d is out of range\n", offset);
188 return -E1000_ERR_PARAM;
189 }
190
191 /* Set up Op-code, Phy Address, and register offset in the MDI
192 * Control register. The MAC will take care of interfacing with the
193 * PHY to retrieve the desired data.
194 */
195 mdic = (((u32)data) |
196 (offset << E1000_MDIC_REG_SHIFT) |
197 (phy->addr << E1000_MDIC_PHY_SHIFT) |
198 (E1000_MDIC_OP_WRITE));
199
200 ew32(MDIC, mdic);
201
202 /* Poll the ready bit to see if the MDI read completed
203 * Increasing the time out as testing showed failures with
204 * the lower time out
205 */
206 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
207 udelay(50);
208 mdic = er32(MDIC);
209 if (mdic & E1000_MDIC_READY)
210 break;
211 }
212 if (!(mdic & E1000_MDIC_READY)) {
213 e_dbg("MDI Write did not complete\n");
214 return -E1000_ERR_PHY;
215 }
216 if (mdic & E1000_MDIC_ERROR) {
217 e_dbg("MDI Error\n");
218 return -E1000_ERR_PHY;
219 }
220 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
221 e_dbg("MDI Write offset error - requested %d, returned %d\n",
222 offset,
223 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
224 return -E1000_ERR_PHY;
225 }
226
227 /* Allow some time after each MDIC transaction to avoid
228 * reading duplicate data in the next MDIC transaction.
229 */
230 if (hw->mac.type == e1000_pch2lan)
231 udelay(100);
232
233 return 0;
234 }
235
236 /**
237 * e1000e_read_phy_reg_m88 - Read m88 PHY register
238 * @hw: pointer to the HW structure
239 * @offset: register offset to be read
240 * @data: pointer to the read data
241 *
242 * Acquires semaphore, if necessary, then reads the PHY register at offset
243 * and storing the retrieved information in data. Release any acquired
244 * semaphores before exiting.
245 **/
e1000e_read_phy_reg_m88(struct e1000_hw * hw,u32 offset,u16 * data)246 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
247 {
248 s32 ret_val;
249
250 ret_val = hw->phy.ops.acquire(hw);
251 if (ret_val)
252 return ret_val;
253
254 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
255 data);
256
257 hw->phy.ops.release(hw);
258
259 return ret_val;
260 }
261
262 /**
263 * e1000e_write_phy_reg_m88 - Write m88 PHY register
264 * @hw: pointer to the HW structure
265 * @offset: register offset to write to
266 * @data: data to write at register offset
267 *
268 * Acquires semaphore, if necessary, then writes the data to PHY register
269 * at the offset. Release any acquired semaphores before exiting.
270 **/
e1000e_write_phy_reg_m88(struct e1000_hw * hw,u32 offset,u16 data)271 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
272 {
273 s32 ret_val;
274
275 ret_val = hw->phy.ops.acquire(hw);
276 if (ret_val)
277 return ret_val;
278
279 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
280 data);
281
282 hw->phy.ops.release(hw);
283
284 return ret_val;
285 }
286
287 /**
288 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
289 * @hw: pointer to the HW structure
290 * @page: page to set (shifted left when necessary)
291 *
292 * Sets PHY page required for PHY register access. Assumes semaphore is
293 * already acquired. Note, this function sets phy.addr to 1 so the caller
294 * must set it appropriately (if necessary) after this function returns.
295 **/
e1000_set_page_igp(struct e1000_hw * hw,u16 page)296 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
297 {
298 e_dbg("Setting page 0x%x\n", page);
299
300 hw->phy.addr = 1;
301
302 return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
303 }
304
305 /**
306 * __e1000e_read_phy_reg_igp - Read igp PHY register
307 * @hw: pointer to the HW structure
308 * @offset: register offset to be read
309 * @data: pointer to the read data
310 * @locked: semaphore has already been acquired or not
311 *
312 * Acquires semaphore, if necessary, then reads the PHY register at offset
313 * and stores the retrieved information in data. Release any acquired
314 * semaphores before exiting.
315 **/
__e1000e_read_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 * data,bool locked)316 static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
317 bool locked)
318 {
319 s32 ret_val = 0;
320
321 if (!locked) {
322 if (!hw->phy.ops.acquire)
323 return 0;
324
325 ret_val = hw->phy.ops.acquire(hw);
326 if (ret_val)
327 return ret_val;
328 }
329
330 if (offset > MAX_PHY_MULTI_PAGE_REG)
331 ret_val = e1000e_write_phy_reg_mdic(hw,
332 IGP01E1000_PHY_PAGE_SELECT,
333 (u16)offset);
334 if (!ret_val)
335 ret_val = e1000e_read_phy_reg_mdic(hw,
336 MAX_PHY_REG_ADDRESS & offset,
337 data);
338 if (!locked)
339 hw->phy.ops.release(hw);
340
341 return ret_val;
342 }
343
344 /**
345 * e1000e_read_phy_reg_igp - Read igp PHY register
346 * @hw: pointer to the HW structure
347 * @offset: register offset to be read
348 * @data: pointer to the read data
349 *
350 * Acquires semaphore then reads the PHY register at offset and stores the
351 * retrieved information in data.
352 * Release the acquired semaphore before exiting.
353 **/
e1000e_read_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 * data)354 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
355 {
356 return __e1000e_read_phy_reg_igp(hw, offset, data, false);
357 }
358
359 /**
360 * e1000e_read_phy_reg_igp_locked - Read igp PHY register
361 * @hw: pointer to the HW structure
362 * @offset: register offset to be read
363 * @data: pointer to the read data
364 *
365 * Reads the PHY register at offset and stores the retrieved information
366 * in data. Assumes semaphore already acquired.
367 **/
e1000e_read_phy_reg_igp_locked(struct e1000_hw * hw,u32 offset,u16 * data)368 s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
369 {
370 return __e1000e_read_phy_reg_igp(hw, offset, data, true);
371 }
372
373 /**
374 * e1000e_write_phy_reg_igp - Write igp PHY register
375 * @hw: pointer to the HW structure
376 * @offset: register offset to write to
377 * @data: data to write at register offset
378 * @locked: semaphore has already been acquired or not
379 *
380 * Acquires semaphore, if necessary, then writes the data to PHY register
381 * at the offset. Release any acquired semaphores before exiting.
382 **/
__e1000e_write_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 data,bool locked)383 static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
384 bool locked)
385 {
386 s32 ret_val = 0;
387
388 if (!locked) {
389 if (!hw->phy.ops.acquire)
390 return 0;
391
392 ret_val = hw->phy.ops.acquire(hw);
393 if (ret_val)
394 return ret_val;
395 }
396
397 if (offset > MAX_PHY_MULTI_PAGE_REG)
398 ret_val = e1000e_write_phy_reg_mdic(hw,
399 IGP01E1000_PHY_PAGE_SELECT,
400 (u16)offset);
401 if (!ret_val)
402 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
403 offset, data);
404 if (!locked)
405 hw->phy.ops.release(hw);
406
407 return ret_val;
408 }
409
410 /**
411 * e1000e_write_phy_reg_igp - Write igp PHY register
412 * @hw: pointer to the HW structure
413 * @offset: register offset to write to
414 * @data: data to write at register offset
415 *
416 * Acquires semaphore then writes the data to PHY register
417 * at the offset. Release any acquired semaphores before exiting.
418 **/
e1000e_write_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 data)419 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
420 {
421 return __e1000e_write_phy_reg_igp(hw, offset, data, false);
422 }
423
424 /**
425 * e1000e_write_phy_reg_igp_locked - Write igp PHY register
426 * @hw: pointer to the HW structure
427 * @offset: register offset to write to
428 * @data: data to write at register offset
429 *
430 * Writes the data to PHY register at the offset.
431 * Assumes semaphore already acquired.
432 **/
e1000e_write_phy_reg_igp_locked(struct e1000_hw * hw,u32 offset,u16 data)433 s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
434 {
435 return __e1000e_write_phy_reg_igp(hw, offset, data, true);
436 }
437
438 /**
439 * __e1000_read_kmrn_reg - Read kumeran register
440 * @hw: pointer to the HW structure
441 * @offset: register offset to be read
442 * @data: pointer to the read data
443 * @locked: semaphore has already been acquired or not
444 *
445 * Acquires semaphore, if necessary. Then reads the PHY register at offset
446 * using the kumeran interface. The information retrieved is stored in data.
447 * Release any acquired semaphores before exiting.
448 **/
__e1000_read_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 * data,bool locked)449 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
450 bool locked)
451 {
452 u32 kmrnctrlsta;
453
454 if (!locked) {
455 s32 ret_val = 0;
456
457 if (!hw->phy.ops.acquire)
458 return 0;
459
460 ret_val = hw->phy.ops.acquire(hw);
461 if (ret_val)
462 return ret_val;
463 }
464
465 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
466 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
467 ew32(KMRNCTRLSTA, kmrnctrlsta);
468 e1e_flush();
469
470 udelay(2);
471
472 kmrnctrlsta = er32(KMRNCTRLSTA);
473 *data = (u16)kmrnctrlsta;
474
475 if (!locked)
476 hw->phy.ops.release(hw);
477
478 return 0;
479 }
480
481 /**
482 * e1000e_read_kmrn_reg - Read kumeran register
483 * @hw: pointer to the HW structure
484 * @offset: register offset to be read
485 * @data: pointer to the read data
486 *
487 * Acquires semaphore then reads the PHY register at offset using the
488 * kumeran interface. The information retrieved is stored in data.
489 * Release the acquired semaphore before exiting.
490 **/
e1000e_read_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 * data)491 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
492 {
493 return __e1000_read_kmrn_reg(hw, offset, data, false);
494 }
495
496 /**
497 * e1000e_read_kmrn_reg_locked - Read kumeran register
498 * @hw: pointer to the HW structure
499 * @offset: register offset to be read
500 * @data: pointer to the read data
501 *
502 * Reads the PHY register at offset using the kumeran interface. The
503 * information retrieved is stored in data.
504 * Assumes semaphore already acquired.
505 **/
e1000e_read_kmrn_reg_locked(struct e1000_hw * hw,u32 offset,u16 * data)506 s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
507 {
508 return __e1000_read_kmrn_reg(hw, offset, data, true);
509 }
510
511 /**
512 * __e1000_write_kmrn_reg - Write kumeran register
513 * @hw: pointer to the HW structure
514 * @offset: register offset to write to
515 * @data: data to write at register offset
516 * @locked: semaphore has already been acquired or not
517 *
518 * Acquires semaphore, if necessary. Then write the data to PHY register
519 * at the offset using the kumeran interface. Release any acquired semaphores
520 * before exiting.
521 **/
__e1000_write_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 data,bool locked)522 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
523 bool locked)
524 {
525 u32 kmrnctrlsta;
526
527 if (!locked) {
528 s32 ret_val = 0;
529
530 if (!hw->phy.ops.acquire)
531 return 0;
532
533 ret_val = hw->phy.ops.acquire(hw);
534 if (ret_val)
535 return ret_val;
536 }
537
538 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
539 E1000_KMRNCTRLSTA_OFFSET) | data;
540 ew32(KMRNCTRLSTA, kmrnctrlsta);
541 e1e_flush();
542
543 udelay(2);
544
545 if (!locked)
546 hw->phy.ops.release(hw);
547
548 return 0;
549 }
550
551 /**
552 * e1000e_write_kmrn_reg - Write kumeran register
553 * @hw: pointer to the HW structure
554 * @offset: register offset to write to
555 * @data: data to write at register offset
556 *
557 * Acquires semaphore then writes the data to the PHY register at the offset
558 * using the kumeran interface. Release the acquired semaphore before exiting.
559 **/
e1000e_write_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 data)560 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
561 {
562 return __e1000_write_kmrn_reg(hw, offset, data, false);
563 }
564
565 /**
566 * e1000e_write_kmrn_reg_locked - Write kumeran register
567 * @hw: pointer to the HW structure
568 * @offset: register offset to write to
569 * @data: data to write at register offset
570 *
571 * Write the data to PHY register at the offset using the kumeran interface.
572 * Assumes semaphore already acquired.
573 **/
e1000e_write_kmrn_reg_locked(struct e1000_hw * hw,u32 offset,u16 data)574 s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
575 {
576 return __e1000_write_kmrn_reg(hw, offset, data, true);
577 }
578
579 /**
580 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
581 * @hw: pointer to the HW structure
582 *
583 * Sets up Master/slave mode
584 **/
e1000_set_master_slave_mode(struct e1000_hw * hw)585 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
586 {
587 s32 ret_val;
588 u16 phy_data;
589
590 /* Resolve Master/Slave mode */
591 ret_val = e1e_rphy(hw, MII_CTRL1000, &phy_data);
592 if (ret_val)
593 return ret_val;
594
595 /* load defaults for future use */
596 hw->phy.original_ms_type = (phy_data & CTL1000_ENABLE_MASTER) ?
597 ((phy_data & CTL1000_AS_MASTER) ?
598 e1000_ms_force_master : e1000_ms_force_slave) : e1000_ms_auto;
599
600 switch (hw->phy.ms_type) {
601 case e1000_ms_force_master:
602 phy_data |= (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
603 break;
604 case e1000_ms_force_slave:
605 phy_data |= CTL1000_ENABLE_MASTER;
606 phy_data &= ~(CTL1000_AS_MASTER);
607 break;
608 case e1000_ms_auto:
609 phy_data &= ~CTL1000_ENABLE_MASTER;
610 /* fall-through */
611 default:
612 break;
613 }
614
615 return e1e_wphy(hw, MII_CTRL1000, phy_data);
616 }
617
618 /**
619 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
620 * @hw: pointer to the HW structure
621 *
622 * Sets up Carrier-sense on Transmit and downshift values.
623 **/
e1000_copper_link_setup_82577(struct e1000_hw * hw)624 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
625 {
626 s32 ret_val;
627 u16 phy_data;
628
629 /* Enable CRS on Tx. This must be set for half-duplex operation. */
630 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data);
631 if (ret_val)
632 return ret_val;
633
634 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
635
636 /* Enable downshift */
637 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
638
639 ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data);
640 if (ret_val)
641 return ret_val;
642
643 /* Set MDI/MDIX mode */
644 ret_val = e1e_rphy(hw, I82577_PHY_CTRL_2, &phy_data);
645 if (ret_val)
646 return ret_val;
647 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
648 /* Options:
649 * 0 - Auto (default)
650 * 1 - MDI mode
651 * 2 - MDI-X mode
652 */
653 switch (hw->phy.mdix) {
654 case 1:
655 break;
656 case 2:
657 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
658 break;
659 case 0:
660 default:
661 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
662 break;
663 }
664 ret_val = e1e_wphy(hw, I82577_PHY_CTRL_2, phy_data);
665 if (ret_val)
666 return ret_val;
667
668 return e1000_set_master_slave_mode(hw);
669 }
670
671 /**
672 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
673 * @hw: pointer to the HW structure
674 *
675 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
676 * and downshift values are set also.
677 **/
e1000e_copper_link_setup_m88(struct e1000_hw * hw)678 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
679 {
680 struct e1000_phy_info *phy = &hw->phy;
681 s32 ret_val;
682 u16 phy_data;
683
684 /* Enable CRS on Tx. This must be set for half-duplex operation. */
685 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
686 if (ret_val)
687 return ret_val;
688
689 /* For BM PHY this bit is downshift enable */
690 if (phy->type != e1000_phy_bm)
691 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
692
693 /* Options:
694 * MDI/MDI-X = 0 (default)
695 * 0 - Auto for all speeds
696 * 1 - MDI mode
697 * 2 - MDI-X mode
698 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
699 */
700 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
701
702 switch (phy->mdix) {
703 case 1:
704 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
705 break;
706 case 2:
707 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
708 break;
709 case 3:
710 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
711 break;
712 case 0:
713 default:
714 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
715 break;
716 }
717
718 /* Options:
719 * disable_polarity_correction = 0 (default)
720 * Automatic Correction for Reversed Cable Polarity
721 * 0 - Disabled
722 * 1 - Enabled
723 */
724 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
725 if (phy->disable_polarity_correction)
726 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
727
728 /* Enable downshift on BM (disabled by default) */
729 if (phy->type == e1000_phy_bm) {
730 /* For 82574/82583, first disable then enable downshift */
731 if (phy->id == BME1000_E_PHY_ID_R2) {
732 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
733 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL,
734 phy_data);
735 if (ret_val)
736 return ret_val;
737 /* Commit the changes. */
738 ret_val = phy->ops.commit(hw);
739 if (ret_val) {
740 e_dbg("Error committing the PHY changes\n");
741 return ret_val;
742 }
743 }
744
745 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
746 }
747
748 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
749 if (ret_val)
750 return ret_val;
751
752 if ((phy->type == e1000_phy_m88) &&
753 (phy->revision < E1000_REVISION_4) &&
754 (phy->id != BME1000_E_PHY_ID_R2)) {
755 /* Force TX_CLK in the Extended PHY Specific Control Register
756 * to 25MHz clock.
757 */
758 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
759 if (ret_val)
760 return ret_val;
761
762 phy_data |= M88E1000_EPSCR_TX_CLK_25;
763
764 if ((phy->revision == 2) && (phy->id == M88E1111_I_PHY_ID)) {
765 /* 82573L PHY - set the downshift counter to 5x. */
766 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
767 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
768 } else {
769 /* Configure Master and Slave downshift values */
770 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
771 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
772 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
773 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
774 }
775 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
776 if (ret_val)
777 return ret_val;
778 }
779
780 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
781 /* Set PHY page 0, register 29 to 0x0003 */
782 ret_val = e1e_wphy(hw, 29, 0x0003);
783 if (ret_val)
784 return ret_val;
785
786 /* Set PHY page 0, register 30 to 0x0000 */
787 ret_val = e1e_wphy(hw, 30, 0x0000);
788 if (ret_val)
789 return ret_val;
790 }
791
792 /* Commit the changes. */
793 if (phy->ops.commit) {
794 ret_val = phy->ops.commit(hw);
795 if (ret_val) {
796 e_dbg("Error committing the PHY changes\n");
797 return ret_val;
798 }
799 }
800
801 if (phy->type == e1000_phy_82578) {
802 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
803 if (ret_val)
804 return ret_val;
805
806 /* 82578 PHY - set the downshift count to 1x. */
807 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
808 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
809 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
810 if (ret_val)
811 return ret_val;
812 }
813
814 return 0;
815 }
816
817 /**
818 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
819 * @hw: pointer to the HW structure
820 *
821 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
822 * igp PHY's.
823 **/
e1000e_copper_link_setup_igp(struct e1000_hw * hw)824 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
825 {
826 struct e1000_phy_info *phy = &hw->phy;
827 s32 ret_val;
828 u16 data;
829
830 ret_val = e1000_phy_hw_reset(hw);
831 if (ret_val) {
832 e_dbg("Error resetting the PHY.\n");
833 return ret_val;
834 }
835
836 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
837 * timeout issues when LFS is enabled.
838 */
839 msleep(100);
840
841 /* disable lplu d0 during driver init */
842 if (hw->phy.ops.set_d0_lplu_state) {
843 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
844 if (ret_val) {
845 e_dbg("Error Disabling LPLU D0\n");
846 return ret_val;
847 }
848 }
849 /* Configure mdi-mdix settings */
850 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
851 if (ret_val)
852 return ret_val;
853
854 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
855
856 switch (phy->mdix) {
857 case 1:
858 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
859 break;
860 case 2:
861 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
862 break;
863 case 0:
864 default:
865 data |= IGP01E1000_PSCR_AUTO_MDIX;
866 break;
867 }
868 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
869 if (ret_val)
870 return ret_val;
871
872 /* set auto-master slave resolution settings */
873 if (hw->mac.autoneg) {
874 /* when autonegotiation advertisement is only 1000Mbps then we
875 * should disable SmartSpeed and enable Auto MasterSlave
876 * resolution as hardware default.
877 */
878 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
879 /* Disable SmartSpeed */
880 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
881 &data);
882 if (ret_val)
883 return ret_val;
884
885 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
886 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
887 data);
888 if (ret_val)
889 return ret_val;
890
891 /* Set auto Master/Slave resolution process */
892 ret_val = e1e_rphy(hw, MII_CTRL1000, &data);
893 if (ret_val)
894 return ret_val;
895
896 data &= ~CTL1000_ENABLE_MASTER;
897 ret_val = e1e_wphy(hw, MII_CTRL1000, data);
898 if (ret_val)
899 return ret_val;
900 }
901
902 ret_val = e1000_set_master_slave_mode(hw);
903 }
904
905 return ret_val;
906 }
907
908 /**
909 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
910 * @hw: pointer to the HW structure
911 *
912 * Reads the MII auto-neg advertisement register and/or the 1000T control
913 * register and if the PHY is already setup for auto-negotiation, then
914 * return successful. Otherwise, setup advertisement and flow control to
915 * the appropriate values for the wanted auto-negotiation.
916 **/
e1000_phy_setup_autoneg(struct e1000_hw * hw)917 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
918 {
919 struct e1000_phy_info *phy = &hw->phy;
920 s32 ret_val;
921 u16 mii_autoneg_adv_reg;
922 u16 mii_1000t_ctrl_reg = 0;
923
924 phy->autoneg_advertised &= phy->autoneg_mask;
925
926 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
927 ret_val = e1e_rphy(hw, MII_ADVERTISE, &mii_autoneg_adv_reg);
928 if (ret_val)
929 return ret_val;
930
931 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
932 /* Read the MII 1000Base-T Control Register (Address 9). */
933 ret_val = e1e_rphy(hw, MII_CTRL1000, &mii_1000t_ctrl_reg);
934 if (ret_val)
935 return ret_val;
936 }
937
938 /* Need to parse both autoneg_advertised and fc and set up
939 * the appropriate PHY registers. First we will parse for
940 * autoneg_advertised software override. Since we can advertise
941 * a plethora of combinations, we need to check each bit
942 * individually.
943 */
944
945 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
946 * Advertisement Register (Address 4) and the 1000 mb speed bits in
947 * the 1000Base-T Control Register (Address 9).
948 */
949 mii_autoneg_adv_reg &= ~(ADVERTISE_100FULL |
950 ADVERTISE_100HALF |
951 ADVERTISE_10FULL | ADVERTISE_10HALF);
952 mii_1000t_ctrl_reg &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
953
954 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
955
956 /* Do we want to advertise 10 Mb Half Duplex? */
957 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
958 e_dbg("Advertise 10mb Half duplex\n");
959 mii_autoneg_adv_reg |= ADVERTISE_10HALF;
960 }
961
962 /* Do we want to advertise 10 Mb Full Duplex? */
963 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
964 e_dbg("Advertise 10mb Full duplex\n");
965 mii_autoneg_adv_reg |= ADVERTISE_10FULL;
966 }
967
968 /* Do we want to advertise 100 Mb Half Duplex? */
969 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
970 e_dbg("Advertise 100mb Half duplex\n");
971 mii_autoneg_adv_reg |= ADVERTISE_100HALF;
972 }
973
974 /* Do we want to advertise 100 Mb Full Duplex? */
975 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
976 e_dbg("Advertise 100mb Full duplex\n");
977 mii_autoneg_adv_reg |= ADVERTISE_100FULL;
978 }
979
980 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
981 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
982 e_dbg("Advertise 1000mb Half duplex request denied!\n");
983
984 /* Do we want to advertise 1000 Mb Full Duplex? */
985 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
986 e_dbg("Advertise 1000mb Full duplex\n");
987 mii_1000t_ctrl_reg |= ADVERTISE_1000FULL;
988 }
989
990 /* Check for a software override of the flow control settings, and
991 * setup the PHY advertisement registers accordingly. If
992 * auto-negotiation is enabled, then software will have to set the
993 * "PAUSE" bits to the correct value in the Auto-Negotiation
994 * Advertisement Register (MII_ADVERTISE) and re-start auto-
995 * negotiation.
996 *
997 * The possible values of the "fc" parameter are:
998 * 0: Flow control is completely disabled
999 * 1: Rx flow control is enabled (we can receive pause frames
1000 * but not send pause frames).
1001 * 2: Tx flow control is enabled (we can send pause frames
1002 * but we do not support receiving pause frames).
1003 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1004 * other: No software override. The flow control configuration
1005 * in the EEPROM is used.
1006 */
1007 switch (hw->fc.current_mode) {
1008 case e1000_fc_none:
1009 /* Flow control (Rx & Tx) is completely disabled by a
1010 * software over-ride.
1011 */
1012 mii_autoneg_adv_reg &=
1013 ~(ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1014 break;
1015 case e1000_fc_rx_pause:
1016 /* Rx Flow control is enabled, and Tx Flow control is
1017 * disabled, by a software over-ride.
1018 *
1019 * Since there really isn't a way to advertise that we are
1020 * capable of Rx Pause ONLY, we will advertise that we
1021 * support both symmetric and asymmetric Rx PAUSE. Later
1022 * (in e1000e_config_fc_after_link_up) we will disable the
1023 * hw's ability to send PAUSE frames.
1024 */
1025 mii_autoneg_adv_reg |=
1026 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1027 break;
1028 case e1000_fc_tx_pause:
1029 /* Tx Flow control is enabled, and Rx Flow control is
1030 * disabled, by a software over-ride.
1031 */
1032 mii_autoneg_adv_reg |= ADVERTISE_PAUSE_ASYM;
1033 mii_autoneg_adv_reg &= ~ADVERTISE_PAUSE_CAP;
1034 break;
1035 case e1000_fc_full:
1036 /* Flow control (both Rx and Tx) is enabled by a software
1037 * over-ride.
1038 */
1039 mii_autoneg_adv_reg |=
1040 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1041 break;
1042 default:
1043 e_dbg("Flow control param set incorrectly\n");
1044 return -E1000_ERR_CONFIG;
1045 }
1046
1047 ret_val = e1e_wphy(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
1048 if (ret_val)
1049 return ret_val;
1050
1051 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1052
1053 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1054 ret_val = e1e_wphy(hw, MII_CTRL1000, mii_1000t_ctrl_reg);
1055
1056 return ret_val;
1057 }
1058
1059 /**
1060 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1061 * @hw: pointer to the HW structure
1062 *
1063 * Performs initial bounds checking on autoneg advertisement parameter, then
1064 * configure to advertise the full capability. Setup the PHY to autoneg
1065 * and restart the negotiation process between the link partner. If
1066 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1067 **/
e1000_copper_link_autoneg(struct e1000_hw * hw)1068 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1069 {
1070 struct e1000_phy_info *phy = &hw->phy;
1071 s32 ret_val;
1072 u16 phy_ctrl;
1073
1074 /* Perform some bounds checking on the autoneg advertisement
1075 * parameter.
1076 */
1077 phy->autoneg_advertised &= phy->autoneg_mask;
1078
1079 /* If autoneg_advertised is zero, we assume it was not defaulted
1080 * by the calling code so we set to advertise full capability.
1081 */
1082 if (!phy->autoneg_advertised)
1083 phy->autoneg_advertised = phy->autoneg_mask;
1084
1085 e_dbg("Reconfiguring auto-neg advertisement params\n");
1086 ret_val = e1000_phy_setup_autoneg(hw);
1087 if (ret_val) {
1088 e_dbg("Error Setting up Auto-Negotiation\n");
1089 return ret_val;
1090 }
1091 e_dbg("Restarting Auto-Neg\n");
1092
1093 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1094 * the Auto Neg Restart bit in the PHY control register.
1095 */
1096 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl);
1097 if (ret_val)
1098 return ret_val;
1099
1100 phy_ctrl |= (BMCR_ANENABLE | BMCR_ANRESTART);
1101 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl);
1102 if (ret_val)
1103 return ret_val;
1104
1105 /* Does the user want to wait for Auto-Neg to complete here, or
1106 * check at a later time (for example, callback routine).
1107 */
1108 if (phy->autoneg_wait_to_complete) {
1109 ret_val = e1000_wait_autoneg(hw);
1110 if (ret_val) {
1111 e_dbg("Error while waiting for autoneg to complete\n");
1112 return ret_val;
1113 }
1114 }
1115
1116 hw->mac.get_link_status = true;
1117
1118 return ret_val;
1119 }
1120
1121 /**
1122 * e1000e_setup_copper_link - Configure copper link settings
1123 * @hw: pointer to the HW structure
1124 *
1125 * Calls the appropriate function to configure the link for auto-neg or forced
1126 * speed and duplex. Then we check for link, once link is established calls
1127 * to configure collision distance and flow control are called. If link is
1128 * not established, we return -E1000_ERR_PHY (-2).
1129 **/
e1000e_setup_copper_link(struct e1000_hw * hw)1130 s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1131 {
1132 s32 ret_val;
1133 bool link;
1134
1135 if (hw->mac.autoneg) {
1136 /* Setup autoneg and flow control advertisement and perform
1137 * autonegotiation.
1138 */
1139 ret_val = e1000_copper_link_autoneg(hw);
1140 if (ret_val)
1141 return ret_val;
1142 } else {
1143 /* PHY will be set to 10H, 10F, 100H or 100F
1144 * depending on user settings.
1145 */
1146 e_dbg("Forcing Speed and Duplex\n");
1147 ret_val = hw->phy.ops.force_speed_duplex(hw);
1148 if (ret_val) {
1149 e_dbg("Error Forcing Speed and Duplex\n");
1150 return ret_val;
1151 }
1152 }
1153
1154 /* Check link status. Wait up to 100 microseconds for link to become
1155 * valid.
1156 */
1157 ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1158 &link);
1159 if (ret_val)
1160 return ret_val;
1161
1162 if (link) {
1163 e_dbg("Valid link established!!!\n");
1164 hw->mac.ops.config_collision_dist(hw);
1165 ret_val = e1000e_config_fc_after_link_up(hw);
1166 } else {
1167 e_dbg("Unable to establish link!!!\n");
1168 }
1169
1170 return ret_val;
1171 }
1172
1173 /**
1174 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1175 * @hw: pointer to the HW structure
1176 *
1177 * Calls the PHY setup function to force speed and duplex. Clears the
1178 * auto-crossover to force MDI manually. Waits for link and returns
1179 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1180 **/
e1000e_phy_force_speed_duplex_igp(struct e1000_hw * hw)1181 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1182 {
1183 struct e1000_phy_info *phy = &hw->phy;
1184 s32 ret_val;
1185 u16 phy_data;
1186 bool link;
1187
1188 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1189 if (ret_val)
1190 return ret_val;
1191
1192 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1193
1194 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1195 if (ret_val)
1196 return ret_val;
1197
1198 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1199 * forced whenever speed and duplex are forced.
1200 */
1201 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1202 if (ret_val)
1203 return ret_val;
1204
1205 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1206 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1207
1208 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1209 if (ret_val)
1210 return ret_val;
1211
1212 e_dbg("IGP PSCR: %X\n", phy_data);
1213
1214 udelay(1);
1215
1216 if (phy->autoneg_wait_to_complete) {
1217 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1218
1219 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1220 100000, &link);
1221 if (ret_val)
1222 return ret_val;
1223
1224 if (!link)
1225 e_dbg("Link taking longer than expected.\n");
1226
1227 /* Try once more */
1228 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1229 100000, &link);
1230 }
1231
1232 return ret_val;
1233 }
1234
1235 /**
1236 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1237 * @hw: pointer to the HW structure
1238 *
1239 * Calls the PHY setup function to force speed and duplex. Clears the
1240 * auto-crossover to force MDI manually. Resets the PHY to commit the
1241 * changes. If time expires while waiting for link up, we reset the DSP.
1242 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1243 * successful completion, else return corresponding error code.
1244 **/
e1000e_phy_force_speed_duplex_m88(struct e1000_hw * hw)1245 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1246 {
1247 struct e1000_phy_info *phy = &hw->phy;
1248 s32 ret_val;
1249 u16 phy_data;
1250 bool link;
1251
1252 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1253 * forced whenever speed and duplex are forced.
1254 */
1255 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1256 if (ret_val)
1257 return ret_val;
1258
1259 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1260 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1261 if (ret_val)
1262 return ret_val;
1263
1264 e_dbg("M88E1000 PSCR: %X\n", phy_data);
1265
1266 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1267 if (ret_val)
1268 return ret_val;
1269
1270 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1271
1272 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1273 if (ret_val)
1274 return ret_val;
1275
1276 /* Reset the phy to commit changes. */
1277 if (hw->phy.ops.commit) {
1278 ret_val = hw->phy.ops.commit(hw);
1279 if (ret_val)
1280 return ret_val;
1281 }
1282
1283 if (phy->autoneg_wait_to_complete) {
1284 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1285
1286 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1287 100000, &link);
1288 if (ret_val)
1289 return ret_val;
1290
1291 if (!link) {
1292 if (hw->phy.type != e1000_phy_m88) {
1293 e_dbg("Link taking longer than expected.\n");
1294 } else {
1295 /* We didn't get link.
1296 * Reset the DSP and cross our fingers.
1297 */
1298 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
1299 0x001d);
1300 if (ret_val)
1301 return ret_val;
1302 ret_val = e1000e_phy_reset_dsp(hw);
1303 if (ret_val)
1304 return ret_val;
1305 }
1306 }
1307
1308 /* Try once more */
1309 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1310 100000, &link);
1311 if (ret_val)
1312 return ret_val;
1313 }
1314
1315 if (hw->phy.type != e1000_phy_m88)
1316 return 0;
1317
1318 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1319 if (ret_val)
1320 return ret_val;
1321
1322 /* Resetting the phy means we need to re-force TX_CLK in the
1323 * Extended PHY Specific Control Register to 25MHz clock from
1324 * the reset value of 2.5MHz.
1325 */
1326 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1327 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1328 if (ret_val)
1329 return ret_val;
1330
1331 /* In addition, we must re-enable CRS on Tx for both half and full
1332 * duplex.
1333 */
1334 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1335 if (ret_val)
1336 return ret_val;
1337
1338 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1339 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1340
1341 return ret_val;
1342 }
1343
1344 /**
1345 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1346 * @hw: pointer to the HW structure
1347 *
1348 * Forces the speed and duplex settings of the PHY.
1349 * This is a function pointer entry point only called by
1350 * PHY setup routines.
1351 **/
e1000_phy_force_speed_duplex_ife(struct e1000_hw * hw)1352 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1353 {
1354 struct e1000_phy_info *phy = &hw->phy;
1355 s32 ret_val;
1356 u16 data;
1357 bool link;
1358
1359 ret_val = e1e_rphy(hw, MII_BMCR, &data);
1360 if (ret_val)
1361 return ret_val;
1362
1363 e1000e_phy_force_speed_duplex_setup(hw, &data);
1364
1365 ret_val = e1e_wphy(hw, MII_BMCR, data);
1366 if (ret_val)
1367 return ret_val;
1368
1369 /* Disable MDI-X support for 10/100 */
1370 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1371 if (ret_val)
1372 return ret_val;
1373
1374 data &= ~IFE_PMC_AUTO_MDIX;
1375 data &= ~IFE_PMC_FORCE_MDIX;
1376
1377 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
1378 if (ret_val)
1379 return ret_val;
1380
1381 e_dbg("IFE PMC: %X\n", data);
1382
1383 udelay(1);
1384
1385 if (phy->autoneg_wait_to_complete) {
1386 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
1387
1388 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1389 100000, &link);
1390 if (ret_val)
1391 return ret_val;
1392
1393 if (!link)
1394 e_dbg("Link taking longer than expected.\n");
1395
1396 /* Try once more */
1397 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1398 100000, &link);
1399 if (ret_val)
1400 return ret_val;
1401 }
1402
1403 return 0;
1404 }
1405
1406 /**
1407 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1408 * @hw: pointer to the HW structure
1409 * @phy_ctrl: pointer to current value of MII_BMCR
1410 *
1411 * Forces speed and duplex on the PHY by doing the following: disable flow
1412 * control, force speed/duplex on the MAC, disable auto speed detection,
1413 * disable auto-negotiation, configure duplex, configure speed, configure
1414 * the collision distance, write configuration to CTRL register. The
1415 * caller must write to the MII_BMCR register for these settings to
1416 * take affect.
1417 **/
e1000e_phy_force_speed_duplex_setup(struct e1000_hw * hw,u16 * phy_ctrl)1418 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1419 {
1420 struct e1000_mac_info *mac = &hw->mac;
1421 u32 ctrl;
1422
1423 /* Turn off flow control when forcing speed/duplex */
1424 hw->fc.current_mode = e1000_fc_none;
1425
1426 /* Force speed/duplex on the mac */
1427 ctrl = er32(CTRL);
1428 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1429 ctrl &= ~E1000_CTRL_SPD_SEL;
1430
1431 /* Disable Auto Speed Detection */
1432 ctrl &= ~E1000_CTRL_ASDE;
1433
1434 /* Disable autoneg on the phy */
1435 *phy_ctrl &= ~BMCR_ANENABLE;
1436
1437 /* Forcing Full or Half Duplex? */
1438 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1439 ctrl &= ~E1000_CTRL_FD;
1440 *phy_ctrl &= ~BMCR_FULLDPLX;
1441 e_dbg("Half Duplex\n");
1442 } else {
1443 ctrl |= E1000_CTRL_FD;
1444 *phy_ctrl |= BMCR_FULLDPLX;
1445 e_dbg("Full Duplex\n");
1446 }
1447
1448 /* Forcing 10mb or 100mb? */
1449 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1450 ctrl |= E1000_CTRL_SPD_100;
1451 *phy_ctrl |= BMCR_SPEED100;
1452 *phy_ctrl &= ~BMCR_SPEED1000;
1453 e_dbg("Forcing 100mb\n");
1454 } else {
1455 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1456 *phy_ctrl &= ~(BMCR_SPEED1000 | BMCR_SPEED100);
1457 e_dbg("Forcing 10mb\n");
1458 }
1459
1460 hw->mac.ops.config_collision_dist(hw);
1461
1462 ew32(CTRL, ctrl);
1463 }
1464
1465 /**
1466 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1467 * @hw: pointer to the HW structure
1468 * @active: boolean used to enable/disable lplu
1469 *
1470 * Success returns 0, Failure returns 1
1471 *
1472 * The low power link up (lplu) state is set to the power management level D3
1473 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1474 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1475 * is used during Dx states where the power conservation is most important.
1476 * During driver activity, SmartSpeed should be enabled so performance is
1477 * maintained.
1478 **/
e1000e_set_d3_lplu_state(struct e1000_hw * hw,bool active)1479 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1480 {
1481 struct e1000_phy_info *phy = &hw->phy;
1482 s32 ret_val;
1483 u16 data;
1484
1485 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1486 if (ret_val)
1487 return ret_val;
1488
1489 if (!active) {
1490 data &= ~IGP02E1000_PM_D3_LPLU;
1491 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1492 if (ret_val)
1493 return ret_val;
1494 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1495 * during Dx states where the power conservation is most
1496 * important. During driver activity we should enable
1497 * SmartSpeed, so performance is maintained.
1498 */
1499 if (phy->smart_speed == e1000_smart_speed_on) {
1500 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1501 &data);
1502 if (ret_val)
1503 return ret_val;
1504
1505 data |= IGP01E1000_PSCFR_SMART_SPEED;
1506 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1507 data);
1508 if (ret_val)
1509 return ret_val;
1510 } else if (phy->smart_speed == e1000_smart_speed_off) {
1511 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1512 &data);
1513 if (ret_val)
1514 return ret_val;
1515
1516 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1517 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1518 data);
1519 if (ret_val)
1520 return ret_val;
1521 }
1522 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1523 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1524 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1525 data |= IGP02E1000_PM_D3_LPLU;
1526 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1527 if (ret_val)
1528 return ret_val;
1529
1530 /* When LPLU is enabled, we should disable SmartSpeed */
1531 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1532 if (ret_val)
1533 return ret_val;
1534
1535 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1536 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1537 }
1538
1539 return ret_val;
1540 }
1541
1542 /**
1543 * e1000e_check_downshift - Checks whether a downshift in speed occurred
1544 * @hw: pointer to the HW structure
1545 *
1546 * Success returns 0, Failure returns 1
1547 *
1548 * A downshift is detected by querying the PHY link health.
1549 **/
e1000e_check_downshift(struct e1000_hw * hw)1550 s32 e1000e_check_downshift(struct e1000_hw *hw)
1551 {
1552 struct e1000_phy_info *phy = &hw->phy;
1553 s32 ret_val;
1554 u16 phy_data, offset, mask;
1555
1556 switch (phy->type) {
1557 case e1000_phy_m88:
1558 case e1000_phy_gg82563:
1559 case e1000_phy_bm:
1560 case e1000_phy_82578:
1561 offset = M88E1000_PHY_SPEC_STATUS;
1562 mask = M88E1000_PSSR_DOWNSHIFT;
1563 break;
1564 case e1000_phy_igp_2:
1565 case e1000_phy_igp_3:
1566 offset = IGP01E1000_PHY_LINK_HEALTH;
1567 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1568 break;
1569 default:
1570 /* speed downshift not supported */
1571 phy->speed_downgraded = false;
1572 return 0;
1573 }
1574
1575 ret_val = e1e_rphy(hw, offset, &phy_data);
1576
1577 if (!ret_val)
1578 phy->speed_downgraded = !!(phy_data & mask);
1579
1580 return ret_val;
1581 }
1582
1583 /**
1584 * e1000_check_polarity_m88 - Checks the polarity.
1585 * @hw: pointer to the HW structure
1586 *
1587 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1588 *
1589 * Polarity is determined based on the PHY specific status register.
1590 **/
e1000_check_polarity_m88(struct e1000_hw * hw)1591 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1592 {
1593 struct e1000_phy_info *phy = &hw->phy;
1594 s32 ret_val;
1595 u16 data;
1596
1597 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1598
1599 if (!ret_val)
1600 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
1601 ? e1000_rev_polarity_reversed
1602 : e1000_rev_polarity_normal);
1603
1604 return ret_val;
1605 }
1606
1607 /**
1608 * e1000_check_polarity_igp - Checks the polarity.
1609 * @hw: pointer to the HW structure
1610 *
1611 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1612 *
1613 * Polarity is determined based on the PHY port status register, and the
1614 * current speed (since there is no polarity at 100Mbps).
1615 **/
e1000_check_polarity_igp(struct e1000_hw * hw)1616 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1617 {
1618 struct e1000_phy_info *phy = &hw->phy;
1619 s32 ret_val;
1620 u16 data, offset, mask;
1621
1622 /* Polarity is determined based on the speed of
1623 * our connection.
1624 */
1625 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1626 if (ret_val)
1627 return ret_val;
1628
1629 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1630 IGP01E1000_PSSR_SPEED_1000MBPS) {
1631 offset = IGP01E1000_PHY_PCS_INIT_REG;
1632 mask = IGP01E1000_PHY_POLARITY_MASK;
1633 } else {
1634 /* This really only applies to 10Mbps since
1635 * there is no polarity for 100Mbps (always 0).
1636 */
1637 offset = IGP01E1000_PHY_PORT_STATUS;
1638 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1639 }
1640
1641 ret_val = e1e_rphy(hw, offset, &data);
1642
1643 if (!ret_val)
1644 phy->cable_polarity = ((data & mask)
1645 ? e1000_rev_polarity_reversed
1646 : e1000_rev_polarity_normal);
1647
1648 return ret_val;
1649 }
1650
1651 /**
1652 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1653 * @hw: pointer to the HW structure
1654 *
1655 * Polarity is determined on the polarity reversal feature being enabled.
1656 **/
e1000_check_polarity_ife(struct e1000_hw * hw)1657 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1658 {
1659 struct e1000_phy_info *phy = &hw->phy;
1660 s32 ret_val;
1661 u16 phy_data, offset, mask;
1662
1663 /* Polarity is determined based on the reversal feature being enabled.
1664 */
1665 if (phy->polarity_correction) {
1666 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1667 mask = IFE_PESC_POLARITY_REVERSED;
1668 } else {
1669 offset = IFE_PHY_SPECIAL_CONTROL;
1670 mask = IFE_PSC_FORCE_POLARITY;
1671 }
1672
1673 ret_val = e1e_rphy(hw, offset, &phy_data);
1674
1675 if (!ret_val)
1676 phy->cable_polarity = ((phy_data & mask)
1677 ? e1000_rev_polarity_reversed
1678 : e1000_rev_polarity_normal);
1679
1680 return ret_val;
1681 }
1682
1683 /**
1684 * e1000_wait_autoneg - Wait for auto-neg completion
1685 * @hw: pointer to the HW structure
1686 *
1687 * Waits for auto-negotiation to complete or for the auto-negotiation time
1688 * limit to expire, which ever happens first.
1689 **/
e1000_wait_autoneg(struct e1000_hw * hw)1690 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1691 {
1692 s32 ret_val = 0;
1693 u16 i, phy_status;
1694
1695 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1696 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1697 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1698 if (ret_val)
1699 break;
1700 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1701 if (ret_val)
1702 break;
1703 if (phy_status & BMSR_ANEGCOMPLETE)
1704 break;
1705 msleep(100);
1706 }
1707
1708 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1709 * has completed.
1710 */
1711 return ret_val;
1712 }
1713
1714 /**
1715 * e1000e_phy_has_link_generic - Polls PHY for link
1716 * @hw: pointer to the HW structure
1717 * @iterations: number of times to poll for link
1718 * @usec_interval: delay between polling attempts
1719 * @success: pointer to whether polling was successful or not
1720 *
1721 * Polls the PHY status register for link, 'iterations' number of times.
1722 **/
e1000e_phy_has_link_generic(struct e1000_hw * hw,u32 iterations,u32 usec_interval,bool * success)1723 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1724 u32 usec_interval, bool *success)
1725 {
1726 s32 ret_val = 0;
1727 u16 i, phy_status;
1728
1729 *success = false;
1730 for (i = 0; i < iterations; i++) {
1731 /* Some PHYs require the MII_BMSR register to be read
1732 * twice due to the link bit being sticky. No harm doing
1733 * it across the board.
1734 */
1735 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1736 if (ret_val) {
1737 /* If the first read fails, another entity may have
1738 * ownership of the resources, wait and try again to
1739 * see if they have relinquished the resources yet.
1740 */
1741 if (usec_interval >= 1000)
1742 msleep(usec_interval / 1000);
1743 else
1744 udelay(usec_interval);
1745 }
1746 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1747 if (ret_val)
1748 break;
1749 if (phy_status & BMSR_LSTATUS) {
1750 *success = true;
1751 break;
1752 }
1753 if (usec_interval >= 1000)
1754 msleep(usec_interval / 1000);
1755 else
1756 udelay(usec_interval);
1757 }
1758
1759 return ret_val;
1760 }
1761
1762 /**
1763 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1764 * @hw: pointer to the HW structure
1765 *
1766 * Reads the PHY specific status register to retrieve the cable length
1767 * information. The cable length is determined by averaging the minimum and
1768 * maximum values to get the "average" cable length. The m88 PHY has four
1769 * possible cable length values, which are:
1770 * Register Value Cable Length
1771 * 0 < 50 meters
1772 * 1 50 - 80 meters
1773 * 2 80 - 110 meters
1774 * 3 110 - 140 meters
1775 * 4 > 140 meters
1776 **/
e1000e_get_cable_length_m88(struct e1000_hw * hw)1777 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1778 {
1779 struct e1000_phy_info *phy = &hw->phy;
1780 s32 ret_val;
1781 u16 phy_data, index;
1782
1783 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1784 if (ret_val)
1785 return ret_val;
1786
1787 index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1788 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
1789
1790 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
1791 return -E1000_ERR_PHY;
1792
1793 phy->min_cable_length = e1000_m88_cable_length_table[index];
1794 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1795
1796 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1797
1798 return 0;
1799 }
1800
1801 /**
1802 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1803 * @hw: pointer to the HW structure
1804 *
1805 * The automatic gain control (agc) normalizes the amplitude of the
1806 * received signal, adjusting for the attenuation produced by the
1807 * cable. By reading the AGC registers, which represent the
1808 * combination of coarse and fine gain value, the value can be put
1809 * into a lookup table to obtain the approximate cable length
1810 * for each channel.
1811 **/
e1000e_get_cable_length_igp_2(struct e1000_hw * hw)1812 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1813 {
1814 struct e1000_phy_info *phy = &hw->phy;
1815 s32 ret_val;
1816 u16 phy_data, i, agc_value = 0;
1817 u16 cur_agc_index, max_agc_index = 0;
1818 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1819 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1820 IGP02E1000_PHY_AGC_A,
1821 IGP02E1000_PHY_AGC_B,
1822 IGP02E1000_PHY_AGC_C,
1823 IGP02E1000_PHY_AGC_D
1824 };
1825
1826 /* Read the AGC registers for all channels */
1827 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1828 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1829 if (ret_val)
1830 return ret_val;
1831
1832 /* Getting bits 15:9, which represent the combination of
1833 * coarse and fine gain values. The result is a number
1834 * that can be put into the lookup table to obtain the
1835 * approximate cable length.
1836 */
1837 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1838 IGP02E1000_AGC_LENGTH_MASK);
1839
1840 /* Array index bound check. */
1841 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1842 (cur_agc_index == 0))
1843 return -E1000_ERR_PHY;
1844
1845 /* Remove min & max AGC values from calculation. */
1846 if (e1000_igp_2_cable_length_table[min_agc_index] >
1847 e1000_igp_2_cable_length_table[cur_agc_index])
1848 min_agc_index = cur_agc_index;
1849 if (e1000_igp_2_cable_length_table[max_agc_index] <
1850 e1000_igp_2_cable_length_table[cur_agc_index])
1851 max_agc_index = cur_agc_index;
1852
1853 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1854 }
1855
1856 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1857 e1000_igp_2_cable_length_table[max_agc_index]);
1858 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1859
1860 /* Calculate cable length with the error range of +/- 10 meters. */
1861 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1862 (agc_value - IGP02E1000_AGC_RANGE) : 0);
1863 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1864
1865 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1866
1867 return 0;
1868 }
1869
1870 /**
1871 * e1000e_get_phy_info_m88 - Retrieve PHY information
1872 * @hw: pointer to the HW structure
1873 *
1874 * Valid for only copper links. Read the PHY status register (sticky read)
1875 * to verify that link is up. Read the PHY special control register to
1876 * determine the polarity and 10base-T extended distance. Read the PHY
1877 * special status register to determine MDI/MDIx and current speed. If
1878 * speed is 1000, then determine cable length, local and remote receiver.
1879 **/
e1000e_get_phy_info_m88(struct e1000_hw * hw)1880 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1881 {
1882 struct e1000_phy_info *phy = &hw->phy;
1883 s32 ret_val;
1884 u16 phy_data;
1885 bool link;
1886
1887 if (phy->media_type != e1000_media_type_copper) {
1888 e_dbg("Phy info is only valid for copper media\n");
1889 return -E1000_ERR_CONFIG;
1890 }
1891
1892 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1893 if (ret_val)
1894 return ret_val;
1895
1896 if (!link) {
1897 e_dbg("Phy info is only valid if link is up\n");
1898 return -E1000_ERR_CONFIG;
1899 }
1900
1901 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1902 if (ret_val)
1903 return ret_val;
1904
1905 phy->polarity_correction = !!(phy_data &
1906 M88E1000_PSCR_POLARITY_REVERSAL);
1907
1908 ret_val = e1000_check_polarity_m88(hw);
1909 if (ret_val)
1910 return ret_val;
1911
1912 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1913 if (ret_val)
1914 return ret_val;
1915
1916 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
1917
1918 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1919 ret_val = hw->phy.ops.get_cable_length(hw);
1920 if (ret_val)
1921 return ret_val;
1922
1923 ret_val = e1e_rphy(hw, MII_STAT1000, &phy_data);
1924 if (ret_val)
1925 return ret_val;
1926
1927 phy->local_rx = (phy_data & LPA_1000LOCALRXOK)
1928 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1929
1930 phy->remote_rx = (phy_data & LPA_1000REMRXOK)
1931 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1932 } else {
1933 /* Set values to "undefined" */
1934 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1935 phy->local_rx = e1000_1000t_rx_status_undefined;
1936 phy->remote_rx = e1000_1000t_rx_status_undefined;
1937 }
1938
1939 return ret_val;
1940 }
1941
1942 /**
1943 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1944 * @hw: pointer to the HW structure
1945 *
1946 * Read PHY status to determine if link is up. If link is up, then
1947 * set/determine 10base-T extended distance and polarity correction. Read
1948 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1949 * determine on the cable length, local and remote receiver.
1950 **/
e1000e_get_phy_info_igp(struct e1000_hw * hw)1951 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
1952 {
1953 struct e1000_phy_info *phy = &hw->phy;
1954 s32 ret_val;
1955 u16 data;
1956 bool link;
1957
1958 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1959 if (ret_val)
1960 return ret_val;
1961
1962 if (!link) {
1963 e_dbg("Phy info is only valid if link is up\n");
1964 return -E1000_ERR_CONFIG;
1965 }
1966
1967 phy->polarity_correction = true;
1968
1969 ret_val = e1000_check_polarity_igp(hw);
1970 if (ret_val)
1971 return ret_val;
1972
1973 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1974 if (ret_val)
1975 return ret_val;
1976
1977 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
1978
1979 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1980 IGP01E1000_PSSR_SPEED_1000MBPS) {
1981 ret_val = phy->ops.get_cable_length(hw);
1982 if (ret_val)
1983 return ret_val;
1984
1985 ret_val = e1e_rphy(hw, MII_STAT1000, &data);
1986 if (ret_val)
1987 return ret_val;
1988
1989 phy->local_rx = (data & LPA_1000LOCALRXOK)
1990 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1991
1992 phy->remote_rx = (data & LPA_1000REMRXOK)
1993 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1994 } else {
1995 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1996 phy->local_rx = e1000_1000t_rx_status_undefined;
1997 phy->remote_rx = e1000_1000t_rx_status_undefined;
1998 }
1999
2000 return ret_val;
2001 }
2002
2003 /**
2004 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2005 * @hw: pointer to the HW structure
2006 *
2007 * Populates "phy" structure with various feature states.
2008 **/
e1000_get_phy_info_ife(struct e1000_hw * hw)2009 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2010 {
2011 struct e1000_phy_info *phy = &hw->phy;
2012 s32 ret_val;
2013 u16 data;
2014 bool link;
2015
2016 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2017 if (ret_val)
2018 return ret_val;
2019
2020 if (!link) {
2021 e_dbg("Phy info is only valid if link is up\n");
2022 return -E1000_ERR_CONFIG;
2023 }
2024
2025 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2026 if (ret_val)
2027 return ret_val;
2028 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2029
2030 if (phy->polarity_correction) {
2031 ret_val = e1000_check_polarity_ife(hw);
2032 if (ret_val)
2033 return ret_val;
2034 } else {
2035 /* Polarity is forced */
2036 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2037 ? e1000_rev_polarity_reversed
2038 : e1000_rev_polarity_normal);
2039 }
2040
2041 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
2042 if (ret_val)
2043 return ret_val;
2044
2045 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2046
2047 /* The following parameters are undefined for 10/100 operation. */
2048 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2049 phy->local_rx = e1000_1000t_rx_status_undefined;
2050 phy->remote_rx = e1000_1000t_rx_status_undefined;
2051
2052 return 0;
2053 }
2054
2055 /**
2056 * e1000e_phy_sw_reset - PHY software reset
2057 * @hw: pointer to the HW structure
2058 *
2059 * Does a software reset of the PHY by reading the PHY control register and
2060 * setting/write the control register reset bit to the PHY.
2061 **/
e1000e_phy_sw_reset(struct e1000_hw * hw)2062 s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
2063 {
2064 s32 ret_val;
2065 u16 phy_ctrl;
2066
2067 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl);
2068 if (ret_val)
2069 return ret_val;
2070
2071 phy_ctrl |= BMCR_RESET;
2072 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl);
2073 if (ret_val)
2074 return ret_val;
2075
2076 udelay(1);
2077
2078 return ret_val;
2079 }
2080
2081 /**
2082 * e1000e_phy_hw_reset_generic - PHY hardware reset
2083 * @hw: pointer to the HW structure
2084 *
2085 * Verify the reset block is not blocking us from resetting. Acquire
2086 * semaphore (if necessary) and read/set/write the device control reset
2087 * bit in the PHY. Wait the appropriate delay time for the device to
2088 * reset and release the semaphore (if necessary).
2089 **/
e1000e_phy_hw_reset_generic(struct e1000_hw * hw)2090 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
2091 {
2092 struct e1000_phy_info *phy = &hw->phy;
2093 s32 ret_val;
2094 u32 ctrl;
2095
2096 if (phy->ops.check_reset_block) {
2097 ret_val = phy->ops.check_reset_block(hw);
2098 if (ret_val)
2099 return 0;
2100 }
2101
2102 ret_val = phy->ops.acquire(hw);
2103 if (ret_val)
2104 return ret_val;
2105
2106 ctrl = er32(CTRL);
2107 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
2108 e1e_flush();
2109
2110 udelay(phy->reset_delay_us);
2111
2112 ew32(CTRL, ctrl);
2113 e1e_flush();
2114
2115 usleep_range(150, 300);
2116
2117 phy->ops.release(hw);
2118
2119 return phy->ops.get_cfg_done(hw);
2120 }
2121
2122 /**
2123 * e1000e_get_cfg_done_generic - Generic configuration done
2124 * @hw: pointer to the HW structure
2125 *
2126 * Generic function to wait 10 milli-seconds for configuration to complete
2127 * and return success.
2128 **/
e1000e_get_cfg_done_generic(struct e1000_hw __always_unused * hw)2129 s32 e1000e_get_cfg_done_generic(struct e1000_hw __always_unused *hw)
2130 {
2131 mdelay(10);
2132
2133 return 0;
2134 }
2135
2136 /**
2137 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
2138 * @hw: pointer to the HW structure
2139 *
2140 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2141 **/
e1000e_phy_init_script_igp3(struct e1000_hw * hw)2142 s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
2143 {
2144 e_dbg("Running IGP 3 PHY init script\n");
2145
2146 /* PHY init IGP 3 */
2147 /* Enable rise/fall, 10-mode work in class-A */
2148 e1e_wphy(hw, 0x2F5B, 0x9018);
2149 /* Remove all caps from Replica path filter */
2150 e1e_wphy(hw, 0x2F52, 0x0000);
2151 /* Bias trimming for ADC, AFE and Driver (Default) */
2152 e1e_wphy(hw, 0x2FB1, 0x8B24);
2153 /* Increase Hybrid poly bias */
2154 e1e_wphy(hw, 0x2FB2, 0xF8F0);
2155 /* Add 4% to Tx amplitude in Gig mode */
2156 e1e_wphy(hw, 0x2010, 0x10B0);
2157 /* Disable trimming (TTT) */
2158 e1e_wphy(hw, 0x2011, 0x0000);
2159 /* Poly DC correction to 94.6% + 2% for all channels */
2160 e1e_wphy(hw, 0x20DD, 0x249A);
2161 /* ABS DC correction to 95.9% */
2162 e1e_wphy(hw, 0x20DE, 0x00D3);
2163 /* BG temp curve trim */
2164 e1e_wphy(hw, 0x28B4, 0x04CE);
2165 /* Increasing ADC OPAMP stage 1 currents to max */
2166 e1e_wphy(hw, 0x2F70, 0x29E4);
2167 /* Force 1000 ( required for enabling PHY regs configuration) */
2168 e1e_wphy(hw, 0x0000, 0x0140);
2169 /* Set upd_freq to 6 */
2170 e1e_wphy(hw, 0x1F30, 0x1606);
2171 /* Disable NPDFE */
2172 e1e_wphy(hw, 0x1F31, 0xB814);
2173 /* Disable adaptive fixed FFE (Default) */
2174 e1e_wphy(hw, 0x1F35, 0x002A);
2175 /* Enable FFE hysteresis */
2176 e1e_wphy(hw, 0x1F3E, 0x0067);
2177 /* Fixed FFE for short cable lengths */
2178 e1e_wphy(hw, 0x1F54, 0x0065);
2179 /* Fixed FFE for medium cable lengths */
2180 e1e_wphy(hw, 0x1F55, 0x002A);
2181 /* Fixed FFE for long cable lengths */
2182 e1e_wphy(hw, 0x1F56, 0x002A);
2183 /* Enable Adaptive Clip Threshold */
2184 e1e_wphy(hw, 0x1F72, 0x3FB0);
2185 /* AHT reset limit to 1 */
2186 e1e_wphy(hw, 0x1F76, 0xC0FF);
2187 /* Set AHT master delay to 127 msec */
2188 e1e_wphy(hw, 0x1F77, 0x1DEC);
2189 /* Set scan bits for AHT */
2190 e1e_wphy(hw, 0x1F78, 0xF9EF);
2191 /* Set AHT Preset bits */
2192 e1e_wphy(hw, 0x1F79, 0x0210);
2193 /* Change integ_factor of channel A to 3 */
2194 e1e_wphy(hw, 0x1895, 0x0003);
2195 /* Change prop_factor of channels BCD to 8 */
2196 e1e_wphy(hw, 0x1796, 0x0008);
2197 /* Change cg_icount + enable integbp for channels BCD */
2198 e1e_wphy(hw, 0x1798, 0xD008);
2199 /* Change cg_icount + enable integbp + change prop_factor_master
2200 * to 8 for channel A
2201 */
2202 e1e_wphy(hw, 0x1898, 0xD918);
2203 /* Disable AHT in Slave mode on channel A */
2204 e1e_wphy(hw, 0x187A, 0x0800);
2205 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2206 * Enable SPD+B2B
2207 */
2208 e1e_wphy(hw, 0x0019, 0x008D);
2209 /* Enable restart AN on an1000_dis change */
2210 e1e_wphy(hw, 0x001B, 0x2080);
2211 /* Enable wh_fifo read clock in 10/100 modes */
2212 e1e_wphy(hw, 0x0014, 0x0045);
2213 /* Restart AN, Speed selection is 1000 */
2214 e1e_wphy(hw, 0x0000, 0x1340);
2215
2216 return 0;
2217 }
2218
2219 /**
2220 * e1000e_get_phy_type_from_id - Get PHY type from id
2221 * @phy_id: phy_id read from the phy
2222 *
2223 * Returns the phy type from the id.
2224 **/
e1000e_get_phy_type_from_id(u32 phy_id)2225 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
2226 {
2227 enum e1000_phy_type phy_type = e1000_phy_unknown;
2228
2229 switch (phy_id) {
2230 case M88E1000_I_PHY_ID:
2231 case M88E1000_E_PHY_ID:
2232 case M88E1111_I_PHY_ID:
2233 case M88E1011_I_PHY_ID:
2234 phy_type = e1000_phy_m88;
2235 break;
2236 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2237 phy_type = e1000_phy_igp_2;
2238 break;
2239 case GG82563_E_PHY_ID:
2240 phy_type = e1000_phy_gg82563;
2241 break;
2242 case IGP03E1000_E_PHY_ID:
2243 phy_type = e1000_phy_igp_3;
2244 break;
2245 case IFE_E_PHY_ID:
2246 case IFE_PLUS_E_PHY_ID:
2247 case IFE_C_E_PHY_ID:
2248 phy_type = e1000_phy_ife;
2249 break;
2250 case BME1000_E_PHY_ID:
2251 case BME1000_E_PHY_ID_R2:
2252 phy_type = e1000_phy_bm;
2253 break;
2254 case I82578_E_PHY_ID:
2255 phy_type = e1000_phy_82578;
2256 break;
2257 case I82577_E_PHY_ID:
2258 phy_type = e1000_phy_82577;
2259 break;
2260 case I82579_E_PHY_ID:
2261 phy_type = e1000_phy_82579;
2262 break;
2263 case I217_E_PHY_ID:
2264 phy_type = e1000_phy_i217;
2265 break;
2266 default:
2267 phy_type = e1000_phy_unknown;
2268 break;
2269 }
2270 return phy_type;
2271 }
2272
2273 /**
2274 * e1000e_determine_phy_address - Determines PHY address.
2275 * @hw: pointer to the HW structure
2276 *
2277 * This uses a trial and error method to loop through possible PHY
2278 * addresses. It tests each by reading the PHY ID registers and
2279 * checking for a match.
2280 **/
e1000e_determine_phy_address(struct e1000_hw * hw)2281 s32 e1000e_determine_phy_address(struct e1000_hw *hw)
2282 {
2283 u32 phy_addr = 0;
2284 u32 i;
2285 enum e1000_phy_type phy_type = e1000_phy_unknown;
2286
2287 hw->phy.id = phy_type;
2288
2289 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2290 hw->phy.addr = phy_addr;
2291 i = 0;
2292
2293 do {
2294 e1000e_get_phy_id(hw);
2295 phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
2296
2297 /* If phy_type is valid, break - we found our
2298 * PHY address
2299 */
2300 if (phy_type != e1000_phy_unknown)
2301 return 0;
2302
2303 usleep_range(1000, 2000);
2304 i++;
2305 } while (i < 10);
2306 }
2307
2308 return -E1000_ERR_PHY_TYPE;
2309 }
2310
2311 /**
2312 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2313 * @page: page to access
2314 *
2315 * Returns the phy address for the page requested.
2316 **/
e1000_get_phy_addr_for_bm_page(u32 page,u32 reg)2317 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2318 {
2319 u32 phy_addr = 2;
2320
2321 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2322 phy_addr = 1;
2323
2324 return phy_addr;
2325 }
2326
2327 /**
2328 * e1000e_write_phy_reg_bm - Write BM PHY register
2329 * @hw: pointer to the HW structure
2330 * @offset: register offset to write to
2331 * @data: data to write at register offset
2332 *
2333 * Acquires semaphore, if necessary, then writes the data to PHY register
2334 * at the offset. Release any acquired semaphores before exiting.
2335 **/
e1000e_write_phy_reg_bm(struct e1000_hw * hw,u32 offset,u16 data)2336 s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2337 {
2338 s32 ret_val;
2339 u32 page = offset >> IGP_PAGE_SHIFT;
2340
2341 ret_val = hw->phy.ops.acquire(hw);
2342 if (ret_val)
2343 return ret_val;
2344
2345 /* Page 800 works differently than the rest so it has its own func */
2346 if (page == BM_WUC_PAGE) {
2347 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2348 false, false);
2349 goto release;
2350 }
2351
2352 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2353
2354 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2355 u32 page_shift, page_select;
2356
2357 /* Page select is register 31 for phy address 1 and 22 for
2358 * phy address 2 and 3. Page select is shifted only for
2359 * phy address 1.
2360 */
2361 if (hw->phy.addr == 1) {
2362 page_shift = IGP_PAGE_SHIFT;
2363 page_select = IGP01E1000_PHY_PAGE_SELECT;
2364 } else {
2365 page_shift = 0;
2366 page_select = BM_PHY_PAGE_SELECT;
2367 }
2368
2369 /* Page is shifted left, PHY expects (page x 32) */
2370 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2371 (page << page_shift));
2372 if (ret_val)
2373 goto release;
2374 }
2375
2376 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2377 data);
2378
2379 release:
2380 hw->phy.ops.release(hw);
2381 return ret_val;
2382 }
2383
2384 /**
2385 * e1000e_read_phy_reg_bm - Read BM PHY register
2386 * @hw: pointer to the HW structure
2387 * @offset: register offset to be read
2388 * @data: pointer to the read data
2389 *
2390 * Acquires semaphore, if necessary, then reads the PHY register at offset
2391 * and storing the retrieved information in data. Release any acquired
2392 * semaphores before exiting.
2393 **/
e1000e_read_phy_reg_bm(struct e1000_hw * hw,u32 offset,u16 * data)2394 s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2395 {
2396 s32 ret_val;
2397 u32 page = offset >> IGP_PAGE_SHIFT;
2398
2399 ret_val = hw->phy.ops.acquire(hw);
2400 if (ret_val)
2401 return ret_val;
2402
2403 /* Page 800 works differently than the rest so it has its own func */
2404 if (page == BM_WUC_PAGE) {
2405 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2406 true, false);
2407 goto release;
2408 }
2409
2410 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2411
2412 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2413 u32 page_shift, page_select;
2414
2415 /* Page select is register 31 for phy address 1 and 22 for
2416 * phy address 2 and 3. Page select is shifted only for
2417 * phy address 1.
2418 */
2419 if (hw->phy.addr == 1) {
2420 page_shift = IGP_PAGE_SHIFT;
2421 page_select = IGP01E1000_PHY_PAGE_SELECT;
2422 } else {
2423 page_shift = 0;
2424 page_select = BM_PHY_PAGE_SELECT;
2425 }
2426
2427 /* Page is shifted left, PHY expects (page x 32) */
2428 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2429 (page << page_shift));
2430 if (ret_val)
2431 goto release;
2432 }
2433
2434 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2435 data);
2436 release:
2437 hw->phy.ops.release(hw);
2438 return ret_val;
2439 }
2440
2441 /**
2442 * e1000e_read_phy_reg_bm2 - Read BM PHY register
2443 * @hw: pointer to the HW structure
2444 * @offset: register offset to be read
2445 * @data: pointer to the read data
2446 *
2447 * Acquires semaphore, if necessary, then reads the PHY register at offset
2448 * and storing the retrieved information in data. Release any acquired
2449 * semaphores before exiting.
2450 **/
e1000e_read_phy_reg_bm2(struct e1000_hw * hw,u32 offset,u16 * data)2451 s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2452 {
2453 s32 ret_val;
2454 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2455
2456 ret_val = hw->phy.ops.acquire(hw);
2457 if (ret_val)
2458 return ret_val;
2459
2460 /* Page 800 works differently than the rest so it has its own func */
2461 if (page == BM_WUC_PAGE) {
2462 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2463 true, false);
2464 goto release;
2465 }
2466
2467 hw->phy.addr = 1;
2468
2469 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2470 /* Page is shifted left, PHY expects (page x 32) */
2471 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2472 page);
2473
2474 if (ret_val)
2475 goto release;
2476 }
2477
2478 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2479 data);
2480 release:
2481 hw->phy.ops.release(hw);
2482 return ret_val;
2483 }
2484
2485 /**
2486 * e1000e_write_phy_reg_bm2 - Write BM PHY register
2487 * @hw: pointer to the HW structure
2488 * @offset: register offset to write to
2489 * @data: data to write at register offset
2490 *
2491 * Acquires semaphore, if necessary, then writes the data to PHY register
2492 * at the offset. Release any acquired semaphores before exiting.
2493 **/
e1000e_write_phy_reg_bm2(struct e1000_hw * hw,u32 offset,u16 data)2494 s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2495 {
2496 s32 ret_val;
2497 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2498
2499 ret_val = hw->phy.ops.acquire(hw);
2500 if (ret_val)
2501 return ret_val;
2502
2503 /* Page 800 works differently than the rest so it has its own func */
2504 if (page == BM_WUC_PAGE) {
2505 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2506 false, false);
2507 goto release;
2508 }
2509
2510 hw->phy.addr = 1;
2511
2512 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2513 /* Page is shifted left, PHY expects (page x 32) */
2514 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2515 page);
2516
2517 if (ret_val)
2518 goto release;
2519 }
2520
2521 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2522 data);
2523
2524 release:
2525 hw->phy.ops.release(hw);
2526 return ret_val;
2527 }
2528
2529 /**
2530 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
2531 * @hw: pointer to the HW structure
2532 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
2533 *
2534 * Assumes semaphore already acquired and phy_reg points to a valid memory
2535 * address to store contents of the BM_WUC_ENABLE_REG register.
2536 **/
e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw * hw,u16 * phy_reg)2537 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2538 {
2539 s32 ret_val;
2540 u16 temp;
2541
2542 /* All page select, port ctrl and wakeup registers use phy address 1 */
2543 hw->phy.addr = 1;
2544
2545 /* Select Port Control Registers page */
2546 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2547 if (ret_val) {
2548 e_dbg("Could not set Port Control page\n");
2549 return ret_val;
2550 }
2551
2552 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2553 if (ret_val) {
2554 e_dbg("Could not read PHY register %d.%d\n",
2555 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2556 return ret_val;
2557 }
2558
2559 /* Enable both PHY wakeup mode and Wakeup register page writes.
2560 * Prevent a power state change by disabling ME and Host PHY wakeup.
2561 */
2562 temp = *phy_reg;
2563 temp |= BM_WUC_ENABLE_BIT;
2564 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
2565
2566 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
2567 if (ret_val) {
2568 e_dbg("Could not write PHY register %d.%d\n",
2569 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2570 return ret_val;
2571 }
2572
2573 /* Select Host Wakeup Registers page - caller now able to write
2574 * registers on the Wakeup registers page
2575 */
2576 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
2577 }
2578
2579 /**
2580 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
2581 * @hw: pointer to the HW structure
2582 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
2583 *
2584 * Restore BM_WUC_ENABLE_REG to its original value.
2585 *
2586 * Assumes semaphore already acquired and *phy_reg is the contents of the
2587 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
2588 * caller.
2589 **/
e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw * hw,u16 * phy_reg)2590 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2591 {
2592 s32 ret_val;
2593
2594 /* Select Port Control Registers page */
2595 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2596 if (ret_val) {
2597 e_dbg("Could not set Port Control page\n");
2598 return ret_val;
2599 }
2600
2601 /* Restore 769.17 to its original value */
2602 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
2603 if (ret_val)
2604 e_dbg("Could not restore PHY register %d.%d\n",
2605 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2606
2607 return ret_val;
2608 }
2609
2610 /**
2611 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
2612 * @hw: pointer to the HW structure
2613 * @offset: register offset to be read or written
2614 * @data: pointer to the data to read or write
2615 * @read: determines if operation is read or write
2616 * @page_set: BM_WUC_PAGE already set and access enabled
2617 *
2618 * Read the PHY register at offset and store the retrieved information in
2619 * data, or write data to PHY register at offset. Note the procedure to
2620 * access the PHY wakeup registers is different than reading the other PHY
2621 * registers. It works as such:
2622 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
2623 * 2) Set page to 800 for host (801 if we were manageability)
2624 * 3) Write the address using the address opcode (0x11)
2625 * 4) Read or write the data using the data opcode (0x12)
2626 * 5) Restore 769.17.2 to its original value
2627 *
2628 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
2629 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
2630 *
2631 * Assumes semaphore is already acquired. When page_set==true, assumes
2632 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
2633 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
2634 **/
e1000_access_phy_wakeup_reg_bm(struct e1000_hw * hw,u32 offset,u16 * data,bool read,bool page_set)2635 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2636 u16 *data, bool read, bool page_set)
2637 {
2638 s32 ret_val;
2639 u16 reg = BM_PHY_REG_NUM(offset);
2640 u16 page = BM_PHY_REG_PAGE(offset);
2641 u16 phy_reg = 0;
2642
2643 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
2644 if ((hw->mac.type == e1000_pchlan) &&
2645 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2646 e_dbg("Attempting to access page %d while gig enabled.\n",
2647 page);
2648
2649 if (!page_set) {
2650 /* Enable access to PHY wakeup registers */
2651 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2652 if (ret_val) {
2653 e_dbg("Could not enable PHY wakeup reg access\n");
2654 return ret_val;
2655 }
2656 }
2657
2658 e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg);
2659
2660 /* Write the Wakeup register page offset value using opcode 0x11 */
2661 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2662 if (ret_val) {
2663 e_dbg("Could not write address opcode to page %d\n", page);
2664 return ret_val;
2665 }
2666
2667 if (read) {
2668 /* Read the Wakeup register page value using opcode 0x12 */
2669 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2670 data);
2671 } else {
2672 /* Write the Wakeup register page value using opcode 0x12 */
2673 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2674 *data);
2675 }
2676
2677 if (ret_val) {
2678 e_dbg("Could not access PHY reg %d.%d\n", page, reg);
2679 return ret_val;
2680 }
2681
2682 if (!page_set)
2683 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2684
2685 return ret_val;
2686 }
2687
2688 /**
2689 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2690 * @hw: pointer to the HW structure
2691 *
2692 * In the case of a PHY power down to save power, or to turn off link during a
2693 * driver unload, or wake on lan is not enabled, restore the link to previous
2694 * settings.
2695 **/
e1000_power_up_phy_copper(struct e1000_hw * hw)2696 void e1000_power_up_phy_copper(struct e1000_hw *hw)
2697 {
2698 u16 mii_reg = 0;
2699
2700 /* The PHY will retain its settings across a power down/up cycle */
2701 e1e_rphy(hw, MII_BMCR, &mii_reg);
2702 mii_reg &= ~BMCR_PDOWN;
2703 e1e_wphy(hw, MII_BMCR, mii_reg);
2704 }
2705
2706 /**
2707 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2708 * @hw: pointer to the HW structure
2709 *
2710 * In the case of a PHY power down to save power, or to turn off link during a
2711 * driver unload, or wake on lan is not enabled, restore the link to previous
2712 * settings.
2713 **/
e1000_power_down_phy_copper(struct e1000_hw * hw)2714 void e1000_power_down_phy_copper(struct e1000_hw *hw)
2715 {
2716 u16 mii_reg = 0;
2717
2718 /* The PHY will retain its settings across a power down/up cycle */
2719 e1e_rphy(hw, MII_BMCR, &mii_reg);
2720 mii_reg |= BMCR_PDOWN;
2721 e1e_wphy(hw, MII_BMCR, mii_reg);
2722 usleep_range(1000, 2000);
2723 }
2724
2725 /**
2726 * __e1000_read_phy_reg_hv - Read HV PHY register
2727 * @hw: pointer to the HW structure
2728 * @offset: register offset to be read
2729 * @data: pointer to the read data
2730 * @locked: semaphore has already been acquired or not
2731 *
2732 * Acquires semaphore, if necessary, then reads the PHY register at offset
2733 * and stores the retrieved information in data. Release any acquired
2734 * semaphore before exiting.
2735 **/
__e1000_read_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 * data,bool locked,bool page_set)2736 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2737 bool locked, bool page_set)
2738 {
2739 s32 ret_val;
2740 u16 page = BM_PHY_REG_PAGE(offset);
2741 u16 reg = BM_PHY_REG_NUM(offset);
2742 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2743
2744 if (!locked) {
2745 ret_val = hw->phy.ops.acquire(hw);
2746 if (ret_val)
2747 return ret_val;
2748 }
2749
2750 /* Page 800 works differently than the rest so it has its own func */
2751 if (page == BM_WUC_PAGE) {
2752 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2753 true, page_set);
2754 goto out;
2755 }
2756
2757 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2758 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2759 data, true);
2760 goto out;
2761 }
2762
2763 if (!page_set) {
2764 if (page == HV_INTC_FC_PAGE_START)
2765 page = 0;
2766
2767 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2768 /* Page is shifted left, PHY expects (page x 32) */
2769 ret_val = e1000_set_page_igp(hw,
2770 (page << IGP_PAGE_SHIFT));
2771
2772 hw->phy.addr = phy_addr;
2773
2774 if (ret_val)
2775 goto out;
2776 }
2777 }
2778
2779 e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2780 page << IGP_PAGE_SHIFT, reg);
2781
2782 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, data);
2783 out:
2784 if (!locked)
2785 hw->phy.ops.release(hw);
2786
2787 return ret_val;
2788 }
2789
2790 /**
2791 * e1000_read_phy_reg_hv - Read HV PHY register
2792 * @hw: pointer to the HW structure
2793 * @offset: register offset to be read
2794 * @data: pointer to the read data
2795 *
2796 * Acquires semaphore then reads the PHY register at offset and stores
2797 * the retrieved information in data. Release the acquired semaphore
2798 * before exiting.
2799 **/
e1000_read_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 * data)2800 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2801 {
2802 return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
2803 }
2804
2805 /**
2806 * e1000_read_phy_reg_hv_locked - Read HV PHY register
2807 * @hw: pointer to the HW structure
2808 * @offset: register offset to be read
2809 * @data: pointer to the read data
2810 *
2811 * Reads the PHY register at offset and stores the retrieved information
2812 * in data. Assumes semaphore already acquired.
2813 **/
e1000_read_phy_reg_hv_locked(struct e1000_hw * hw,u32 offset,u16 * data)2814 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
2815 {
2816 return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
2817 }
2818
2819 /**
2820 * e1000_read_phy_reg_page_hv - Read HV PHY register
2821 * @hw: pointer to the HW structure
2822 * @offset: register offset to write to
2823 * @data: data to write at register offset
2824 *
2825 * Reads the PHY register at offset and stores the retrieved information
2826 * in data. Assumes semaphore already acquired and page already set.
2827 **/
e1000_read_phy_reg_page_hv(struct e1000_hw * hw,u32 offset,u16 * data)2828 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2829 {
2830 return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
2831 }
2832
2833 /**
2834 * __e1000_write_phy_reg_hv - Write HV PHY register
2835 * @hw: pointer to the HW structure
2836 * @offset: register offset to write to
2837 * @data: data to write at register offset
2838 * @locked: semaphore has already been acquired or not
2839 *
2840 * Acquires semaphore, if necessary, then writes the data to PHY register
2841 * at the offset. Release any acquired semaphores before exiting.
2842 **/
__e1000_write_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 data,bool locked,bool page_set)2843 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2844 bool locked, bool page_set)
2845 {
2846 s32 ret_val;
2847 u16 page = BM_PHY_REG_PAGE(offset);
2848 u16 reg = BM_PHY_REG_NUM(offset);
2849 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2850
2851 if (!locked) {
2852 ret_val = hw->phy.ops.acquire(hw);
2853 if (ret_val)
2854 return ret_val;
2855 }
2856
2857 /* Page 800 works differently than the rest so it has its own func */
2858 if (page == BM_WUC_PAGE) {
2859 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2860 false, page_set);
2861 goto out;
2862 }
2863
2864 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2865 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2866 &data, false);
2867 goto out;
2868 }
2869
2870 if (!page_set) {
2871 if (page == HV_INTC_FC_PAGE_START)
2872 page = 0;
2873
2874 /* Workaround MDIO accesses being disabled after entering IEEE
2875 * Power Down (when bit 11 of the PHY Control register is set)
2876 */
2877 if ((hw->phy.type == e1000_phy_82578) &&
2878 (hw->phy.revision >= 1) &&
2879 (hw->phy.addr == 2) &&
2880 !(MAX_PHY_REG_ADDRESS & reg) && (data & BIT(11))) {
2881 u16 data2 = 0x7EFF;
2882
2883 ret_val = e1000_access_phy_debug_regs_hv(hw,
2884 BIT(6) | 0x3,
2885 &data2, false);
2886 if (ret_val)
2887 goto out;
2888 }
2889
2890 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2891 /* Page is shifted left, PHY expects (page x 32) */
2892 ret_val = e1000_set_page_igp(hw,
2893 (page << IGP_PAGE_SHIFT));
2894
2895 hw->phy.addr = phy_addr;
2896
2897 if (ret_val)
2898 goto out;
2899 }
2900 }
2901
2902 e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2903 page << IGP_PAGE_SHIFT, reg);
2904
2905 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2906 data);
2907
2908 out:
2909 if (!locked)
2910 hw->phy.ops.release(hw);
2911
2912 return ret_val;
2913 }
2914
2915 /**
2916 * e1000_write_phy_reg_hv - Write HV PHY register
2917 * @hw: pointer to the HW structure
2918 * @offset: register offset to write to
2919 * @data: data to write at register offset
2920 *
2921 * Acquires semaphore then writes the data to PHY register at the offset.
2922 * Release the acquired semaphores before exiting.
2923 **/
e1000_write_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 data)2924 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
2925 {
2926 return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
2927 }
2928
2929 /**
2930 * e1000_write_phy_reg_hv_locked - Write HV PHY register
2931 * @hw: pointer to the HW structure
2932 * @offset: register offset to write to
2933 * @data: data to write at register offset
2934 *
2935 * Writes the data to PHY register at the offset. Assumes semaphore
2936 * already acquired.
2937 **/
e1000_write_phy_reg_hv_locked(struct e1000_hw * hw,u32 offset,u16 data)2938 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
2939 {
2940 return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
2941 }
2942
2943 /**
2944 * e1000_write_phy_reg_page_hv - Write HV PHY register
2945 * @hw: pointer to the HW structure
2946 * @offset: register offset to write to
2947 * @data: data to write at register offset
2948 *
2949 * Writes the data to PHY register at the offset. Assumes semaphore
2950 * already acquired and page already set.
2951 **/
e1000_write_phy_reg_page_hv(struct e1000_hw * hw,u32 offset,u16 data)2952 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
2953 {
2954 return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
2955 }
2956
2957 /**
2958 * e1000_get_phy_addr_for_hv_page - Get PHY address based on page
2959 * @page: page to be accessed
2960 **/
e1000_get_phy_addr_for_hv_page(u32 page)2961 static u32 e1000_get_phy_addr_for_hv_page(u32 page)
2962 {
2963 u32 phy_addr = 2;
2964
2965 if (page >= HV_INTC_FC_PAGE_START)
2966 phy_addr = 1;
2967
2968 return phy_addr;
2969 }
2970
2971 /**
2972 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
2973 * @hw: pointer to the HW structure
2974 * @offset: register offset to be read or written
2975 * @data: pointer to the data to be read or written
2976 * @read: determines if operation is read or write
2977 *
2978 * Reads the PHY register at offset and stores the retreived information
2979 * in data. Assumes semaphore already acquired. Note that the procedure
2980 * to access these regs uses the address port and data port to read/write.
2981 * These accesses done with PHY address 2 and without using pages.
2982 **/
e1000_access_phy_debug_regs_hv(struct e1000_hw * hw,u32 offset,u16 * data,bool read)2983 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
2984 u16 *data, bool read)
2985 {
2986 s32 ret_val;
2987 u32 addr_reg;
2988 u32 data_reg;
2989
2990 /* This takes care of the difference with desktop vs mobile phy */
2991 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
2992 I82578_ADDR_REG : I82577_ADDR_REG);
2993 data_reg = addr_reg + 1;
2994
2995 /* All operations in this function are phy address 2 */
2996 hw->phy.addr = 2;
2997
2998 /* masking with 0x3F to remove the page from offset */
2999 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3000 if (ret_val) {
3001 e_dbg("Could not write the Address Offset port register\n");
3002 return ret_val;
3003 }
3004
3005 /* Read or write the data value next */
3006 if (read)
3007 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data);
3008 else
3009 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
3010
3011 if (ret_val)
3012 e_dbg("Could not access the Data port register\n");
3013
3014 return ret_val;
3015 }
3016
3017 /**
3018 * e1000_link_stall_workaround_hv - Si workaround
3019 * @hw: pointer to the HW structure
3020 *
3021 * This function works around a Si bug where the link partner can get
3022 * a link up indication before the PHY does. If small packets are sent
3023 * by the link partner they can be placed in the packet buffer without
3024 * being properly accounted for by the PHY and will stall preventing
3025 * further packets from being received. The workaround is to clear the
3026 * packet buffer after the PHY detects link up.
3027 **/
e1000_link_stall_workaround_hv(struct e1000_hw * hw)3028 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3029 {
3030 s32 ret_val = 0;
3031 u16 data;
3032
3033 if (hw->phy.type != e1000_phy_82578)
3034 return 0;
3035
3036 /* Do not apply workaround if in PHY loopback bit 14 set */
3037 e1e_rphy(hw, MII_BMCR, &data);
3038 if (data & BMCR_LOOPBACK)
3039 return 0;
3040
3041 /* check if link is up and at 1Gbps */
3042 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data);
3043 if (ret_val)
3044 return ret_val;
3045
3046 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3047 BM_CS_STATUS_SPEED_MASK);
3048
3049 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3050 BM_CS_STATUS_SPEED_1000))
3051 return 0;
3052
3053 msleep(200);
3054
3055 /* flush the packets in the fifo buffer */
3056 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL,
3057 (HV_MUX_DATA_CTRL_GEN_TO_MAC |
3058 HV_MUX_DATA_CTRL_FORCE_SPEED));
3059 if (ret_val)
3060 return ret_val;
3061
3062 return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC);
3063 }
3064
3065 /**
3066 * e1000_check_polarity_82577 - Checks the polarity.
3067 * @hw: pointer to the HW structure
3068 *
3069 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3070 *
3071 * Polarity is determined based on the PHY specific status register.
3072 **/
e1000_check_polarity_82577(struct e1000_hw * hw)3073 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3074 {
3075 struct e1000_phy_info *phy = &hw->phy;
3076 s32 ret_val;
3077 u16 data;
3078
3079 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3080
3081 if (!ret_val)
3082 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3083 ? e1000_rev_polarity_reversed
3084 : e1000_rev_polarity_normal);
3085
3086 return ret_val;
3087 }
3088
3089 /**
3090 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3091 * @hw: pointer to the HW structure
3092 *
3093 * Calls the PHY setup function to force speed and duplex.
3094 **/
e1000_phy_force_speed_duplex_82577(struct e1000_hw * hw)3095 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3096 {
3097 struct e1000_phy_info *phy = &hw->phy;
3098 s32 ret_val;
3099 u16 phy_data;
3100 bool link;
3101
3102 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
3103 if (ret_val)
3104 return ret_val;
3105
3106 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
3107
3108 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
3109 if (ret_val)
3110 return ret_val;
3111
3112 udelay(1);
3113
3114 if (phy->autoneg_wait_to_complete) {
3115 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
3116
3117 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3118 100000, &link);
3119 if (ret_val)
3120 return ret_val;
3121
3122 if (!link)
3123 e_dbg("Link taking longer than expected.\n");
3124
3125 /* Try once more */
3126 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3127 100000, &link);
3128 }
3129
3130 return ret_val;
3131 }
3132
3133 /**
3134 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3135 * @hw: pointer to the HW structure
3136 *
3137 * Read PHY status to determine if link is up. If link is up, then
3138 * set/determine 10base-T extended distance and polarity correction. Read
3139 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3140 * determine on the cable length, local and remote receiver.
3141 **/
e1000_get_phy_info_82577(struct e1000_hw * hw)3142 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3143 {
3144 struct e1000_phy_info *phy = &hw->phy;
3145 s32 ret_val;
3146 u16 data;
3147 bool link;
3148
3149 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3150 if (ret_val)
3151 return ret_val;
3152
3153 if (!link) {
3154 e_dbg("Phy info is only valid if link is up\n");
3155 return -E1000_ERR_CONFIG;
3156 }
3157
3158 phy->polarity_correction = true;
3159
3160 ret_val = e1000_check_polarity_82577(hw);
3161 if (ret_val)
3162 return ret_val;
3163
3164 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3165 if (ret_val)
3166 return ret_val;
3167
3168 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3169
3170 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3171 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3172 ret_val = hw->phy.ops.get_cable_length(hw);
3173 if (ret_val)
3174 return ret_val;
3175
3176 ret_val = e1e_rphy(hw, MII_STAT1000, &data);
3177 if (ret_val)
3178 return ret_val;
3179
3180 phy->local_rx = (data & LPA_1000LOCALRXOK)
3181 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3182
3183 phy->remote_rx = (data & LPA_1000REMRXOK)
3184 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3185 } else {
3186 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3187 phy->local_rx = e1000_1000t_rx_status_undefined;
3188 phy->remote_rx = e1000_1000t_rx_status_undefined;
3189 }
3190
3191 return 0;
3192 }
3193
3194 /**
3195 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3196 * @hw: pointer to the HW structure
3197 *
3198 * Reads the diagnostic status register and verifies result is valid before
3199 * placing it in the phy_cable_length field.
3200 **/
e1000_get_cable_length_82577(struct e1000_hw * hw)3201 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3202 {
3203 struct e1000_phy_info *phy = &hw->phy;
3204 s32 ret_val;
3205 u16 phy_data, length;
3206
3207 ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3208 if (ret_val)
3209 return ret_val;
3210
3211 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
3212 I82577_DSTATUS_CABLE_LENGTH_SHIFT);
3213
3214 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3215 return -E1000_ERR_PHY;
3216
3217 phy->cable_length = length;
3218
3219 return 0;
3220 }
3221
