1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4 /* 80003ES2LAN Gigabit Ethernet Controller (Copper)
5 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
6 */
7
8 #include "e1000.h"
9
10 /* A table for the GG82563 cable length where the range is defined
11 * with a lower bound at "index" and the upper bound at
12 * "index + 5".
13 */
14 static const u16 e1000_gg82563_cable_length_table[] = {
15 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF
16 };
17
18 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
19 ARRAY_SIZE(e1000_gg82563_cable_length_table)
20
21 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
22 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
23 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
24 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
25 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
26 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
27 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
28 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
29 u16 *data);
30 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
31 u16 data);
32 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
33
34 /**
35 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
36 * @hw: pointer to the HW structure
37 **/
e1000_init_phy_params_80003es2lan(struct e1000_hw * hw)38 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
39 {
40 struct e1000_phy_info *phy = &hw->phy;
41 s32 ret_val;
42
43 if (hw->phy.media_type != e1000_media_type_copper) {
44 phy->type = e1000_phy_none;
45 return 0;
46 } else {
47 phy->ops.power_up = e1000_power_up_phy_copper;
48 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
49 }
50
51 phy->addr = 1;
52 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
53 phy->reset_delay_us = 100;
54 phy->type = e1000_phy_gg82563;
55
56 /* This can only be done after all function pointers are setup. */
57 ret_val = e1000e_get_phy_id(hw);
58
59 /* Verify phy id */
60 if (phy->id != GG82563_E_PHY_ID)
61 return -E1000_ERR_PHY;
62
63 return ret_val;
64 }
65
66 /**
67 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
68 * @hw: pointer to the HW structure
69 **/
e1000_init_nvm_params_80003es2lan(struct e1000_hw * hw)70 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
71 {
72 struct e1000_nvm_info *nvm = &hw->nvm;
73 u32 eecd = er32(EECD);
74 u16 size;
75
76 nvm->opcode_bits = 8;
77 nvm->delay_usec = 1;
78 switch (nvm->override) {
79 case e1000_nvm_override_spi_large:
80 nvm->page_size = 32;
81 nvm->address_bits = 16;
82 break;
83 case e1000_nvm_override_spi_small:
84 nvm->page_size = 8;
85 nvm->address_bits = 8;
86 break;
87 default:
88 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
89 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
90 break;
91 }
92
93 nvm->type = e1000_nvm_eeprom_spi;
94
95 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
96 E1000_EECD_SIZE_EX_SHIFT);
97
98 /* Added to a constant, "size" becomes the left-shift value
99 * for setting word_size.
100 */
101 size += NVM_WORD_SIZE_BASE_SHIFT;
102
103 /* EEPROM access above 16k is unsupported */
104 if (size > 14)
105 size = 14;
106 nvm->word_size = BIT(size);
107
108 return 0;
109 }
110
111 /**
112 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
113 * @hw: pointer to the HW structure
114 **/
e1000_init_mac_params_80003es2lan(struct e1000_hw * hw)115 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
116 {
117 struct e1000_mac_info *mac = &hw->mac;
118
119 /* Set media type and media-dependent function pointers */
120 switch (hw->adapter->pdev->device) {
121 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
122 hw->phy.media_type = e1000_media_type_internal_serdes;
123 mac->ops.check_for_link = e1000e_check_for_serdes_link;
124 mac->ops.setup_physical_interface =
125 e1000e_setup_fiber_serdes_link;
126 break;
127 default:
128 hw->phy.media_type = e1000_media_type_copper;
129 mac->ops.check_for_link = e1000e_check_for_copper_link;
130 mac->ops.setup_physical_interface =
131 e1000_setup_copper_link_80003es2lan;
132 break;
133 }
134
135 /* Set mta register count */
136 mac->mta_reg_count = 128;
137 /* Set rar entry count */
138 mac->rar_entry_count = E1000_RAR_ENTRIES;
139 /* FWSM register */
140 mac->has_fwsm = true;
141 /* ARC supported; valid only if manageability features are enabled. */
142 mac->arc_subsystem_valid = !!(er32(FWSM) & E1000_FWSM_MODE_MASK);
143 /* Adaptive IFS not supported */
144 mac->adaptive_ifs = false;
145
146 /* set lan id for port to determine which phy lock to use */
147 hw->mac.ops.set_lan_id(hw);
148
149 return 0;
150 }
151
e1000_get_variants_80003es2lan(struct e1000_adapter * adapter)152 static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
153 {
154 struct e1000_hw *hw = &adapter->hw;
155 s32 rc;
156
157 rc = e1000_init_mac_params_80003es2lan(hw);
158 if (rc)
159 return rc;
160
161 rc = e1000_init_nvm_params_80003es2lan(hw);
162 if (rc)
163 return rc;
164
165 rc = e1000_init_phy_params_80003es2lan(hw);
166 if (rc)
167 return rc;
168
169 return 0;
170 }
171
172 /**
173 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
174 * @hw: pointer to the HW structure
175 *
176 * A wrapper to acquire access rights to the correct PHY.
177 **/
e1000_acquire_phy_80003es2lan(struct e1000_hw * hw)178 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
179 {
180 u16 mask;
181
182 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
183 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
184 }
185
186 /**
187 * e1000_release_phy_80003es2lan - Release rights to access PHY
188 * @hw: pointer to the HW structure
189 *
190 * A wrapper to release access rights to the correct PHY.
191 **/
e1000_release_phy_80003es2lan(struct e1000_hw * hw)192 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
193 {
194 u16 mask;
195
196 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
197 e1000_release_swfw_sync_80003es2lan(hw, mask);
198 }
199
200 /**
201 * e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register
202 * @hw: pointer to the HW structure
203 *
204 * Acquire the semaphore to access the Kumeran interface.
205 *
206 **/
e1000_acquire_mac_csr_80003es2lan(struct e1000_hw * hw)207 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
208 {
209 u16 mask;
210
211 mask = E1000_SWFW_CSR_SM;
212
213 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
214 }
215
216 /**
217 * e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register
218 * @hw: pointer to the HW structure
219 *
220 * Release the semaphore used to access the Kumeran interface
221 **/
e1000_release_mac_csr_80003es2lan(struct e1000_hw * hw)222 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
223 {
224 u16 mask;
225
226 mask = E1000_SWFW_CSR_SM;
227
228 e1000_release_swfw_sync_80003es2lan(hw, mask);
229 }
230
231 /**
232 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
233 * @hw: pointer to the HW structure
234 *
235 * Acquire the semaphore to access the EEPROM.
236 **/
e1000_acquire_nvm_80003es2lan(struct e1000_hw * hw)237 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
238 {
239 s32 ret_val;
240
241 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
242 if (ret_val)
243 return ret_val;
244
245 ret_val = e1000e_acquire_nvm(hw);
246
247 if (ret_val)
248 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
249
250 return ret_val;
251 }
252
253 /**
254 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
255 * @hw: pointer to the HW structure
256 *
257 * Release the semaphore used to access the EEPROM.
258 **/
e1000_release_nvm_80003es2lan(struct e1000_hw * hw)259 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
260 {
261 e1000e_release_nvm(hw);
262 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
263 }
264
265 /**
266 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
267 * @hw: pointer to the HW structure
268 * @mask: specifies which semaphore to acquire
269 *
270 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
271 * will also specify which port we're acquiring the lock for.
272 **/
e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw * hw,u16 mask)273 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
274 {
275 u32 swfw_sync;
276 u32 swmask = mask;
277 u32 fwmask = mask << 16;
278 s32 i = 0;
279 s32 timeout = 50;
280
281 while (i < timeout) {
282 if (e1000e_get_hw_semaphore(hw))
283 return -E1000_ERR_SWFW_SYNC;
284
285 swfw_sync = er32(SW_FW_SYNC);
286 if (!(swfw_sync & (fwmask | swmask)))
287 break;
288
289 /* Firmware currently using resource (fwmask)
290 * or other software thread using resource (swmask)
291 */
292 e1000e_put_hw_semaphore(hw);
293 mdelay(5);
294 i++;
295 }
296
297 if (i == timeout) {
298 e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
299 return -E1000_ERR_SWFW_SYNC;
300 }
301
302 swfw_sync |= swmask;
303 ew32(SW_FW_SYNC, swfw_sync);
304
305 e1000e_put_hw_semaphore(hw);
306
307 return 0;
308 }
309
310 /**
311 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
312 * @hw: pointer to the HW structure
313 * @mask: specifies which semaphore to acquire
314 *
315 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
316 * will also specify which port we're releasing the lock for.
317 **/
e1000_release_swfw_sync_80003es2lan(struct e1000_hw * hw,u16 mask)318 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
319 {
320 u32 swfw_sync;
321
322 while (e1000e_get_hw_semaphore(hw) != 0)
323 ; /* Empty */
324
325 swfw_sync = er32(SW_FW_SYNC);
326 swfw_sync &= ~mask;
327 ew32(SW_FW_SYNC, swfw_sync);
328
329 e1000e_put_hw_semaphore(hw);
330 }
331
332 /**
333 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
334 * @hw: pointer to the HW structure
335 * @offset: offset of the register to read
336 * @data: pointer to the data returned from the operation
337 *
338 * Read the GG82563 PHY register.
339 **/
e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw * hw,u32 offset,u16 * data)340 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
341 u32 offset, u16 *data)
342 {
343 s32 ret_val;
344 u32 page_select;
345 u16 temp;
346
347 ret_val = e1000_acquire_phy_80003es2lan(hw);
348 if (ret_val)
349 return ret_val;
350
351 /* Select Configuration Page */
352 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
353 page_select = GG82563_PHY_PAGE_SELECT;
354 } else {
355 /* Use Alternative Page Select register to access
356 * registers 30 and 31
357 */
358 page_select = GG82563_PHY_PAGE_SELECT_ALT;
359 }
360
361 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
362 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
363 if (ret_val) {
364 e1000_release_phy_80003es2lan(hw);
365 return ret_val;
366 }
367
368 if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
369 /* The "ready" bit in the MDIC register may be incorrectly set
370 * before the device has completed the "Page Select" MDI
371 * transaction. So we wait 200us after each MDI command...
372 */
373 usleep_range(200, 400);
374
375 /* ...and verify the command was successful. */
376 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
377
378 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
379 e1000_release_phy_80003es2lan(hw);
380 return -E1000_ERR_PHY;
381 }
382
383 usleep_range(200, 400);
384
385 ret_val = e1000e_read_phy_reg_mdic(hw,
386 MAX_PHY_REG_ADDRESS & offset,
387 data);
388
389 usleep_range(200, 400);
390 } else {
391 ret_val = e1000e_read_phy_reg_mdic(hw,
392 MAX_PHY_REG_ADDRESS & offset,
393 data);
394 }
395
396 e1000_release_phy_80003es2lan(hw);
397
398 return ret_val;
399 }
400
401 /**
402 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
403 * @hw: pointer to the HW structure
404 * @offset: offset of the register to read
405 * @data: value to write to the register
406 *
407 * Write to the GG82563 PHY register.
408 **/
e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw * hw,u32 offset,u16 data)409 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
410 u32 offset, u16 data)
411 {
412 s32 ret_val;
413 u32 page_select;
414 u16 temp;
415
416 ret_val = e1000_acquire_phy_80003es2lan(hw);
417 if (ret_val)
418 return ret_val;
419
420 /* Select Configuration Page */
421 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
422 page_select = GG82563_PHY_PAGE_SELECT;
423 } else {
424 /* Use Alternative Page Select register to access
425 * registers 30 and 31
426 */
427 page_select = GG82563_PHY_PAGE_SELECT_ALT;
428 }
429
430 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
431 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
432 if (ret_val) {
433 e1000_release_phy_80003es2lan(hw);
434 return ret_val;
435 }
436
437 if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
438 /* The "ready" bit in the MDIC register may be incorrectly set
439 * before the device has completed the "Page Select" MDI
440 * transaction. So we wait 200us after each MDI command...
441 */
442 usleep_range(200, 400);
443
444 /* ...and verify the command was successful. */
445 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
446
447 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
448 e1000_release_phy_80003es2lan(hw);
449 return -E1000_ERR_PHY;
450 }
451
452 usleep_range(200, 400);
453
454 ret_val = e1000e_write_phy_reg_mdic(hw,
455 MAX_PHY_REG_ADDRESS &
456 offset, data);
457
458 usleep_range(200, 400);
459 } else {
460 ret_val = e1000e_write_phy_reg_mdic(hw,
461 MAX_PHY_REG_ADDRESS &
462 offset, data);
463 }
464
465 e1000_release_phy_80003es2lan(hw);
466
467 return ret_val;
468 }
469
470 /**
471 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM
472 * @hw: pointer to the HW structure
473 * @offset: offset of the register to read
474 * @words: number of words to write
475 * @data: buffer of data to write to the NVM
476 *
477 * Write "words" of data to the ESB2 NVM.
478 **/
e1000_write_nvm_80003es2lan(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)479 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
480 u16 words, u16 *data)
481 {
482 return e1000e_write_nvm_spi(hw, offset, words, data);
483 }
484
485 /**
486 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
487 * @hw: pointer to the HW structure
488 *
489 * Wait a specific amount of time for manageability processes to complete.
490 * This is a function pointer entry point called by the phy module.
491 **/
e1000_get_cfg_done_80003es2lan(struct e1000_hw * hw)492 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
493 {
494 s32 timeout = PHY_CFG_TIMEOUT;
495 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
496
497 if (hw->bus.func == 1)
498 mask = E1000_NVM_CFG_DONE_PORT_1;
499
500 while (timeout) {
501 if (er32(EEMNGCTL) & mask)
502 break;
503 usleep_range(1000, 2000);
504 timeout--;
505 }
506 if (!timeout) {
507 e_dbg("MNG configuration cycle has not completed.\n");
508 return -E1000_ERR_RESET;
509 }
510
511 return 0;
512 }
513
514 /**
515 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
516 * @hw: pointer to the HW structure
517 *
518 * Force the speed and duplex settings onto the PHY. This is a
519 * function pointer entry point called by the phy module.
520 **/
e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw * hw)521 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
522 {
523 s32 ret_val;
524 u16 phy_data;
525 bool link;
526
527 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
528 * forced whenever speed and duplex are forced.
529 */
530 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
531 if (ret_val)
532 return ret_val;
533
534 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
535 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
536 if (ret_val)
537 return ret_val;
538
539 e_dbg("GG82563 PSCR: %X\n", phy_data);
540
541 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
542 if (ret_val)
543 return ret_val;
544
545 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
546
547 /* Reset the phy to commit changes. */
548 phy_data |= BMCR_RESET;
549
550 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
551 if (ret_val)
552 return ret_val;
553
554 udelay(1);
555
556 if (hw->phy.autoneg_wait_to_complete) {
557 e_dbg("Waiting for forced speed/duplex link on GG82563 phy.\n");
558
559 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
560 100000, &link);
561 if (ret_val)
562 return ret_val;
563
564 if (!link) {
565 /* We didn't get link.
566 * Reset the DSP and cross our fingers.
567 */
568 ret_val = e1000e_phy_reset_dsp(hw);
569 if (ret_val)
570 return ret_val;
571 }
572
573 /* Try once more */
574 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
575 100000, &link);
576 if (ret_val)
577 return ret_val;
578 }
579
580 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
581 if (ret_val)
582 return ret_val;
583
584 /* Resetting the phy means we need to verify the TX_CLK corresponds
585 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
586 */
587 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
588 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
589 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
590 else
591 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
592
593 /* In addition, we must re-enable CRS on Tx for both half and full
594 * duplex.
595 */
596 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
597 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
598
599 return ret_val;
600 }
601
602 /**
603 * e1000_get_cable_length_80003es2lan - Set approximate cable length
604 * @hw: pointer to the HW structure
605 *
606 * Find the approximate cable length as measured by the GG82563 PHY.
607 * This is a function pointer entry point called by the phy module.
608 **/
e1000_get_cable_length_80003es2lan(struct e1000_hw * hw)609 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
610 {
611 struct e1000_phy_info *phy = &hw->phy;
612 s32 ret_val;
613 u16 phy_data, index;
614
615 ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
616 if (ret_val)
617 return ret_val;
618
619 index = phy_data & GG82563_DSPD_CABLE_LENGTH;
620
621 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5)
622 return -E1000_ERR_PHY;
623
624 phy->min_cable_length = e1000_gg82563_cable_length_table[index];
625 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
626
627 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
628
629 return 0;
630 }
631
632 /**
633 * e1000_get_link_up_info_80003es2lan - Report speed and duplex
634 * @hw: pointer to the HW structure
635 * @speed: pointer to speed buffer
636 * @duplex: pointer to duplex buffer
637 *
638 * Retrieve the current speed and duplex configuration.
639 **/
e1000_get_link_up_info_80003es2lan(struct e1000_hw * hw,u16 * speed,u16 * duplex)640 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
641 u16 *duplex)
642 {
643 s32 ret_val;
644
645 if (hw->phy.media_type == e1000_media_type_copper) {
646 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
647 hw->phy.ops.cfg_on_link_up(hw);
648 } else {
649 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
650 speed,
651 duplex);
652 }
653
654 return ret_val;
655 }
656
657 /**
658 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
659 * @hw: pointer to the HW structure
660 *
661 * Perform a global reset to the ESB2 controller.
662 **/
e1000_reset_hw_80003es2lan(struct e1000_hw * hw)663 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
664 {
665 u32 ctrl;
666 s32 ret_val;
667 u16 kum_reg_data;
668
669 /* Prevent the PCI-E bus from sticking if there is no TLP connection
670 * on the last TLP read/write transaction when MAC is reset.
671 */
672 ret_val = e1000e_disable_pcie_master(hw);
673 if (ret_val)
674 e_dbg("PCI-E Master disable polling has failed.\n");
675
676 e_dbg("Masking off all interrupts\n");
677 ew32(IMC, 0xffffffff);
678
679 ew32(RCTL, 0);
680 ew32(TCTL, E1000_TCTL_PSP);
681 e1e_flush();
682
683 usleep_range(10000, 20000);
684
685 ctrl = er32(CTRL);
686
687 ret_val = e1000_acquire_phy_80003es2lan(hw);
688 if (ret_val)
689 return ret_val;
690
691 e_dbg("Issuing a global reset to MAC\n");
692 ew32(CTRL, ctrl | E1000_CTRL_RST);
693 e1000_release_phy_80003es2lan(hw);
694
695 /* Disable IBIST slave mode (far-end loopback) */
696 ret_val =
697 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
698 &kum_reg_data);
699 if (ret_val)
700 return ret_val;
701 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
702 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
703 kum_reg_data);
704
705 ret_val = e1000e_get_auto_rd_done(hw);
706 if (ret_val)
707 /* We don't want to continue accessing MAC registers. */
708 return ret_val;
709
710 /* Clear any pending interrupt events. */
711 ew32(IMC, 0xffffffff);
712 er32(ICR);
713
714 return e1000_check_alt_mac_addr_generic(hw);
715 }
716
717 /**
718 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
719 * @hw: pointer to the HW structure
720 *
721 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
722 **/
e1000_init_hw_80003es2lan(struct e1000_hw * hw)723 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
724 {
725 struct e1000_mac_info *mac = &hw->mac;
726 u32 reg_data;
727 s32 ret_val;
728 u16 kum_reg_data;
729 u16 i;
730
731 e1000_initialize_hw_bits_80003es2lan(hw);
732
733 /* Initialize identification LED */
734 ret_val = mac->ops.id_led_init(hw);
735 /* An error is not fatal and we should not stop init due to this */
736 if (ret_val)
737 e_dbg("Error initializing identification LED\n");
738
739 /* Disabling VLAN filtering */
740 e_dbg("Initializing the IEEE VLAN\n");
741 mac->ops.clear_vfta(hw);
742
743 /* Setup the receive address. */
744 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
745
746 /* Zero out the Multicast HASH table */
747 e_dbg("Zeroing the MTA\n");
748 for (i = 0; i < mac->mta_reg_count; i++)
749 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
750
751 /* Setup link and flow control */
752 ret_val = mac->ops.setup_link(hw);
753 if (ret_val)
754 return ret_val;
755
756 /* Disable IBIST slave mode (far-end loopback) */
757 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
758 &kum_reg_data);
759 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
760 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
761 kum_reg_data);
762
763 /* Set the transmit descriptor write-back policy */
764 reg_data = er32(TXDCTL(0));
765 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
766 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
767 ew32(TXDCTL(0), reg_data);
768
769 /* ...for both queues. */
770 reg_data = er32(TXDCTL(1));
771 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
772 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
773 ew32(TXDCTL(1), reg_data);
774
775 /* Enable retransmit on late collisions */
776 reg_data = er32(TCTL);
777 reg_data |= E1000_TCTL_RTLC;
778 ew32(TCTL, reg_data);
779
780 /* Configure Gigabit Carry Extend Padding */
781 reg_data = er32(TCTL_EXT);
782 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
783 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
784 ew32(TCTL_EXT, reg_data);
785
786 /* Configure Transmit Inter-Packet Gap */
787 reg_data = er32(TIPG);
788 reg_data &= ~E1000_TIPG_IPGT_MASK;
789 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
790 ew32(TIPG, reg_data);
791
792 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
793 reg_data &= ~0x00100000;
794 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
795
796 /* default to true to enable the MDIC W/A */
797 hw->dev_spec.e80003es2lan.mdic_wa_enable = true;
798
799 ret_val =
800 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >>
801 E1000_KMRNCTRLSTA_OFFSET_SHIFT, &i);
802 if (!ret_val) {
803 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
804 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
805 hw->dev_spec.e80003es2lan.mdic_wa_enable = false;
806 }
807
808 /* Clear all of the statistics registers (clear on read). It is
809 * important that we do this after we have tried to establish link
810 * because the symbol error count will increment wildly if there
811 * is no link.
812 */
813 e1000_clear_hw_cntrs_80003es2lan(hw);
814
815 return ret_val;
816 }
817
818 /**
819 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
820 * @hw: pointer to the HW structure
821 *
822 * Initializes required hardware-dependent bits needed for normal operation.
823 **/
e1000_initialize_hw_bits_80003es2lan(struct e1000_hw * hw)824 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
825 {
826 u32 reg;
827
828 /* Transmit Descriptor Control 0 */
829 reg = er32(TXDCTL(0));
830 reg |= BIT(22);
831 ew32(TXDCTL(0), reg);
832
833 /* Transmit Descriptor Control 1 */
834 reg = er32(TXDCTL(1));
835 reg |= BIT(22);
836 ew32(TXDCTL(1), reg);
837
838 /* Transmit Arbitration Control 0 */
839 reg = er32(TARC(0));
840 reg &= ~(0xF << 27); /* 30:27 */
841 if (hw->phy.media_type != e1000_media_type_copper)
842 reg &= ~BIT(20);
843 ew32(TARC(0), reg);
844
845 /* Transmit Arbitration Control 1 */
846 reg = er32(TARC(1));
847 if (er32(TCTL) & E1000_TCTL_MULR)
848 reg &= ~BIT(28);
849 else
850 reg |= BIT(28);
851 ew32(TARC(1), reg);
852
853 /* Disable IPv6 extension header parsing because some malformed
854 * IPv6 headers can hang the Rx.
855 */
856 reg = er32(RFCTL);
857 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
858 ew32(RFCTL, reg);
859 }
860
861 /**
862 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
863 * @hw: pointer to the HW structure
864 *
865 * Setup some GG82563 PHY registers for obtaining link
866 **/
e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw * hw)867 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
868 {
869 struct e1000_phy_info *phy = &hw->phy;
870 s32 ret_val;
871 u32 reg;
872 u16 data;
873
874 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
875 if (ret_val)
876 return ret_val;
877
878 data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
879 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
880 data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
881
882 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
883 if (ret_val)
884 return ret_val;
885
886 /* Options:
887 * MDI/MDI-X = 0 (default)
888 * 0 - Auto for all speeds
889 * 1 - MDI mode
890 * 2 - MDI-X mode
891 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
892 */
893 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
894 if (ret_val)
895 return ret_val;
896
897 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
898
899 switch (phy->mdix) {
900 case 1:
901 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
902 break;
903 case 2:
904 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
905 break;
906 case 0:
907 default:
908 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
909 break;
910 }
911
912 /* Options:
913 * disable_polarity_correction = 0 (default)
914 * Automatic Correction for Reversed Cable Polarity
915 * 0 - Disabled
916 * 1 - Enabled
917 */
918 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
919 if (phy->disable_polarity_correction)
920 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
921
922 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
923 if (ret_val)
924 return ret_val;
925
926 /* SW Reset the PHY so all changes take effect */
927 ret_val = hw->phy.ops.commit(hw);
928 if (ret_val) {
929 e_dbg("Error Resetting the PHY\n");
930 return ret_val;
931 }
932
933 /* Bypass Rx and Tx FIFO's */
934 reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL;
935 data = (E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
936 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
937 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
938 if (ret_val)
939 return ret_val;
940
941 reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE;
942 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data);
943 if (ret_val)
944 return ret_val;
945 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
946 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
947 if (ret_val)
948 return ret_val;
949
950 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
951 if (ret_val)
952 return ret_val;
953
954 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
955 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
956 if (ret_val)
957 return ret_val;
958
959 reg = er32(CTRL_EXT);
960 reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
961 ew32(CTRL_EXT, reg);
962
963 ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
964 if (ret_val)
965 return ret_val;
966
967 /* Do not init these registers when the HW is in IAMT mode, since the
968 * firmware will have already initialized them. We only initialize
969 * them if the HW is not in IAMT mode.
970 */
971 if (!hw->mac.ops.check_mng_mode(hw)) {
972 /* Enable Electrical Idle on the PHY */
973 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
974 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
975 if (ret_val)
976 return ret_val;
977
978 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
979 if (ret_val)
980 return ret_val;
981
982 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
983 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
984 if (ret_val)
985 return ret_val;
986 }
987
988 /* Workaround: Disable padding in Kumeran interface in the MAC
989 * and in the PHY to avoid CRC errors.
990 */
991 ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
992 if (ret_val)
993 return ret_val;
994
995 data |= GG82563_ICR_DIS_PADDING;
996 ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
997 if (ret_val)
998 return ret_val;
999
1000 return 0;
1001 }
1002
1003 /**
1004 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1005 * @hw: pointer to the HW structure
1006 *
1007 * Essentially a wrapper for setting up all things "copper" related.
1008 * This is a function pointer entry point called by the mac module.
1009 **/
e1000_setup_copper_link_80003es2lan(struct e1000_hw * hw)1010 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1011 {
1012 u32 ctrl;
1013 s32 ret_val;
1014 u16 reg_data;
1015
1016 ctrl = er32(CTRL);
1017 ctrl |= E1000_CTRL_SLU;
1018 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1019 ew32(CTRL, ctrl);
1020
1021 /* Set the mac to wait the maximum time between each
1022 * iteration and increase the max iterations when
1023 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1024 */
1025 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1026 0xFFFF);
1027 if (ret_val)
1028 return ret_val;
1029 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1030 ®_data);
1031 if (ret_val)
1032 return ret_val;
1033 reg_data |= 0x3F;
1034 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1035 reg_data);
1036 if (ret_val)
1037 return ret_val;
1038 ret_val =
1039 e1000_read_kmrn_reg_80003es2lan(hw,
1040 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1041 ®_data);
1042 if (ret_val)
1043 return ret_val;
1044 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1045 ret_val =
1046 e1000_write_kmrn_reg_80003es2lan(hw,
1047 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1048 reg_data);
1049 if (ret_val)
1050 return ret_val;
1051
1052 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1053 if (ret_val)
1054 return ret_val;
1055
1056 return e1000e_setup_copper_link(hw);
1057 }
1058
1059 /**
1060 * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1061 * @hw: pointer to the HW structure
1062 * @duplex: current duplex setting
1063 *
1064 * Configure the KMRN interface by applying last minute quirks for
1065 * 10/100 operation.
1066 **/
e1000_cfg_on_link_up_80003es2lan(struct e1000_hw * hw)1067 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1068 {
1069 s32 ret_val = 0;
1070 u16 speed;
1071 u16 duplex;
1072
1073 if (hw->phy.media_type == e1000_media_type_copper) {
1074 ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed,
1075 &duplex);
1076 if (ret_val)
1077 return ret_val;
1078
1079 if (speed == SPEED_1000)
1080 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1081 else
1082 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1083 }
1084
1085 return ret_val;
1086 }
1087
1088 /**
1089 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1090 * @hw: pointer to the HW structure
1091 * @duplex: current duplex setting
1092 *
1093 * Configure the KMRN interface by applying last minute quirks for
1094 * 10/100 operation.
1095 **/
e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw * hw,u16 duplex)1096 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1097 {
1098 s32 ret_val;
1099 u32 tipg;
1100 u32 i = 0;
1101 u16 reg_data, reg_data2;
1102
1103 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1104 ret_val =
1105 e1000_write_kmrn_reg_80003es2lan(hw,
1106 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1107 reg_data);
1108 if (ret_val)
1109 return ret_val;
1110
1111 /* Configure Transmit Inter-Packet Gap */
1112 tipg = er32(TIPG);
1113 tipg &= ~E1000_TIPG_IPGT_MASK;
1114 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1115 ew32(TIPG, tipg);
1116
1117 do {
1118 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
1119 if (ret_val)
1120 return ret_val;
1121
1122 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2);
1123 if (ret_val)
1124 return ret_val;
1125 i++;
1126 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1127
1128 if (duplex == HALF_DUPLEX)
1129 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1130 else
1131 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1132
1133 return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1134 }
1135
1136 /**
1137 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1138 * @hw: pointer to the HW structure
1139 *
1140 * Configure the KMRN interface by applying last minute quirks for
1141 * gigabit operation.
1142 **/
e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw * hw)1143 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1144 {
1145 s32 ret_val;
1146 u16 reg_data, reg_data2;
1147 u32 tipg;
1148 u32 i = 0;
1149
1150 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1151 ret_val =
1152 e1000_write_kmrn_reg_80003es2lan(hw,
1153 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1154 reg_data);
1155 if (ret_val)
1156 return ret_val;
1157
1158 /* Configure Transmit Inter-Packet Gap */
1159 tipg = er32(TIPG);
1160 tipg &= ~E1000_TIPG_IPGT_MASK;
1161 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1162 ew32(TIPG, tipg);
1163
1164 do {
1165 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
1166 if (ret_val)
1167 return ret_val;
1168
1169 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2);
1170 if (ret_val)
1171 return ret_val;
1172 i++;
1173 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1174
1175 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1176
1177 return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1178 }
1179
1180 /**
1181 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1182 * @hw: pointer to the HW structure
1183 * @offset: register offset to be read
1184 * @data: pointer to the read data
1185 *
1186 * Acquire semaphore, then read the PHY register at offset
1187 * using the kumeran interface. The information retrieved is stored in data.
1188 * Release the semaphore before exiting.
1189 **/
e1000_read_kmrn_reg_80003es2lan(struct e1000_hw * hw,u32 offset,u16 * data)1190 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1191 u16 *data)
1192 {
1193 u32 kmrnctrlsta;
1194 s32 ret_val;
1195
1196 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1197 if (ret_val)
1198 return ret_val;
1199
1200 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1201 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1202 ew32(KMRNCTRLSTA, kmrnctrlsta);
1203 e1e_flush();
1204
1205 udelay(2);
1206
1207 kmrnctrlsta = er32(KMRNCTRLSTA);
1208 *data = (u16)kmrnctrlsta;
1209
1210 e1000_release_mac_csr_80003es2lan(hw);
1211
1212 return ret_val;
1213 }
1214
1215 /**
1216 * e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1217 * @hw: pointer to the HW structure
1218 * @offset: register offset to write to
1219 * @data: data to write at register offset
1220 *
1221 * Acquire semaphore, then write the data to PHY register
1222 * at the offset using the kumeran interface. Release semaphore
1223 * before exiting.
1224 **/
e1000_write_kmrn_reg_80003es2lan(struct e1000_hw * hw,u32 offset,u16 data)1225 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1226 u16 data)
1227 {
1228 u32 kmrnctrlsta;
1229 s32 ret_val;
1230
1231 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1232 if (ret_val)
1233 return ret_val;
1234
1235 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1236 E1000_KMRNCTRLSTA_OFFSET) | data;
1237 ew32(KMRNCTRLSTA, kmrnctrlsta);
1238 e1e_flush();
1239
1240 udelay(2);
1241
1242 e1000_release_mac_csr_80003es2lan(hw);
1243
1244 return ret_val;
1245 }
1246
1247 /**
1248 * e1000_read_mac_addr_80003es2lan - Read device MAC address
1249 * @hw: pointer to the HW structure
1250 **/
e1000_read_mac_addr_80003es2lan(struct e1000_hw * hw)1251 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1252 {
1253 s32 ret_val;
1254
1255 /* If there's an alternate MAC address place it in RAR0
1256 * so that it will override the Si installed default perm
1257 * address.
1258 */
1259 ret_val = e1000_check_alt_mac_addr_generic(hw);
1260 if (ret_val)
1261 return ret_val;
1262
1263 return e1000_read_mac_addr_generic(hw);
1264 }
1265
1266 /**
1267 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1268 * @hw: pointer to the HW structure
1269 *
1270 * In the case of a PHY power down to save power, or to turn off link during a
1271 * driver unload, or wake on lan is not enabled, remove the link.
1272 **/
e1000_power_down_phy_copper_80003es2lan(struct e1000_hw * hw)1273 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1274 {
1275 /* If the management interface is not enabled, then power down */
1276 if (!(hw->mac.ops.check_mng_mode(hw) ||
1277 hw->phy.ops.check_reset_block(hw)))
1278 e1000_power_down_phy_copper(hw);
1279 }
1280
1281 /**
1282 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1283 * @hw: pointer to the HW structure
1284 *
1285 * Clears the hardware counters by reading the counter registers.
1286 **/
e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw * hw)1287 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1288 {
1289 e1000e_clear_hw_cntrs_base(hw);
1290
1291 er32(PRC64);
1292 er32(PRC127);
1293 er32(PRC255);
1294 er32(PRC511);
1295 er32(PRC1023);
1296 er32(PRC1522);
1297 er32(PTC64);
1298 er32(PTC127);
1299 er32(PTC255);
1300 er32(PTC511);
1301 er32(PTC1023);
1302 er32(PTC1522);
1303
1304 er32(ALGNERRC);
1305 er32(RXERRC);
1306 er32(TNCRS);
1307 er32(CEXTERR);
1308 er32(TSCTC);
1309 er32(TSCTFC);
1310
1311 er32(MGTPRC);
1312 er32(MGTPDC);
1313 er32(MGTPTC);
1314
1315 er32(IAC);
1316 er32(ICRXOC);
1317
1318 er32(ICRXPTC);
1319 er32(ICRXATC);
1320 er32(ICTXPTC);
1321 er32(ICTXATC);
1322 er32(ICTXQEC);
1323 er32(ICTXQMTC);
1324 er32(ICRXDMTC);
1325 }
1326
1327 static const struct e1000_mac_operations es2_mac_ops = {
1328 .read_mac_addr = e1000_read_mac_addr_80003es2lan,
1329 .id_led_init = e1000e_id_led_init_generic,
1330 .blink_led = e1000e_blink_led_generic,
1331 .check_mng_mode = e1000e_check_mng_mode_generic,
1332 /* check_for_link dependent on media type */
1333 .cleanup_led = e1000e_cleanup_led_generic,
1334 .clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan,
1335 .get_bus_info = e1000e_get_bus_info_pcie,
1336 .set_lan_id = e1000_set_lan_id_multi_port_pcie,
1337 .get_link_up_info = e1000_get_link_up_info_80003es2lan,
1338 .led_on = e1000e_led_on_generic,
1339 .led_off = e1000e_led_off_generic,
1340 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
1341 .write_vfta = e1000_write_vfta_generic,
1342 .clear_vfta = e1000_clear_vfta_generic,
1343 .reset_hw = e1000_reset_hw_80003es2lan,
1344 .init_hw = e1000_init_hw_80003es2lan,
1345 .setup_link = e1000e_setup_link_generic,
1346 /* setup_physical_interface dependent on media type */
1347 .setup_led = e1000e_setup_led_generic,
1348 .config_collision_dist = e1000e_config_collision_dist_generic,
1349 .rar_set = e1000e_rar_set_generic,
1350 .rar_get_count = e1000e_rar_get_count_generic,
1351 };
1352
1353 static const struct e1000_phy_operations es2_phy_ops = {
1354 .acquire = e1000_acquire_phy_80003es2lan,
1355 .check_polarity = e1000_check_polarity_m88,
1356 .check_reset_block = e1000e_check_reset_block_generic,
1357 .commit = e1000e_phy_sw_reset,
1358 .force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan,
1359 .get_cfg_done = e1000_get_cfg_done_80003es2lan,
1360 .get_cable_length = e1000_get_cable_length_80003es2lan,
1361 .get_info = e1000e_get_phy_info_m88,
1362 .read_reg = e1000_read_phy_reg_gg82563_80003es2lan,
1363 .release = e1000_release_phy_80003es2lan,
1364 .reset = e1000e_phy_hw_reset_generic,
1365 .set_d0_lplu_state = NULL,
1366 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1367 .write_reg = e1000_write_phy_reg_gg82563_80003es2lan,
1368 .cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan,
1369 };
1370
1371 static const struct e1000_nvm_operations es2_nvm_ops = {
1372 .acquire = e1000_acquire_nvm_80003es2lan,
1373 .read = e1000e_read_nvm_eerd,
1374 .release = e1000_release_nvm_80003es2lan,
1375 .reload = e1000e_reload_nvm_generic,
1376 .update = e1000e_update_nvm_checksum_generic,
1377 .valid_led_default = e1000e_valid_led_default,
1378 .validate = e1000e_validate_nvm_checksum_generic,
1379 .write = e1000_write_nvm_80003es2lan,
1380 };
1381
1382 const struct e1000_info e1000_es2_info = {
1383 .mac = e1000_80003es2lan,
1384 .flags = FLAG_HAS_HW_VLAN_FILTER
1385 | FLAG_HAS_JUMBO_FRAMES
1386 | FLAG_HAS_WOL
1387 | FLAG_APME_IN_CTRL3
1388 | FLAG_HAS_CTRLEXT_ON_LOAD
1389 | FLAG_RX_NEEDS_RESTART /* errata */
1390 | FLAG_TARC_SET_BIT_ZERO /* errata */
1391 | FLAG_APME_CHECK_PORT_B
1392 | FLAG_DISABLE_FC_PAUSE_TIME, /* errata */
1393 .flags2 = FLAG2_DMA_BURST,
1394 .pba = 38,
1395 .max_hw_frame_size = DEFAULT_JUMBO,
1396 .get_variants = e1000_get_variants_80003es2lan,
1397 .mac_ops = &es2_mac_ops,
1398 .phy_ops = &es2_phy_ops,
1399 .nvm_ops = &es2_nvm_ops,
1400 };
1401
