1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
4 * stmmac XGMAC support.
5 */
6
7 #include <linux/iopoll.h>
8 #include "stmmac.h"
9 #include "dwxgmac2.h"
10
dwxgmac2_dma_reset(void __iomem * ioaddr)11 static int dwxgmac2_dma_reset(void __iomem *ioaddr)
12 {
13 u32 value = readl(ioaddr + XGMAC_DMA_MODE);
14
15 /* DMA SW reset */
16 writel(value | XGMAC_SWR, ioaddr + XGMAC_DMA_MODE);
17
18 return readl_poll_timeout(ioaddr + XGMAC_DMA_MODE, value,
19 !(value & XGMAC_SWR), 0, 100000);
20 }
21
dwxgmac2_dma_init(void __iomem * ioaddr,struct stmmac_dma_cfg * dma_cfg,int atds)22 static void dwxgmac2_dma_init(void __iomem *ioaddr,
23 struct stmmac_dma_cfg *dma_cfg, int atds)
24 {
25 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
26
27 if (dma_cfg->aal)
28 value |= XGMAC_AAL;
29
30 writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
31 }
32
dwxgmac2_dma_init_chan(void __iomem * ioaddr,struct stmmac_dma_cfg * dma_cfg,u32 chan)33 static void dwxgmac2_dma_init_chan(void __iomem *ioaddr,
34 struct stmmac_dma_cfg *dma_cfg, u32 chan)
35 {
36 u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan));
37
38 if (dma_cfg->pblx8)
39 value |= XGMAC_PBLx8;
40
41 writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan));
42 writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
43 }
44
dwxgmac2_dma_init_rx_chan(void __iomem * ioaddr,struct stmmac_dma_cfg * dma_cfg,u32 dma_rx_phy,u32 chan)45 static void dwxgmac2_dma_init_rx_chan(void __iomem *ioaddr,
46 struct stmmac_dma_cfg *dma_cfg,
47 u32 dma_rx_phy, u32 chan)
48 {
49 u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
50 u32 value;
51
52 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
53 value &= ~XGMAC_RxPBL;
54 value |= (rxpbl << XGMAC_RxPBL_SHIFT) & XGMAC_RxPBL;
55 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
56
57 writel(dma_rx_phy, ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(chan));
58 }
59
dwxgmac2_dma_init_tx_chan(void __iomem * ioaddr,struct stmmac_dma_cfg * dma_cfg,u32 dma_tx_phy,u32 chan)60 static void dwxgmac2_dma_init_tx_chan(void __iomem *ioaddr,
61 struct stmmac_dma_cfg *dma_cfg,
62 u32 dma_tx_phy, u32 chan)
63 {
64 u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
65 u32 value;
66
67 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
68 value &= ~XGMAC_TxPBL;
69 value |= (txpbl << XGMAC_TxPBL_SHIFT) & XGMAC_TxPBL;
70 value |= XGMAC_OSP;
71 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
72
73 writel(dma_tx_phy, ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan));
74 }
75
dwxgmac2_dma_axi(void __iomem * ioaddr,struct stmmac_axi * axi)76 static void dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
77 {
78 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
79 int i;
80
81 if (axi->axi_lpi_en)
82 value |= XGMAC_EN_LPI;
83 if (axi->axi_xit_frm)
84 value |= XGMAC_LPI_XIT_PKT;
85
86 value &= ~XGMAC_WR_OSR_LMT;
87 value |= (axi->axi_wr_osr_lmt << XGMAC_WR_OSR_LMT_SHIFT) &
88 XGMAC_WR_OSR_LMT;
89
90 value &= ~XGMAC_RD_OSR_LMT;
91 value |= (axi->axi_rd_osr_lmt << XGMAC_RD_OSR_LMT_SHIFT) &
92 XGMAC_RD_OSR_LMT;
93
94 value &= ~XGMAC_BLEN;
95 for (i = 0; i < AXI_BLEN; i++) {
96 if (axi->axi_blen[i])
97 value &= ~XGMAC_UNDEF;
98
99 switch (axi->axi_blen[i]) {
100 case 256:
101 value |= XGMAC_BLEN256;
102 break;
103 case 128:
104 value |= XGMAC_BLEN128;
105 break;
106 case 64:
107 value |= XGMAC_BLEN64;
108 break;
109 case 32:
110 value |= XGMAC_BLEN32;
111 break;
112 case 16:
113 value |= XGMAC_BLEN16;
114 break;
115 case 8:
116 value |= XGMAC_BLEN8;
117 break;
118 case 4:
119 value |= XGMAC_BLEN4;
120 break;
121 }
122 }
123
124 writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
125 }
126
dwxgmac2_dma_rx_mode(void __iomem * ioaddr,int mode,u32 channel,int fifosz,u8 qmode)127 static void dwxgmac2_dma_rx_mode(void __iomem *ioaddr, int mode,
128 u32 channel, int fifosz, u8 qmode)
129 {
130 u32 value = readl(ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));
131 unsigned int rqs = fifosz / 256 - 1;
132
133 if (mode == SF_DMA_MODE) {
134 value |= XGMAC_RSF;
135 } else {
136 value &= ~XGMAC_RSF;
137 value &= ~XGMAC_RTC;
138
139 if (mode <= 64)
140 value |= 0x0 << XGMAC_RTC_SHIFT;
141 else if (mode <= 96)
142 value |= 0x2 << XGMAC_RTC_SHIFT;
143 else
144 value |= 0x3 << XGMAC_RTC_SHIFT;
145 }
146
147 value &= ~XGMAC_RQS;
148 value |= (rqs << XGMAC_RQS_SHIFT) & XGMAC_RQS;
149
150 writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));
151
152 /* Enable MTL RX overflow */
153 value = readl(ioaddr + XGMAC_MTL_QINTEN(channel));
154 writel(value | XGMAC_RXOIE, ioaddr + XGMAC_MTL_QINTEN(channel));
155 }
156
dwxgmac2_dma_tx_mode(void __iomem * ioaddr,int mode,u32 channel,int fifosz,u8 qmode)157 static void dwxgmac2_dma_tx_mode(void __iomem *ioaddr, int mode,
158 u32 channel, int fifosz, u8 qmode)
159 {
160 u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
161 unsigned int tqs = fifosz / 256 - 1;
162
163 if (mode == SF_DMA_MODE) {
164 value |= XGMAC_TSF;
165 } else {
166 value &= ~XGMAC_TSF;
167 value &= ~XGMAC_TTC;
168
169 if (mode <= 64)
170 value |= 0x0 << XGMAC_TTC_SHIFT;
171 else if (mode <= 96)
172 value |= 0x2 << XGMAC_TTC_SHIFT;
173 else if (mode <= 128)
174 value |= 0x3 << XGMAC_TTC_SHIFT;
175 else if (mode <= 192)
176 value |= 0x4 << XGMAC_TTC_SHIFT;
177 else if (mode <= 256)
178 value |= 0x5 << XGMAC_TTC_SHIFT;
179 else if (mode <= 384)
180 value |= 0x6 << XGMAC_TTC_SHIFT;
181 else
182 value |= 0x7 << XGMAC_TTC_SHIFT;
183 }
184
185 value &= ~XGMAC_TXQEN;
186 if (qmode != MTL_QUEUE_AVB)
187 value |= 0x2 << XGMAC_TXQEN_SHIFT;
188 else
189 value |= 0x1 << XGMAC_TXQEN_SHIFT;
190
191 value &= ~XGMAC_TQS;
192 value |= (tqs << XGMAC_TQS_SHIFT) & XGMAC_TQS;
193
194 writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
195 }
196
dwxgmac2_enable_dma_irq(void __iomem * ioaddr,u32 chan)197 static void dwxgmac2_enable_dma_irq(void __iomem *ioaddr, u32 chan)
198 {
199 writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
200 }
201
dwxgmac2_disable_dma_irq(void __iomem * ioaddr,u32 chan)202 static void dwxgmac2_disable_dma_irq(void __iomem *ioaddr, u32 chan)
203 {
204 writel(0, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
205 }
206
dwxgmac2_dma_start_tx(void __iomem * ioaddr,u32 chan)207 static void dwxgmac2_dma_start_tx(void __iomem *ioaddr, u32 chan)
208 {
209 u32 value;
210
211 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
212 value |= XGMAC_TXST;
213 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
214
215 value = readl(ioaddr + XGMAC_TX_CONFIG);
216 value |= XGMAC_CONFIG_TE;
217 writel(value, ioaddr + XGMAC_TX_CONFIG);
218 }
219
dwxgmac2_dma_stop_tx(void __iomem * ioaddr,u32 chan)220 static void dwxgmac2_dma_stop_tx(void __iomem *ioaddr, u32 chan)
221 {
222 u32 value;
223
224 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
225 value &= ~XGMAC_TXST;
226 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
227
228 value = readl(ioaddr + XGMAC_TX_CONFIG);
229 value &= ~XGMAC_CONFIG_TE;
230 writel(value, ioaddr + XGMAC_TX_CONFIG);
231 }
232
dwxgmac2_dma_start_rx(void __iomem * ioaddr,u32 chan)233 static void dwxgmac2_dma_start_rx(void __iomem *ioaddr, u32 chan)
234 {
235 u32 value;
236
237 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
238 value |= XGMAC_RXST;
239 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
240
241 value = readl(ioaddr + XGMAC_RX_CONFIG);
242 value |= XGMAC_CONFIG_RE;
243 writel(value, ioaddr + XGMAC_RX_CONFIG);
244 }
245
dwxgmac2_dma_stop_rx(void __iomem * ioaddr,u32 chan)246 static void dwxgmac2_dma_stop_rx(void __iomem *ioaddr, u32 chan)
247 {
248 u32 value;
249
250 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
251 value &= ~XGMAC_RXST;
252 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
253
254 value = readl(ioaddr + XGMAC_RX_CONFIG);
255 value &= ~XGMAC_CONFIG_RE;
256 writel(value, ioaddr + XGMAC_RX_CONFIG);
257 }
258
dwxgmac2_dma_interrupt(void __iomem * ioaddr,struct stmmac_extra_stats * x,u32 chan)259 static int dwxgmac2_dma_interrupt(void __iomem *ioaddr,
260 struct stmmac_extra_stats *x, u32 chan)
261 {
262 u32 intr_status = readl(ioaddr + XGMAC_DMA_CH_STATUS(chan));
263 int ret = 0;
264
265 /* ABNORMAL interrupts */
266 if (unlikely(intr_status & XGMAC_AIS)) {
267 if (unlikely(intr_status & XGMAC_TPS)) {
268 x->tx_process_stopped_irq++;
269 ret |= tx_hard_error;
270 }
271 if (unlikely(intr_status & XGMAC_FBE)) {
272 x->fatal_bus_error_irq++;
273 ret |= tx_hard_error;
274 }
275 }
276
277 /* TX/RX NORMAL interrupts */
278 if (likely(intr_status & XGMAC_NIS)) {
279 x->normal_irq_n++;
280
281 if (likely(intr_status & XGMAC_RI)) {
282 u32 value = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan));
283 if (likely(value & XGMAC_RIE)) {
284 x->rx_normal_irq_n++;
285 ret |= handle_rx;
286 }
287 }
288 if (likely(intr_status & XGMAC_TI)) {
289 x->tx_normal_irq_n++;
290 ret |= handle_tx;
291 }
292 }
293
294 /* Clear interrupts */
295 writel(~0x0, ioaddr + XGMAC_DMA_CH_STATUS(chan));
296
297 return ret;
298 }
299
dwxgmac2_get_hw_feature(void __iomem * ioaddr,struct dma_features * dma_cap)300 static void dwxgmac2_get_hw_feature(void __iomem *ioaddr,
301 struct dma_features *dma_cap)
302 {
303 u32 hw_cap;
304
305 /* MAC HW feature 0 */
306 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE0);
307 dma_cap->rx_coe = (hw_cap & XGMAC_HWFEAT_RXCOESEL) >> 16;
308 dma_cap->tx_coe = (hw_cap & XGMAC_HWFEAT_TXCOESEL) >> 14;
309 dma_cap->atime_stamp = (hw_cap & XGMAC_HWFEAT_TSSEL) >> 12;
310 dma_cap->av = (hw_cap & XGMAC_HWFEAT_AVSEL) >> 11;
311 dma_cap->av &= (hw_cap & XGMAC_HWFEAT_RAVSEL) >> 10;
312 dma_cap->pmt_magic_frame = (hw_cap & XGMAC_HWFEAT_MGKSEL) >> 7;
313 dma_cap->pmt_remote_wake_up = (hw_cap & XGMAC_HWFEAT_RWKSEL) >> 6;
314 dma_cap->mbps_1000 = (hw_cap & XGMAC_HWFEAT_GMIISEL) >> 1;
315
316 /* MAC HW feature 1 */
317 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE1);
318 dma_cap->tsoen = (hw_cap & XGMAC_HWFEAT_TSOEN) >> 18;
319 dma_cap->tx_fifo_size =
320 128 << ((hw_cap & XGMAC_HWFEAT_TXFIFOSIZE) >> 6);
321 dma_cap->rx_fifo_size =
322 128 << ((hw_cap & XGMAC_HWFEAT_RXFIFOSIZE) >> 0);
323
324 /* MAC HW feature 2 */
325 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE2);
326 dma_cap->pps_out_num = (hw_cap & XGMAC_HWFEAT_PPSOUTNUM) >> 24;
327 dma_cap->number_tx_channel =
328 ((hw_cap & XGMAC_HWFEAT_TXCHCNT) >> 18) + 1;
329 dma_cap->number_rx_channel =
330 ((hw_cap & XGMAC_HWFEAT_RXCHCNT) >> 12) + 1;
331 dma_cap->number_tx_queues =
332 ((hw_cap & XGMAC_HWFEAT_TXQCNT) >> 6) + 1;
333 dma_cap->number_rx_queues =
334 ((hw_cap & XGMAC_HWFEAT_RXQCNT) >> 0) + 1;
335 }
336
dwxgmac2_rx_watchdog(void __iomem * ioaddr,u32 riwt,u32 nchan)337 static void dwxgmac2_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 nchan)
338 {
339 u32 i;
340
341 for (i = 0; i < nchan; i++)
342 writel(riwt & XGMAC_RWT, ioaddr + XGMAC_DMA_CH_Rx_WATCHDOG(i));
343 }
344
dwxgmac2_set_rx_ring_len(void __iomem * ioaddr,u32 len,u32 chan)345 static void dwxgmac2_set_rx_ring_len(void __iomem *ioaddr, u32 len, u32 chan)
346 {
347 writel(len, ioaddr + XGMAC_DMA_CH_RxDESC_RING_LEN(chan));
348 }
349
dwxgmac2_set_tx_ring_len(void __iomem * ioaddr,u32 len,u32 chan)350 static void dwxgmac2_set_tx_ring_len(void __iomem *ioaddr, u32 len, u32 chan)
351 {
352 writel(len, ioaddr + XGMAC_DMA_CH_TxDESC_RING_LEN(chan));
353 }
354
dwxgmac2_set_rx_tail_ptr(void __iomem * ioaddr,u32 ptr,u32 chan)355 static void dwxgmac2_set_rx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan)
356 {
357 writel(ptr, ioaddr + XGMAC_DMA_CH_RxDESC_TAIL_LPTR(chan));
358 }
359
dwxgmac2_set_tx_tail_ptr(void __iomem * ioaddr,u32 ptr,u32 chan)360 static void dwxgmac2_set_tx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan)
361 {
362 writel(ptr, ioaddr + XGMAC_DMA_CH_TxDESC_TAIL_LPTR(chan));
363 }
364
dwxgmac2_enable_tso(void __iomem * ioaddr,bool en,u32 chan)365 static void dwxgmac2_enable_tso(void __iomem *ioaddr, bool en, u32 chan)
366 {
367 u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
368
369 if (en)
370 value |= XGMAC_TSE;
371 else
372 value &= ~XGMAC_TSE;
373
374 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
375 }
376
dwxgmac2_set_bfsize(void __iomem * ioaddr,int bfsize,u32 chan)377 static void dwxgmac2_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan)
378 {
379 u32 value;
380
381 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
382 value |= bfsize << 1;
383 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
384 }
385
386 const struct stmmac_dma_ops dwxgmac210_dma_ops = {
387 .reset = dwxgmac2_dma_reset,
388 .init = dwxgmac2_dma_init,
389 .init_chan = dwxgmac2_dma_init_chan,
390 .init_rx_chan = dwxgmac2_dma_init_rx_chan,
391 .init_tx_chan = dwxgmac2_dma_init_tx_chan,
392 .axi = dwxgmac2_dma_axi,
393 .dump_regs = NULL,
394 .dma_rx_mode = dwxgmac2_dma_rx_mode,
395 .dma_tx_mode = dwxgmac2_dma_tx_mode,
396 .enable_dma_irq = dwxgmac2_enable_dma_irq,
397 .disable_dma_irq = dwxgmac2_disable_dma_irq,
398 .start_tx = dwxgmac2_dma_start_tx,
399 .stop_tx = dwxgmac2_dma_stop_tx,
400 .start_rx = dwxgmac2_dma_start_rx,
401 .stop_rx = dwxgmac2_dma_stop_rx,
402 .dma_interrupt = dwxgmac2_dma_interrupt,
403 .get_hw_feature = dwxgmac2_get_hw_feature,
404 .rx_watchdog = dwxgmac2_rx_watchdog,
405 .set_rx_ring_len = dwxgmac2_set_rx_ring_len,
406 .set_tx_ring_len = dwxgmac2_set_tx_ring_len,
407 .set_rx_tail_ptr = dwxgmac2_set_rx_tail_ptr,
408 .set_tx_tail_ptr = dwxgmac2_set_tx_tail_ptr,
409 .enable_tso = dwxgmac2_enable_tso,
410 .set_bfsize = dwxgmac2_set_bfsize,
411 };
412
