1 // SPDX-License-Identifier: GPL-2.0-only
2 /*******************************************************************************
3 Copyright (C) 2007-2009 STMicroelectronics Ltd
4
5
6 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
7 *******************************************************************************/
8
9 #include <linux/io.h>
10 #include <linux/iopoll.h>
11 #include "common.h"
12 #include "dwmac_dma.h"
13 #include "stmmac.h"
14
15 #define GMAC_HI_REG_AE 0x80000000
16
dwmac_dma_reset(void __iomem * ioaddr)17 int dwmac_dma_reset(void __iomem *ioaddr)
18 {
19 u32 value = readl(ioaddr + DMA_BUS_MODE);
20
21 /* DMA SW reset */
22 value |= DMA_BUS_MODE_SFT_RESET;
23 writel(value, ioaddr + DMA_BUS_MODE);
24
25 return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value,
26 !(value & DMA_BUS_MODE_SFT_RESET),
27 10000, 200000);
28 }
29
30 /* CSR1 enables the transmit DMA to check for new descriptor */
dwmac_enable_dma_transmission(void __iomem * ioaddr)31 void dwmac_enable_dma_transmission(void __iomem *ioaddr)
32 {
33 writel(1, ioaddr + DMA_XMT_POLL_DEMAND);
34 }
35
dwmac_enable_dma_irq(struct stmmac_priv * priv,void __iomem * ioaddr,u32 chan,bool rx,bool tx)36 void dwmac_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
37 u32 chan, bool rx, bool tx)
38 {
39 u32 value = readl(ioaddr + DMA_INTR_ENA);
40
41 if (rx)
42 value |= DMA_INTR_DEFAULT_RX;
43 if (tx)
44 value |= DMA_INTR_DEFAULT_TX;
45
46 writel(value, ioaddr + DMA_INTR_ENA);
47 }
48
dwmac_disable_dma_irq(struct stmmac_priv * priv,void __iomem * ioaddr,u32 chan,bool rx,bool tx)49 void dwmac_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
50 u32 chan, bool rx, bool tx)
51 {
52 u32 value = readl(ioaddr + DMA_INTR_ENA);
53
54 if (rx)
55 value &= ~DMA_INTR_DEFAULT_RX;
56 if (tx)
57 value &= ~DMA_INTR_DEFAULT_TX;
58
59 writel(value, ioaddr + DMA_INTR_ENA);
60 }
61
dwmac_dma_start_tx(struct stmmac_priv * priv,void __iomem * ioaddr,u32 chan)62 void dwmac_dma_start_tx(struct stmmac_priv *priv, void __iomem *ioaddr,
63 u32 chan)
64 {
65 u32 value = readl(ioaddr + DMA_CONTROL);
66 value |= DMA_CONTROL_ST;
67 writel(value, ioaddr + DMA_CONTROL);
68 }
69
dwmac_dma_stop_tx(struct stmmac_priv * priv,void __iomem * ioaddr,u32 chan)70 void dwmac_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan)
71 {
72 u32 value = readl(ioaddr + DMA_CONTROL);
73 value &= ~DMA_CONTROL_ST;
74 writel(value, ioaddr + DMA_CONTROL);
75 }
76
dwmac_dma_start_rx(struct stmmac_priv * priv,void __iomem * ioaddr,u32 chan)77 void dwmac_dma_start_rx(struct stmmac_priv *priv, void __iomem *ioaddr,
78 u32 chan)
79 {
80 u32 value = readl(ioaddr + DMA_CONTROL);
81 value |= DMA_CONTROL_SR;
82 writel(value, ioaddr + DMA_CONTROL);
83 }
84
dwmac_dma_stop_rx(struct stmmac_priv * priv,void __iomem * ioaddr,u32 chan)85 void dwmac_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan)
86 {
87 u32 value = readl(ioaddr + DMA_CONTROL);
88 value &= ~DMA_CONTROL_SR;
89 writel(value, ioaddr + DMA_CONTROL);
90 }
91
92 #ifdef DWMAC_DMA_DEBUG
show_tx_process_state(unsigned int status)93 static void show_tx_process_state(unsigned int status)
94 {
95 unsigned int state;
96 state = (status & DMA_STATUS_TS_MASK) >> DMA_STATUS_TS_SHIFT;
97
98 switch (state) {
99 case 0:
100 pr_debug("- TX (Stopped): Reset or Stop command\n");
101 break;
102 case 1:
103 pr_debug("- TX (Running): Fetching the Tx desc\n");
104 break;
105 case 2:
106 pr_debug("- TX (Running): Waiting for end of tx\n");
107 break;
108 case 3:
109 pr_debug("- TX (Running): Reading the data "
110 "and queuing the data into the Tx buf\n");
111 break;
112 case 6:
113 pr_debug("- TX (Suspended): Tx Buff Underflow "
114 "or an unavailable Transmit descriptor\n");
115 break;
116 case 7:
117 pr_debug("- TX (Running): Closing Tx descriptor\n");
118 break;
119 default:
120 break;
121 }
122 }
123
show_rx_process_state(unsigned int status)124 static void show_rx_process_state(unsigned int status)
125 {
126 unsigned int state;
127 state = (status & DMA_STATUS_RS_MASK) >> DMA_STATUS_RS_SHIFT;
128
129 switch (state) {
130 case 0:
131 pr_debug("- RX (Stopped): Reset or Stop command\n");
132 break;
133 case 1:
134 pr_debug("- RX (Running): Fetching the Rx desc\n");
135 break;
136 case 2:
137 pr_debug("- RX (Running): Checking for end of pkt\n");
138 break;
139 case 3:
140 pr_debug("- RX (Running): Waiting for Rx pkt\n");
141 break;
142 case 4:
143 pr_debug("- RX (Suspended): Unavailable Rx buf\n");
144 break;
145 case 5:
146 pr_debug("- RX (Running): Closing Rx descriptor\n");
147 break;
148 case 6:
149 pr_debug("- RX(Running): Flushing the current frame"
150 " from the Rx buf\n");
151 break;
152 case 7:
153 pr_debug("- RX (Running): Queuing the Rx frame"
154 " from the Rx buf into memory\n");
155 break;
156 default:
157 break;
158 }
159 }
160 #endif
161
dwmac_dma_interrupt(struct stmmac_priv * priv,void __iomem * ioaddr,struct stmmac_extra_stats * x,u32 chan,u32 dir)162 int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
163 struct stmmac_extra_stats *x, u32 chan, u32 dir)
164 {
165 struct stmmac_rxq_stats *rxq_stats = &priv->xstats.rxq_stats[chan];
166 struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[chan];
167 int ret = 0;
168 /* read the status register (CSR5) */
169 u32 intr_status = readl(ioaddr + DMA_STATUS);
170
171 #ifdef DWMAC_DMA_DEBUG
172 /* Enable it to monitor DMA rx/tx status in case of critical problems */
173 pr_debug("%s: [CSR5: 0x%08x]\n", __func__, intr_status);
174 show_tx_process_state(intr_status);
175 show_rx_process_state(intr_status);
176 #endif
177
178 if (dir == DMA_DIR_RX)
179 intr_status &= DMA_STATUS_MSK_RX;
180 else if (dir == DMA_DIR_TX)
181 intr_status &= DMA_STATUS_MSK_TX;
182
183 /* ABNORMAL interrupts */
184 if (unlikely(intr_status & DMA_STATUS_AIS)) {
185 if (unlikely(intr_status & DMA_STATUS_UNF)) {
186 ret = tx_hard_error_bump_tc;
187 x->tx_undeflow_irq++;
188 }
189 if (unlikely(intr_status & DMA_STATUS_TJT))
190 x->tx_jabber_irq++;
191
192 if (unlikely(intr_status & DMA_STATUS_OVF))
193 x->rx_overflow_irq++;
194
195 if (unlikely(intr_status & DMA_STATUS_RU))
196 x->rx_buf_unav_irq++;
197 if (unlikely(intr_status & DMA_STATUS_RPS))
198 x->rx_process_stopped_irq++;
199 if (unlikely(intr_status & DMA_STATUS_RWT))
200 x->rx_watchdog_irq++;
201 if (unlikely(intr_status & DMA_STATUS_ETI))
202 x->tx_early_irq++;
203 if (unlikely(intr_status & DMA_STATUS_TPS)) {
204 x->tx_process_stopped_irq++;
205 ret = tx_hard_error;
206 }
207 if (unlikely(intr_status & DMA_STATUS_FBI)) {
208 x->fatal_bus_error_irq++;
209 ret = tx_hard_error;
210 }
211 }
212 /* TX/RX NORMAL interrupts */
213 if (likely(intr_status & DMA_STATUS_NIS)) {
214 if (likely(intr_status & DMA_STATUS_RI)) {
215 u32 value = readl(ioaddr + DMA_INTR_ENA);
216 /* to schedule NAPI on real RIE event. */
217 if (likely(value & DMA_INTR_ENA_RIE)) {
218 u64_stats_update_begin(&rxq_stats->syncp);
219 rxq_stats->rx_normal_irq_n++;
220 u64_stats_update_end(&rxq_stats->syncp);
221 ret |= handle_rx;
222 }
223 }
224 if (likely(intr_status & DMA_STATUS_TI)) {
225 u64_stats_update_begin(&txq_stats->syncp);
226 txq_stats->tx_normal_irq_n++;
227 u64_stats_update_end(&txq_stats->syncp);
228 ret |= handle_tx;
229 }
230 if (unlikely(intr_status & DMA_STATUS_ERI))
231 x->rx_early_irq++;
232 }
233 /* Optional hardware blocks, interrupts should be disabled */
234 if (unlikely(intr_status &
235 (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI)))
236 pr_warn("%s: unexpected status %08x\n", __func__, intr_status);
237
238 /* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */
239 writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS);
240
241 return ret;
242 }
243
dwmac_dma_flush_tx_fifo(void __iomem * ioaddr)244 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr)
245 {
246 u32 csr6 = readl(ioaddr + DMA_CONTROL);
247 writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL);
248
249 do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF));
250 }
251
stmmac_set_mac_addr(void __iomem * ioaddr,const u8 addr[6],unsigned int high,unsigned int low)252 void stmmac_set_mac_addr(void __iomem *ioaddr, const u8 addr[6],
253 unsigned int high, unsigned int low)
254 {
255 unsigned long data;
256
257 data = (addr[5] << 8) | addr[4];
258 /* For MAC Addr registers we have to set the Address Enable (AE)
259 * bit that has no effect on the High Reg 0 where the bit 31 (MO)
260 * is RO.
261 */
262 writel(data | GMAC_HI_REG_AE, ioaddr + high);
263 data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
264 writel(data, ioaddr + low);
265 }
266 EXPORT_SYMBOL_GPL(stmmac_set_mac_addr);
267
268 /* Enable disable MAC RX/TX */
stmmac_set_mac(void __iomem * ioaddr,bool enable)269 void stmmac_set_mac(void __iomem *ioaddr, bool enable)
270 {
271 u32 old_val, value;
272
273 old_val = readl(ioaddr + MAC_CTRL_REG);
274 value = old_val;
275
276 if (enable)
277 value |= MAC_ENABLE_RX | MAC_ENABLE_TX;
278 else
279 value &= ~(MAC_ENABLE_TX | MAC_ENABLE_RX);
280
281 if (value != old_val)
282 writel(value, ioaddr + MAC_CTRL_REG);
283 }
284
stmmac_get_mac_addr(void __iomem * ioaddr,unsigned char * addr,unsigned int high,unsigned int low)285 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
286 unsigned int high, unsigned int low)
287 {
288 unsigned int hi_addr, lo_addr;
289
290 /* Read the MAC address from the hardware */
291 hi_addr = readl(ioaddr + high);
292 lo_addr = readl(ioaddr + low);
293
294 /* Extract the MAC address from the high and low words */
295 addr[0] = lo_addr & 0xff;
296 addr[1] = (lo_addr >> 8) & 0xff;
297 addr[2] = (lo_addr >> 16) & 0xff;
298 addr[3] = (lo_addr >> 24) & 0xff;
299 addr[4] = hi_addr & 0xff;
300 addr[5] = (hi_addr >> 8) & 0xff;
301 }
302 EXPORT_SYMBOL_GPL(stmmac_get_mac_addr);
303
