1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11 #include <linux/clk.h>
12 #include <linux/version.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/spinlock.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/io.h>
22 #include <linux/list.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/of.h>
26 #include <linux/acpi.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/reset.h>
29
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <linux/usb/of.h>
33 #include <linux/usb/otg.h>
34
35 #include "core.h"
36 #include "gadget.h"
37 #include "io.h"
38
39 #include "debug.h"
40
41 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
42
43 /**
44 * dwc3_get_dr_mode - Validates and sets dr_mode
45 * @dwc: pointer to our context structure
46 */
dwc3_get_dr_mode(struct dwc3 * dwc)47 static int dwc3_get_dr_mode(struct dwc3 *dwc)
48 {
49 enum usb_dr_mode mode;
50 struct device *dev = dwc->dev;
51 unsigned int hw_mode;
52
53 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
54 dwc->dr_mode = USB_DR_MODE_OTG;
55
56 mode = dwc->dr_mode;
57 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
58
59 switch (hw_mode) {
60 case DWC3_GHWPARAMS0_MODE_GADGET:
61 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
62 dev_err(dev,
63 "Controller does not support host mode.\n");
64 return -EINVAL;
65 }
66 mode = USB_DR_MODE_PERIPHERAL;
67 break;
68 case DWC3_GHWPARAMS0_MODE_HOST:
69 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
70 dev_err(dev,
71 "Controller does not support device mode.\n");
72 return -EINVAL;
73 }
74 mode = USB_DR_MODE_HOST;
75 break;
76 default:
77 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
78 mode = USB_DR_MODE_HOST;
79 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
80 mode = USB_DR_MODE_PERIPHERAL;
81
82 /*
83 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
84 * mode. If the controller supports DRD but the dr_mode is not
85 * specified or set to OTG, then set the mode to peripheral.
86 */
87 if (mode == USB_DR_MODE_OTG &&
88 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
89 !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
90 !DWC3_VER_IS_PRIOR(DWC3, 330A))
91 mode = USB_DR_MODE_PERIPHERAL;
92 }
93
94 if (mode != dwc->dr_mode) {
95 dev_warn(dev,
96 "Configuration mismatch. dr_mode forced to %s\n",
97 mode == USB_DR_MODE_HOST ? "host" : "gadget");
98
99 dwc->dr_mode = mode;
100 }
101
102 return 0;
103 }
104
dwc3_set_prtcap(struct dwc3 * dwc,u32 mode)105 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
106 {
107 u32 reg;
108
109 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
110 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
111 reg |= DWC3_GCTL_PRTCAPDIR(mode);
112 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
113
114 dwc->current_dr_role = mode;
115 }
116
117 static int dwc3_core_soft_reset(struct dwc3 *dwc);
118
__dwc3_set_mode(struct work_struct * work)119 static void __dwc3_set_mode(struct work_struct *work)
120 {
121 struct dwc3 *dwc = work_to_dwc(work);
122 unsigned long flags;
123 int ret;
124 u32 reg;
125
126 mutex_lock(&dwc->mutex);
127
128 pm_runtime_get_sync(dwc->dev);
129
130 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
131 dwc3_otg_update(dwc, 0);
132
133 if (!dwc->desired_dr_role)
134 goto out;
135
136 if (dwc->desired_dr_role == dwc->current_dr_role)
137 goto out;
138
139 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
140 goto out;
141
142 switch (dwc->current_dr_role) {
143 case DWC3_GCTL_PRTCAP_HOST:
144 dwc3_host_exit(dwc);
145 break;
146 case DWC3_GCTL_PRTCAP_DEVICE:
147 dwc3_gadget_exit(dwc);
148 dwc3_event_buffers_cleanup(dwc);
149 break;
150 case DWC3_GCTL_PRTCAP_OTG:
151 dwc3_otg_exit(dwc);
152 spin_lock_irqsave(&dwc->lock, flags);
153 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
154 spin_unlock_irqrestore(&dwc->lock, flags);
155 dwc3_otg_update(dwc, 1);
156 break;
157 default:
158 break;
159 }
160
161 /* For DRD host or device mode only */
162 if (dwc->desired_dr_role != DWC3_GCTL_PRTCAP_OTG) {
163 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
164 reg |= DWC3_GCTL_CORESOFTRESET;
165 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
166
167 /*
168 * Wait for internal clocks to synchronized. DWC_usb31 and
169 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
170 * keep it consistent across different IPs, let's wait up to
171 * 100ms before clearing GCTL.CORESOFTRESET.
172 */
173 msleep(100);
174
175 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
176 reg &= ~DWC3_GCTL_CORESOFTRESET;
177 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
178 }
179
180 spin_lock_irqsave(&dwc->lock, flags);
181
182 dwc3_set_prtcap(dwc, dwc->desired_dr_role);
183
184 spin_unlock_irqrestore(&dwc->lock, flags);
185
186 switch (dwc->desired_dr_role) {
187 case DWC3_GCTL_PRTCAP_HOST:
188 ret = dwc3_host_init(dwc);
189 if (ret) {
190 dev_err(dwc->dev, "failed to initialize host\n");
191 } else {
192 if (dwc->usb2_phy)
193 otg_set_vbus(dwc->usb2_phy->otg, true);
194 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
195 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
196 if (dwc->dis_split_quirk) {
197 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
198 reg |= DWC3_GUCTL3_SPLITDISABLE;
199 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
200 }
201 }
202 break;
203 case DWC3_GCTL_PRTCAP_DEVICE:
204 dwc3_core_soft_reset(dwc);
205
206 dwc3_event_buffers_setup(dwc);
207
208 if (dwc->usb2_phy)
209 otg_set_vbus(dwc->usb2_phy->otg, false);
210 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
211 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
212
213 ret = dwc3_gadget_init(dwc);
214 if (ret)
215 dev_err(dwc->dev, "failed to initialize peripheral\n");
216 break;
217 case DWC3_GCTL_PRTCAP_OTG:
218 dwc3_otg_init(dwc);
219 dwc3_otg_update(dwc, 0);
220 break;
221 default:
222 break;
223 }
224
225 out:
226 pm_runtime_mark_last_busy(dwc->dev);
227 pm_runtime_put_autosuspend(dwc->dev);
228 mutex_unlock(&dwc->mutex);
229 }
230
dwc3_set_mode(struct dwc3 * dwc,u32 mode)231 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
232 {
233 unsigned long flags;
234
235 if (dwc->dr_mode != USB_DR_MODE_OTG)
236 return;
237
238 spin_lock_irqsave(&dwc->lock, flags);
239 dwc->desired_dr_role = mode;
240 spin_unlock_irqrestore(&dwc->lock, flags);
241
242 queue_work(system_freezable_wq, &dwc->drd_work);
243 }
244
dwc3_core_fifo_space(struct dwc3_ep * dep,u8 type)245 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
246 {
247 struct dwc3 *dwc = dep->dwc;
248 u32 reg;
249
250 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
251 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
252 DWC3_GDBGFIFOSPACE_TYPE(type));
253
254 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
255
256 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
257 }
258
259 /**
260 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
261 * @dwc: pointer to our context structure
262 */
dwc3_core_soft_reset(struct dwc3 * dwc)263 static int dwc3_core_soft_reset(struct dwc3 *dwc)
264 {
265 u32 reg;
266 int retries = 1000;
267
268 /*
269 * We're resetting only the device side because, if we're in host mode,
270 * XHCI driver will reset the host block. If dwc3 was configured for
271 * host-only mode, then we can return early.
272 */
273 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
274 return 0;
275
276 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
277 reg |= DWC3_DCTL_CSFTRST;
278 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
279
280 /*
281 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
282 * is cleared only after all the clocks are synchronized. This can
283 * take a little more than 50ms. Set the polling rate at 20ms
284 * for 10 times instead.
285 */
286 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
287 retries = 10;
288
289 do {
290 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
291 if (!(reg & DWC3_DCTL_CSFTRST))
292 goto done;
293
294 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
295 msleep(20);
296 else
297 udelay(1);
298 } while (--retries);
299
300 return -ETIMEDOUT;
301
302 done:
303 /*
304 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
305 * is cleared, we must wait at least 50ms before accessing the PHY
306 * domain (synchronization delay).
307 */
308 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
309 msleep(50);
310
311 return 0;
312 }
313
314 /*
315 * dwc3_frame_length_adjustment - Adjusts frame length if required
316 * @dwc3: Pointer to our controller context structure
317 */
dwc3_frame_length_adjustment(struct dwc3 * dwc)318 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
319 {
320 u32 reg;
321 u32 dft;
322
323 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
324 return;
325
326 if (dwc->fladj == 0)
327 return;
328
329 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
330 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
331 if (dft != dwc->fladj) {
332 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
333 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
334 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
335 }
336 }
337
338 /**
339 * dwc3_free_one_event_buffer - Frees one event buffer
340 * @dwc: Pointer to our controller context structure
341 * @evt: Pointer to event buffer to be freed
342 */
dwc3_free_one_event_buffer(struct dwc3 * dwc,struct dwc3_event_buffer * evt)343 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
344 struct dwc3_event_buffer *evt)
345 {
346 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
347 }
348
349 /**
350 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
351 * @dwc: Pointer to our controller context structure
352 * @length: size of the event buffer
353 *
354 * Returns a pointer to the allocated event buffer structure on success
355 * otherwise ERR_PTR(errno).
356 */
dwc3_alloc_one_event_buffer(struct dwc3 * dwc,unsigned length)357 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
358 unsigned length)
359 {
360 struct dwc3_event_buffer *evt;
361
362 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
363 if (!evt)
364 return ERR_PTR(-ENOMEM);
365
366 evt->dwc = dwc;
367 evt->length = length;
368 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
369 if (!evt->cache)
370 return ERR_PTR(-ENOMEM);
371
372 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
373 &evt->dma, GFP_KERNEL);
374 if (!evt->buf)
375 return ERR_PTR(-ENOMEM);
376
377 return evt;
378 }
379
380 /**
381 * dwc3_free_event_buffers - frees all allocated event buffers
382 * @dwc: Pointer to our controller context structure
383 */
dwc3_free_event_buffers(struct dwc3 * dwc)384 static void dwc3_free_event_buffers(struct dwc3 *dwc)
385 {
386 struct dwc3_event_buffer *evt;
387
388 evt = dwc->ev_buf;
389 if (evt)
390 dwc3_free_one_event_buffer(dwc, evt);
391 }
392
393 /**
394 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
395 * @dwc: pointer to our controller context structure
396 * @length: size of event buffer
397 *
398 * Returns 0 on success otherwise negative errno. In the error case, dwc
399 * may contain some buffers allocated but not all which were requested.
400 */
dwc3_alloc_event_buffers(struct dwc3 * dwc,unsigned length)401 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
402 {
403 struct dwc3_event_buffer *evt;
404
405 evt = dwc3_alloc_one_event_buffer(dwc, length);
406 if (IS_ERR(evt)) {
407 dev_err(dwc->dev, "can't allocate event buffer\n");
408 return PTR_ERR(evt);
409 }
410 dwc->ev_buf = evt;
411
412 return 0;
413 }
414
415 /**
416 * dwc3_event_buffers_setup - setup our allocated event buffers
417 * @dwc: pointer to our controller context structure
418 *
419 * Returns 0 on success otherwise negative errno.
420 */
dwc3_event_buffers_setup(struct dwc3 * dwc)421 int dwc3_event_buffers_setup(struct dwc3 *dwc)
422 {
423 struct dwc3_event_buffer *evt;
424
425 evt = dwc->ev_buf;
426 evt->lpos = 0;
427 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
428 lower_32_bits(evt->dma));
429 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
430 upper_32_bits(evt->dma));
431 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
432 DWC3_GEVNTSIZ_SIZE(evt->length));
433 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
434
435 return 0;
436 }
437
dwc3_event_buffers_cleanup(struct dwc3 * dwc)438 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
439 {
440 struct dwc3_event_buffer *evt;
441
442 evt = dwc->ev_buf;
443
444 evt->lpos = 0;
445
446 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
447 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
448 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
449 | DWC3_GEVNTSIZ_SIZE(0));
450 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
451 }
452
dwc3_alloc_scratch_buffers(struct dwc3 * dwc)453 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
454 {
455 if (!dwc->has_hibernation)
456 return 0;
457
458 if (!dwc->nr_scratch)
459 return 0;
460
461 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
462 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
463 if (!dwc->scratchbuf)
464 return -ENOMEM;
465
466 return 0;
467 }
468
dwc3_setup_scratch_buffers(struct dwc3 * dwc)469 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
470 {
471 dma_addr_t scratch_addr;
472 u32 param;
473 int ret;
474
475 if (!dwc->has_hibernation)
476 return 0;
477
478 if (!dwc->nr_scratch)
479 return 0;
480
481 /* should never fall here */
482 if (!WARN_ON(dwc->scratchbuf))
483 return 0;
484
485 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
486 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
487 DMA_BIDIRECTIONAL);
488 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
489 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
490 ret = -EFAULT;
491 goto err0;
492 }
493
494 dwc->scratch_addr = scratch_addr;
495
496 param = lower_32_bits(scratch_addr);
497
498 ret = dwc3_send_gadget_generic_command(dwc,
499 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
500 if (ret < 0)
501 goto err1;
502
503 param = upper_32_bits(scratch_addr);
504
505 ret = dwc3_send_gadget_generic_command(dwc,
506 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
507 if (ret < 0)
508 goto err1;
509
510 return 0;
511
512 err1:
513 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
514 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
515
516 err0:
517 return ret;
518 }
519
dwc3_free_scratch_buffers(struct dwc3 * dwc)520 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
521 {
522 if (!dwc->has_hibernation)
523 return;
524
525 if (!dwc->nr_scratch)
526 return;
527
528 /* should never fall here */
529 if (!WARN_ON(dwc->scratchbuf))
530 return;
531
532 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
533 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
534 kfree(dwc->scratchbuf);
535 }
536
dwc3_core_num_eps(struct dwc3 * dwc)537 static void dwc3_core_num_eps(struct dwc3 *dwc)
538 {
539 struct dwc3_hwparams *parms = &dwc->hwparams;
540
541 dwc->num_eps = DWC3_NUM_EPS(parms);
542 }
543
dwc3_cache_hwparams(struct dwc3 * dwc)544 static void dwc3_cache_hwparams(struct dwc3 *dwc)
545 {
546 struct dwc3_hwparams *parms = &dwc->hwparams;
547
548 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
549 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
550 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
551 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
552 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
553 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
554 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
555 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
556 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
557
558 if (DWC3_IP_IS(DWC32))
559 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
560 }
561
dwc3_core_ulpi_init(struct dwc3 * dwc)562 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
563 {
564 int intf;
565 int ret = 0;
566
567 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
568
569 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
570 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
571 dwc->hsphy_interface &&
572 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
573 ret = dwc3_ulpi_init(dwc);
574
575 return ret;
576 }
577
578 /**
579 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
580 * @dwc: Pointer to our controller context structure
581 *
582 * Returns 0 on success. The USB PHY interfaces are configured but not
583 * initialized. The PHY interfaces and the PHYs get initialized together with
584 * the core in dwc3_core_init.
585 */
dwc3_phy_setup(struct dwc3 * dwc)586 static int dwc3_phy_setup(struct dwc3 *dwc)
587 {
588 unsigned int hw_mode;
589 u32 reg;
590
591 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
592
593 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
594
595 /*
596 * Make sure UX_EXIT_PX is cleared as that causes issues with some
597 * PHYs. Also, this bit is not supposed to be used in normal operation.
598 */
599 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
600
601 /*
602 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
603 * to '0' during coreConsultant configuration. So default value
604 * will be '0' when the core is reset. Application needs to set it
605 * to '1' after the core initialization is completed.
606 */
607 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
608 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
609
610 /*
611 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
612 * power-on reset, and it can be set after core initialization, which is
613 * after device soft-reset during initialization.
614 */
615 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
616 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
617
618 if (dwc->u2ss_inp3_quirk)
619 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
620
621 if (dwc->dis_rxdet_inp3_quirk)
622 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
623
624 if (dwc->req_p1p2p3_quirk)
625 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
626
627 if (dwc->del_p1p2p3_quirk)
628 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
629
630 if (dwc->del_phy_power_chg_quirk)
631 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
632
633 if (dwc->lfps_filter_quirk)
634 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
635
636 if (dwc->rx_detect_poll_quirk)
637 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
638
639 if (dwc->tx_de_emphasis_quirk)
640 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
641
642 if (dwc->dis_u3_susphy_quirk)
643 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
644
645 if (dwc->dis_del_phy_power_chg_quirk)
646 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
647
648 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
649
650 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
651
652 /* Select the HS PHY interface */
653 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
654 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
655 if (dwc->hsphy_interface &&
656 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
657 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
658 break;
659 } else if (dwc->hsphy_interface &&
660 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
661 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
662 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
663 } else {
664 /* Relying on default value. */
665 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
666 break;
667 }
668 fallthrough;
669 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
670 default:
671 break;
672 }
673
674 switch (dwc->hsphy_mode) {
675 case USBPHY_INTERFACE_MODE_UTMI:
676 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
677 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
678 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
679 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
680 break;
681 case USBPHY_INTERFACE_MODE_UTMIW:
682 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
683 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
684 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
685 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
686 break;
687 default:
688 break;
689 }
690
691 /*
692 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
693 * '0' during coreConsultant configuration. So default value will
694 * be '0' when the core is reset. Application needs to set it to
695 * '1' after the core initialization is completed.
696 */
697 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
698 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
699
700 /*
701 * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
702 * power-on reset, and it can be set after core initialization, which is
703 * after device soft-reset during initialization.
704 */
705 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
706 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
707
708 if (dwc->dis_u2_susphy_quirk)
709 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
710
711 if (dwc->dis_enblslpm_quirk)
712 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
713 else
714 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
715
716 if (dwc->dis_u2_freeclk_exists_quirk)
717 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
718
719 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
720
721 return 0;
722 }
723
dwc3_core_exit(struct dwc3 * dwc)724 static void dwc3_core_exit(struct dwc3 *dwc)
725 {
726 dwc3_event_buffers_cleanup(dwc);
727
728 usb_phy_shutdown(dwc->usb2_phy);
729 usb_phy_shutdown(dwc->usb3_phy);
730 phy_exit(dwc->usb2_generic_phy);
731 phy_exit(dwc->usb3_generic_phy);
732
733 usb_phy_set_suspend(dwc->usb2_phy, 1);
734 usb_phy_set_suspend(dwc->usb3_phy, 1);
735 phy_power_off(dwc->usb2_generic_phy);
736 phy_power_off(dwc->usb3_generic_phy);
737 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
738 reset_control_assert(dwc->reset);
739 }
740
dwc3_core_is_valid(struct dwc3 * dwc)741 static bool dwc3_core_is_valid(struct dwc3 *dwc)
742 {
743 u32 reg;
744
745 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
746 dwc->ip = DWC3_GSNPS_ID(reg);
747
748 /* This should read as U3 followed by revision number */
749 if (DWC3_IP_IS(DWC3)) {
750 dwc->revision = reg;
751 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
752 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
753 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
754 } else {
755 return false;
756 }
757
758 return true;
759 }
760
dwc3_core_setup_global_control(struct dwc3 * dwc)761 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
762 {
763 u32 hwparams4 = dwc->hwparams.hwparams4;
764 u32 reg;
765
766 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
767 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
768
769 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
770 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
771 /**
772 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
773 * issue which would cause xHCI compliance tests to fail.
774 *
775 * Because of that we cannot enable clock gating on such
776 * configurations.
777 *
778 * Refers to:
779 *
780 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
781 * SOF/ITP Mode Used
782 */
783 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
784 dwc->dr_mode == USB_DR_MODE_OTG) &&
785 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
786 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
787 else
788 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
789 break;
790 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
791 /* enable hibernation here */
792 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
793
794 /*
795 * REVISIT Enabling this bit so that host-mode hibernation
796 * will work. Device-mode hibernation is not yet implemented.
797 */
798 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
799 break;
800 default:
801 /* nothing */
802 break;
803 }
804
805 /* check if current dwc3 is on simulation board */
806 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
807 dev_info(dwc->dev, "Running with FPGA optimizations\n");
808 dwc->is_fpga = true;
809 }
810
811 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
812 "disable_scramble cannot be used on non-FPGA builds\n");
813
814 if (dwc->disable_scramble_quirk && dwc->is_fpga)
815 reg |= DWC3_GCTL_DISSCRAMBLE;
816 else
817 reg &= ~DWC3_GCTL_DISSCRAMBLE;
818
819 if (dwc->u2exit_lfps_quirk)
820 reg |= DWC3_GCTL_U2EXIT_LFPS;
821
822 /*
823 * WORKAROUND: DWC3 revisions <1.90a have a bug
824 * where the device can fail to connect at SuperSpeed
825 * and falls back to high-speed mode which causes
826 * the device to enter a Connect/Disconnect loop
827 */
828 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
829 reg |= DWC3_GCTL_U2RSTECN;
830
831 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
832 }
833
834 static int dwc3_core_get_phy(struct dwc3 *dwc);
835 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
836
837 /* set global incr burst type configuration registers */
dwc3_set_incr_burst_type(struct dwc3 * dwc)838 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
839 {
840 struct device *dev = dwc->dev;
841 /* incrx_mode : for INCR burst type. */
842 bool incrx_mode;
843 /* incrx_size : for size of INCRX burst. */
844 u32 incrx_size;
845 u32 *vals;
846 u32 cfg;
847 int ntype;
848 int ret;
849 int i;
850
851 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
852
853 /*
854 * Handle property "snps,incr-burst-type-adjustment".
855 * Get the number of value from this property:
856 * result <= 0, means this property is not supported.
857 * result = 1, means INCRx burst mode supported.
858 * result > 1, means undefined length burst mode supported.
859 */
860 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
861 if (ntype <= 0)
862 return;
863
864 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
865 if (!vals) {
866 dev_err(dev, "Error to get memory\n");
867 return;
868 }
869
870 /* Get INCR burst type, and parse it */
871 ret = device_property_read_u32_array(dev,
872 "snps,incr-burst-type-adjustment", vals, ntype);
873 if (ret) {
874 kfree(vals);
875 dev_err(dev, "Error to get property\n");
876 return;
877 }
878
879 incrx_size = *vals;
880
881 if (ntype > 1) {
882 /* INCRX (undefined length) burst mode */
883 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
884 for (i = 1; i < ntype; i++) {
885 if (vals[i] > incrx_size)
886 incrx_size = vals[i];
887 }
888 } else {
889 /* INCRX burst mode */
890 incrx_mode = INCRX_BURST_MODE;
891 }
892
893 kfree(vals);
894
895 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
896 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
897 if (incrx_mode)
898 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
899 switch (incrx_size) {
900 case 256:
901 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
902 break;
903 case 128:
904 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
905 break;
906 case 64:
907 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
908 break;
909 case 32:
910 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
911 break;
912 case 16:
913 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
914 break;
915 case 8:
916 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
917 break;
918 case 4:
919 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
920 break;
921 case 1:
922 break;
923 default:
924 dev_err(dev, "Invalid property\n");
925 break;
926 }
927
928 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
929 }
930
931 /**
932 * dwc3_core_init - Low-level initialization of DWC3 Core
933 * @dwc: Pointer to our controller context structure
934 *
935 * Returns 0 on success otherwise negative errno.
936 */
dwc3_core_init(struct dwc3 * dwc)937 static int dwc3_core_init(struct dwc3 *dwc)
938 {
939 unsigned int hw_mode;
940 u32 reg;
941 int ret;
942
943 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
944
945 /*
946 * Write Linux Version Code to our GUID register so it's easy to figure
947 * out which kernel version a bug was found.
948 */
949 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
950
951 ret = dwc3_phy_setup(dwc);
952 if (ret)
953 goto err0;
954
955 if (!dwc->ulpi_ready) {
956 ret = dwc3_core_ulpi_init(dwc);
957 if (ret)
958 goto err0;
959 dwc->ulpi_ready = true;
960 }
961
962 if (!dwc->phys_ready) {
963 ret = dwc3_core_get_phy(dwc);
964 if (ret)
965 goto err0a;
966 dwc->phys_ready = true;
967 }
968
969 usb_phy_init(dwc->usb2_phy);
970 usb_phy_init(dwc->usb3_phy);
971 ret = phy_init(dwc->usb2_generic_phy);
972 if (ret < 0)
973 goto err0a;
974
975 ret = phy_init(dwc->usb3_generic_phy);
976 if (ret < 0) {
977 phy_exit(dwc->usb2_generic_phy);
978 goto err0a;
979 }
980
981 ret = dwc3_core_soft_reset(dwc);
982 if (ret)
983 goto err1;
984
985 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
986 !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
987 if (!dwc->dis_u3_susphy_quirk) {
988 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
989 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
990 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
991 }
992
993 if (!dwc->dis_u2_susphy_quirk) {
994 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
995 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
996 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
997 }
998 }
999
1000 dwc3_core_setup_global_control(dwc);
1001 dwc3_core_num_eps(dwc);
1002
1003 ret = dwc3_setup_scratch_buffers(dwc);
1004 if (ret)
1005 goto err1;
1006
1007 /* Adjust Frame Length */
1008 dwc3_frame_length_adjustment(dwc);
1009
1010 dwc3_set_incr_burst_type(dwc);
1011
1012 usb_phy_set_suspend(dwc->usb2_phy, 0);
1013 usb_phy_set_suspend(dwc->usb3_phy, 0);
1014 ret = phy_power_on(dwc->usb2_generic_phy);
1015 if (ret < 0)
1016 goto err2;
1017
1018 ret = phy_power_on(dwc->usb3_generic_phy);
1019 if (ret < 0)
1020 goto err3;
1021
1022 ret = dwc3_event_buffers_setup(dwc);
1023 if (ret) {
1024 dev_err(dwc->dev, "failed to setup event buffers\n");
1025 goto err4;
1026 }
1027
1028 /*
1029 * ENDXFER polling is available on version 3.10a and later of
1030 * the DWC_usb3 controller. It is NOT available in the
1031 * DWC_usb31 controller.
1032 */
1033 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1034 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1035 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1036 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1037 }
1038
1039 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1040 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1041
1042 /*
1043 * Enable hardware control of sending remote wakeup
1044 * in HS when the device is in the L1 state.
1045 */
1046 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1047 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1048
1049 /*
1050 * Decouple USB 2.0 L1 & L2 events which will allow for
1051 * gadget driver to only receive U3/L2 suspend & wakeup
1052 * events and prevent the more frequent L1 LPM transitions
1053 * from interrupting the driver.
1054 */
1055 if (!DWC3_VER_IS_PRIOR(DWC3, 300A))
1056 reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT;
1057
1058 if (dwc->dis_tx_ipgap_linecheck_quirk)
1059 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1060
1061 if (dwc->parkmode_disable_ss_quirk)
1062 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1063
1064 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1065 }
1066
1067 if (dwc->dr_mode == USB_DR_MODE_HOST ||
1068 dwc->dr_mode == USB_DR_MODE_OTG) {
1069 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1070
1071 /*
1072 * Enable Auto retry Feature to make the controller operating in
1073 * Host mode on seeing transaction errors(CRC errors or internal
1074 * overrun scenerios) on IN transfers to reply to the device
1075 * with a non-terminating retry ACK (i.e, an ACK transcation
1076 * packet with Retry=1 & Nump != 0)
1077 */
1078 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1079
1080 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1081 }
1082
1083 /*
1084 * Must config both number of packets and max burst settings to enable
1085 * RX and/or TX threshold.
1086 */
1087 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1088 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1089 u8 rx_maxburst = dwc->rx_max_burst_prd;
1090 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1091 u8 tx_maxburst = dwc->tx_max_burst_prd;
1092
1093 if (rx_thr_num && rx_maxburst) {
1094 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1095 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1096
1097 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1098 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1099
1100 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1101 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1102
1103 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1104 }
1105
1106 if (tx_thr_num && tx_maxburst) {
1107 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1108 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1109
1110 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1111 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1112
1113 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1114 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1115
1116 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1117 }
1118 }
1119
1120 return 0;
1121
1122 err4:
1123 phy_power_off(dwc->usb3_generic_phy);
1124
1125 err3:
1126 phy_power_off(dwc->usb2_generic_phy);
1127
1128 err2:
1129 usb_phy_set_suspend(dwc->usb2_phy, 1);
1130 usb_phy_set_suspend(dwc->usb3_phy, 1);
1131
1132 err1:
1133 usb_phy_shutdown(dwc->usb2_phy);
1134 usb_phy_shutdown(dwc->usb3_phy);
1135 phy_exit(dwc->usb2_generic_phy);
1136 phy_exit(dwc->usb3_generic_phy);
1137
1138 err0a:
1139 dwc3_ulpi_exit(dwc);
1140
1141 err0:
1142 return ret;
1143 }
1144
dwc3_core_get_phy(struct dwc3 * dwc)1145 static int dwc3_core_get_phy(struct dwc3 *dwc)
1146 {
1147 struct device *dev = dwc->dev;
1148 struct device_node *node = dev->of_node;
1149 int ret;
1150
1151 if (node) {
1152 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1153 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1154 } else {
1155 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1156 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1157 }
1158
1159 if (IS_ERR(dwc->usb2_phy)) {
1160 ret = PTR_ERR(dwc->usb2_phy);
1161 if (ret == -ENXIO || ret == -ENODEV) {
1162 dwc->usb2_phy = NULL;
1163 } else {
1164 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1165 }
1166 }
1167
1168 if (IS_ERR(dwc->usb3_phy)) {
1169 ret = PTR_ERR(dwc->usb3_phy);
1170 if (ret == -ENXIO || ret == -ENODEV) {
1171 dwc->usb3_phy = NULL;
1172 } else {
1173 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1174 }
1175 }
1176
1177 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1178 if (IS_ERR(dwc->usb2_generic_phy)) {
1179 ret = PTR_ERR(dwc->usb2_generic_phy);
1180 if (ret == -ENOSYS || ret == -ENODEV) {
1181 dwc->usb2_generic_phy = NULL;
1182 } else {
1183 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1184 }
1185 }
1186
1187 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1188 if (IS_ERR(dwc->usb3_generic_phy)) {
1189 ret = PTR_ERR(dwc->usb3_generic_phy);
1190 if (ret == -ENOSYS || ret == -ENODEV) {
1191 dwc->usb3_generic_phy = NULL;
1192 } else {
1193 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1194 }
1195 }
1196
1197 return 0;
1198 }
1199
dwc3_core_init_mode(struct dwc3 * dwc)1200 static int dwc3_core_init_mode(struct dwc3 *dwc)
1201 {
1202 struct device *dev = dwc->dev;
1203 int ret;
1204
1205 switch (dwc->dr_mode) {
1206 case USB_DR_MODE_PERIPHERAL:
1207 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1208
1209 if (dwc->usb2_phy)
1210 otg_set_vbus(dwc->usb2_phy->otg, false);
1211 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1212 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1213
1214 ret = dwc3_gadget_init(dwc);
1215 if (ret)
1216 return dev_err_probe(dev, ret, "failed to initialize gadget\n");
1217 break;
1218 case USB_DR_MODE_HOST:
1219 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1220
1221 if (dwc->usb2_phy)
1222 otg_set_vbus(dwc->usb2_phy->otg, true);
1223 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1224 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1225
1226 ret = dwc3_host_init(dwc);
1227 if (ret)
1228 return dev_err_probe(dev, ret, "failed to initialize host\n");
1229 break;
1230 case USB_DR_MODE_OTG:
1231 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1232 ret = dwc3_drd_init(dwc);
1233 if (ret)
1234 return dev_err_probe(dev, ret, "failed to initialize dual-role\n");
1235 break;
1236 default:
1237 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1238 return -EINVAL;
1239 }
1240
1241 return 0;
1242 }
1243
dwc3_core_exit_mode(struct dwc3 * dwc)1244 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1245 {
1246 switch (dwc->dr_mode) {
1247 case USB_DR_MODE_PERIPHERAL:
1248 dwc3_gadget_exit(dwc);
1249 break;
1250 case USB_DR_MODE_HOST:
1251 dwc3_host_exit(dwc);
1252 break;
1253 case USB_DR_MODE_OTG:
1254 dwc3_drd_exit(dwc);
1255 break;
1256 default:
1257 /* do nothing */
1258 break;
1259 }
1260
1261 /* de-assert DRVVBUS for HOST and OTG mode */
1262 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1263 }
1264
dwc3_get_properties(struct dwc3 * dwc)1265 static void dwc3_get_properties(struct dwc3 *dwc)
1266 {
1267 struct device *dev = dwc->dev;
1268 u8 lpm_nyet_threshold;
1269 u8 tx_de_emphasis;
1270 u8 hird_threshold;
1271 u8 rx_thr_num_pkt_prd;
1272 u8 rx_max_burst_prd;
1273 u8 tx_thr_num_pkt_prd;
1274 u8 tx_max_burst_prd;
1275 u8 tx_fifo_resize_max_num;
1276 const char *usb_psy_name;
1277 int ret;
1278
1279 /* default to highest possible threshold */
1280 lpm_nyet_threshold = 0xf;
1281
1282 /* default to -3.5dB de-emphasis */
1283 tx_de_emphasis = 1;
1284
1285 /*
1286 * default to assert utmi_sleep_n and use maximum allowed HIRD
1287 * threshold value of 0b1100
1288 */
1289 hird_threshold = 12;
1290
1291 /*
1292 * default to a TXFIFO size large enough to fit 6 max packets. This
1293 * allows for systems with larger bus latencies to have some headroom
1294 * for endpoints that have a large bMaxBurst value.
1295 */
1296 tx_fifo_resize_max_num = 6;
1297
1298 dwc->maximum_speed = usb_get_maximum_speed(dev);
1299 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
1300 dwc->dr_mode = usb_get_dr_mode(dev);
1301 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1302
1303 dwc->sysdev_is_parent = device_property_read_bool(dev,
1304 "linux,sysdev_is_parent");
1305 if (dwc->sysdev_is_parent)
1306 dwc->sysdev = dwc->dev->parent;
1307 else
1308 dwc->sysdev = dwc->dev;
1309
1310 ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name);
1311 if (ret >= 0) {
1312 dwc->usb_psy = power_supply_get_by_name(usb_psy_name);
1313 if (!dwc->usb_psy)
1314 dev_err(dev, "couldn't get usb power supply\n");
1315 }
1316
1317 dwc->has_lpm_erratum = device_property_read_bool(dev,
1318 "snps,has-lpm-erratum");
1319 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1320 &lpm_nyet_threshold);
1321 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1322 "snps,is-utmi-l1-suspend");
1323 device_property_read_u8(dev, "snps,hird-threshold",
1324 &hird_threshold);
1325 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1326 "snps,dis-start-transfer-quirk");
1327 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1328 "snps,usb3_lpm_capable");
1329 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1330 "snps,usb2-lpm-disable");
1331 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1332 "snps,usb2-gadget-lpm-disable");
1333 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1334 &rx_thr_num_pkt_prd);
1335 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1336 &rx_max_burst_prd);
1337 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1338 &tx_thr_num_pkt_prd);
1339 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1340 &tx_max_burst_prd);
1341 dwc->do_fifo_resize = device_property_read_bool(dev,
1342 "tx-fifo-resize");
1343 if (dwc->do_fifo_resize)
1344 device_property_read_u8(dev, "tx-fifo-max-num",
1345 &tx_fifo_resize_max_num);
1346
1347 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1348 "snps,disable_scramble_quirk");
1349 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1350 "snps,u2exit_lfps_quirk");
1351 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1352 "snps,u2ss_inp3_quirk");
1353 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1354 "snps,req_p1p2p3_quirk");
1355 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1356 "snps,del_p1p2p3_quirk");
1357 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1358 "snps,del_phy_power_chg_quirk");
1359 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1360 "snps,lfps_filter_quirk");
1361 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1362 "snps,rx_detect_poll_quirk");
1363 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1364 "snps,dis_u3_susphy_quirk");
1365 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1366 "snps,dis_u2_susphy_quirk");
1367 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1368 "snps,dis_enblslpm_quirk");
1369 dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1370 "snps,dis-u1-entry-quirk");
1371 dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1372 "snps,dis-u2-entry-quirk");
1373 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1374 "snps,dis_rxdet_inp3_quirk");
1375 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1376 "snps,dis-u2-freeclk-exists-quirk");
1377 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1378 "snps,dis-del-phy-power-chg-quirk");
1379 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1380 "snps,dis-tx-ipgap-linecheck-quirk");
1381 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1382 "snps,parkmode-disable-ss-quirk");
1383
1384 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1385 "snps,tx_de_emphasis_quirk");
1386 device_property_read_u8(dev, "snps,tx_de_emphasis",
1387 &tx_de_emphasis);
1388 device_property_read_string(dev, "snps,hsphy_interface",
1389 &dwc->hsphy_interface);
1390 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1391 &dwc->fladj);
1392
1393 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1394 "snps,dis_metastability_quirk");
1395
1396 dwc->dis_split_quirk = device_property_read_bool(dev,
1397 "snps,dis-split-quirk");
1398
1399 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1400 dwc->tx_de_emphasis = tx_de_emphasis;
1401
1402 dwc->hird_threshold = hird_threshold;
1403
1404 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1405 dwc->rx_max_burst_prd = rx_max_burst_prd;
1406
1407 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1408 dwc->tx_max_burst_prd = tx_max_burst_prd;
1409
1410 dwc->imod_interval = 0;
1411
1412 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
1413 }
1414
1415 /* check whether the core supports IMOD */
dwc3_has_imod(struct dwc3 * dwc)1416 bool dwc3_has_imod(struct dwc3 *dwc)
1417 {
1418 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1419 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1420 DWC3_IP_IS(DWC32);
1421 }
1422
dwc3_check_params(struct dwc3 * dwc)1423 static void dwc3_check_params(struct dwc3 *dwc)
1424 {
1425 struct device *dev = dwc->dev;
1426 unsigned int hwparam_gen =
1427 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1428
1429 /* Check for proper value of imod_interval */
1430 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1431 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1432 dwc->imod_interval = 0;
1433 }
1434
1435 /*
1436 * Workaround for STAR 9000961433 which affects only version
1437 * 3.00a of the DWC_usb3 core. This prevents the controller
1438 * interrupt from being masked while handling events. IMOD
1439 * allows us to work around this issue. Enable it for the
1440 * affected version.
1441 */
1442 if (!dwc->imod_interval &&
1443 DWC3_VER_IS(DWC3, 300A))
1444 dwc->imod_interval = 1;
1445
1446 /* Check the maximum_speed parameter */
1447 switch (dwc->maximum_speed) {
1448 case USB_SPEED_FULL:
1449 case USB_SPEED_HIGH:
1450 break;
1451 case USB_SPEED_SUPER:
1452 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1453 dev_warn(dev, "UDC doesn't support Gen 1\n");
1454 break;
1455 case USB_SPEED_SUPER_PLUS:
1456 if ((DWC3_IP_IS(DWC32) &&
1457 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1458 (!DWC3_IP_IS(DWC32) &&
1459 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1460 dev_warn(dev, "UDC doesn't support SSP\n");
1461 break;
1462 default:
1463 dev_err(dev, "invalid maximum_speed parameter %d\n",
1464 dwc->maximum_speed);
1465 fallthrough;
1466 case USB_SPEED_UNKNOWN:
1467 switch (hwparam_gen) {
1468 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1469 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1470 break;
1471 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1472 if (DWC3_IP_IS(DWC32))
1473 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1474 else
1475 dwc->maximum_speed = USB_SPEED_SUPER;
1476 break;
1477 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1478 dwc->maximum_speed = USB_SPEED_HIGH;
1479 break;
1480 default:
1481 dwc->maximum_speed = USB_SPEED_SUPER;
1482 break;
1483 }
1484 break;
1485 }
1486
1487 /*
1488 * Currently the controller does not have visibility into the HW
1489 * parameter to determine the maximum number of lanes the HW supports.
1490 * If the number of lanes is not specified in the device property, then
1491 * set the default to support dual-lane for DWC_usb32 and single-lane
1492 * for DWC_usb31 for super-speed-plus.
1493 */
1494 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
1495 switch (dwc->max_ssp_rate) {
1496 case USB_SSP_GEN_2x1:
1497 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1)
1498 dev_warn(dev, "UDC only supports Gen 1\n");
1499 break;
1500 case USB_SSP_GEN_1x2:
1501 case USB_SSP_GEN_2x2:
1502 if (DWC3_IP_IS(DWC31))
1503 dev_warn(dev, "UDC only supports single lane\n");
1504 break;
1505 case USB_SSP_GEN_UNKNOWN:
1506 default:
1507 switch (hwparam_gen) {
1508 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1509 if (DWC3_IP_IS(DWC32))
1510 dwc->max_ssp_rate = USB_SSP_GEN_2x2;
1511 else
1512 dwc->max_ssp_rate = USB_SSP_GEN_2x1;
1513 break;
1514 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1515 if (DWC3_IP_IS(DWC32))
1516 dwc->max_ssp_rate = USB_SSP_GEN_1x2;
1517 break;
1518 }
1519 break;
1520 }
1521 }
1522 }
1523
dwc3_probe(struct platform_device * pdev)1524 static int dwc3_probe(struct platform_device *pdev)
1525 {
1526 struct device *dev = &pdev->dev;
1527 struct resource *res, dwc_res;
1528 struct dwc3 *dwc;
1529
1530 int ret;
1531
1532 void __iomem *regs;
1533
1534 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1535 if (!dwc)
1536 return -ENOMEM;
1537
1538 dwc->dev = dev;
1539
1540 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1541 if (!res) {
1542 dev_err(dev, "missing memory resource\n");
1543 return -ENODEV;
1544 }
1545
1546 dwc->xhci_resources[0].start = res->start;
1547 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1548 DWC3_XHCI_REGS_END;
1549 dwc->xhci_resources[0].flags = res->flags;
1550 dwc->xhci_resources[0].name = res->name;
1551
1552 /*
1553 * Request memory region but exclude xHCI regs,
1554 * since it will be requested by the xhci-plat driver.
1555 */
1556 dwc_res = *res;
1557 dwc_res.start += DWC3_GLOBALS_REGS_START;
1558
1559 regs = devm_ioremap_resource(dev, &dwc_res);
1560 if (IS_ERR(regs))
1561 return PTR_ERR(regs);
1562
1563 dwc->regs = regs;
1564 dwc->regs_size = resource_size(&dwc_res);
1565
1566 dwc3_get_properties(dwc);
1567
1568 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
1569 if (ret)
1570 return ret;
1571
1572 dwc->reset = devm_reset_control_array_get_optional_shared(dev);
1573 if (IS_ERR(dwc->reset))
1574 return PTR_ERR(dwc->reset);
1575
1576 if (dev->of_node) {
1577 ret = devm_clk_bulk_get_all(dev, &dwc->clks);
1578 if (ret == -EPROBE_DEFER)
1579 return ret;
1580 /*
1581 * Clocks are optional, but new DT platforms should support all
1582 * clocks as required by the DT-binding.
1583 */
1584 if (ret < 0)
1585 dwc->num_clks = 0;
1586 else
1587 dwc->num_clks = ret;
1588
1589 }
1590
1591 ret = reset_control_deassert(dwc->reset);
1592 if (ret)
1593 return ret;
1594
1595 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1596 if (ret)
1597 goto assert_reset;
1598
1599 if (!dwc3_core_is_valid(dwc)) {
1600 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1601 ret = -ENODEV;
1602 goto disable_clks;
1603 }
1604
1605 platform_set_drvdata(pdev, dwc);
1606 dwc3_cache_hwparams(dwc);
1607
1608 spin_lock_init(&dwc->lock);
1609 mutex_init(&dwc->mutex);
1610
1611 pm_runtime_set_active(dev);
1612 pm_runtime_use_autosuspend(dev);
1613 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1614 pm_runtime_enable(dev);
1615 ret = pm_runtime_get_sync(dev);
1616 if (ret < 0)
1617 goto err1;
1618
1619 pm_runtime_forbid(dev);
1620
1621 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1622 if (ret) {
1623 dev_err(dwc->dev, "failed to allocate event buffers\n");
1624 ret = -ENOMEM;
1625 goto err2;
1626 }
1627
1628 ret = dwc3_get_dr_mode(dwc);
1629 if (ret)
1630 goto err3;
1631
1632 ret = dwc3_alloc_scratch_buffers(dwc);
1633 if (ret)
1634 goto err3;
1635
1636 ret = dwc3_core_init(dwc);
1637 if (ret) {
1638 dev_err_probe(dev, ret, "failed to initialize core\n");
1639 goto err4;
1640 }
1641
1642 dwc3_check_params(dwc);
1643 dwc3_debugfs_init(dwc);
1644
1645 ret = dwc3_core_init_mode(dwc);
1646 if (ret)
1647 goto err5;
1648
1649 pm_runtime_put(dev);
1650
1651 return 0;
1652
1653 err5:
1654 dwc3_debugfs_exit(dwc);
1655 dwc3_event_buffers_cleanup(dwc);
1656
1657 usb_phy_shutdown(dwc->usb2_phy);
1658 usb_phy_shutdown(dwc->usb3_phy);
1659 phy_exit(dwc->usb2_generic_phy);
1660 phy_exit(dwc->usb3_generic_phy);
1661
1662 usb_phy_set_suspend(dwc->usb2_phy, 1);
1663 usb_phy_set_suspend(dwc->usb3_phy, 1);
1664 phy_power_off(dwc->usb2_generic_phy);
1665 phy_power_off(dwc->usb3_generic_phy);
1666
1667 dwc3_ulpi_exit(dwc);
1668
1669 err4:
1670 dwc3_free_scratch_buffers(dwc);
1671
1672 err3:
1673 dwc3_free_event_buffers(dwc);
1674
1675 err2:
1676 pm_runtime_allow(&pdev->dev);
1677
1678 err1:
1679 pm_runtime_put_sync(&pdev->dev);
1680 pm_runtime_disable(&pdev->dev);
1681
1682 disable_clks:
1683 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1684 assert_reset:
1685 reset_control_assert(dwc->reset);
1686
1687 if (dwc->usb_psy)
1688 power_supply_put(dwc->usb_psy);
1689
1690 return ret;
1691 }
1692
dwc3_remove(struct platform_device * pdev)1693 static int dwc3_remove(struct platform_device *pdev)
1694 {
1695 struct dwc3 *dwc = platform_get_drvdata(pdev);
1696
1697 pm_runtime_get_sync(&pdev->dev);
1698
1699 dwc3_core_exit_mode(dwc);
1700 dwc3_debugfs_exit(dwc);
1701
1702 dwc3_core_exit(dwc);
1703 dwc3_ulpi_exit(dwc);
1704
1705 pm_runtime_disable(&pdev->dev);
1706 pm_runtime_put_noidle(&pdev->dev);
1707 pm_runtime_set_suspended(&pdev->dev);
1708
1709 dwc3_free_event_buffers(dwc);
1710 dwc3_free_scratch_buffers(dwc);
1711
1712 if (dwc->usb_psy)
1713 power_supply_put(dwc->usb_psy);
1714
1715 return 0;
1716 }
1717
1718 #ifdef CONFIG_PM
dwc3_core_init_for_resume(struct dwc3 * dwc)1719 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1720 {
1721 int ret;
1722
1723 ret = reset_control_deassert(dwc->reset);
1724 if (ret)
1725 return ret;
1726
1727 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1728 if (ret)
1729 goto assert_reset;
1730
1731 ret = dwc3_core_init(dwc);
1732 if (ret)
1733 goto disable_clks;
1734
1735 return 0;
1736
1737 disable_clks:
1738 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1739 assert_reset:
1740 reset_control_assert(dwc->reset);
1741
1742 return ret;
1743 }
1744
dwc3_suspend_common(struct dwc3 * dwc,pm_message_t msg)1745 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1746 {
1747 unsigned long flags;
1748 u32 reg;
1749
1750 switch (dwc->current_dr_role) {
1751 case DWC3_GCTL_PRTCAP_DEVICE:
1752 if (pm_runtime_suspended(dwc->dev))
1753 break;
1754 spin_lock_irqsave(&dwc->lock, flags);
1755 dwc3_gadget_suspend(dwc);
1756 spin_unlock_irqrestore(&dwc->lock, flags);
1757 synchronize_irq(dwc->irq_gadget);
1758 dwc3_core_exit(dwc);
1759 break;
1760 case DWC3_GCTL_PRTCAP_HOST:
1761 if (!PMSG_IS_AUTO(msg)) {
1762 dwc3_core_exit(dwc);
1763 break;
1764 }
1765
1766 /* Let controller to suspend HSPHY before PHY driver suspends */
1767 if (dwc->dis_u2_susphy_quirk ||
1768 dwc->dis_enblslpm_quirk) {
1769 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1770 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
1771 DWC3_GUSB2PHYCFG_SUSPHY;
1772 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1773
1774 /* Give some time for USB2 PHY to suspend */
1775 usleep_range(5000, 6000);
1776 }
1777
1778 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1779 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1780 break;
1781 case DWC3_GCTL_PRTCAP_OTG:
1782 /* do nothing during runtime_suspend */
1783 if (PMSG_IS_AUTO(msg))
1784 break;
1785
1786 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1787 spin_lock_irqsave(&dwc->lock, flags);
1788 dwc3_gadget_suspend(dwc);
1789 spin_unlock_irqrestore(&dwc->lock, flags);
1790 synchronize_irq(dwc->irq_gadget);
1791 }
1792
1793 dwc3_otg_exit(dwc);
1794 dwc3_core_exit(dwc);
1795 break;
1796 default:
1797 /* do nothing */
1798 break;
1799 }
1800
1801 return 0;
1802 }
1803
dwc3_resume_common(struct dwc3 * dwc,pm_message_t msg)1804 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1805 {
1806 unsigned long flags;
1807 int ret;
1808 u32 reg;
1809
1810 switch (dwc->current_dr_role) {
1811 case DWC3_GCTL_PRTCAP_DEVICE:
1812 ret = dwc3_core_init_for_resume(dwc);
1813 if (ret)
1814 return ret;
1815
1816 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1817 spin_lock_irqsave(&dwc->lock, flags);
1818 dwc3_gadget_resume(dwc);
1819 spin_unlock_irqrestore(&dwc->lock, flags);
1820 break;
1821 case DWC3_GCTL_PRTCAP_HOST:
1822 if (!PMSG_IS_AUTO(msg)) {
1823 ret = dwc3_core_init_for_resume(dwc);
1824 if (ret)
1825 return ret;
1826 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1827 break;
1828 }
1829 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1830 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1831 if (dwc->dis_u2_susphy_quirk)
1832 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1833
1834 if (dwc->dis_enblslpm_quirk)
1835 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1836
1837 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1838
1839 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1840 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
1841 break;
1842 case DWC3_GCTL_PRTCAP_OTG:
1843 /* nothing to do on runtime_resume */
1844 if (PMSG_IS_AUTO(msg))
1845 break;
1846
1847 ret = dwc3_core_init_for_resume(dwc);
1848 if (ret)
1849 return ret;
1850
1851 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1852
1853 dwc3_otg_init(dwc);
1854 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1855 dwc3_otg_host_init(dwc);
1856 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1857 spin_lock_irqsave(&dwc->lock, flags);
1858 dwc3_gadget_resume(dwc);
1859 spin_unlock_irqrestore(&dwc->lock, flags);
1860 }
1861
1862 break;
1863 default:
1864 /* do nothing */
1865 break;
1866 }
1867
1868 return 0;
1869 }
1870
dwc3_runtime_checks(struct dwc3 * dwc)1871 static int dwc3_runtime_checks(struct dwc3 *dwc)
1872 {
1873 switch (dwc->current_dr_role) {
1874 case DWC3_GCTL_PRTCAP_DEVICE:
1875 if (dwc->connected)
1876 return -EBUSY;
1877 break;
1878 case DWC3_GCTL_PRTCAP_HOST:
1879 default:
1880 /* do nothing */
1881 break;
1882 }
1883
1884 return 0;
1885 }
1886
dwc3_runtime_suspend(struct device * dev)1887 static int dwc3_runtime_suspend(struct device *dev)
1888 {
1889 struct dwc3 *dwc = dev_get_drvdata(dev);
1890 int ret;
1891
1892 if (dwc3_runtime_checks(dwc))
1893 return -EBUSY;
1894
1895 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1896 if (ret)
1897 return ret;
1898
1899 device_init_wakeup(dev, true);
1900
1901 return 0;
1902 }
1903
dwc3_runtime_resume(struct device * dev)1904 static int dwc3_runtime_resume(struct device *dev)
1905 {
1906 struct dwc3 *dwc = dev_get_drvdata(dev);
1907 int ret;
1908
1909 device_init_wakeup(dev, false);
1910
1911 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1912 if (ret)
1913 return ret;
1914
1915 switch (dwc->current_dr_role) {
1916 case DWC3_GCTL_PRTCAP_DEVICE:
1917 dwc3_gadget_process_pending_events(dwc);
1918 break;
1919 case DWC3_GCTL_PRTCAP_HOST:
1920 default:
1921 /* do nothing */
1922 break;
1923 }
1924
1925 pm_runtime_mark_last_busy(dev);
1926
1927 return 0;
1928 }
1929
dwc3_runtime_idle(struct device * dev)1930 static int dwc3_runtime_idle(struct device *dev)
1931 {
1932 struct dwc3 *dwc = dev_get_drvdata(dev);
1933
1934 switch (dwc->current_dr_role) {
1935 case DWC3_GCTL_PRTCAP_DEVICE:
1936 if (dwc3_runtime_checks(dwc))
1937 return -EBUSY;
1938 break;
1939 case DWC3_GCTL_PRTCAP_HOST:
1940 default:
1941 /* do nothing */
1942 break;
1943 }
1944
1945 pm_runtime_mark_last_busy(dev);
1946 pm_runtime_autosuspend(dev);
1947
1948 return 0;
1949 }
1950 #endif /* CONFIG_PM */
1951
1952 #ifdef CONFIG_PM_SLEEP
dwc3_suspend(struct device * dev)1953 static int dwc3_suspend(struct device *dev)
1954 {
1955 struct dwc3 *dwc = dev_get_drvdata(dev);
1956 int ret;
1957
1958 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
1959 if (ret)
1960 return ret;
1961
1962 pinctrl_pm_select_sleep_state(dev);
1963
1964 return 0;
1965 }
1966
dwc3_resume(struct device * dev)1967 static int dwc3_resume(struct device *dev)
1968 {
1969 struct dwc3 *dwc = dev_get_drvdata(dev);
1970 int ret;
1971
1972 pinctrl_pm_select_default_state(dev);
1973
1974 ret = dwc3_resume_common(dwc, PMSG_RESUME);
1975 if (ret)
1976 return ret;
1977
1978 pm_runtime_disable(dev);
1979 pm_runtime_set_active(dev);
1980 pm_runtime_enable(dev);
1981
1982 return 0;
1983 }
1984
dwc3_complete(struct device * dev)1985 static void dwc3_complete(struct device *dev)
1986 {
1987 struct dwc3 *dwc = dev_get_drvdata(dev);
1988 u32 reg;
1989
1990 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
1991 dwc->dis_split_quirk) {
1992 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
1993 reg |= DWC3_GUCTL3_SPLITDISABLE;
1994 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
1995 }
1996 }
1997 #else
1998 #define dwc3_complete NULL
1999 #endif /* CONFIG_PM_SLEEP */
2000
2001 static const struct dev_pm_ops dwc3_dev_pm_ops = {
2002 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
2003 .complete = dwc3_complete,
2004 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
2005 dwc3_runtime_idle)
2006 };
2007
2008 #ifdef CONFIG_OF
2009 static const struct of_device_id of_dwc3_match[] = {
2010 {
2011 .compatible = "snps,dwc3"
2012 },
2013 {
2014 .compatible = "synopsys,dwc3"
2015 },
2016 { },
2017 };
2018 MODULE_DEVICE_TABLE(of, of_dwc3_match);
2019 #endif
2020
2021 #ifdef CONFIG_ACPI
2022
2023 #define ACPI_ID_INTEL_BSW "808622B7"
2024
2025 static const struct acpi_device_id dwc3_acpi_match[] = {
2026 { ACPI_ID_INTEL_BSW, 0 },
2027 { },
2028 };
2029 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
2030 #endif
2031
2032 static struct platform_driver dwc3_driver = {
2033 .probe = dwc3_probe,
2034 .remove = dwc3_remove,
2035 .driver = {
2036 .name = "dwc3",
2037 .of_match_table = of_match_ptr(of_dwc3_match),
2038 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
2039 .pm = &dwc3_dev_pm_ops,
2040 },
2041 };
2042
2043 module_platform_driver(dwc3_driver);
2044
2045 MODULE_ALIAS("platform:dwc3");
2046 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
2047 MODULE_LICENSE("GPL v2");
2048 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
2049
