1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #ifndef __AMDGPU_SMU_H__ 23 #define __AMDGPU_SMU_H__ 24 25 #include "amdgpu.h" 26 #include "kgd_pp_interface.h" 27 #include "dm_pp_interface.h" 28 #include "dm_pp_smu.h" 29 #include "smu_types.h" 30 31 #define SMU_THERMAL_MINIMUM_ALERT_TEMP 0 32 #define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255 33 #define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000 34 35 struct smu_hw_power_state { 36 unsigned int magic; 37 }; 38 39 struct smu_power_state; 40 41 enum smu_state_ui_label { 42 SMU_STATE_UI_LABEL_NONE, 43 SMU_STATE_UI_LABEL_BATTERY, 44 SMU_STATE_UI_TABEL_MIDDLE_LOW, 45 SMU_STATE_UI_LABEL_BALLANCED, 46 SMU_STATE_UI_LABEL_MIDDLE_HIGHT, 47 SMU_STATE_UI_LABEL_PERFORMANCE, 48 SMU_STATE_UI_LABEL_BACO, 49 }; 50 51 enum smu_state_classification_flag { 52 SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001, 53 SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002, 54 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004, 55 SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008, 56 SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010, 57 SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020, 58 SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040, 59 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080, 60 SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100, 61 SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200, 62 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400, 63 SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800, 64 SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000, 65 SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000, 66 SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000, 67 SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000, 68 SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000, 69 SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000, 70 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000, 71 SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000, 72 SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000, 73 }; 74 75 struct smu_state_classification_block { 76 enum smu_state_ui_label ui_label; 77 enum smu_state_classification_flag flags; 78 int bios_index; 79 bool temporary_state; 80 bool to_be_deleted; 81 }; 82 83 struct smu_state_pcie_block { 84 unsigned int lanes; 85 }; 86 87 enum smu_refreshrate_source { 88 SMU_REFRESHRATE_SOURCE_EDID, 89 SMU_REFRESHRATE_SOURCE_EXPLICIT 90 }; 91 92 struct smu_state_display_block { 93 bool disable_frame_modulation; 94 bool limit_refreshrate; 95 enum smu_refreshrate_source refreshrate_source; 96 int explicit_refreshrate; 97 int edid_refreshrate_index; 98 bool enable_vari_bright; 99 }; 100 101 struct smu_state_memroy_block { 102 bool dll_off; 103 uint8_t m3arb; 104 uint8_t unused[3]; 105 }; 106 107 struct smu_state_software_algorithm_block { 108 bool disable_load_balancing; 109 bool enable_sleep_for_timestamps; 110 }; 111 112 struct smu_temperature_range { 113 int min; 114 int max; 115 int edge_emergency_max; 116 int hotspot_min; 117 int hotspot_crit_max; 118 int hotspot_emergency_max; 119 int mem_min; 120 int mem_crit_max; 121 int mem_emergency_max; 122 int software_shutdown_temp; 123 }; 124 125 struct smu_state_validation_block { 126 bool single_display_only; 127 bool disallow_on_dc; 128 uint8_t supported_power_levels; 129 }; 130 131 struct smu_uvd_clocks { 132 uint32_t vclk; 133 uint32_t dclk; 134 }; 135 136 /** 137 * Structure to hold a SMU Power State. 138 */ 139 struct smu_power_state { 140 uint32_t id; 141 struct list_head ordered_list; 142 struct list_head all_states_list; 143 144 struct smu_state_classification_block classification; 145 struct smu_state_validation_block validation; 146 struct smu_state_pcie_block pcie; 147 struct smu_state_display_block display; 148 struct smu_state_memroy_block memory; 149 struct smu_state_software_algorithm_block software; 150 struct smu_uvd_clocks uvd_clocks; 151 struct smu_hw_power_state hardware; 152 }; 153 154 enum smu_power_src_type 155 { 156 SMU_POWER_SOURCE_AC, 157 SMU_POWER_SOURCE_DC, 158 SMU_POWER_SOURCE_COUNT, 159 }; 160 161 enum smu_memory_pool_size 162 { 163 SMU_MEMORY_POOL_SIZE_ZERO = 0, 164 SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000, 165 SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000, 166 SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000, 167 SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000, 168 }; 169 170 #define SMU_TABLE_INIT(tables, table_id, s, a, d) \ 171 do { \ 172 tables[table_id].size = s; \ 173 tables[table_id].align = a; \ 174 tables[table_id].domain = d; \ 175 } while (0) 176 177 struct smu_table { 178 uint64_t size; 179 uint32_t align; 180 uint8_t domain; 181 uint64_t mc_address; 182 void *cpu_addr; 183 struct amdgpu_bo *bo; 184 }; 185 186 enum smu_perf_level_designation { 187 PERF_LEVEL_ACTIVITY, 188 PERF_LEVEL_POWER_CONTAINMENT, 189 }; 190 191 struct smu_performance_level { 192 uint32_t core_clock; 193 uint32_t memory_clock; 194 uint32_t vddc; 195 uint32_t vddci; 196 uint32_t non_local_mem_freq; 197 uint32_t non_local_mem_width; 198 }; 199 200 struct smu_clock_info { 201 uint32_t min_mem_clk; 202 uint32_t max_mem_clk; 203 uint32_t min_eng_clk; 204 uint32_t max_eng_clk; 205 uint32_t min_bus_bandwidth; 206 uint32_t max_bus_bandwidth; 207 }; 208 209 struct smu_bios_boot_up_values 210 { 211 uint32_t revision; 212 uint32_t gfxclk; 213 uint32_t uclk; 214 uint32_t socclk; 215 uint32_t dcefclk; 216 uint32_t eclk; 217 uint32_t vclk; 218 uint32_t dclk; 219 uint16_t vddc; 220 uint16_t vddci; 221 uint16_t mvddc; 222 uint16_t vdd_gfx; 223 uint8_t cooling_id; 224 uint32_t pp_table_id; 225 uint32_t format_revision; 226 uint32_t content_revision; 227 uint32_t fclk; 228 }; 229 230 enum smu_table_id 231 { 232 SMU_TABLE_PPTABLE = 0, 233 SMU_TABLE_WATERMARKS, 234 SMU_TABLE_CUSTOM_DPM, 235 SMU_TABLE_DPMCLOCKS, 236 SMU_TABLE_AVFS, 237 SMU_TABLE_AVFS_PSM_DEBUG, 238 SMU_TABLE_AVFS_FUSE_OVERRIDE, 239 SMU_TABLE_PMSTATUSLOG, 240 SMU_TABLE_SMU_METRICS, 241 SMU_TABLE_DRIVER_SMU_CONFIG, 242 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 243 SMU_TABLE_OVERDRIVE, 244 SMU_TABLE_I2C_COMMANDS, 245 SMU_TABLE_PACE, 246 SMU_TABLE_COUNT, 247 }; 248 249 struct smu_table_context 250 { 251 void *power_play_table; 252 uint32_t power_play_table_size; 253 void *hardcode_pptable; 254 unsigned long metrics_time; 255 void *metrics_table; 256 void *clocks_table; 257 void *watermarks_table; 258 259 void *max_sustainable_clocks; 260 struct smu_bios_boot_up_values boot_values; 261 void *driver_pptable; 262 struct smu_table tables[SMU_TABLE_COUNT]; 263 /* 264 * The driver table is just a staging buffer for 265 * uploading/downloading content from the SMU. 266 * 267 * And the table_id for SMU_MSG_TransferTableSmu2Dram/ 268 * SMU_MSG_TransferTableDram2Smu instructs SMU 269 * which content driver is interested. 270 */ 271 struct smu_table driver_table; 272 struct smu_table memory_pool; 273 struct smu_table dummy_read_1_table; 274 uint8_t thermal_controller_type; 275 276 void *overdrive_table; 277 void *boot_overdrive_table; 278 279 uint32_t gpu_metrics_table_size; 280 void *gpu_metrics_table; 281 }; 282 283 struct smu_dpm_context { 284 uint32_t dpm_context_size; 285 void *dpm_context; 286 void *golden_dpm_context; 287 bool enable_umd_pstate; 288 enum amd_dpm_forced_level dpm_level; 289 enum amd_dpm_forced_level saved_dpm_level; 290 enum amd_dpm_forced_level requested_dpm_level; 291 struct smu_power_state *dpm_request_power_state; 292 struct smu_power_state *dpm_current_power_state; 293 struct mclock_latency_table *mclk_latency_table; 294 }; 295 296 struct smu_power_gate { 297 bool uvd_gated; 298 bool vce_gated; 299 atomic_t vcn_gated; 300 atomic_t jpeg_gated; 301 struct mutex vcn_gate_lock; 302 struct mutex jpeg_gate_lock; 303 }; 304 305 struct smu_power_context { 306 void *power_context; 307 uint32_t power_context_size; 308 struct smu_power_gate power_gate; 309 }; 310 311 312 #define SMU_FEATURE_MAX (64) 313 struct smu_feature 314 { 315 uint32_t feature_num; 316 DECLARE_BITMAP(supported, SMU_FEATURE_MAX); 317 DECLARE_BITMAP(allowed, SMU_FEATURE_MAX); 318 DECLARE_BITMAP(enabled, SMU_FEATURE_MAX); 319 struct mutex mutex; 320 }; 321 322 struct smu_clocks { 323 uint32_t engine_clock; 324 uint32_t memory_clock; 325 uint32_t bus_bandwidth; 326 uint32_t engine_clock_in_sr; 327 uint32_t dcef_clock; 328 uint32_t dcef_clock_in_sr; 329 }; 330 331 #define MAX_REGULAR_DPM_NUM 16 332 struct mclk_latency_entries { 333 uint32_t frequency; 334 uint32_t latency; 335 }; 336 struct mclock_latency_table { 337 uint32_t count; 338 struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM]; 339 }; 340 341 enum smu_reset_mode 342 { 343 SMU_RESET_MODE_0, 344 SMU_RESET_MODE_1, 345 SMU_RESET_MODE_2, 346 }; 347 348 enum smu_baco_state 349 { 350 SMU_BACO_STATE_ENTER = 0, 351 SMU_BACO_STATE_EXIT, 352 }; 353 354 struct smu_baco_context 355 { 356 struct mutex mutex; 357 uint32_t state; 358 bool platform_support; 359 }; 360 361 struct pstates_clk_freq { 362 uint32_t min; 363 uint32_t standard; 364 uint32_t peak; 365 }; 366 367 struct smu_umd_pstate_table { 368 struct pstates_clk_freq gfxclk_pstate; 369 struct pstates_clk_freq socclk_pstate; 370 struct pstates_clk_freq uclk_pstate; 371 struct pstates_clk_freq vclk_pstate; 372 struct pstates_clk_freq dclk_pstate; 373 }; 374 375 struct cmn2asic_msg_mapping { 376 int valid_mapping; 377 int map_to; 378 int valid_in_vf; 379 }; 380 381 struct cmn2asic_mapping { 382 int valid_mapping; 383 int map_to; 384 }; 385 386 #define WORKLOAD_POLICY_MAX 7 387 struct smu_context 388 { 389 struct amdgpu_device *adev; 390 struct amdgpu_irq_src irq_source; 391 392 const struct pptable_funcs *ppt_funcs; 393 const struct cmn2asic_msg_mapping *message_map; 394 const struct cmn2asic_mapping *clock_map; 395 const struct cmn2asic_mapping *feature_map; 396 const struct cmn2asic_mapping *table_map; 397 const struct cmn2asic_mapping *pwr_src_map; 398 const struct cmn2asic_mapping *workload_map; 399 struct mutex mutex; 400 struct mutex sensor_lock; 401 struct mutex metrics_lock; 402 struct mutex message_lock; 403 uint64_t pool_size; 404 405 struct smu_table_context smu_table; 406 struct smu_dpm_context smu_dpm; 407 struct smu_power_context smu_power; 408 struct smu_feature smu_feature; 409 struct amd_pp_display_configuration *display_config; 410 struct smu_baco_context smu_baco; 411 struct smu_temperature_range thermal_range; 412 void *od_settings; 413 #if defined(CONFIG_DEBUG_FS) 414 struct dentry *debugfs_sclk; 415 #endif 416 417 struct smu_umd_pstate_table pstate_table; 418 uint32_t pstate_sclk; 419 uint32_t pstate_mclk; 420 421 bool od_enabled; 422 uint32_t current_power_limit; 423 uint32_t max_power_limit; 424 425 /* soft pptable */ 426 uint32_t ppt_offset_bytes; 427 uint32_t ppt_size_bytes; 428 uint8_t *ppt_start_addr; 429 430 bool support_power_containment; 431 bool disable_watermark; 432 433 #define WATERMARKS_EXIST (1 << 0) 434 #define WATERMARKS_LOADED (1 << 1) 435 uint32_t watermarks_bitmap; 436 uint32_t hard_min_uclk_req_from_dal; 437 bool disable_uclk_switch; 438 439 uint32_t workload_mask; 440 uint32_t workload_prority[WORKLOAD_POLICY_MAX]; 441 uint32_t workload_setting[WORKLOAD_POLICY_MAX]; 442 uint32_t power_profile_mode; 443 uint32_t default_power_profile_mode; 444 bool pm_enabled; 445 bool is_apu; 446 447 uint32_t smc_driver_if_version; 448 uint32_t smc_fw_if_version; 449 uint32_t smc_fw_version; 450 451 bool uploading_custom_pp_table; 452 bool dc_controlled_by_gpio; 453 454 struct work_struct throttling_logging_work; 455 atomic64_t throttle_int_counter; 456 struct work_struct interrupt_work; 457 458 unsigned fan_max_rpm; 459 unsigned manual_fan_speed_rpm; 460 }; 461 462 struct i2c_adapter; 463 464 struct pptable_funcs { 465 int (*run_btc)(struct smu_context *smu); 466 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); 467 enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu); 468 int (*set_default_dpm_table)(struct smu_context *smu); 469 int (*set_power_state)(struct smu_context *smu); 470 int (*populate_umd_state_clk)(struct smu_context *smu); 471 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf); 472 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask); 473 int (*set_default_od8_settings)(struct smu_context *smu); 474 int (*get_od_percentage)(struct smu_context *smu, enum smu_clk_type clk_type); 475 int (*set_od_percentage)(struct smu_context *smu, 476 enum smu_clk_type clk_type, 477 uint32_t value); 478 int (*od_edit_dpm_table)(struct smu_context *smu, 479 enum PP_OD_DPM_TABLE_COMMAND type, 480 long *input, uint32_t size); 481 int (*get_clock_by_type_with_latency)(struct smu_context *smu, 482 enum smu_clk_type clk_type, 483 struct 484 pp_clock_levels_with_latency 485 *clocks); 486 int (*get_clock_by_type_with_voltage)(struct smu_context *smu, 487 enum amd_pp_clock_type type, 488 struct 489 pp_clock_levels_with_voltage 490 *clocks); 491 int (*get_power_profile_mode)(struct smu_context *smu, char *buf); 492 int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size); 493 int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable); 494 int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable); 495 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor, 496 void *data, uint32_t *size); 497 int (*pre_display_config_changed)(struct smu_context *smu); 498 int (*display_config_changed)(struct smu_context *smu); 499 int (*apply_clocks_adjust_rules)(struct smu_context *smu); 500 int (*notify_smc_display_config)(struct smu_context *smu); 501 int (*set_cpu_power_state)(struct smu_context *smu); 502 bool (*is_dpm_running)(struct smu_context *smu); 503 int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed); 504 int (*set_watermarks_table)(struct smu_context *smu, 505 struct pp_smu_wm_range_sets *clock_ranges); 506 int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range); 507 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states); 508 int (*set_default_od_settings)(struct smu_context *smu); 509 int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level); 510 int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch); 511 void (*dump_pptable)(struct smu_context *smu); 512 int (*get_power_limit)(struct smu_context *smu); 513 int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state); 514 int (*allow_xgmi_power_down)(struct smu_context *smu, bool en); 515 int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap); 516 int (*i2c_init)(struct smu_context *smu, struct i2c_adapter *control); 517 void (*i2c_fini)(struct smu_context *smu, struct i2c_adapter *control); 518 void (*get_unique_id)(struct smu_context *smu); 519 int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table); 520 int (*init_microcode)(struct smu_context *smu); 521 int (*load_microcode)(struct smu_context *smu); 522 void (*fini_microcode)(struct smu_context *smu); 523 int (*init_smc_tables)(struct smu_context *smu); 524 int (*fini_smc_tables)(struct smu_context *smu); 525 int (*init_power)(struct smu_context *smu); 526 int (*fini_power)(struct smu_context *smu); 527 int (*check_fw_status)(struct smu_context *smu); 528 int (*setup_pptable)(struct smu_context *smu); 529 int (*get_vbios_bootup_values)(struct smu_context *smu); 530 int (*check_fw_version)(struct smu_context *smu); 531 int (*powergate_sdma)(struct smu_context *smu, bool gate); 532 int (*set_gfx_cgpg)(struct smu_context *smu, bool enable); 533 int (*write_pptable)(struct smu_context *smu); 534 int (*set_driver_table_location)(struct smu_context *smu); 535 int (*set_tool_table_location)(struct smu_context *smu); 536 int (*notify_memory_pool_location)(struct smu_context *smu); 537 int (*set_last_dcef_min_deep_sleep_clk)(struct smu_context *smu); 538 int (*system_features_control)(struct smu_context *smu, bool en); 539 int (*send_smc_msg_with_param)(struct smu_context *smu, 540 enum smu_message_type msg, uint32_t param, uint32_t *read_arg); 541 int (*send_smc_msg)(struct smu_context *smu, 542 enum smu_message_type msg, 543 uint32_t *read_arg); 544 int (*init_display_count)(struct smu_context *smu, uint32_t count); 545 int (*set_allowed_mask)(struct smu_context *smu); 546 int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); 547 int (*feature_is_enabled)(struct smu_context *smu, enum smu_feature_mask mask); 548 int (*disable_all_features_with_exception)(struct smu_context *smu, enum smu_feature_mask mask); 549 int (*notify_display_change)(struct smu_context *smu); 550 int (*set_power_limit)(struct smu_context *smu, uint32_t n); 551 int (*init_max_sustainable_clocks)(struct smu_context *smu); 552 int (*enable_thermal_alert)(struct smu_context *smu); 553 int (*disable_thermal_alert)(struct smu_context *smu); 554 int (*set_min_dcef_deep_sleep)(struct smu_context *smu, uint32_t clk); 555 int (*set_active_display_count)(struct smu_context *smu, uint32_t count); 556 int (*store_cc6_data)(struct smu_context *smu, uint32_t separation_time, 557 bool cc6_disable, bool pstate_disable, 558 bool pstate_switch_disable); 559 int (*get_clock_by_type)(struct smu_context *smu, 560 enum amd_pp_clock_type type, 561 struct amd_pp_clocks *clocks); 562 int (*get_max_high_clocks)(struct smu_context *smu, 563 struct amd_pp_simple_clock_info *clocks); 564 int (*display_clock_voltage_request)(struct smu_context *smu, struct 565 pp_display_clock_request 566 *clock_req); 567 int (*get_dal_power_level)(struct smu_context *smu, 568 struct amd_pp_simple_clock_info *clocks); 569 int (*get_perf_level)(struct smu_context *smu, 570 enum smu_perf_level_designation designation, 571 struct smu_performance_level *level); 572 int (*get_current_shallow_sleep_clocks)(struct smu_context *smu, 573 struct smu_clock_info *clocks); 574 int (*notify_smu_enable_pwe)(struct smu_context *smu); 575 int (*conv_power_profile_to_pplib_workload)(int power_profile); 576 uint32_t (*get_fan_control_mode)(struct smu_context *smu); 577 int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode); 578 int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed); 579 int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate); 580 int (*gfx_off_control)(struct smu_context *smu, bool enable); 581 uint32_t (*get_gfx_off_status)(struct smu_context *smu); 582 int (*register_irq_handler)(struct smu_context *smu); 583 int (*set_azalia_d3_pme)(struct smu_context *smu); 584 int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks); 585 bool (*baco_is_support)(struct smu_context *smu); 586 enum smu_baco_state (*baco_get_state)(struct smu_context *smu); 587 int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state); 588 int (*baco_enter)(struct smu_context *smu); 589 int (*baco_exit)(struct smu_context *smu); 590 bool (*mode1_reset_is_support)(struct smu_context *smu); 591 int (*mode1_reset)(struct smu_context *smu); 592 int (*mode2_reset)(struct smu_context *smu); 593 int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max); 594 int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max); 595 int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src); 596 void (*log_thermal_throttling_event)(struct smu_context *smu); 597 size_t (*get_pp_feature_mask)(struct smu_context *smu, char *buf); 598 int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask); 599 ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table); 600 int (*enable_mgpu_fan_boost)(struct smu_context *smu); 601 int (*gfx_ulv_control)(struct smu_context *smu, bool enablement); 602 int (*deep_sleep_control)(struct smu_context *smu, bool enablement); 603 int (*get_fan_parameters)(struct smu_context *smu); 604 int (*post_init)(struct smu_context *smu); 605 void (*interrupt_work)(struct smu_context *smu); 606 }; 607 608 typedef enum { 609 METRICS_CURR_GFXCLK, 610 METRICS_CURR_SOCCLK, 611 METRICS_CURR_UCLK, 612 METRICS_CURR_VCLK, 613 METRICS_CURR_VCLK1, 614 METRICS_CURR_DCLK, 615 METRICS_CURR_DCLK1, 616 METRICS_CURR_FCLK, 617 METRICS_CURR_DCEFCLK, 618 METRICS_AVERAGE_GFXCLK, 619 METRICS_AVERAGE_SOCCLK, 620 METRICS_AVERAGE_FCLK, 621 METRICS_AVERAGE_UCLK, 622 METRICS_AVERAGE_VCLK, 623 METRICS_AVERAGE_DCLK, 624 METRICS_AVERAGE_GFXACTIVITY, 625 METRICS_AVERAGE_MEMACTIVITY, 626 METRICS_AVERAGE_VCNACTIVITY, 627 METRICS_AVERAGE_SOCKETPOWER, 628 METRICS_TEMPERATURE_EDGE, 629 METRICS_TEMPERATURE_HOTSPOT, 630 METRICS_TEMPERATURE_MEM, 631 METRICS_TEMPERATURE_VRGFX, 632 METRICS_TEMPERATURE_VRSOC, 633 METRICS_TEMPERATURE_VRMEM, 634 METRICS_THROTTLER_STATUS, 635 METRICS_CURR_FANSPEED, 636 } MetricsMember_t; 637 638 enum smu_cmn2asic_mapping_type { 639 CMN2ASIC_MAPPING_MSG, 640 CMN2ASIC_MAPPING_CLK, 641 CMN2ASIC_MAPPING_FEATURE, 642 CMN2ASIC_MAPPING_TABLE, 643 CMN2ASIC_MAPPING_PWR, 644 CMN2ASIC_MAPPING_WORKLOAD, 645 }; 646 647 #define MSG_MAP(msg, index, valid_in_vf) \ 648 [SMU_MSG_##msg] = {1, (index), (valid_in_vf)} 649 650 #define CLK_MAP(clk, index) \ 651 [SMU_##clk] = {1, (index)} 652 653 #define FEA_MAP(fea) \ 654 [SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT} 655 656 #define TAB_MAP(tab) \ 657 [SMU_TABLE_##tab] = {1, TABLE_##tab} 658 659 #define TAB_MAP_VALID(tab) \ 660 [SMU_TABLE_##tab] = {1, TABLE_##tab} 661 662 #define TAB_MAP_INVALID(tab) \ 663 [SMU_TABLE_##tab] = {0, TABLE_##tab} 664 665 #define PWR_MAP(tab) \ 666 [SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab} 667 668 #define WORKLOAD_MAP(profile, workload) \ 669 [profile] = {1, (workload)} 670 671 #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4) 672 int smu_load_microcode(struct smu_context *smu); 673 674 int smu_check_fw_status(struct smu_context *smu); 675 676 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 677 678 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed); 679 680 int smu_get_power_limit(struct smu_context *smu, 681 uint32_t *limit, 682 bool max_setting); 683 684 int smu_set_power_limit(struct smu_context *smu, uint32_t limit); 685 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf); 686 int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type); 687 int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value); 688 689 int smu_od_edit_dpm_table(struct smu_context *smu, 690 enum PP_OD_DPM_TABLE_COMMAND type, 691 long *input, uint32_t size); 692 693 int smu_read_sensor(struct smu_context *smu, 694 enum amd_pp_sensors sensor, 695 void *data, uint32_t *size); 696 int smu_get_power_profile_mode(struct smu_context *smu, char *buf); 697 698 int smu_set_power_profile_mode(struct smu_context *smu, 699 long *param, 700 uint32_t param_size, 701 bool lock_needed); 702 int smu_get_fan_control_mode(struct smu_context *smu); 703 int smu_set_fan_control_mode(struct smu_context *smu, int value); 704 int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed); 705 int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed); 706 int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed); 707 708 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk); 709 710 int smu_get_clock_by_type(struct smu_context *smu, 711 enum amd_pp_clock_type type, 712 struct amd_pp_clocks *clocks); 713 714 int smu_get_max_high_clocks(struct smu_context *smu, 715 struct amd_pp_simple_clock_info *clocks); 716 717 int smu_get_clock_by_type_with_latency(struct smu_context *smu, 718 enum smu_clk_type clk_type, 719 struct pp_clock_levels_with_latency *clocks); 720 721 int smu_get_clock_by_type_with_voltage(struct smu_context *smu, 722 enum amd_pp_clock_type type, 723 struct pp_clock_levels_with_voltage *clocks); 724 725 int smu_display_clock_voltage_request(struct smu_context *smu, 726 struct pp_display_clock_request *clock_req); 727 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch); 728 int smu_notify_smu_enable_pwe(struct smu_context *smu); 729 730 int smu_set_xgmi_pstate(struct smu_context *smu, 731 uint32_t pstate); 732 733 int smu_set_azalia_d3_pme(struct smu_context *smu); 734 735 bool smu_baco_is_support(struct smu_context *smu); 736 737 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state); 738 739 int smu_baco_enter(struct smu_context *smu); 740 int smu_baco_exit(struct smu_context *smu); 741 742 bool smu_mode1_reset_is_support(struct smu_context *smu); 743 int smu_mode1_reset(struct smu_context *smu); 744 int smu_mode2_reset(struct smu_context *smu); 745 746 extern const struct amd_ip_funcs smu_ip_funcs; 747 748 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; 749 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; 750 751 bool is_support_sw_smu(struct amdgpu_device *adev); 752 int smu_reset(struct smu_context *smu); 753 int smu_sys_get_pp_table(struct smu_context *smu, void **table); 754 int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size); 755 int smu_get_power_num_states(struct smu_context *smu, struct pp_states_info *state_info); 756 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu); 757 int smu_write_watermarks_table(struct smu_context *smu); 758 int smu_set_watermarks_for_clock_ranges( 759 struct smu_context *smu, 760 struct pp_smu_wm_range_sets *clock_ranges); 761 762 /* smu to display interface */ 763 extern int smu_display_configuration_change(struct smu_context *smu, const 764 struct amd_pp_display_configuration 765 *display_config); 766 extern int smu_get_current_clocks(struct smu_context *smu, 767 struct amd_pp_clock_info *clocks); 768 extern int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t block_type, bool gate); 769 extern int smu_handle_task(struct smu_context *smu, 770 enum amd_dpm_forced_level level, 771 enum amd_pp_task task_id, 772 bool lock_needed); 773 int smu_switch_power_profile(struct smu_context *smu, 774 enum PP_SMC_POWER_PROFILE type, 775 bool en); 776 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 777 uint32_t *min, uint32_t *max); 778 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 779 uint32_t min, uint32_t max); 780 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu); 781 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level); 782 int smu_set_display_count(struct smu_context *smu, uint32_t count); 783 int smu_set_ac_dc(struct smu_context *smu); 784 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf); 785 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask); 786 int smu_force_clk_levels(struct smu_context *smu, 787 enum smu_clk_type clk_type, 788 uint32_t mask); 789 int smu_set_mp1_state(struct smu_context *smu, 790 enum pp_mp1_state mp1_state); 791 int smu_set_df_cstate(struct smu_context *smu, 792 enum pp_df_cstate state); 793 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en); 794 795 int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu, 796 struct pp_smu_nv_clock_table *max_clocks); 797 798 int smu_get_uclk_dpm_states(struct smu_context *smu, 799 unsigned int *clock_values_in_khz, 800 unsigned int *num_states); 801 802 int smu_get_dpm_clock_table(struct smu_context *smu, 803 struct dpm_clocks *clock_table); 804 805 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value); 806 807 ssize_t smu_sys_get_gpu_metrics(struct smu_context *smu, void **table); 808 809 int smu_enable_mgpu_fan_boost(struct smu_context *smu); 810 811 #endif 812 #endif 813
