1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * linux/drivers/video/omap2/dss/dsi.c
4 *
5 * Copyright (C) 2009 Nokia Corporation
6 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 */
8
9 #define DSS_SUBSYS_NAME "DSI"
10
11 #include <linux/kernel.h>
12 #include <linux/io.h>
13 #include <linux/clk.h>
14 #include <linux/device.h>
15 #include <linux/err.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/mutex.h>
19 #include <linux/module.h>
20 #include <linux/semaphore.h>
21 #include <linux/seq_file.h>
22 #include <linux/platform_device.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/wait.h>
25 #include <linux/workqueue.h>
26 #include <linux/sched.h>
27 #include <linux/slab.h>
28 #include <linux/debugfs.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/of.h>
31 #include <linux/of_platform.h>
32 #include <linux/component.h>
33
34 #include <video/omapfb_dss.h>
35 #include <video/mipi_display.h>
36
37 #include "dss.h"
38 #include "dss_features.h"
39
40 #define DSI_CATCH_MISSING_TE
41
42 struct dsi_reg { u16 module; u16 idx; };
43
44 #define DSI_REG(mod, idx) ((const struct dsi_reg) { mod, idx })
45
46 /* DSI Protocol Engine */
47
48 #define DSI_PROTO 0
49 #define DSI_PROTO_SZ 0x200
50
51 #define DSI_REVISION DSI_REG(DSI_PROTO, 0x0000)
52 #define DSI_SYSCONFIG DSI_REG(DSI_PROTO, 0x0010)
53 #define DSI_SYSSTATUS DSI_REG(DSI_PROTO, 0x0014)
54 #define DSI_IRQSTATUS DSI_REG(DSI_PROTO, 0x0018)
55 #define DSI_IRQENABLE DSI_REG(DSI_PROTO, 0x001C)
56 #define DSI_CTRL DSI_REG(DSI_PROTO, 0x0040)
57 #define DSI_GNQ DSI_REG(DSI_PROTO, 0x0044)
58 #define DSI_COMPLEXIO_CFG1 DSI_REG(DSI_PROTO, 0x0048)
59 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(DSI_PROTO, 0x004C)
60 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(DSI_PROTO, 0x0050)
61 #define DSI_CLK_CTRL DSI_REG(DSI_PROTO, 0x0054)
62 #define DSI_TIMING1 DSI_REG(DSI_PROTO, 0x0058)
63 #define DSI_TIMING2 DSI_REG(DSI_PROTO, 0x005C)
64 #define DSI_VM_TIMING1 DSI_REG(DSI_PROTO, 0x0060)
65 #define DSI_VM_TIMING2 DSI_REG(DSI_PROTO, 0x0064)
66 #define DSI_VM_TIMING3 DSI_REG(DSI_PROTO, 0x0068)
67 #define DSI_CLK_TIMING DSI_REG(DSI_PROTO, 0x006C)
68 #define DSI_TX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0070)
69 #define DSI_RX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0074)
70 #define DSI_COMPLEXIO_CFG2 DSI_REG(DSI_PROTO, 0x0078)
71 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(DSI_PROTO, 0x007C)
72 #define DSI_VM_TIMING4 DSI_REG(DSI_PROTO, 0x0080)
73 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(DSI_PROTO, 0x0084)
74 #define DSI_VM_TIMING5 DSI_REG(DSI_PROTO, 0x0088)
75 #define DSI_VM_TIMING6 DSI_REG(DSI_PROTO, 0x008C)
76 #define DSI_VM_TIMING7 DSI_REG(DSI_PROTO, 0x0090)
77 #define DSI_STOPCLK_TIMING DSI_REG(DSI_PROTO, 0x0094)
78 #define DSI_VC_CTRL(n) DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20))
79 #define DSI_VC_TE(n) DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20))
80 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20))
81 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(DSI_PROTO, 0x010C + (n * 0x20))
82 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20))
83 #define DSI_VC_IRQSTATUS(n) DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20))
84 #define DSI_VC_IRQENABLE(n) DSI_REG(DSI_PROTO, 0x011C + (n * 0x20))
85
86 /* DSIPHY_SCP */
87
88 #define DSI_PHY 1
89 #define DSI_PHY_OFFSET 0x200
90 #define DSI_PHY_SZ 0x40
91
92 #define DSI_DSIPHY_CFG0 DSI_REG(DSI_PHY, 0x0000)
93 #define DSI_DSIPHY_CFG1 DSI_REG(DSI_PHY, 0x0004)
94 #define DSI_DSIPHY_CFG2 DSI_REG(DSI_PHY, 0x0008)
95 #define DSI_DSIPHY_CFG5 DSI_REG(DSI_PHY, 0x0014)
96 #define DSI_DSIPHY_CFG10 DSI_REG(DSI_PHY, 0x0028)
97
98 /* DSI_PLL_CTRL_SCP */
99
100 #define DSI_PLL 2
101 #define DSI_PLL_OFFSET 0x300
102 #define DSI_PLL_SZ 0x20
103
104 #define DSI_PLL_CONTROL DSI_REG(DSI_PLL, 0x0000)
105 #define DSI_PLL_STATUS DSI_REG(DSI_PLL, 0x0004)
106 #define DSI_PLL_GO DSI_REG(DSI_PLL, 0x0008)
107 #define DSI_PLL_CONFIGURATION1 DSI_REG(DSI_PLL, 0x000C)
108 #define DSI_PLL_CONFIGURATION2 DSI_REG(DSI_PLL, 0x0010)
109
110 #define REG_GET(dsidev, idx, start, end) \
111 FLD_GET(dsi_read_reg(dsidev, idx), start, end)
112
113 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
114 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
115
116 /* Global interrupts */
117 #define DSI_IRQ_VC0 (1 << 0)
118 #define DSI_IRQ_VC1 (1 << 1)
119 #define DSI_IRQ_VC2 (1 << 2)
120 #define DSI_IRQ_VC3 (1 << 3)
121 #define DSI_IRQ_WAKEUP (1 << 4)
122 #define DSI_IRQ_RESYNC (1 << 5)
123 #define DSI_IRQ_PLL_LOCK (1 << 7)
124 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
125 #define DSI_IRQ_PLL_RECALL (1 << 9)
126 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
127 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
128 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
129 #define DSI_IRQ_TE_TRIGGER (1 << 16)
130 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
131 #define DSI_IRQ_SYNC_LOST (1 << 18)
132 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
133 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
134 #define DSI_IRQ_ERROR_MASK \
135 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
136 DSI_IRQ_TA_TIMEOUT)
137 #define DSI_IRQ_CHANNEL_MASK 0xf
138
139 /* Virtual channel interrupts */
140 #define DSI_VC_IRQ_CS (1 << 0)
141 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
142 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
143 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
144 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
145 #define DSI_VC_IRQ_BTA (1 << 5)
146 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
147 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
148 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
149 #define DSI_VC_IRQ_ERROR_MASK \
150 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
151 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
152 DSI_VC_IRQ_FIFO_TX_UDF)
153
154 /* ComplexIO interrupts */
155 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
156 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
157 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
158 #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3)
159 #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4)
160 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
161 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
162 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
163 #define DSI_CIO_IRQ_ERRESC4 (1 << 8)
164 #define DSI_CIO_IRQ_ERRESC5 (1 << 9)
165 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
166 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
167 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
168 #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13)
169 #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14)
170 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
171 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
172 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
173 #define DSI_CIO_IRQ_STATEULPS4 (1 << 18)
174 #define DSI_CIO_IRQ_STATEULPS5 (1 << 19)
175 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
176 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
177 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
178 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
179 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
180 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
181 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26)
182 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27)
183 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28)
184 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29)
185 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
186 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
187 #define DSI_CIO_IRQ_ERROR_MASK \
188 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
189 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
190 DSI_CIO_IRQ_ERRSYNCESC5 | \
191 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
192 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
193 DSI_CIO_IRQ_ERRESC5 | \
194 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
195 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
196 DSI_CIO_IRQ_ERRCONTROL5 | \
197 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
198 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
199 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
200 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
201 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
202
203 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
204
205 static int dsi_display_init_dispc(struct platform_device *dsidev,
206 struct omap_overlay_manager *mgr);
207 static void dsi_display_uninit_dispc(struct platform_device *dsidev,
208 struct omap_overlay_manager *mgr);
209
210 static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
211
212 /* DSI PLL HSDIV indices */
213 #define HSDIV_DISPC 0
214 #define HSDIV_DSI 1
215
216 #define DSI_MAX_NR_ISRS 2
217 #define DSI_MAX_NR_LANES 5
218
219 enum dsi_lane_function {
220 DSI_LANE_UNUSED = 0,
221 DSI_LANE_CLK,
222 DSI_LANE_DATA1,
223 DSI_LANE_DATA2,
224 DSI_LANE_DATA3,
225 DSI_LANE_DATA4,
226 };
227
228 struct dsi_lane_config {
229 enum dsi_lane_function function;
230 u8 polarity;
231 };
232
233 struct dsi_isr_data {
234 omap_dsi_isr_t isr;
235 void *arg;
236 u32 mask;
237 };
238
239 enum fifo_size {
240 DSI_FIFO_SIZE_0 = 0,
241 DSI_FIFO_SIZE_32 = 1,
242 DSI_FIFO_SIZE_64 = 2,
243 DSI_FIFO_SIZE_96 = 3,
244 DSI_FIFO_SIZE_128 = 4,
245 };
246
247 enum dsi_vc_source {
248 DSI_VC_SOURCE_L4 = 0,
249 DSI_VC_SOURCE_VP,
250 };
251
252 struct dsi_irq_stats {
253 unsigned long last_reset;
254 unsigned irq_count;
255 unsigned dsi_irqs[32];
256 unsigned vc_irqs[4][32];
257 unsigned cio_irqs[32];
258 };
259
260 struct dsi_isr_tables {
261 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
262 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
263 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
264 };
265
266 struct dsi_clk_calc_ctx {
267 struct platform_device *dsidev;
268 struct dss_pll *pll;
269
270 /* inputs */
271
272 const struct omap_dss_dsi_config *config;
273
274 unsigned long req_pck_min, req_pck_nom, req_pck_max;
275
276 /* outputs */
277
278 struct dss_pll_clock_info dsi_cinfo;
279 struct dispc_clock_info dispc_cinfo;
280
281 struct omap_video_timings dispc_vm;
282 struct omap_dss_dsi_videomode_timings dsi_vm;
283 };
284
285 struct dsi_lp_clock_info {
286 unsigned long lp_clk;
287 u16 lp_clk_div;
288 };
289
290 struct dsi_data {
291 struct platform_device *pdev;
292 void __iomem *proto_base;
293 void __iomem *phy_base;
294 void __iomem *pll_base;
295
296 int module_id;
297
298 int irq;
299
300 bool is_enabled;
301
302 struct clk *dss_clk;
303
304 struct dispc_clock_info user_dispc_cinfo;
305 struct dss_pll_clock_info user_dsi_cinfo;
306
307 struct dsi_lp_clock_info user_lp_cinfo;
308 struct dsi_lp_clock_info current_lp_cinfo;
309
310 struct dss_pll pll;
311
312 bool vdds_dsi_enabled;
313 struct regulator *vdds_dsi_reg;
314
315 struct {
316 enum dsi_vc_source source;
317 struct omap_dss_device *dssdev;
318 enum fifo_size tx_fifo_size;
319 enum fifo_size rx_fifo_size;
320 int vc_id;
321 } vc[4];
322
323 struct mutex lock;
324 struct semaphore bus_lock;
325
326 spinlock_t irq_lock;
327 struct dsi_isr_tables isr_tables;
328 /* space for a copy used by the interrupt handler */
329 struct dsi_isr_tables isr_tables_copy;
330
331 int update_channel;
332 #ifdef DSI_PERF_MEASURE
333 unsigned update_bytes;
334 #endif
335
336 bool te_enabled;
337 bool ulps_enabled;
338
339 void (*framedone_callback)(int, void *);
340 void *framedone_data;
341
342 struct delayed_work framedone_timeout_work;
343
344 #ifdef DSI_CATCH_MISSING_TE
345 struct timer_list te_timer;
346 #endif
347
348 unsigned long cache_req_pck;
349 unsigned long cache_clk_freq;
350 struct dss_pll_clock_info cache_cinfo;
351
352 u32 errors;
353 spinlock_t errors_lock;
354 #ifdef DSI_PERF_MEASURE
355 ktime_t perf_setup_time;
356 ktime_t perf_start_time;
357 #endif
358 int debug_read;
359 int debug_write;
360
361 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
362 spinlock_t irq_stats_lock;
363 struct dsi_irq_stats irq_stats;
364 #endif
365
366 unsigned num_lanes_supported;
367 unsigned line_buffer_size;
368
369 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
370 unsigned num_lanes_used;
371
372 unsigned scp_clk_refcount;
373
374 struct dss_lcd_mgr_config mgr_config;
375 struct omap_video_timings timings;
376 enum omap_dss_dsi_pixel_format pix_fmt;
377 enum omap_dss_dsi_mode mode;
378 struct omap_dss_dsi_videomode_timings vm_timings;
379
380 struct omap_dss_device output;
381 };
382
383 struct dsi_packet_sent_handler_data {
384 struct platform_device *dsidev;
385 struct completion *completion;
386 };
387
388 struct dsi_module_id_data {
389 u32 address;
390 int id;
391 };
392
393 static const struct of_device_id dsi_of_match[];
394
395 #ifdef DSI_PERF_MEASURE
396 static bool dsi_perf;
397 module_param(dsi_perf, bool, 0644);
398 #endif
399
dsi_get_dsidrv_data(struct platform_device * dsidev)400 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
401 {
402 return platform_get_drvdata(dsidev);
403 }
404
dsi_get_dsidev_from_dssdev(struct omap_dss_device * dssdev)405 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
406 {
407 return to_platform_device(dssdev->dev);
408 }
409
dsi_get_dsidev_from_id(int module)410 static struct platform_device *dsi_get_dsidev_from_id(int module)
411 {
412 struct omap_dss_device *out;
413 enum omap_dss_output_id id;
414
415 switch (module) {
416 case 0:
417 id = OMAP_DSS_OUTPUT_DSI1;
418 break;
419 case 1:
420 id = OMAP_DSS_OUTPUT_DSI2;
421 break;
422 default:
423 return NULL;
424 }
425
426 out = omap_dss_get_output(id);
427
428 return out ? to_platform_device(out->dev) : NULL;
429 }
430
dsi_write_reg(struct platform_device * dsidev,const struct dsi_reg idx,u32 val)431 static inline void dsi_write_reg(struct platform_device *dsidev,
432 const struct dsi_reg idx, u32 val)
433 {
434 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
435 void __iomem *base;
436
437 switch(idx.module) {
438 case DSI_PROTO: base = dsi->proto_base; break;
439 case DSI_PHY: base = dsi->phy_base; break;
440 case DSI_PLL: base = dsi->pll_base; break;
441 default: return;
442 }
443
444 __raw_writel(val, base + idx.idx);
445 }
446
dsi_read_reg(struct platform_device * dsidev,const struct dsi_reg idx)447 static inline u32 dsi_read_reg(struct platform_device *dsidev,
448 const struct dsi_reg idx)
449 {
450 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
451 void __iomem *base;
452
453 switch(idx.module) {
454 case DSI_PROTO: base = dsi->proto_base; break;
455 case DSI_PHY: base = dsi->phy_base; break;
456 case DSI_PLL: base = dsi->pll_base; break;
457 default: return 0;
458 }
459
460 return __raw_readl(base + idx.idx);
461 }
462
dsi_bus_lock(struct omap_dss_device * dssdev)463 static void dsi_bus_lock(struct omap_dss_device *dssdev)
464 {
465 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
466 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
467
468 down(&dsi->bus_lock);
469 }
470
dsi_bus_unlock(struct omap_dss_device * dssdev)471 static void dsi_bus_unlock(struct omap_dss_device *dssdev)
472 {
473 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
474 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
475
476 up(&dsi->bus_lock);
477 }
478
dsi_bus_is_locked(struct platform_device * dsidev)479 static bool dsi_bus_is_locked(struct platform_device *dsidev)
480 {
481 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
482
483 return dsi->bus_lock.count == 0;
484 }
485
dsi_completion_handler(void * data,u32 mask)486 static void dsi_completion_handler(void *data, u32 mask)
487 {
488 complete((struct completion *)data);
489 }
490
wait_for_bit_change(struct platform_device * dsidev,const struct dsi_reg idx,int bitnum,int value)491 static inline int wait_for_bit_change(struct platform_device *dsidev,
492 const struct dsi_reg idx, int bitnum, int value)
493 {
494 unsigned long timeout;
495 ktime_t wait;
496 int t;
497
498 /* first busyloop to see if the bit changes right away */
499 t = 100;
500 while (t-- > 0) {
501 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
502 return value;
503 }
504
505 /* then loop for 500ms, sleeping for 1ms in between */
506 timeout = jiffies + msecs_to_jiffies(500);
507 while (time_before(jiffies, timeout)) {
508 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
509 return value;
510
511 wait = ns_to_ktime(1000 * 1000);
512 set_current_state(TASK_UNINTERRUPTIBLE);
513 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
514 }
515
516 return !value;
517 }
518
dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)519 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
520 {
521 switch (fmt) {
522 case OMAP_DSS_DSI_FMT_RGB888:
523 case OMAP_DSS_DSI_FMT_RGB666:
524 return 24;
525 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
526 return 18;
527 case OMAP_DSS_DSI_FMT_RGB565:
528 return 16;
529 default:
530 BUG();
531 return 0;
532 }
533 }
534
535 #ifdef DSI_PERF_MEASURE
dsi_perf_mark_setup(struct platform_device * dsidev)536 static void dsi_perf_mark_setup(struct platform_device *dsidev)
537 {
538 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
539 dsi->perf_setup_time = ktime_get();
540 }
541
dsi_perf_mark_start(struct platform_device * dsidev)542 static void dsi_perf_mark_start(struct platform_device *dsidev)
543 {
544 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
545 dsi->perf_start_time = ktime_get();
546 }
547
dsi_perf_show(struct platform_device * dsidev,const char * name)548 static void dsi_perf_show(struct platform_device *dsidev, const char *name)
549 {
550 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
551 ktime_t t, setup_time, trans_time;
552 u32 total_bytes;
553 u32 setup_us, trans_us, total_us;
554
555 if (!dsi_perf)
556 return;
557
558 t = ktime_get();
559
560 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
561 setup_us = (u32)ktime_to_us(setup_time);
562 if (setup_us == 0)
563 setup_us = 1;
564
565 trans_time = ktime_sub(t, dsi->perf_start_time);
566 trans_us = (u32)ktime_to_us(trans_time);
567 if (trans_us == 0)
568 trans_us = 1;
569
570 total_us = setup_us + trans_us;
571
572 total_bytes = dsi->update_bytes;
573
574 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
575 "%u bytes, %u kbytes/sec\n",
576 name,
577 setup_us,
578 trans_us,
579 total_us,
580 1000*1000 / total_us,
581 total_bytes,
582 total_bytes * 1000 / total_us);
583 }
584 #else
dsi_perf_mark_setup(struct platform_device * dsidev)585 static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
586 {
587 }
588
dsi_perf_mark_start(struct platform_device * dsidev)589 static inline void dsi_perf_mark_start(struct platform_device *dsidev)
590 {
591 }
592
dsi_perf_show(struct platform_device * dsidev,const char * name)593 static inline void dsi_perf_show(struct platform_device *dsidev,
594 const char *name)
595 {
596 }
597 #endif
598
599 static int verbose_irq;
600
print_irq_status(u32 status)601 static void print_irq_status(u32 status)
602 {
603 if (status == 0)
604 return;
605
606 if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0)
607 return;
608
609 #define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : ""
610
611 pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
612 status,
613 verbose_irq ? PIS(VC0) : "",
614 verbose_irq ? PIS(VC1) : "",
615 verbose_irq ? PIS(VC2) : "",
616 verbose_irq ? PIS(VC3) : "",
617 PIS(WAKEUP),
618 PIS(RESYNC),
619 PIS(PLL_LOCK),
620 PIS(PLL_UNLOCK),
621 PIS(PLL_RECALL),
622 PIS(COMPLEXIO_ERR),
623 PIS(HS_TX_TIMEOUT),
624 PIS(LP_RX_TIMEOUT),
625 PIS(TE_TRIGGER),
626 PIS(ACK_TRIGGER),
627 PIS(SYNC_LOST),
628 PIS(LDO_POWER_GOOD),
629 PIS(TA_TIMEOUT));
630 #undef PIS
631 }
632
print_irq_status_vc(int channel,u32 status)633 static void print_irq_status_vc(int channel, u32 status)
634 {
635 if (status == 0)
636 return;
637
638 if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
639 return;
640
641 #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : ""
642
643 pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n",
644 channel,
645 status,
646 PIS(CS),
647 PIS(ECC_CORR),
648 PIS(ECC_NO_CORR),
649 verbose_irq ? PIS(PACKET_SENT) : "",
650 PIS(BTA),
651 PIS(FIFO_TX_OVF),
652 PIS(FIFO_RX_OVF),
653 PIS(FIFO_TX_UDF),
654 PIS(PP_BUSY_CHANGE));
655 #undef PIS
656 }
657
print_irq_status_cio(u32 status)658 static void print_irq_status_cio(u32 status)
659 {
660 if (status == 0)
661 return;
662
663 #define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : ""
664
665 pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
666 status,
667 PIS(ERRSYNCESC1),
668 PIS(ERRSYNCESC2),
669 PIS(ERRSYNCESC3),
670 PIS(ERRESC1),
671 PIS(ERRESC2),
672 PIS(ERRESC3),
673 PIS(ERRCONTROL1),
674 PIS(ERRCONTROL2),
675 PIS(ERRCONTROL3),
676 PIS(STATEULPS1),
677 PIS(STATEULPS2),
678 PIS(STATEULPS3),
679 PIS(ERRCONTENTIONLP0_1),
680 PIS(ERRCONTENTIONLP1_1),
681 PIS(ERRCONTENTIONLP0_2),
682 PIS(ERRCONTENTIONLP1_2),
683 PIS(ERRCONTENTIONLP0_3),
684 PIS(ERRCONTENTIONLP1_3),
685 PIS(ULPSACTIVENOT_ALL0),
686 PIS(ULPSACTIVENOT_ALL1));
687 #undef PIS
688 }
689
690 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
dsi_collect_irq_stats(struct platform_device * dsidev,u32 irqstatus,u32 * vcstatus,u32 ciostatus)691 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
692 u32 *vcstatus, u32 ciostatus)
693 {
694 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
695 int i;
696
697 spin_lock(&dsi->irq_stats_lock);
698
699 dsi->irq_stats.irq_count++;
700 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
701
702 for (i = 0; i < 4; ++i)
703 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
704
705 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
706
707 spin_unlock(&dsi->irq_stats_lock);
708 }
709 #else
710 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
711 #endif
712
713 static int debug_irq;
714
dsi_handle_irq_errors(struct platform_device * dsidev,u32 irqstatus,u32 * vcstatus,u32 ciostatus)715 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
716 u32 *vcstatus, u32 ciostatus)
717 {
718 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
719 int i;
720
721 if (irqstatus & DSI_IRQ_ERROR_MASK) {
722 DSSERR("DSI error, irqstatus %x\n", irqstatus);
723 print_irq_status(irqstatus);
724 spin_lock(&dsi->errors_lock);
725 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
726 spin_unlock(&dsi->errors_lock);
727 } else if (debug_irq) {
728 print_irq_status(irqstatus);
729 }
730
731 for (i = 0; i < 4; ++i) {
732 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
733 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
734 i, vcstatus[i]);
735 print_irq_status_vc(i, vcstatus[i]);
736 } else if (debug_irq) {
737 print_irq_status_vc(i, vcstatus[i]);
738 }
739 }
740
741 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
742 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
743 print_irq_status_cio(ciostatus);
744 } else if (debug_irq) {
745 print_irq_status_cio(ciostatus);
746 }
747 }
748
dsi_call_isrs(struct dsi_isr_data * isr_array,unsigned isr_array_size,u32 irqstatus)749 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
750 unsigned isr_array_size, u32 irqstatus)
751 {
752 struct dsi_isr_data *isr_data;
753 int i;
754
755 for (i = 0; i < isr_array_size; i++) {
756 isr_data = &isr_array[i];
757 if (isr_data->isr && isr_data->mask & irqstatus)
758 isr_data->isr(isr_data->arg, irqstatus);
759 }
760 }
761
dsi_handle_isrs(struct dsi_isr_tables * isr_tables,u32 irqstatus,u32 * vcstatus,u32 ciostatus)762 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
763 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
764 {
765 int i;
766
767 dsi_call_isrs(isr_tables->isr_table,
768 ARRAY_SIZE(isr_tables->isr_table),
769 irqstatus);
770
771 for (i = 0; i < 4; ++i) {
772 if (vcstatus[i] == 0)
773 continue;
774 dsi_call_isrs(isr_tables->isr_table_vc[i],
775 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
776 vcstatus[i]);
777 }
778
779 if (ciostatus != 0)
780 dsi_call_isrs(isr_tables->isr_table_cio,
781 ARRAY_SIZE(isr_tables->isr_table_cio),
782 ciostatus);
783 }
784
omap_dsi_irq_handler(int irq,void * arg)785 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
786 {
787 struct platform_device *dsidev;
788 struct dsi_data *dsi;
789 u32 irqstatus, vcstatus[4], ciostatus;
790 int i;
791
792 dsidev = (struct platform_device *) arg;
793 dsi = dsi_get_dsidrv_data(dsidev);
794
795 if (!dsi->is_enabled)
796 return IRQ_NONE;
797
798 spin_lock(&dsi->irq_lock);
799
800 irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
801
802 /* IRQ is not for us */
803 if (!irqstatus) {
804 spin_unlock(&dsi->irq_lock);
805 return IRQ_NONE;
806 }
807
808 dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
809 /* flush posted write */
810 dsi_read_reg(dsidev, DSI_IRQSTATUS);
811
812 for (i = 0; i < 4; ++i) {
813 if ((irqstatus & (1 << i)) == 0) {
814 vcstatus[i] = 0;
815 continue;
816 }
817
818 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
819
820 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
821 /* flush posted write */
822 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
823 }
824
825 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
826 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
827
828 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
829 /* flush posted write */
830 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
831 } else {
832 ciostatus = 0;
833 }
834
835 #ifdef DSI_CATCH_MISSING_TE
836 if (irqstatus & DSI_IRQ_TE_TRIGGER)
837 del_timer(&dsi->te_timer);
838 #endif
839
840 /* make a copy and unlock, so that isrs can unregister
841 * themselves */
842 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
843 sizeof(dsi->isr_tables));
844
845 spin_unlock(&dsi->irq_lock);
846
847 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
848
849 dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
850
851 dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
852
853 return IRQ_HANDLED;
854 }
855
856 /* dsi->irq_lock has to be locked by the caller */
_omap_dsi_configure_irqs(struct platform_device * dsidev,struct dsi_isr_data * isr_array,unsigned isr_array_size,u32 default_mask,const struct dsi_reg enable_reg,const struct dsi_reg status_reg)857 static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
858 struct dsi_isr_data *isr_array,
859 unsigned isr_array_size, u32 default_mask,
860 const struct dsi_reg enable_reg,
861 const struct dsi_reg status_reg)
862 {
863 struct dsi_isr_data *isr_data;
864 u32 mask;
865 u32 old_mask;
866 int i;
867
868 mask = default_mask;
869
870 for (i = 0; i < isr_array_size; i++) {
871 isr_data = &isr_array[i];
872
873 if (isr_data->isr == NULL)
874 continue;
875
876 mask |= isr_data->mask;
877 }
878
879 old_mask = dsi_read_reg(dsidev, enable_reg);
880 /* clear the irqstatus for newly enabled irqs */
881 dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
882 dsi_write_reg(dsidev, enable_reg, mask);
883
884 /* flush posted writes */
885 dsi_read_reg(dsidev, enable_reg);
886 dsi_read_reg(dsidev, status_reg);
887 }
888
889 /* dsi->irq_lock has to be locked by the caller */
_omap_dsi_set_irqs(struct platform_device * dsidev)890 static void _omap_dsi_set_irqs(struct platform_device *dsidev)
891 {
892 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
893 u32 mask = DSI_IRQ_ERROR_MASK;
894 #ifdef DSI_CATCH_MISSING_TE
895 mask |= DSI_IRQ_TE_TRIGGER;
896 #endif
897 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
898 ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
899 DSI_IRQENABLE, DSI_IRQSTATUS);
900 }
901
902 /* dsi->irq_lock has to be locked by the caller */
_omap_dsi_set_irqs_vc(struct platform_device * dsidev,int vc)903 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
904 {
905 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
906
907 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
908 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
909 DSI_VC_IRQ_ERROR_MASK,
910 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
911 }
912
913 /* dsi->irq_lock has to be locked by the caller */
_omap_dsi_set_irqs_cio(struct platform_device * dsidev)914 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
915 {
916 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
917
918 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
919 ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
920 DSI_CIO_IRQ_ERROR_MASK,
921 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
922 }
923
_dsi_initialize_irq(struct platform_device * dsidev)924 static void _dsi_initialize_irq(struct platform_device *dsidev)
925 {
926 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
927 unsigned long flags;
928 int vc;
929
930 spin_lock_irqsave(&dsi->irq_lock, flags);
931
932 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
933
934 _omap_dsi_set_irqs(dsidev);
935 for (vc = 0; vc < 4; ++vc)
936 _omap_dsi_set_irqs_vc(dsidev, vc);
937 _omap_dsi_set_irqs_cio(dsidev);
938
939 spin_unlock_irqrestore(&dsi->irq_lock, flags);
940 }
941
_dsi_register_isr(omap_dsi_isr_t isr,void * arg,u32 mask,struct dsi_isr_data * isr_array,unsigned isr_array_size)942 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
943 struct dsi_isr_data *isr_array, unsigned isr_array_size)
944 {
945 struct dsi_isr_data *isr_data;
946 int free_idx;
947 int i;
948
949 BUG_ON(isr == NULL);
950
951 /* check for duplicate entry and find a free slot */
952 free_idx = -1;
953 for (i = 0; i < isr_array_size; i++) {
954 isr_data = &isr_array[i];
955
956 if (isr_data->isr == isr && isr_data->arg == arg &&
957 isr_data->mask == mask) {
958 return -EINVAL;
959 }
960
961 if (isr_data->isr == NULL && free_idx == -1)
962 free_idx = i;
963 }
964
965 if (free_idx == -1)
966 return -EBUSY;
967
968 isr_data = &isr_array[free_idx];
969 isr_data->isr = isr;
970 isr_data->arg = arg;
971 isr_data->mask = mask;
972
973 return 0;
974 }
975
_dsi_unregister_isr(omap_dsi_isr_t isr,void * arg,u32 mask,struct dsi_isr_data * isr_array,unsigned isr_array_size)976 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
977 struct dsi_isr_data *isr_array, unsigned isr_array_size)
978 {
979 struct dsi_isr_data *isr_data;
980 int i;
981
982 for (i = 0; i < isr_array_size; i++) {
983 isr_data = &isr_array[i];
984 if (isr_data->isr != isr || isr_data->arg != arg ||
985 isr_data->mask != mask)
986 continue;
987
988 isr_data->isr = NULL;
989 isr_data->arg = NULL;
990 isr_data->mask = 0;
991
992 return 0;
993 }
994
995 return -EINVAL;
996 }
997
dsi_register_isr(struct platform_device * dsidev,omap_dsi_isr_t isr,void * arg,u32 mask)998 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
999 void *arg, u32 mask)
1000 {
1001 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1002 unsigned long flags;
1003 int r;
1004
1005 spin_lock_irqsave(&dsi->irq_lock, flags);
1006
1007 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
1008 ARRAY_SIZE(dsi->isr_tables.isr_table));
1009
1010 if (r == 0)
1011 _omap_dsi_set_irqs(dsidev);
1012
1013 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1014
1015 return r;
1016 }
1017
dsi_unregister_isr(struct platform_device * dsidev,omap_dsi_isr_t isr,void * arg,u32 mask)1018 static int dsi_unregister_isr(struct platform_device *dsidev,
1019 omap_dsi_isr_t isr, void *arg, u32 mask)
1020 {
1021 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1022 unsigned long flags;
1023 int r;
1024
1025 spin_lock_irqsave(&dsi->irq_lock, flags);
1026
1027 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
1028 ARRAY_SIZE(dsi->isr_tables.isr_table));
1029
1030 if (r == 0)
1031 _omap_dsi_set_irqs(dsidev);
1032
1033 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1034
1035 return r;
1036 }
1037
dsi_register_isr_vc(struct platform_device * dsidev,int channel,omap_dsi_isr_t isr,void * arg,u32 mask)1038 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
1039 omap_dsi_isr_t isr, void *arg, u32 mask)
1040 {
1041 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1042 unsigned long flags;
1043 int r;
1044
1045 spin_lock_irqsave(&dsi->irq_lock, flags);
1046
1047 r = _dsi_register_isr(isr, arg, mask,
1048 dsi->isr_tables.isr_table_vc[channel],
1049 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1050
1051 if (r == 0)
1052 _omap_dsi_set_irqs_vc(dsidev, channel);
1053
1054 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1055
1056 return r;
1057 }
1058
dsi_unregister_isr_vc(struct platform_device * dsidev,int channel,omap_dsi_isr_t isr,void * arg,u32 mask)1059 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
1060 omap_dsi_isr_t isr, void *arg, u32 mask)
1061 {
1062 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1063 unsigned long flags;
1064 int r;
1065
1066 spin_lock_irqsave(&dsi->irq_lock, flags);
1067
1068 r = _dsi_unregister_isr(isr, arg, mask,
1069 dsi->isr_tables.isr_table_vc[channel],
1070 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1071
1072 if (r == 0)
1073 _omap_dsi_set_irqs_vc(dsidev, channel);
1074
1075 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1076
1077 return r;
1078 }
1079
dsi_register_isr_cio(struct platform_device * dsidev,omap_dsi_isr_t isr,void * arg,u32 mask)1080 static int dsi_register_isr_cio(struct platform_device *dsidev,
1081 omap_dsi_isr_t isr, void *arg, u32 mask)
1082 {
1083 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1084 unsigned long flags;
1085 int r;
1086
1087 spin_lock_irqsave(&dsi->irq_lock, flags);
1088
1089 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1090 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1091
1092 if (r == 0)
1093 _omap_dsi_set_irqs_cio(dsidev);
1094
1095 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1096
1097 return r;
1098 }
1099
dsi_unregister_isr_cio(struct platform_device * dsidev,omap_dsi_isr_t isr,void * arg,u32 mask)1100 static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1101 omap_dsi_isr_t isr, void *arg, u32 mask)
1102 {
1103 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1104 unsigned long flags;
1105 int r;
1106
1107 spin_lock_irqsave(&dsi->irq_lock, flags);
1108
1109 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1110 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1111
1112 if (r == 0)
1113 _omap_dsi_set_irqs_cio(dsidev);
1114
1115 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1116
1117 return r;
1118 }
1119
dsi_get_errors(struct platform_device * dsidev)1120 static u32 dsi_get_errors(struct platform_device *dsidev)
1121 {
1122 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1123 unsigned long flags;
1124 u32 e;
1125 spin_lock_irqsave(&dsi->errors_lock, flags);
1126 e = dsi->errors;
1127 dsi->errors = 0;
1128 spin_unlock_irqrestore(&dsi->errors_lock, flags);
1129 return e;
1130 }
1131
dsi_runtime_get(struct platform_device * dsidev)1132 static int dsi_runtime_get(struct platform_device *dsidev)
1133 {
1134 int r;
1135 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1136
1137 DSSDBG("dsi_runtime_get\n");
1138
1139 r = pm_runtime_resume_and_get(&dsi->pdev->dev);
1140 if (WARN_ON(r < 0))
1141 return r;
1142 return 0;
1143 }
1144
dsi_runtime_put(struct platform_device * dsidev)1145 static void dsi_runtime_put(struct platform_device *dsidev)
1146 {
1147 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1148 int r;
1149
1150 DSSDBG("dsi_runtime_put\n");
1151
1152 r = pm_runtime_put_sync(&dsi->pdev->dev);
1153 WARN_ON(r < 0 && r != -ENOSYS);
1154 }
1155
dsi_regulator_init(struct platform_device * dsidev)1156 static int dsi_regulator_init(struct platform_device *dsidev)
1157 {
1158 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1159 struct regulator *vdds_dsi;
1160
1161 if (dsi->vdds_dsi_reg != NULL)
1162 return 0;
1163
1164 vdds_dsi = devm_regulator_get(&dsi->pdev->dev, "vdd");
1165
1166 if (IS_ERR(vdds_dsi)) {
1167 if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER)
1168 DSSERR("can't get DSI VDD regulator\n");
1169 return PTR_ERR(vdds_dsi);
1170 }
1171
1172 dsi->vdds_dsi_reg = vdds_dsi;
1173
1174 return 0;
1175 }
1176
_dsi_print_reset_status(struct platform_device * dsidev)1177 static void _dsi_print_reset_status(struct platform_device *dsidev)
1178 {
1179 int b0, b1, b2;
1180
1181 /* A dummy read using the SCP interface to any DSIPHY register is
1182 * required after DSIPHY reset to complete the reset of the DSI complex
1183 * I/O. */
1184 dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1185
1186 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
1187 b0 = 28;
1188 b1 = 27;
1189 b2 = 26;
1190 } else {
1191 b0 = 24;
1192 b1 = 25;
1193 b2 = 26;
1194 }
1195
1196 #define DSI_FLD_GET(fld, start, end)\
1197 FLD_GET(dsi_read_reg(dsidev, DSI_##fld), start, end)
1198
1199 pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n",
1200 DSI_FLD_GET(PLL_STATUS, 0, 0),
1201 DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29),
1202 DSI_FLD_GET(DSIPHY_CFG5, b0, b0),
1203 DSI_FLD_GET(DSIPHY_CFG5, b1, b1),
1204 DSI_FLD_GET(DSIPHY_CFG5, b2, b2),
1205 DSI_FLD_GET(DSIPHY_CFG5, 29, 29),
1206 DSI_FLD_GET(DSIPHY_CFG5, 30, 30),
1207 DSI_FLD_GET(DSIPHY_CFG5, 31, 31));
1208
1209 #undef DSI_FLD_GET
1210 }
1211
dsi_if_enable(struct platform_device * dsidev,bool enable)1212 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
1213 {
1214 DSSDBG("dsi_if_enable(%d)\n", enable);
1215
1216 enable = enable ? 1 : 0;
1217 REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
1218
1219 if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
1220 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1221 return -EIO;
1222 }
1223
1224 return 0;
1225 }
1226
dsi_get_pll_hsdiv_dispc_rate(struct platform_device * dsidev)1227 static unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
1228 {
1229 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1230
1231 return dsi->pll.cinfo.clkout[HSDIV_DISPC];
1232 }
1233
dsi_get_pll_hsdiv_dsi_rate(struct platform_device * dsidev)1234 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
1235 {
1236 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1237
1238 return dsi->pll.cinfo.clkout[HSDIV_DSI];
1239 }
1240
dsi_get_txbyteclkhs(struct platform_device * dsidev)1241 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
1242 {
1243 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1244
1245 return dsi->pll.cinfo.clkdco / 16;
1246 }
1247
dsi_fclk_rate(struct platform_device * dsidev)1248 static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
1249 {
1250 unsigned long r;
1251 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1252
1253 if (dss_get_dsi_clk_source(dsi->module_id) == OMAP_DSS_CLK_SRC_FCK) {
1254 /* DSI FCLK source is DSS_CLK_FCK */
1255 r = clk_get_rate(dsi->dss_clk);
1256 } else {
1257 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1258 r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
1259 }
1260
1261 return r;
1262 }
1263
dsi_lp_clock_calc(unsigned long dsi_fclk,unsigned long lp_clk_min,unsigned long lp_clk_max,struct dsi_lp_clock_info * lp_cinfo)1264 static int dsi_lp_clock_calc(unsigned long dsi_fclk,
1265 unsigned long lp_clk_min, unsigned long lp_clk_max,
1266 struct dsi_lp_clock_info *lp_cinfo)
1267 {
1268 unsigned lp_clk_div;
1269 unsigned long lp_clk;
1270
1271 lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2);
1272 lp_clk = dsi_fclk / 2 / lp_clk_div;
1273
1274 if (lp_clk < lp_clk_min || lp_clk > lp_clk_max)
1275 return -EINVAL;
1276
1277 lp_cinfo->lp_clk_div = lp_clk_div;
1278 lp_cinfo->lp_clk = lp_clk;
1279
1280 return 0;
1281 }
1282
dsi_set_lp_clk_divisor(struct platform_device * dsidev)1283 static int dsi_set_lp_clk_divisor(struct platform_device *dsidev)
1284 {
1285 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1286 unsigned long dsi_fclk;
1287 unsigned lp_clk_div;
1288 unsigned long lp_clk;
1289 unsigned lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
1290
1291
1292 lp_clk_div = dsi->user_lp_cinfo.lp_clk_div;
1293
1294 if (lp_clk_div == 0 || lp_clk_div > lpdiv_max)
1295 return -EINVAL;
1296
1297 dsi_fclk = dsi_fclk_rate(dsidev);
1298
1299 lp_clk = dsi_fclk / 2 / lp_clk_div;
1300
1301 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1302 dsi->current_lp_cinfo.lp_clk = lp_clk;
1303 dsi->current_lp_cinfo.lp_clk_div = lp_clk_div;
1304
1305 /* LP_CLK_DIVISOR */
1306 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1307
1308 /* LP_RX_SYNCHRO_ENABLE */
1309 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1310
1311 return 0;
1312 }
1313
dsi_enable_scp_clk(struct platform_device * dsidev)1314 static void dsi_enable_scp_clk(struct platform_device *dsidev)
1315 {
1316 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1317
1318 if (dsi->scp_clk_refcount++ == 0)
1319 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1320 }
1321
dsi_disable_scp_clk(struct platform_device * dsidev)1322 static void dsi_disable_scp_clk(struct platform_device *dsidev)
1323 {
1324 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1325
1326 WARN_ON(dsi->scp_clk_refcount == 0);
1327 if (--dsi->scp_clk_refcount == 0)
1328 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1329 }
1330
1331 enum dsi_pll_power_state {
1332 DSI_PLL_POWER_OFF = 0x0,
1333 DSI_PLL_POWER_ON_HSCLK = 0x1,
1334 DSI_PLL_POWER_ON_ALL = 0x2,
1335 DSI_PLL_POWER_ON_DIV = 0x3,
1336 };
1337
dsi_pll_power(struct platform_device * dsidev,enum dsi_pll_power_state state)1338 static int dsi_pll_power(struct platform_device *dsidev,
1339 enum dsi_pll_power_state state)
1340 {
1341 int t = 0;
1342
1343 /* DSI-PLL power command 0x3 is not working */
1344 if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
1345 state == DSI_PLL_POWER_ON_DIV)
1346 state = DSI_PLL_POWER_ON_ALL;
1347
1348 /* PLL_PWR_CMD */
1349 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
1350
1351 /* PLL_PWR_STATUS */
1352 while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1353 if (++t > 1000) {
1354 DSSERR("Failed to set DSI PLL power mode to %d\n",
1355 state);
1356 return -ENODEV;
1357 }
1358 udelay(1);
1359 }
1360
1361 return 0;
1362 }
1363
1364
dsi_pll_calc_dsi_fck(struct dss_pll_clock_info * cinfo)1365 static void dsi_pll_calc_dsi_fck(struct dss_pll_clock_info *cinfo)
1366 {
1367 unsigned long max_dsi_fck;
1368
1369 max_dsi_fck = dss_feat_get_param_max(FEAT_PARAM_DSI_FCK);
1370
1371 cinfo->mX[HSDIV_DSI] = DIV_ROUND_UP(cinfo->clkdco, max_dsi_fck);
1372 cinfo->clkout[HSDIV_DSI] = cinfo->clkdco / cinfo->mX[HSDIV_DSI];
1373 }
1374
dsi_pll_enable(struct dss_pll * pll)1375 static int dsi_pll_enable(struct dss_pll *pll)
1376 {
1377 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
1378 struct platform_device *dsidev = dsi->pdev;
1379 int r = 0;
1380
1381 DSSDBG("PLL init\n");
1382
1383 r = dsi_regulator_init(dsidev);
1384 if (r)
1385 return r;
1386
1387 r = dsi_runtime_get(dsidev);
1388 if (r)
1389 return r;
1390
1391 /*
1392 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1393 */
1394 dsi_enable_scp_clk(dsidev);
1395
1396 if (!dsi->vdds_dsi_enabled) {
1397 r = regulator_enable(dsi->vdds_dsi_reg);
1398 if (r)
1399 goto err0;
1400 dsi->vdds_dsi_enabled = true;
1401 }
1402
1403 /* XXX PLL does not come out of reset without this... */
1404 dispc_pck_free_enable(1);
1405
1406 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
1407 DSSERR("PLL not coming out of reset.\n");
1408 r = -ENODEV;
1409 dispc_pck_free_enable(0);
1410 goto err1;
1411 }
1412
1413 /* XXX ... but if left on, we get problems when planes do not
1414 * fill the whole display. No idea about this */
1415 dispc_pck_free_enable(0);
1416
1417 r = dsi_pll_power(dsidev, DSI_PLL_POWER_ON_ALL);
1418
1419 if (r)
1420 goto err1;
1421
1422 DSSDBG("PLL init done\n");
1423
1424 return 0;
1425 err1:
1426 if (dsi->vdds_dsi_enabled) {
1427 regulator_disable(dsi->vdds_dsi_reg);
1428 dsi->vdds_dsi_enabled = false;
1429 }
1430 err0:
1431 dsi_disable_scp_clk(dsidev);
1432 dsi_runtime_put(dsidev);
1433 return r;
1434 }
1435
dsi_pll_uninit(struct platform_device * dsidev,bool disconnect_lanes)1436 static void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
1437 {
1438 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1439
1440 dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1441 if (disconnect_lanes) {
1442 WARN_ON(!dsi->vdds_dsi_enabled);
1443 regulator_disable(dsi->vdds_dsi_reg);
1444 dsi->vdds_dsi_enabled = false;
1445 }
1446
1447 dsi_disable_scp_clk(dsidev);
1448 dsi_runtime_put(dsidev);
1449
1450 DSSDBG("PLL uninit done\n");
1451 }
1452
dsi_pll_disable(struct dss_pll * pll)1453 static void dsi_pll_disable(struct dss_pll *pll)
1454 {
1455 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
1456 struct platform_device *dsidev = dsi->pdev;
1457
1458 dsi_pll_uninit(dsidev, true);
1459 }
1460
dsi_dump_dsidev_clocks(struct platform_device * dsidev,struct seq_file * s)1461 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1462 struct seq_file *s)
1463 {
1464 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1465 struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo;
1466 enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1467 int dsi_module = dsi->module_id;
1468 struct dss_pll *pll = &dsi->pll;
1469
1470 dispc_clk_src = dss_get_dispc_clk_source();
1471 dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
1472
1473 if (dsi_runtime_get(dsidev))
1474 return;
1475
1476 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1);
1477
1478 seq_printf(s, "dsi pll clkin\t%lu\n", clk_get_rate(pll->clkin));
1479
1480 seq_printf(s, "Fint\t\t%-16lun %u\n", cinfo->fint, cinfo->n);
1481
1482 seq_printf(s, "CLKIN4DDR\t%-16lum %u\n",
1483 cinfo->clkdco, cinfo->m);
1484
1485 seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16lum_dispc %u\t(%s)\n",
1486 dss_feat_get_clk_source_name(dsi_module == 0 ?
1487 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
1488 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC),
1489 cinfo->clkout[HSDIV_DISPC],
1490 cinfo->mX[HSDIV_DISPC],
1491 dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1492 "off" : "on");
1493
1494 seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16lum_dsi %u\t(%s)\n",
1495 dss_feat_get_clk_source_name(dsi_module == 0 ?
1496 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
1497 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI),
1498 cinfo->clkout[HSDIV_DSI],
1499 cinfo->mX[HSDIV_DSI],
1500 dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1501 "off" : "on");
1502
1503 seq_printf(s, "- DSI%d -\n", dsi_module + 1);
1504
1505 seq_printf(s, "dsi fclk source = %s (%s)\n",
1506 dss_get_generic_clk_source_name(dsi_clk_src),
1507 dss_feat_get_clk_source_name(dsi_clk_src));
1508
1509 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
1510
1511 seq_printf(s, "DDR_CLK\t\t%lu\n",
1512 cinfo->clkdco / 4);
1513
1514 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
1515
1516 seq_printf(s, "LP_CLK\t\t%lu\n", dsi->current_lp_cinfo.lp_clk);
1517
1518 dsi_runtime_put(dsidev);
1519 }
1520
dsi_dump_clocks(struct seq_file * s)1521 void dsi_dump_clocks(struct seq_file *s)
1522 {
1523 struct platform_device *dsidev;
1524 int i;
1525
1526 for (i = 0; i < MAX_NUM_DSI; i++) {
1527 dsidev = dsi_get_dsidev_from_id(i);
1528 if (dsidev)
1529 dsi_dump_dsidev_clocks(dsidev, s);
1530 }
1531 }
1532
1533 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
dsi_dump_dsidev_irqs(struct platform_device * dsidev,struct seq_file * s)1534 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1535 struct seq_file *s)
1536 {
1537 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1538 unsigned long flags;
1539 struct dsi_irq_stats stats;
1540
1541 spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1542
1543 stats = dsi->irq_stats;
1544 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1545 dsi->irq_stats.last_reset = jiffies;
1546
1547 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1548
1549 seq_printf(s, "period %u ms\n",
1550 jiffies_to_msecs(jiffies - stats.last_reset));
1551
1552 seq_printf(s, "irqs %d\n", stats.irq_count);
1553 #define PIS(x) \
1554 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1])
1555
1556 seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1);
1557 PIS(VC0);
1558 PIS(VC1);
1559 PIS(VC2);
1560 PIS(VC3);
1561 PIS(WAKEUP);
1562 PIS(RESYNC);
1563 PIS(PLL_LOCK);
1564 PIS(PLL_UNLOCK);
1565 PIS(PLL_RECALL);
1566 PIS(COMPLEXIO_ERR);
1567 PIS(HS_TX_TIMEOUT);
1568 PIS(LP_RX_TIMEOUT);
1569 PIS(TE_TRIGGER);
1570 PIS(ACK_TRIGGER);
1571 PIS(SYNC_LOST);
1572 PIS(LDO_POWER_GOOD);
1573 PIS(TA_TIMEOUT);
1574 #undef PIS
1575
1576 #define PIS(x) \
1577 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1578 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1579 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1580 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1581 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1582
1583 seq_printf(s, "-- VC interrupts --\n");
1584 PIS(CS);
1585 PIS(ECC_CORR);
1586 PIS(PACKET_SENT);
1587 PIS(FIFO_TX_OVF);
1588 PIS(FIFO_RX_OVF);
1589 PIS(BTA);
1590 PIS(ECC_NO_CORR);
1591 PIS(FIFO_TX_UDF);
1592 PIS(PP_BUSY_CHANGE);
1593 #undef PIS
1594
1595 #define PIS(x) \
1596 seq_printf(s, "%-20s %10d\n", #x, \
1597 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1598
1599 seq_printf(s, "-- CIO interrupts --\n");
1600 PIS(ERRSYNCESC1);
1601 PIS(ERRSYNCESC2);
1602 PIS(ERRSYNCESC3);
1603 PIS(ERRESC1);
1604 PIS(ERRESC2);
1605 PIS(ERRESC3);
1606 PIS(ERRCONTROL1);
1607 PIS(ERRCONTROL2);
1608 PIS(ERRCONTROL3);
1609 PIS(STATEULPS1);
1610 PIS(STATEULPS2);
1611 PIS(STATEULPS3);
1612 PIS(ERRCONTENTIONLP0_1);
1613 PIS(ERRCONTENTIONLP1_1);
1614 PIS(ERRCONTENTIONLP0_2);
1615 PIS(ERRCONTENTIONLP1_2);
1616 PIS(ERRCONTENTIONLP0_3);
1617 PIS(ERRCONTENTIONLP1_3);
1618 PIS(ULPSACTIVENOT_ALL0);
1619 PIS(ULPSACTIVENOT_ALL1);
1620 #undef PIS
1621 }
1622
dsi1_dump_irqs(struct seq_file * s)1623 static void dsi1_dump_irqs(struct seq_file *s)
1624 {
1625 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1626
1627 dsi_dump_dsidev_irqs(dsidev, s);
1628 }
1629
dsi2_dump_irqs(struct seq_file * s)1630 static void dsi2_dump_irqs(struct seq_file *s)
1631 {
1632 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1633
1634 dsi_dump_dsidev_irqs(dsidev, s);
1635 }
1636 #endif
1637
dsi_dump_dsidev_regs(struct platform_device * dsidev,struct seq_file * s)1638 static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
1639 struct seq_file *s)
1640 {
1641 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
1642
1643 if (dsi_runtime_get(dsidev))
1644 return;
1645 dsi_enable_scp_clk(dsidev);
1646
1647 DUMPREG(DSI_REVISION);
1648 DUMPREG(DSI_SYSCONFIG);
1649 DUMPREG(DSI_SYSSTATUS);
1650 DUMPREG(DSI_IRQSTATUS);
1651 DUMPREG(DSI_IRQENABLE);
1652 DUMPREG(DSI_CTRL);
1653 DUMPREG(DSI_COMPLEXIO_CFG1);
1654 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1655 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1656 DUMPREG(DSI_CLK_CTRL);
1657 DUMPREG(DSI_TIMING1);
1658 DUMPREG(DSI_TIMING2);
1659 DUMPREG(DSI_VM_TIMING1);
1660 DUMPREG(DSI_VM_TIMING2);
1661 DUMPREG(DSI_VM_TIMING3);
1662 DUMPREG(DSI_CLK_TIMING);
1663 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1664 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1665 DUMPREG(DSI_COMPLEXIO_CFG2);
1666 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1667 DUMPREG(DSI_VM_TIMING4);
1668 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1669 DUMPREG(DSI_VM_TIMING5);
1670 DUMPREG(DSI_VM_TIMING6);
1671 DUMPREG(DSI_VM_TIMING7);
1672 DUMPREG(DSI_STOPCLK_TIMING);
1673
1674 DUMPREG(DSI_VC_CTRL(0));
1675 DUMPREG(DSI_VC_TE(0));
1676 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1677 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1678 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1679 DUMPREG(DSI_VC_IRQSTATUS(0));
1680 DUMPREG(DSI_VC_IRQENABLE(0));
1681
1682 DUMPREG(DSI_VC_CTRL(1));
1683 DUMPREG(DSI_VC_TE(1));
1684 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1685 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1686 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1687 DUMPREG(DSI_VC_IRQSTATUS(1));
1688 DUMPREG(DSI_VC_IRQENABLE(1));
1689
1690 DUMPREG(DSI_VC_CTRL(2));
1691 DUMPREG(DSI_VC_TE(2));
1692 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1693 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1694 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1695 DUMPREG(DSI_VC_IRQSTATUS(2));
1696 DUMPREG(DSI_VC_IRQENABLE(2));
1697
1698 DUMPREG(DSI_VC_CTRL(3));
1699 DUMPREG(DSI_VC_TE(3));
1700 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1701 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1702 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1703 DUMPREG(DSI_VC_IRQSTATUS(3));
1704 DUMPREG(DSI_VC_IRQENABLE(3));
1705
1706 DUMPREG(DSI_DSIPHY_CFG0);
1707 DUMPREG(DSI_DSIPHY_CFG1);
1708 DUMPREG(DSI_DSIPHY_CFG2);
1709 DUMPREG(DSI_DSIPHY_CFG5);
1710
1711 DUMPREG(DSI_PLL_CONTROL);
1712 DUMPREG(DSI_PLL_STATUS);
1713 DUMPREG(DSI_PLL_GO);
1714 DUMPREG(DSI_PLL_CONFIGURATION1);
1715 DUMPREG(DSI_PLL_CONFIGURATION2);
1716
1717 dsi_disable_scp_clk(dsidev);
1718 dsi_runtime_put(dsidev);
1719 #undef DUMPREG
1720 }
1721
dsi1_dump_regs(struct seq_file * s)1722 static void dsi1_dump_regs(struct seq_file *s)
1723 {
1724 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1725
1726 dsi_dump_dsidev_regs(dsidev, s);
1727 }
1728
dsi2_dump_regs(struct seq_file * s)1729 static void dsi2_dump_regs(struct seq_file *s)
1730 {
1731 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1732
1733 dsi_dump_dsidev_regs(dsidev, s);
1734 }
1735
1736 enum dsi_cio_power_state {
1737 DSI_COMPLEXIO_POWER_OFF = 0x0,
1738 DSI_COMPLEXIO_POWER_ON = 0x1,
1739 DSI_COMPLEXIO_POWER_ULPS = 0x2,
1740 };
1741
dsi_cio_power(struct platform_device * dsidev,enum dsi_cio_power_state state)1742 static int dsi_cio_power(struct platform_device *dsidev,
1743 enum dsi_cio_power_state state)
1744 {
1745 int t = 0;
1746
1747 /* PWR_CMD */
1748 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
1749
1750 /* PWR_STATUS */
1751 while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
1752 26, 25) != state) {
1753 if (++t > 1000) {
1754 DSSERR("failed to set complexio power state to "
1755 "%d\n", state);
1756 return -ENODEV;
1757 }
1758 udelay(1);
1759 }
1760
1761 return 0;
1762 }
1763
dsi_get_line_buf_size(struct platform_device * dsidev)1764 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
1765 {
1766 int val;
1767
1768 /* line buffer on OMAP3 is 1024 x 24bits */
1769 /* XXX: for some reason using full buffer size causes
1770 * considerable TX slowdown with update sizes that fill the
1771 * whole buffer */
1772 if (!dss_has_feature(FEAT_DSI_GNQ))
1773 return 1023 * 3;
1774
1775 val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
1776
1777 switch (val) {
1778 case 1:
1779 return 512 * 3; /* 512x24 bits */
1780 case 2:
1781 return 682 * 3; /* 682x24 bits */
1782 case 3:
1783 return 853 * 3; /* 853x24 bits */
1784 case 4:
1785 return 1024 * 3; /* 1024x24 bits */
1786 case 5:
1787 return 1194 * 3; /* 1194x24 bits */
1788 case 6:
1789 return 1365 * 3; /* 1365x24 bits */
1790 case 7:
1791 return 1920 * 3; /* 1920x24 bits */
1792 default:
1793 BUG();
1794 return 0;
1795 }
1796 }
1797
dsi_set_lane_config(struct platform_device * dsidev)1798 static int dsi_set_lane_config(struct platform_device *dsidev)
1799 {
1800 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1801 static const u8 offsets[] = { 0, 4, 8, 12, 16 };
1802 static const enum dsi_lane_function functions[] = {
1803 DSI_LANE_CLK,
1804 DSI_LANE_DATA1,
1805 DSI_LANE_DATA2,
1806 DSI_LANE_DATA3,
1807 DSI_LANE_DATA4,
1808 };
1809 u32 r;
1810 int i;
1811
1812 r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
1813
1814 for (i = 0; i < dsi->num_lanes_used; ++i) {
1815 unsigned offset = offsets[i];
1816 unsigned polarity, lane_number;
1817 unsigned t;
1818
1819 for (t = 0; t < dsi->num_lanes_supported; ++t)
1820 if (dsi->lanes[t].function == functions[i])
1821 break;
1822
1823 if (t == dsi->num_lanes_supported)
1824 return -EINVAL;
1825
1826 lane_number = t;
1827 polarity = dsi->lanes[t].polarity;
1828
1829 r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
1830 r = FLD_MOD(r, polarity, offset + 3, offset + 3);
1831 }
1832
1833 /* clear the unused lanes */
1834 for (; i < dsi->num_lanes_supported; ++i) {
1835 unsigned offset = offsets[i];
1836
1837 r = FLD_MOD(r, 0, offset + 2, offset);
1838 r = FLD_MOD(r, 0, offset + 3, offset + 3);
1839 }
1840
1841 dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
1842
1843 return 0;
1844 }
1845
ns2ddr(struct platform_device * dsidev,unsigned ns)1846 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
1847 {
1848 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1849
1850 /* convert time in ns to ddr ticks, rounding up */
1851 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
1852 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
1853 }
1854
ddr2ns(struct platform_device * dsidev,unsigned ddr)1855 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
1856 {
1857 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1858
1859 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
1860 return ddr * 1000 * 1000 / (ddr_clk / 1000);
1861 }
1862
dsi_cio_timings(struct platform_device * dsidev)1863 static void dsi_cio_timings(struct platform_device *dsidev)
1864 {
1865 u32 r;
1866 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
1867 u32 tlpx_half, tclk_trail, tclk_zero;
1868 u32 tclk_prepare;
1869
1870 /* calculate timings */
1871
1872 /* 1 * DDR_CLK = 2 * UI */
1873
1874 /* min 40ns + 4*UI max 85ns + 6*UI */
1875 ths_prepare = ns2ddr(dsidev, 70) + 2;
1876
1877 /* min 145ns + 10*UI */
1878 ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
1879
1880 /* min max(8*UI, 60ns+4*UI) */
1881 ths_trail = ns2ddr(dsidev, 60) + 5;
1882
1883 /* min 100ns */
1884 ths_exit = ns2ddr(dsidev, 145);
1885
1886 /* tlpx min 50n */
1887 tlpx_half = ns2ddr(dsidev, 25);
1888
1889 /* min 60ns */
1890 tclk_trail = ns2ddr(dsidev, 60) + 2;
1891
1892 /* min 38ns, max 95ns */
1893 tclk_prepare = ns2ddr(dsidev, 65);
1894
1895 /* min tclk-prepare + tclk-zero = 300ns */
1896 tclk_zero = ns2ddr(dsidev, 260);
1897
1898 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
1899 ths_prepare, ddr2ns(dsidev, ths_prepare),
1900 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
1901 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
1902 ths_trail, ddr2ns(dsidev, ths_trail),
1903 ths_exit, ddr2ns(dsidev, ths_exit));
1904
1905 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
1906 "tclk_zero %u (%uns)\n",
1907 tlpx_half, ddr2ns(dsidev, tlpx_half),
1908 tclk_trail, ddr2ns(dsidev, tclk_trail),
1909 tclk_zero, ddr2ns(dsidev, tclk_zero));
1910 DSSDBG("tclk_prepare %u (%uns)\n",
1911 tclk_prepare, ddr2ns(dsidev, tclk_prepare));
1912
1913 /* program timings */
1914
1915 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
1916 r = FLD_MOD(r, ths_prepare, 31, 24);
1917 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
1918 r = FLD_MOD(r, ths_trail, 15, 8);
1919 r = FLD_MOD(r, ths_exit, 7, 0);
1920 dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
1921
1922 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
1923 r = FLD_MOD(r, tlpx_half, 20, 16);
1924 r = FLD_MOD(r, tclk_trail, 15, 8);
1925 r = FLD_MOD(r, tclk_zero, 7, 0);
1926
1927 if (dss_has_feature(FEAT_DSI_PHY_DCC)) {
1928 r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */
1929 r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */
1930 r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */
1931 }
1932
1933 dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
1934
1935 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
1936 r = FLD_MOD(r, tclk_prepare, 7, 0);
1937 dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
1938 }
1939
1940 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
dsi_cio_enable_lane_override(struct platform_device * dsidev,unsigned mask_p,unsigned mask_n)1941 static void dsi_cio_enable_lane_override(struct platform_device *dsidev,
1942 unsigned mask_p, unsigned mask_n)
1943 {
1944 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1945 int i;
1946 u32 l;
1947 u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
1948
1949 l = 0;
1950
1951 for (i = 0; i < dsi->num_lanes_supported; ++i) {
1952 unsigned p = dsi->lanes[i].polarity;
1953
1954 if (mask_p & (1 << i))
1955 l |= 1 << (i * 2 + (p ? 0 : 1));
1956
1957 if (mask_n & (1 << i))
1958 l |= 1 << (i * 2 + (p ? 1 : 0));
1959 }
1960
1961 /*
1962 * Bits in REGLPTXSCPDAT4TO0DXDY:
1963 * 17: DY0 18: DX0
1964 * 19: DY1 20: DX1
1965 * 21: DY2 22: DX2
1966 * 23: DY3 24: DX3
1967 * 25: DY4 26: DX4
1968 */
1969
1970 /* Set the lane override configuration */
1971
1972 /* REGLPTXSCPDAT4TO0DXDY */
1973 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
1974
1975 /* Enable lane override */
1976
1977 /* ENLPTXSCPDAT */
1978 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
1979 }
1980
dsi_cio_disable_lane_override(struct platform_device * dsidev)1981 static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
1982 {
1983 /* Disable lane override */
1984 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
1985 /* Reset the lane override configuration */
1986 /* REGLPTXSCPDAT4TO0DXDY */
1987 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
1988 }
1989
dsi_cio_wait_tx_clk_esc_reset(struct platform_device * dsidev)1990 static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device *dsidev)
1991 {
1992 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1993 int t, i;
1994 bool in_use[DSI_MAX_NR_LANES];
1995 static const u8 offsets_old[] = { 28, 27, 26 };
1996 static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
1997 const u8 *offsets;
1998
1999 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC))
2000 offsets = offsets_old;
2001 else
2002 offsets = offsets_new;
2003
2004 for (i = 0; i < dsi->num_lanes_supported; ++i)
2005 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
2006
2007 t = 100000;
2008 while (true) {
2009 u32 l;
2010 int ok;
2011
2012 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2013
2014 ok = 0;
2015 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2016 if (!in_use[i] || (l & (1 << offsets[i])))
2017 ok++;
2018 }
2019
2020 if (ok == dsi->num_lanes_supported)
2021 break;
2022
2023 if (--t == 0) {
2024 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2025 if (!in_use[i] || (l & (1 << offsets[i])))
2026 continue;
2027
2028 DSSERR("CIO TXCLKESC%d domain not coming " \
2029 "out of reset\n", i);
2030 }
2031 return -EIO;
2032 }
2033 }
2034
2035 return 0;
2036 }
2037
2038 /* return bitmask of enabled lanes, lane0 being the lsb */
dsi_get_lane_mask(struct platform_device * dsidev)2039 static unsigned dsi_get_lane_mask(struct platform_device *dsidev)
2040 {
2041 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2042 unsigned mask = 0;
2043 int i;
2044
2045 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2046 if (dsi->lanes[i].function != DSI_LANE_UNUSED)
2047 mask |= 1 << i;
2048 }
2049
2050 return mask;
2051 }
2052
dsi_cio_init(struct platform_device * dsidev)2053 static int dsi_cio_init(struct platform_device *dsidev)
2054 {
2055 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2056 int r;
2057 u32 l;
2058
2059 DSSDBG("DSI CIO init starts");
2060
2061 r = dss_dsi_enable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2062 if (r)
2063 return r;
2064
2065 dsi_enable_scp_clk(dsidev);
2066
2067 /* A dummy read using the SCP interface to any DSIPHY register is
2068 * required after DSIPHY reset to complete the reset of the DSI complex
2069 * I/O. */
2070 dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2071
2072 if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2073 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2074 r = -EIO;
2075 goto err_scp_clk_dom;
2076 }
2077
2078 r = dsi_set_lane_config(dsidev);
2079 if (r)
2080 goto err_scp_clk_dom;
2081
2082 /* set TX STOP MODE timer to maximum for this operation */
2083 l = dsi_read_reg(dsidev, DSI_TIMING1);
2084 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2085 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */
2086 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */
2087 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */
2088 dsi_write_reg(dsidev, DSI_TIMING1, l);
2089
2090 if (dsi->ulps_enabled) {
2091 unsigned mask_p;
2092 int i;
2093
2094 DSSDBG("manual ulps exit\n");
2095
2096 /* ULPS is exited by Mark-1 state for 1ms, followed by
2097 * stop state. DSS HW cannot do this via the normal
2098 * ULPS exit sequence, as after reset the DSS HW thinks
2099 * that we are not in ULPS mode, and refuses to send the
2100 * sequence. So we need to send the ULPS exit sequence
2101 * manually by setting positive lines high and negative lines
2102 * low for 1ms.
2103 */
2104
2105 mask_p = 0;
2106
2107 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2108 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
2109 continue;
2110 mask_p |= 1 << i;
2111 }
2112
2113 dsi_cio_enable_lane_override(dsidev, mask_p, 0);
2114 }
2115
2116 r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
2117 if (r)
2118 goto err_cio_pwr;
2119
2120 if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2121 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2122 r = -ENODEV;
2123 goto err_cio_pwr_dom;
2124 }
2125
2126 dsi_if_enable(dsidev, true);
2127 dsi_if_enable(dsidev, false);
2128 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2129
2130 r = dsi_cio_wait_tx_clk_esc_reset(dsidev);
2131 if (r)
2132 goto err_tx_clk_esc_rst;
2133
2134 if (dsi->ulps_enabled) {
2135 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2136 ktime_t wait = ns_to_ktime(1000 * 1000);
2137 set_current_state(TASK_UNINTERRUPTIBLE);
2138 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2139
2140 /* Disable the override. The lanes should be set to Mark-11
2141 * state by the HW */
2142 dsi_cio_disable_lane_override(dsidev);
2143 }
2144
2145 /* FORCE_TX_STOP_MODE_IO */
2146 REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2147
2148 dsi_cio_timings(dsidev);
2149
2150 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
2151 /* DDR_CLK_ALWAYS_ON */
2152 REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
2153 dsi->vm_timings.ddr_clk_always_on, 13, 13);
2154 }
2155
2156 dsi->ulps_enabled = false;
2157
2158 DSSDBG("CIO init done\n");
2159
2160 return 0;
2161
2162 err_tx_clk_esc_rst:
2163 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2164 err_cio_pwr_dom:
2165 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2166 err_cio_pwr:
2167 if (dsi->ulps_enabled)
2168 dsi_cio_disable_lane_override(dsidev);
2169 err_scp_clk_dom:
2170 dsi_disable_scp_clk(dsidev);
2171 dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2172 return r;
2173 }
2174
dsi_cio_uninit(struct platform_device * dsidev)2175 static void dsi_cio_uninit(struct platform_device *dsidev)
2176 {
2177 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2178
2179 /* DDR_CLK_ALWAYS_ON */
2180 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
2181
2182 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2183 dsi_disable_scp_clk(dsidev);
2184 dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2185 }
2186
dsi_config_tx_fifo(struct platform_device * dsidev,enum fifo_size size1,enum fifo_size size2,enum fifo_size size3,enum fifo_size size4)2187 static void dsi_config_tx_fifo(struct platform_device *dsidev,
2188 enum fifo_size size1, enum fifo_size size2,
2189 enum fifo_size size3, enum fifo_size size4)
2190 {
2191 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2192 u32 r = 0;
2193 int add = 0;
2194 int i;
2195
2196 dsi->vc[0].tx_fifo_size = size1;
2197 dsi->vc[1].tx_fifo_size = size2;
2198 dsi->vc[2].tx_fifo_size = size3;
2199 dsi->vc[3].tx_fifo_size = size4;
2200
2201 for (i = 0; i < 4; i++) {
2202 u8 v;
2203 int size = dsi->vc[i].tx_fifo_size;
2204
2205 if (add + size > 4) {
2206 DSSERR("Illegal FIFO configuration\n");
2207 BUG();
2208 return;
2209 }
2210
2211 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2212 r |= v << (8 * i);
2213 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2214 add += size;
2215 }
2216
2217 dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
2218 }
2219
dsi_config_rx_fifo(struct platform_device * dsidev,enum fifo_size size1,enum fifo_size size2,enum fifo_size size3,enum fifo_size size4)2220 static void dsi_config_rx_fifo(struct platform_device *dsidev,
2221 enum fifo_size size1, enum fifo_size size2,
2222 enum fifo_size size3, enum fifo_size size4)
2223 {
2224 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2225 u32 r = 0;
2226 int add = 0;
2227 int i;
2228
2229 dsi->vc[0].rx_fifo_size = size1;
2230 dsi->vc[1].rx_fifo_size = size2;
2231 dsi->vc[2].rx_fifo_size = size3;
2232 dsi->vc[3].rx_fifo_size = size4;
2233
2234 for (i = 0; i < 4; i++) {
2235 u8 v;
2236 int size = dsi->vc[i].rx_fifo_size;
2237
2238 if (add + size > 4) {
2239 DSSERR("Illegal FIFO configuration\n");
2240 BUG();
2241 return;
2242 }
2243
2244 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2245 r |= v << (8 * i);
2246 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2247 add += size;
2248 }
2249
2250 dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
2251 }
2252
dsi_force_tx_stop_mode_io(struct platform_device * dsidev)2253 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2254 {
2255 u32 r;
2256
2257 r = dsi_read_reg(dsidev, DSI_TIMING1);
2258 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2259 dsi_write_reg(dsidev, DSI_TIMING1, r);
2260
2261 if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
2262 DSSERR("TX_STOP bit not going down\n");
2263 return -EIO;
2264 }
2265
2266 return 0;
2267 }
2268
dsi_vc_is_enabled(struct platform_device * dsidev,int channel)2269 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2270 {
2271 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2272 }
2273
dsi_packet_sent_handler_vp(void * data,u32 mask)2274 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2275 {
2276 struct dsi_packet_sent_handler_data *vp_data =
2277 (struct dsi_packet_sent_handler_data *) data;
2278 struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2279 const int channel = dsi->update_channel;
2280 u8 bit = dsi->te_enabled ? 30 : 31;
2281
2282 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2283 complete(vp_data->completion);
2284 }
2285
dsi_sync_vc_vp(struct platform_device * dsidev,int channel)2286 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2287 {
2288 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2289 DECLARE_COMPLETION_ONSTACK(completion);
2290 struct dsi_packet_sent_handler_data vp_data = {
2291 .dsidev = dsidev,
2292 .completion = &completion
2293 };
2294 int r = 0;
2295 u8 bit;
2296
2297 bit = dsi->te_enabled ? 30 : 31;
2298
2299 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2300 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2301 if (r)
2302 goto err0;
2303
2304 /* Wait for completion only if TE_EN/TE_START is still set */
2305 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2306 if (wait_for_completion_timeout(&completion,
2307 msecs_to_jiffies(10)) == 0) {
2308 DSSERR("Failed to complete previous frame transfer\n");
2309 r = -EIO;
2310 goto err1;
2311 }
2312 }
2313
2314 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2315 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2316
2317 return 0;
2318 err1:
2319 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2320 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2321 err0:
2322 return r;
2323 }
2324
dsi_packet_sent_handler_l4(void * data,u32 mask)2325 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2326 {
2327 struct dsi_packet_sent_handler_data *l4_data =
2328 (struct dsi_packet_sent_handler_data *) data;
2329 struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2330 const int channel = dsi->update_channel;
2331
2332 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2333 complete(l4_data->completion);
2334 }
2335
dsi_sync_vc_l4(struct platform_device * dsidev,int channel)2336 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2337 {
2338 DECLARE_COMPLETION_ONSTACK(completion);
2339 struct dsi_packet_sent_handler_data l4_data = {
2340 .dsidev = dsidev,
2341 .completion = &completion
2342 };
2343 int r = 0;
2344
2345 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2346 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2347 if (r)
2348 goto err0;
2349
2350 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2351 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2352 if (wait_for_completion_timeout(&completion,
2353 msecs_to_jiffies(10)) == 0) {
2354 DSSERR("Failed to complete previous l4 transfer\n");
2355 r = -EIO;
2356 goto err1;
2357 }
2358 }
2359
2360 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2361 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2362
2363 return 0;
2364 err1:
2365 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2366 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2367 err0:
2368 return r;
2369 }
2370
dsi_sync_vc(struct platform_device * dsidev,int channel)2371 static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2372 {
2373 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2374
2375 WARN_ON(!dsi_bus_is_locked(dsidev));
2376
2377 if (!dsi_vc_is_enabled(dsidev, channel))
2378 return 0;
2379
2380 switch (dsi->vc[channel].source) {
2381 case DSI_VC_SOURCE_VP:
2382 return dsi_sync_vc_vp(dsidev, channel);
2383 case DSI_VC_SOURCE_L4:
2384 return dsi_sync_vc_l4(dsidev, channel);
2385 default:
2386 BUG();
2387 return -EINVAL;
2388 }
2389 }
2390
dsi_vc_enable(struct platform_device * dsidev,int channel,bool enable)2391 static int dsi_vc_enable(struct platform_device *dsidev, int channel,
2392 bool enable)
2393 {
2394 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2395 channel, enable);
2396
2397 enable = enable ? 1 : 0;
2398
2399 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
2400
2401 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
2402 0, enable) != enable) {
2403 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2404 return -EIO;
2405 }
2406
2407 return 0;
2408 }
2409
dsi_vc_initial_config(struct platform_device * dsidev,int channel)2410 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2411 {
2412 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2413 u32 r;
2414
2415 DSSDBG("Initial config of virtual channel %d", channel);
2416
2417 r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2418
2419 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2420 DSSERR("VC(%d) busy when trying to configure it!\n",
2421 channel);
2422
2423 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2424 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
2425 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2426 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2427 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2428 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2429 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2430 if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
2431 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */
2432
2433 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2434 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2435
2436 dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
2437
2438 dsi->vc[channel].source = DSI_VC_SOURCE_L4;
2439 }
2440
dsi_vc_config_source(struct platform_device * dsidev,int channel,enum dsi_vc_source source)2441 static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
2442 enum dsi_vc_source source)
2443 {
2444 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2445
2446 if (dsi->vc[channel].source == source)
2447 return 0;
2448
2449 DSSDBG("Source config of virtual channel %d", channel);
2450
2451 dsi_sync_vc(dsidev, channel);
2452
2453 dsi_vc_enable(dsidev, channel, 0);
2454
2455 /* VC_BUSY */
2456 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2457 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2458 return -EIO;
2459 }
2460
2461 /* SOURCE, 0 = L4, 1 = video port */
2462 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
2463
2464 /* DCS_CMD_ENABLE */
2465 if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
2466 bool enable = source == DSI_VC_SOURCE_VP;
2467 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
2468 }
2469
2470 dsi_vc_enable(dsidev, channel, 1);
2471
2472 dsi->vc[channel].source = source;
2473
2474 return 0;
2475 }
2476
dsi_vc_enable_hs(struct omap_dss_device * dssdev,int channel,bool enable)2477 static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2478 bool enable)
2479 {
2480 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2481 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2482
2483 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2484
2485 WARN_ON(!dsi_bus_is_locked(dsidev));
2486
2487 dsi_vc_enable(dsidev, channel, 0);
2488 dsi_if_enable(dsidev, 0);
2489
2490 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
2491
2492 dsi_vc_enable(dsidev, channel, 1);
2493 dsi_if_enable(dsidev, 1);
2494
2495 dsi_force_tx_stop_mode_io(dsidev);
2496
2497 /* start the DDR clock by sending a NULL packet */
2498 if (dsi->vm_timings.ddr_clk_always_on && enable)
2499 dsi_vc_send_null(dssdev, channel);
2500 }
2501
dsi_vc_flush_long_data(struct platform_device * dsidev,int channel)2502 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
2503 {
2504 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2505 u32 val;
2506 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2507 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2508 (val >> 0) & 0xff,
2509 (val >> 8) & 0xff,
2510 (val >> 16) & 0xff,
2511 (val >> 24) & 0xff);
2512 }
2513 }
2514
dsi_show_rx_ack_with_err(u16 err)2515 static void dsi_show_rx_ack_with_err(u16 err)
2516 {
2517 DSSERR("\tACK with ERROR (%#x):\n", err);
2518 if (err & (1 << 0))
2519 DSSERR("\t\tSoT Error\n");
2520 if (err & (1 << 1))
2521 DSSERR("\t\tSoT Sync Error\n");
2522 if (err & (1 << 2))
2523 DSSERR("\t\tEoT Sync Error\n");
2524 if (err & (1 << 3))
2525 DSSERR("\t\tEscape Mode Entry Command Error\n");
2526 if (err & (1 << 4))
2527 DSSERR("\t\tLP Transmit Sync Error\n");
2528 if (err & (1 << 5))
2529 DSSERR("\t\tHS Receive Timeout Error\n");
2530 if (err & (1 << 6))
2531 DSSERR("\t\tFalse Control Error\n");
2532 if (err & (1 << 7))
2533 DSSERR("\t\t(reserved7)\n");
2534 if (err & (1 << 8))
2535 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2536 if (err & (1 << 9))
2537 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2538 if (err & (1 << 10))
2539 DSSERR("\t\tChecksum Error\n");
2540 if (err & (1 << 11))
2541 DSSERR("\t\tData type not recognized\n");
2542 if (err & (1 << 12))
2543 DSSERR("\t\tInvalid VC ID\n");
2544 if (err & (1 << 13))
2545 DSSERR("\t\tInvalid Transmission Length\n");
2546 if (err & (1 << 14))
2547 DSSERR("\t\t(reserved14)\n");
2548 if (err & (1 << 15))
2549 DSSERR("\t\tDSI Protocol Violation\n");
2550 }
2551
dsi_vc_flush_receive_data(struct platform_device * dsidev,int channel)2552 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2553 int channel)
2554 {
2555 /* RX_FIFO_NOT_EMPTY */
2556 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2557 u32 val;
2558 u8 dt;
2559 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2560 DSSERR("\trawval %#08x\n", val);
2561 dt = FLD_GET(val, 5, 0);
2562 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2563 u16 err = FLD_GET(val, 23, 8);
2564 dsi_show_rx_ack_with_err(err);
2565 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2566 DSSERR("\tDCS short response, 1 byte: %#x\n",
2567 FLD_GET(val, 23, 8));
2568 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2569 DSSERR("\tDCS short response, 2 byte: %#x\n",
2570 FLD_GET(val, 23, 8));
2571 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2572 DSSERR("\tDCS long response, len %d\n",
2573 FLD_GET(val, 23, 8));
2574 dsi_vc_flush_long_data(dsidev, channel);
2575 } else {
2576 DSSERR("\tunknown datatype 0x%02x\n", dt);
2577 }
2578 }
2579 return 0;
2580 }
2581
dsi_vc_send_bta(struct platform_device * dsidev,int channel)2582 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
2583 {
2584 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2585
2586 if (dsi->debug_write || dsi->debug_read)
2587 DSSDBG("dsi_vc_send_bta %d\n", channel);
2588
2589 WARN_ON(!dsi_bus_is_locked(dsidev));
2590
2591 /* RX_FIFO_NOT_EMPTY */
2592 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2593 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2594 dsi_vc_flush_receive_data(dsidev, channel);
2595 }
2596
2597 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2598
2599 /* flush posted write */
2600 dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2601
2602 return 0;
2603 }
2604
dsi_vc_send_bta_sync(struct omap_dss_device * dssdev,int channel)2605 static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2606 {
2607 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2608 DECLARE_COMPLETION_ONSTACK(completion);
2609 int r = 0;
2610 u32 err;
2611
2612 r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2613 &completion, DSI_VC_IRQ_BTA);
2614 if (r)
2615 goto err0;
2616
2617 r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2618 DSI_IRQ_ERROR_MASK);
2619 if (r)
2620 goto err1;
2621
2622 r = dsi_vc_send_bta(dsidev, channel);
2623 if (r)
2624 goto err2;
2625
2626 if (wait_for_completion_timeout(&completion,
2627 msecs_to_jiffies(500)) == 0) {
2628 DSSERR("Failed to receive BTA\n");
2629 r = -EIO;
2630 goto err2;
2631 }
2632
2633 err = dsi_get_errors(dsidev);
2634 if (err) {
2635 DSSERR("Error while sending BTA: %x\n", err);
2636 r = -EIO;
2637 goto err2;
2638 }
2639 err2:
2640 dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
2641 DSI_IRQ_ERROR_MASK);
2642 err1:
2643 dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
2644 &completion, DSI_VC_IRQ_BTA);
2645 err0:
2646 return r;
2647 }
2648
dsi_vc_write_long_header(struct platform_device * dsidev,int channel,u8 data_type,u16 len,u8 ecc)2649 static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
2650 int channel, u8 data_type, u16 len, u8 ecc)
2651 {
2652 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2653 u32 val;
2654 u8 data_id;
2655
2656 WARN_ON(!dsi_bus_is_locked(dsidev));
2657
2658 data_id = data_type | dsi->vc[channel].vc_id << 6;
2659
2660 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2661 FLD_VAL(ecc, 31, 24);
2662
2663 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
2664 }
2665
dsi_vc_write_long_payload(struct platform_device * dsidev,int channel,u8 b1,u8 b2,u8 b3,u8 b4)2666 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
2667 int channel, u8 b1, u8 b2, u8 b3, u8 b4)
2668 {
2669 u32 val;
2670
2671 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
2672
2673 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2674 b1, b2, b3, b4, val); */
2675
2676 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2677 }
2678
dsi_vc_send_long(struct platform_device * dsidev,int channel,u8 data_type,u8 * data,u16 len,u8 ecc)2679 static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
2680 u8 data_type, u8 *data, u16 len, u8 ecc)
2681 {
2682 /*u32 val; */
2683 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2684 int i;
2685 u8 *p;
2686 int r = 0;
2687 u8 b1, b2, b3, b4;
2688
2689 if (dsi->debug_write)
2690 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
2691
2692 /* len + header */
2693 if (dsi->vc[channel].tx_fifo_size * 32 * 4 < len + 4) {
2694 DSSERR("unable to send long packet: packet too long.\n");
2695 return -EINVAL;
2696 }
2697
2698 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
2699
2700 dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
2701
2702 p = data;
2703 for (i = 0; i < len >> 2; i++) {
2704 if (dsi->debug_write)
2705 DSSDBG("\tsending full packet %d\n", i);
2706
2707 b1 = *p++;
2708 b2 = *p++;
2709 b3 = *p++;
2710 b4 = *p++;
2711
2712 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
2713 }
2714
2715 i = len % 4;
2716 if (i) {
2717 b1 = 0; b2 = 0; b3 = 0;
2718
2719 if (dsi->debug_write)
2720 DSSDBG("\tsending remainder bytes %d\n", i);
2721
2722 switch (i) {
2723 case 3:
2724 b1 = *p++;
2725 b2 = *p++;
2726 b3 = *p++;
2727 break;
2728 case 2:
2729 b1 = *p++;
2730 b2 = *p++;
2731 break;
2732 case 1:
2733 b1 = *p++;
2734 break;
2735 }
2736
2737 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
2738 }
2739
2740 return r;
2741 }
2742
dsi_vc_send_short(struct platform_device * dsidev,int channel,u8 data_type,u16 data,u8 ecc)2743 static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
2744 u8 data_type, u16 data, u8 ecc)
2745 {
2746 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2747 u32 r;
2748 u8 data_id;
2749
2750 WARN_ON(!dsi_bus_is_locked(dsidev));
2751
2752 if (dsi->debug_write)
2753 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2754 channel,
2755 data_type, data & 0xff, (data >> 8) & 0xff);
2756
2757 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
2758
2759 if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
2760 DSSERR("ERROR FIFO FULL, aborting transfer\n");
2761 return -EINVAL;
2762 }
2763
2764 data_id = data_type | dsi->vc[channel].vc_id << 6;
2765
2766 r = (data_id << 0) | (data << 8) | (ecc << 24);
2767
2768 dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
2769
2770 return 0;
2771 }
2772
dsi_vc_send_null(struct omap_dss_device * dssdev,int channel)2773 static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
2774 {
2775 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2776
2777 return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
2778 0, 0);
2779 }
2780
dsi_vc_write_nosync_common(struct platform_device * dsidev,int channel,u8 * data,int len,enum dss_dsi_content_type type)2781 static int dsi_vc_write_nosync_common(struct platform_device *dsidev,
2782 int channel, u8 *data, int len, enum dss_dsi_content_type type)
2783 {
2784 int r;
2785
2786 if (len == 0) {
2787 BUG_ON(type == DSS_DSI_CONTENT_DCS);
2788 r = dsi_vc_send_short(dsidev, channel,
2789 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
2790 } else if (len == 1) {
2791 r = dsi_vc_send_short(dsidev, channel,
2792 type == DSS_DSI_CONTENT_GENERIC ?
2793 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
2794 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
2795 } else if (len == 2) {
2796 r = dsi_vc_send_short(dsidev, channel,
2797 type == DSS_DSI_CONTENT_GENERIC ?
2798 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
2799 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
2800 data[0] | (data[1] << 8), 0);
2801 } else {
2802 r = dsi_vc_send_long(dsidev, channel,
2803 type == DSS_DSI_CONTENT_GENERIC ?
2804 MIPI_DSI_GENERIC_LONG_WRITE :
2805 MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
2806 }
2807
2808 return r;
2809 }
2810
dsi_vc_dcs_write_nosync(struct omap_dss_device * dssdev,int channel,u8 * data,int len)2811 static int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
2812 u8 *data, int len)
2813 {
2814 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2815
2816 return dsi_vc_write_nosync_common(dsidev, channel, data, len,
2817 DSS_DSI_CONTENT_DCS);
2818 }
2819
dsi_vc_generic_write_nosync(struct omap_dss_device * dssdev,int channel,u8 * data,int len)2820 static int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
2821 u8 *data, int len)
2822 {
2823 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2824
2825 return dsi_vc_write_nosync_common(dsidev, channel, data, len,
2826 DSS_DSI_CONTENT_GENERIC);
2827 }
2828
dsi_vc_write_common(struct omap_dss_device * dssdev,int channel,u8 * data,int len,enum dss_dsi_content_type type)2829 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
2830 u8 *data, int len, enum dss_dsi_content_type type)
2831 {
2832 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2833 int r;
2834
2835 r = dsi_vc_write_nosync_common(dsidev, channel, data, len, type);
2836 if (r)
2837 goto err;
2838
2839 r = dsi_vc_send_bta_sync(dssdev, channel);
2840 if (r)
2841 goto err;
2842
2843 /* RX_FIFO_NOT_EMPTY */
2844 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2845 DSSERR("rx fifo not empty after write, dumping data:\n");
2846 dsi_vc_flush_receive_data(dsidev, channel);
2847 r = -EIO;
2848 goto err;
2849 }
2850
2851 return 0;
2852 err:
2853 DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
2854 channel, data[0], len);
2855 return r;
2856 }
2857
dsi_vc_dcs_write(struct omap_dss_device * dssdev,int channel,u8 * data,int len)2858 static int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
2859 int len)
2860 {
2861 return dsi_vc_write_common(dssdev, channel, data, len,
2862 DSS_DSI_CONTENT_DCS);
2863 }
2864
dsi_vc_generic_write(struct omap_dss_device * dssdev,int channel,u8 * data,int len)2865 static int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
2866 int len)
2867 {
2868 return dsi_vc_write_common(dssdev, channel, data, len,
2869 DSS_DSI_CONTENT_GENERIC);
2870 }
2871
dsi_vc_dcs_send_read_request(struct platform_device * dsidev,int channel,u8 dcs_cmd)2872 static int dsi_vc_dcs_send_read_request(struct platform_device *dsidev,
2873 int channel, u8 dcs_cmd)
2874 {
2875 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2876 int r;
2877
2878 if (dsi->debug_read)
2879 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
2880 channel, dcs_cmd);
2881
2882 r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
2883 if (r) {
2884 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
2885 " failed\n", channel, dcs_cmd);
2886 return r;
2887 }
2888
2889 return 0;
2890 }
2891
dsi_vc_generic_send_read_request(struct platform_device * dsidev,int channel,u8 * reqdata,int reqlen)2892 static int dsi_vc_generic_send_read_request(struct platform_device *dsidev,
2893 int channel, u8 *reqdata, int reqlen)
2894 {
2895 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2896 u16 data;
2897 u8 data_type;
2898 int r;
2899
2900 if (dsi->debug_read)
2901 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
2902 channel, reqlen);
2903
2904 if (reqlen == 0) {
2905 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
2906 data = 0;
2907 } else if (reqlen == 1) {
2908 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
2909 data = reqdata[0];
2910 } else if (reqlen == 2) {
2911 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
2912 data = reqdata[0] | (reqdata[1] << 8);
2913 } else {
2914 BUG();
2915 return -EINVAL;
2916 }
2917
2918 r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
2919 if (r) {
2920 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
2921 " failed\n", channel, reqlen);
2922 return r;
2923 }
2924
2925 return 0;
2926 }
2927
dsi_vc_read_rx_fifo(struct platform_device * dsidev,int channel,u8 * buf,int buflen,enum dss_dsi_content_type type)2928 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
2929 u8 *buf, int buflen, enum dss_dsi_content_type type)
2930 {
2931 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2932 u32 val;
2933 u8 dt;
2934 int r;
2935
2936 /* RX_FIFO_NOT_EMPTY */
2937 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
2938 DSSERR("RX fifo empty when trying to read.\n");
2939 r = -EIO;
2940 goto err;
2941 }
2942
2943 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2944 if (dsi->debug_read)
2945 DSSDBG("\theader: %08x\n", val);
2946 dt = FLD_GET(val, 5, 0);
2947 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2948 u16 err = FLD_GET(val, 23, 8);
2949 dsi_show_rx_ack_with_err(err);
2950 r = -EIO;
2951 goto err;
2952
2953 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
2954 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
2955 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
2956 u8 data = FLD_GET(val, 15, 8);
2957 if (dsi->debug_read)
2958 DSSDBG("\t%s short response, 1 byte: %02x\n",
2959 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
2960 "DCS", data);
2961
2962 if (buflen < 1) {
2963 r = -EIO;
2964 goto err;
2965 }
2966
2967 buf[0] = data;
2968
2969 return 1;
2970 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
2971 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
2972 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
2973 u16 data = FLD_GET(val, 23, 8);
2974 if (dsi->debug_read)
2975 DSSDBG("\t%s short response, 2 byte: %04x\n",
2976 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
2977 "DCS", data);
2978
2979 if (buflen < 2) {
2980 r = -EIO;
2981 goto err;
2982 }
2983
2984 buf[0] = data & 0xff;
2985 buf[1] = (data >> 8) & 0xff;
2986
2987 return 2;
2988 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
2989 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
2990 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
2991 int w;
2992 int len = FLD_GET(val, 23, 8);
2993 if (dsi->debug_read)
2994 DSSDBG("\t%s long response, len %d\n",
2995 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
2996 "DCS", len);
2997
2998 if (len > buflen) {
2999 r = -EIO;
3000 goto err;
3001 }
3002
3003 /* two byte checksum ends the packet, not included in len */
3004 for (w = 0; w < len + 2;) {
3005 int b;
3006 val = dsi_read_reg(dsidev,
3007 DSI_VC_SHORT_PACKET_HEADER(channel));
3008 if (dsi->debug_read)
3009 DSSDBG("\t\t%02x %02x %02x %02x\n",
3010 (val >> 0) & 0xff,
3011 (val >> 8) & 0xff,
3012 (val >> 16) & 0xff,
3013 (val >> 24) & 0xff);
3014
3015 for (b = 0; b < 4; ++b) {
3016 if (w < len)
3017 buf[w] = (val >> (b * 8)) & 0xff;
3018 /* we discard the 2 byte checksum */
3019 ++w;
3020 }
3021 }
3022
3023 return len;
3024 } else {
3025 DSSERR("\tunknown datatype 0x%02x\n", dt);
3026 r = -EIO;
3027 goto err;
3028 }
3029
3030 err:
3031 DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
3032 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3033
3034 return r;
3035 }
3036
dsi_vc_dcs_read(struct omap_dss_device * dssdev,int channel,u8 dcs_cmd,u8 * buf,int buflen)3037 static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3038 u8 *buf, int buflen)
3039 {
3040 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3041 int r;
3042
3043 r = dsi_vc_dcs_send_read_request(dsidev, channel, dcs_cmd);
3044 if (r)
3045 goto err;
3046
3047 r = dsi_vc_send_bta_sync(dssdev, channel);
3048 if (r)
3049 goto err;
3050
3051 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3052 DSS_DSI_CONTENT_DCS);
3053 if (r < 0)
3054 goto err;
3055
3056 if (r != buflen) {
3057 r = -EIO;
3058 goto err;
3059 }
3060
3061 return 0;
3062 err:
3063 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
3064 return r;
3065 }
3066
dsi_vc_generic_read(struct omap_dss_device * dssdev,int channel,u8 * reqdata,int reqlen,u8 * buf,int buflen)3067 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3068 u8 *reqdata, int reqlen, u8 *buf, int buflen)
3069 {
3070 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3071 int r;
3072
3073 r = dsi_vc_generic_send_read_request(dsidev, channel, reqdata, reqlen);
3074 if (r)
3075 return r;
3076
3077 r = dsi_vc_send_bta_sync(dssdev, channel);
3078 if (r)
3079 return r;
3080
3081 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3082 DSS_DSI_CONTENT_GENERIC);
3083 if (r < 0)
3084 return r;
3085
3086 if (r != buflen) {
3087 r = -EIO;
3088 return r;
3089 }
3090
3091 return 0;
3092 }
3093
dsi_vc_set_max_rx_packet_size(struct omap_dss_device * dssdev,int channel,u16 len)3094 static int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3095 u16 len)
3096 {
3097 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3098
3099 return dsi_vc_send_short(dsidev, channel,
3100 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3101 }
3102
dsi_enter_ulps(struct platform_device * dsidev)3103 static int dsi_enter_ulps(struct platform_device *dsidev)
3104 {
3105 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3106 DECLARE_COMPLETION_ONSTACK(completion);
3107 int r, i;
3108 unsigned mask;
3109
3110 DSSDBG("Entering ULPS");
3111
3112 WARN_ON(!dsi_bus_is_locked(dsidev));
3113
3114 WARN_ON(dsi->ulps_enabled);
3115
3116 if (dsi->ulps_enabled)
3117 return 0;
3118
3119 /* DDR_CLK_ALWAYS_ON */
3120 if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3121 dsi_if_enable(dsidev, 0);
3122 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
3123 dsi_if_enable(dsidev, 1);
3124 }
3125
3126 dsi_sync_vc(dsidev, 0);
3127 dsi_sync_vc(dsidev, 1);
3128 dsi_sync_vc(dsidev, 2);
3129 dsi_sync_vc(dsidev, 3);
3130
3131 dsi_force_tx_stop_mode_io(dsidev);
3132
3133 dsi_vc_enable(dsidev, 0, false);
3134 dsi_vc_enable(dsidev, 1, false);
3135 dsi_vc_enable(dsidev, 2, false);
3136 dsi_vc_enable(dsidev, 3, false);
3137
3138 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */
3139 DSSERR("HS busy when enabling ULPS\n");
3140 return -EIO;
3141 }
3142
3143 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */
3144 DSSERR("LP busy when enabling ULPS\n");
3145 return -EIO;
3146 }
3147
3148 r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3149 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3150 if (r)
3151 return r;
3152
3153 mask = 0;
3154
3155 for (i = 0; i < dsi->num_lanes_supported; ++i) {
3156 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
3157 continue;
3158 mask |= 1 << i;
3159 }
3160 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3161 /* LANEx_ULPS_SIG2 */
3162 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5);
3163
3164 /* flush posted write and wait for SCP interface to finish the write */
3165 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3166
3167 if (wait_for_completion_timeout(&completion,
3168 msecs_to_jiffies(1000)) == 0) {
3169 DSSERR("ULPS enable timeout\n");
3170 r = -EIO;
3171 goto err;
3172 }
3173
3174 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3175 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3176
3177 /* Reset LANEx_ULPS_SIG2 */
3178 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5);
3179
3180 /* flush posted write and wait for SCP interface to finish the write */
3181 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3182
3183 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3184
3185 dsi_if_enable(dsidev, false);
3186
3187 dsi->ulps_enabled = true;
3188
3189 return 0;
3190
3191 err:
3192 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3193 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3194 return r;
3195 }
3196
dsi_set_lp_rx_timeout(struct platform_device * dsidev,unsigned ticks,bool x4,bool x16)3197 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3198 unsigned ticks, bool x4, bool x16)
3199 {
3200 unsigned long fck;
3201 unsigned long total_ticks;
3202 u32 r;
3203
3204 BUG_ON(ticks > 0x1fff);
3205
3206 /* ticks in DSI_FCK */
3207 fck = dsi_fclk_rate(dsidev);
3208
3209 r = dsi_read_reg(dsidev, DSI_TIMING2);
3210 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
3211 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
3212 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
3213 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
3214 dsi_write_reg(dsidev, DSI_TIMING2, r);
3215
3216 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3217
3218 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3219 total_ticks,
3220 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3221 (total_ticks * 1000) / (fck / 1000 / 1000));
3222 }
3223
dsi_set_ta_timeout(struct platform_device * dsidev,unsigned ticks,bool x8,bool x16)3224 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3225 bool x8, bool x16)
3226 {
3227 unsigned long fck;
3228 unsigned long total_ticks;
3229 u32 r;
3230
3231 BUG_ON(ticks > 0x1fff);
3232
3233 /* ticks in DSI_FCK */
3234 fck = dsi_fclk_rate(dsidev);
3235
3236 r = dsi_read_reg(dsidev, DSI_TIMING1);
3237 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
3238 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
3239 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
3240 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
3241 dsi_write_reg(dsidev, DSI_TIMING1, r);
3242
3243 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3244
3245 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3246 total_ticks,
3247 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3248 (total_ticks * 1000) / (fck / 1000 / 1000));
3249 }
3250
dsi_set_stop_state_counter(struct platform_device * dsidev,unsigned ticks,bool x4,bool x16)3251 static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3252 unsigned ticks, bool x4, bool x16)
3253 {
3254 unsigned long fck;
3255 unsigned long total_ticks;
3256 u32 r;
3257
3258 BUG_ON(ticks > 0x1fff);
3259
3260 /* ticks in DSI_FCK */
3261 fck = dsi_fclk_rate(dsidev);
3262
3263 r = dsi_read_reg(dsidev, DSI_TIMING1);
3264 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
3265 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
3266 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
3267 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
3268 dsi_write_reg(dsidev, DSI_TIMING1, r);
3269
3270 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3271
3272 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3273 total_ticks,
3274 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3275 (total_ticks * 1000) / (fck / 1000 / 1000));
3276 }
3277
dsi_set_hs_tx_timeout(struct platform_device * dsidev,unsigned ticks,bool x4,bool x16)3278 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3279 unsigned ticks, bool x4, bool x16)
3280 {
3281 unsigned long fck;
3282 unsigned long total_ticks;
3283 u32 r;
3284
3285 BUG_ON(ticks > 0x1fff);
3286
3287 /* ticks in TxByteClkHS */
3288 fck = dsi_get_txbyteclkhs(dsidev);
3289
3290 r = dsi_read_reg(dsidev, DSI_TIMING2);
3291 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
3292 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
3293 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
3294 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
3295 dsi_write_reg(dsidev, DSI_TIMING2, r);
3296
3297 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3298
3299 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3300 total_ticks,
3301 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3302 (total_ticks * 1000) / (fck / 1000 / 1000));
3303 }
3304
dsi_config_vp_num_line_buffers(struct platform_device * dsidev)3305 static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev)
3306 {
3307 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3308 int num_line_buffers;
3309
3310 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3311 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3312 struct omap_video_timings *timings = &dsi->timings;
3313 /*
3314 * Don't use line buffers if width is greater than the video
3315 * port's line buffer size
3316 */
3317 if (dsi->line_buffer_size <= timings->x_res * bpp / 8)
3318 num_line_buffers = 0;
3319 else
3320 num_line_buffers = 2;
3321 } else {
3322 /* Use maximum number of line buffers in command mode */
3323 num_line_buffers = 2;
3324 }
3325
3326 /* LINE_BUFFER */
3327 REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
3328 }
3329
dsi_config_vp_sync_events(struct platform_device * dsidev)3330 static void dsi_config_vp_sync_events(struct platform_device *dsidev)
3331 {
3332 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3333 bool sync_end;
3334 u32 r;
3335
3336 if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE)
3337 sync_end = true;
3338 else
3339 sync_end = false;
3340
3341 r = dsi_read_reg(dsidev, DSI_CTRL);
3342 r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */
3343 r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */
3344 r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */
3345 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */
3346 r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */
3347 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */
3348 r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */
3349 dsi_write_reg(dsidev, DSI_CTRL, r);
3350 }
3351
dsi_config_blanking_modes(struct platform_device * dsidev)3352 static void dsi_config_blanking_modes(struct platform_device *dsidev)
3353 {
3354 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3355 int blanking_mode = dsi->vm_timings.blanking_mode;
3356 int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode;
3357 int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode;
3358 int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode;
3359 u32 r;
3360
3361 /*
3362 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3363 * 1 = Long blanking packets are sent in corresponding blanking periods
3364 */
3365 r = dsi_read_reg(dsidev, DSI_CTRL);
3366 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */
3367 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */
3368 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */
3369 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */
3370 dsi_write_reg(dsidev, DSI_CTRL, r);
3371 }
3372
3373 /*
3374 * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3
3375 * results in maximum transition time for data and clock lanes to enter and
3376 * exit HS mode. Hence, this is the scenario where the least amount of command
3377 * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS
3378 * clock cycles that can be used to interleave command mode data in HS so that
3379 * all scenarios are satisfied.
3380 */
dsi_compute_interleave_hs(int blank,bool ddr_alwon,int enter_hs,int exit_hs,int exiths_clk,int ddr_pre,int ddr_post)3381 static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs,
3382 int exit_hs, int exiths_clk, int ddr_pre, int ddr_post)
3383 {
3384 int transition;
3385
3386 /*
3387 * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition
3388 * time of data lanes only, if it isn't set, we need to consider HS
3389 * transition time of both data and clock lanes. HS transition time
3390 * of Scenario 3 is considered.
3391 */
3392 if (ddr_alwon) {
3393 transition = enter_hs + exit_hs + max(enter_hs, 2) + 1;
3394 } else {
3395 int trans1, trans2;
3396 trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1;
3397 trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre +
3398 enter_hs + 1;
3399 transition = max(trans1, trans2);
3400 }
3401
3402 return blank > transition ? blank - transition : 0;
3403 }
3404
3405 /*
3406 * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1
3407 * results in maximum transition time for data lanes to enter and exit LP mode.
3408 * Hence, this is the scenario where the least amount of command mode data can
3409 * be interleaved. We program the minimum amount of bytes that can be
3410 * interleaved in LP so that all scenarios are satisfied.
3411 */
dsi_compute_interleave_lp(int blank,int enter_hs,int exit_hs,int lp_clk_div,int tdsi_fclk)3412 static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs,
3413 int lp_clk_div, int tdsi_fclk)
3414 {
3415 int trans_lp; /* time required for a LP transition, in TXBYTECLKHS */
3416 int tlp_avail; /* time left for interleaving commands, in CLKIN4DDR */
3417 int ttxclkesc; /* period of LP transmit escape clock, in CLKIN4DDR */
3418 int thsbyte_clk = 16; /* Period of TXBYTECLKHS clock, in CLKIN4DDR */
3419 int lp_inter; /* cmd mode data that can be interleaved, in bytes */
3420
3421 /* maximum LP transition time according to Scenario 1 */
3422 trans_lp = exit_hs + max(enter_hs, 2) + 1;
3423
3424 /* CLKIN4DDR = 16 * TXBYTECLKHS */
3425 tlp_avail = thsbyte_clk * (blank - trans_lp);
3426
3427 ttxclkesc = tdsi_fclk * lp_clk_div;
3428
3429 lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc -
3430 26) / 16;
3431
3432 return max(lp_inter, 0);
3433 }
3434
dsi_config_cmd_mode_interleaving(struct platform_device * dsidev)3435 static void dsi_config_cmd_mode_interleaving(struct platform_device *dsidev)
3436 {
3437 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3438 int blanking_mode;
3439 int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode;
3440 int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div;
3441 int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat;
3442 int tclk_trail, ths_exit, exiths_clk;
3443 bool ddr_alwon;
3444 struct omap_video_timings *timings = &dsi->timings;
3445 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3446 int ndl = dsi->num_lanes_used - 1;
3447 int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1;
3448 int hsa_interleave_hs = 0, hsa_interleave_lp = 0;
3449 int hfp_interleave_hs = 0, hfp_interleave_lp = 0;
3450 int hbp_interleave_hs = 0, hbp_interleave_lp = 0;
3451 int bl_interleave_hs = 0, bl_interleave_lp = 0;
3452 u32 r;
3453
3454 r = dsi_read_reg(dsidev, DSI_CTRL);
3455 blanking_mode = FLD_GET(r, 20, 20);
3456 hfp_blanking_mode = FLD_GET(r, 21, 21);
3457 hbp_blanking_mode = FLD_GET(r, 22, 22);
3458 hsa_blanking_mode = FLD_GET(r, 23, 23);
3459
3460 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3461 hbp = FLD_GET(r, 11, 0);
3462 hfp = FLD_GET(r, 23, 12);
3463 hsa = FLD_GET(r, 31, 24);
3464
3465 r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3466 ddr_clk_post = FLD_GET(r, 7, 0);
3467 ddr_clk_pre = FLD_GET(r, 15, 8);
3468
3469 r = dsi_read_reg(dsidev, DSI_VM_TIMING7);
3470 exit_hs_mode_lat = FLD_GET(r, 15, 0);
3471 enter_hs_mode_lat = FLD_GET(r, 31, 16);
3472
3473 r = dsi_read_reg(dsidev, DSI_CLK_CTRL);
3474 lp_clk_div = FLD_GET(r, 12, 0);
3475 ddr_alwon = FLD_GET(r, 13, 13);
3476
3477 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3478 ths_exit = FLD_GET(r, 7, 0);
3479
3480 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3481 tclk_trail = FLD_GET(r, 15, 8);
3482
3483 exiths_clk = ths_exit + tclk_trail;
3484
3485 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3486 bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl);
3487
3488 if (!hsa_blanking_mode) {
3489 hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon,
3490 enter_hs_mode_lat, exit_hs_mode_lat,
3491 exiths_clk, ddr_clk_pre, ddr_clk_post);
3492 hsa_interleave_lp = dsi_compute_interleave_lp(hsa,
3493 enter_hs_mode_lat, exit_hs_mode_lat,
3494 lp_clk_div, dsi_fclk_hsdiv);
3495 }
3496
3497 if (!hfp_blanking_mode) {
3498 hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon,
3499 enter_hs_mode_lat, exit_hs_mode_lat,
3500 exiths_clk, ddr_clk_pre, ddr_clk_post);
3501 hfp_interleave_lp = dsi_compute_interleave_lp(hfp,
3502 enter_hs_mode_lat, exit_hs_mode_lat,
3503 lp_clk_div, dsi_fclk_hsdiv);
3504 }
3505
3506 if (!hbp_blanking_mode) {
3507 hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon,
3508 enter_hs_mode_lat, exit_hs_mode_lat,
3509 exiths_clk, ddr_clk_pre, ddr_clk_post);
3510
3511 hbp_interleave_lp = dsi_compute_interleave_lp(hbp,
3512 enter_hs_mode_lat, exit_hs_mode_lat,
3513 lp_clk_div, dsi_fclk_hsdiv);
3514 }
3515
3516 if (!blanking_mode) {
3517 bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon,
3518 enter_hs_mode_lat, exit_hs_mode_lat,
3519 exiths_clk, ddr_clk_pre, ddr_clk_post);
3520
3521 bl_interleave_lp = dsi_compute_interleave_lp(bllp,
3522 enter_hs_mode_lat, exit_hs_mode_lat,
3523 lp_clk_div, dsi_fclk_hsdiv);
3524 }
3525
3526 DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3527 hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs,
3528 bl_interleave_hs);
3529
3530 DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3531 hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp,
3532 bl_interleave_lp);
3533
3534 r = dsi_read_reg(dsidev, DSI_VM_TIMING4);
3535 r = FLD_MOD(r, hsa_interleave_hs, 23, 16);
3536 r = FLD_MOD(r, hfp_interleave_hs, 15, 8);
3537 r = FLD_MOD(r, hbp_interleave_hs, 7, 0);
3538 dsi_write_reg(dsidev, DSI_VM_TIMING4, r);
3539
3540 r = dsi_read_reg(dsidev, DSI_VM_TIMING5);
3541 r = FLD_MOD(r, hsa_interleave_lp, 23, 16);
3542 r = FLD_MOD(r, hfp_interleave_lp, 15, 8);
3543 r = FLD_MOD(r, hbp_interleave_lp, 7, 0);
3544 dsi_write_reg(dsidev, DSI_VM_TIMING5, r);
3545
3546 r = dsi_read_reg(dsidev, DSI_VM_TIMING6);
3547 r = FLD_MOD(r, bl_interleave_hs, 31, 15);
3548 r = FLD_MOD(r, bl_interleave_lp, 16, 0);
3549 dsi_write_reg(dsidev, DSI_VM_TIMING6, r);
3550 }
3551
dsi_proto_config(struct platform_device * dsidev)3552 static int dsi_proto_config(struct platform_device *dsidev)
3553 {
3554 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3555 u32 r;
3556 int buswidth = 0;
3557
3558 dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
3559 DSI_FIFO_SIZE_32,
3560 DSI_FIFO_SIZE_32,
3561 DSI_FIFO_SIZE_32);
3562
3563 dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
3564 DSI_FIFO_SIZE_32,
3565 DSI_FIFO_SIZE_32,
3566 DSI_FIFO_SIZE_32);
3567
3568 /* XXX what values for the timeouts? */
3569 dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
3570 dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
3571 dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
3572 dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
3573
3574 switch (dsi_get_pixel_size(dsi->pix_fmt)) {
3575 case 16:
3576 buswidth = 0;
3577 break;
3578 case 18:
3579 buswidth = 1;
3580 break;
3581 case 24:
3582 buswidth = 2;
3583 break;
3584 default:
3585 BUG();
3586 return -EINVAL;
3587 }
3588
3589 r = dsi_read_reg(dsidev, DSI_CTRL);
3590 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
3591 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
3592 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
3593 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
3594 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
3595 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
3596 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
3597 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
3598 if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
3599 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
3600 /* DCS_CMD_CODE, 1=start, 0=continue */
3601 r = FLD_MOD(r, 0, 25, 25);
3602 }
3603
3604 dsi_write_reg(dsidev, DSI_CTRL, r);
3605
3606 dsi_config_vp_num_line_buffers(dsidev);
3607
3608 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3609 dsi_config_vp_sync_events(dsidev);
3610 dsi_config_blanking_modes(dsidev);
3611 dsi_config_cmd_mode_interleaving(dsidev);
3612 }
3613
3614 dsi_vc_initial_config(dsidev, 0);
3615 dsi_vc_initial_config(dsidev, 1);
3616 dsi_vc_initial_config(dsidev, 2);
3617 dsi_vc_initial_config(dsidev, 3);
3618
3619 return 0;
3620 }
3621
dsi_proto_timings(struct platform_device * dsidev)3622 static void dsi_proto_timings(struct platform_device *dsidev)
3623 {
3624 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3625 unsigned tlpx, tclk_zero, tclk_prepare;
3626 unsigned tclk_pre, tclk_post;
3627 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
3628 unsigned ths_trail, ths_exit;
3629 unsigned ddr_clk_pre, ddr_clk_post;
3630 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
3631 unsigned ths_eot;
3632 int ndl = dsi->num_lanes_used - 1;
3633 u32 r;
3634
3635 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3636 ths_prepare = FLD_GET(r, 31, 24);
3637 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3638 ths_zero = ths_prepare_ths_zero - ths_prepare;
3639 ths_trail = FLD_GET(r, 15, 8);
3640 ths_exit = FLD_GET(r, 7, 0);
3641
3642 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3643 tlpx = FLD_GET(r, 20, 16) * 2;
3644 tclk_zero = FLD_GET(r, 7, 0);
3645
3646 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
3647 tclk_prepare = FLD_GET(r, 7, 0);
3648
3649 /* min 8*UI */
3650 tclk_pre = 20;
3651 /* min 60ns + 52*UI */
3652 tclk_post = ns2ddr(dsidev, 60) + 26;
3653
3654 ths_eot = DIV_ROUND_UP(4, ndl);
3655
3656 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3657 4);
3658 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3659
3660 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3661 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3662
3663 r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3664 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3665 r = FLD_MOD(r, ddr_clk_post, 7, 0);
3666 dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
3667
3668 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3669 ddr_clk_pre,
3670 ddr_clk_post);
3671
3672 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3673 DIV_ROUND_UP(ths_prepare, 4) +
3674 DIV_ROUND_UP(ths_zero + 3, 4);
3675
3676 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3677
3678 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3679 FLD_VAL(exit_hs_mode_lat, 15, 0);
3680 dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
3681
3682 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3683 enter_hs_mode_lat, exit_hs_mode_lat);
3684
3685 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3686 /* TODO: Implement a video mode check_timings function */
3687 int hsa = dsi->vm_timings.hsa;
3688 int hfp = dsi->vm_timings.hfp;
3689 int hbp = dsi->vm_timings.hbp;
3690 int vsa = dsi->vm_timings.vsa;
3691 int vfp = dsi->vm_timings.vfp;
3692 int vbp = dsi->vm_timings.vbp;
3693 int window_sync = dsi->vm_timings.window_sync;
3694 bool hsync_end;
3695 struct omap_video_timings *timings = &dsi->timings;
3696 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3697 int tl, t_he, width_bytes;
3698
3699 hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE;
3700 t_he = hsync_end ?
3701 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
3702
3703 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3704
3705 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
3706 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
3707 DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
3708
3709 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
3710 hfp, hsync_end ? hsa : 0, tl);
3711 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
3712 vsa, timings->y_res);
3713
3714 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3715 r = FLD_MOD(r, hbp, 11, 0); /* HBP */
3716 r = FLD_MOD(r, hfp, 23, 12); /* HFP */
3717 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */
3718 dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
3719
3720 r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
3721 r = FLD_MOD(r, vbp, 7, 0); /* VBP */
3722 r = FLD_MOD(r, vfp, 15, 8); /* VFP */
3723 r = FLD_MOD(r, vsa, 23, 16); /* VSA */
3724 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */
3725 dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
3726
3727 r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
3728 r = FLD_MOD(r, timings->y_res, 14, 0); /* VACT */
3729 r = FLD_MOD(r, tl, 31, 16); /* TL */
3730 dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
3731 }
3732 }
3733
dsi_configure_pins(struct omap_dss_device * dssdev,const struct omap_dsi_pin_config * pin_cfg)3734 static int dsi_configure_pins(struct omap_dss_device *dssdev,
3735 const struct omap_dsi_pin_config *pin_cfg)
3736 {
3737 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3738 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3739 int num_pins;
3740 const int *pins;
3741 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
3742 int num_lanes;
3743 int i;
3744
3745 static const enum dsi_lane_function functions[] = {
3746 DSI_LANE_CLK,
3747 DSI_LANE_DATA1,
3748 DSI_LANE_DATA2,
3749 DSI_LANE_DATA3,
3750 DSI_LANE_DATA4,
3751 };
3752
3753 num_pins = pin_cfg->num_pins;
3754 pins = pin_cfg->pins;
3755
3756 if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2
3757 || num_pins % 2 != 0)
3758 return -EINVAL;
3759
3760 for (i = 0; i < DSI_MAX_NR_LANES; ++i)
3761 lanes[i].function = DSI_LANE_UNUSED;
3762
3763 num_lanes = 0;
3764
3765 for (i = 0; i < num_pins; i += 2) {
3766 u8 lane, pol;
3767 int dx, dy;
3768
3769 dx = pins[i];
3770 dy = pins[i + 1];
3771
3772 if (dx < 0 || dx >= dsi->num_lanes_supported * 2)
3773 return -EINVAL;
3774
3775 if (dy < 0 || dy >= dsi->num_lanes_supported * 2)
3776 return -EINVAL;
3777
3778 if (dx & 1) {
3779 if (dy != dx - 1)
3780 return -EINVAL;
3781 pol = 1;
3782 } else {
3783 if (dy != dx + 1)
3784 return -EINVAL;
3785 pol = 0;
3786 }
3787
3788 lane = dx / 2;
3789
3790 lanes[lane].function = functions[i / 2];
3791 lanes[lane].polarity = pol;
3792 num_lanes++;
3793 }
3794
3795 memcpy(dsi->lanes, lanes, sizeof(dsi->lanes));
3796 dsi->num_lanes_used = num_lanes;
3797
3798 return 0;
3799 }
3800
dsi_enable_video_output(struct omap_dss_device * dssdev,int channel)3801 static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
3802 {
3803 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3804 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3805 struct omap_overlay_manager *mgr = dsi->output.manager;
3806 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3807 struct omap_dss_device *out = &dsi->output;
3808 u8 data_type;
3809 u16 word_count;
3810 int r;
3811
3812 if (out->manager == NULL) {
3813 DSSERR("failed to enable display: no output/manager\n");
3814 return -ENODEV;
3815 }
3816
3817 r = dsi_display_init_dispc(dsidev, mgr);
3818 if (r)
3819 goto err_init_dispc;
3820
3821 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3822 switch (dsi->pix_fmt) {
3823 case OMAP_DSS_DSI_FMT_RGB888:
3824 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
3825 break;
3826 case OMAP_DSS_DSI_FMT_RGB666:
3827 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
3828 break;
3829 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
3830 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
3831 break;
3832 case OMAP_DSS_DSI_FMT_RGB565:
3833 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
3834 break;
3835 default:
3836 r = -EINVAL;
3837 goto err_pix_fmt;
3838 }
3839
3840 dsi_if_enable(dsidev, false);
3841 dsi_vc_enable(dsidev, channel, false);
3842
3843 /* MODE, 1 = video mode */
3844 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
3845
3846 word_count = DIV_ROUND_UP(dsi->timings.x_res * bpp, 8);
3847
3848 dsi_vc_write_long_header(dsidev, channel, data_type,
3849 word_count, 0);
3850
3851 dsi_vc_enable(dsidev, channel, true);
3852 dsi_if_enable(dsidev, true);
3853 }
3854
3855 r = dss_mgr_enable(mgr);
3856 if (r)
3857 goto err_mgr_enable;
3858
3859 return 0;
3860
3861 err_mgr_enable:
3862 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3863 dsi_if_enable(dsidev, false);
3864 dsi_vc_enable(dsidev, channel, false);
3865 }
3866 err_pix_fmt:
3867 dsi_display_uninit_dispc(dsidev, mgr);
3868 err_init_dispc:
3869 return r;
3870 }
3871
dsi_disable_video_output(struct omap_dss_device * dssdev,int channel)3872 static void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel)
3873 {
3874 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3875 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3876 struct omap_overlay_manager *mgr = dsi->output.manager;
3877
3878 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3879 dsi_if_enable(dsidev, false);
3880 dsi_vc_enable(dsidev, channel, false);
3881
3882 /* MODE, 0 = command mode */
3883 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);
3884
3885 dsi_vc_enable(dsidev, channel, true);
3886 dsi_if_enable(dsidev, true);
3887 }
3888
3889 dss_mgr_disable(mgr);
3890
3891 dsi_display_uninit_dispc(dsidev, mgr);
3892 }
3893
dsi_update_screen_dispc(struct platform_device * dsidev)3894 static void dsi_update_screen_dispc(struct platform_device *dsidev)
3895 {
3896 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3897 struct omap_overlay_manager *mgr = dsi->output.manager;
3898 unsigned bytespp;
3899 unsigned bytespl;
3900 unsigned bytespf;
3901 unsigned total_len;
3902 unsigned packet_payload;
3903 unsigned packet_len;
3904 u32 l;
3905 int r;
3906 const unsigned channel = dsi->update_channel;
3907 const unsigned line_buf_size = dsi->line_buffer_size;
3908 u16 w = dsi->timings.x_res;
3909 u16 h = dsi->timings.y_res;
3910
3911 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
3912
3913 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
3914
3915 bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8;
3916 bytespl = w * bytespp;
3917 bytespf = bytespl * h;
3918
3919 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
3920 * number of lines in a packet. See errata about VP_CLK_RATIO */
3921
3922 if (bytespf < line_buf_size)
3923 packet_payload = bytespf;
3924 else
3925 packet_payload = (line_buf_size) / bytespl * bytespl;
3926
3927 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
3928 total_len = (bytespf / packet_payload) * packet_len;
3929
3930 if (bytespf % packet_payload)
3931 total_len += (bytespf % packet_payload) + 1;
3932
3933 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
3934 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
3935
3936 dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
3937 packet_len, 0);
3938
3939 if (dsi->te_enabled)
3940 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
3941 else
3942 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
3943 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
3944
3945 /* We put SIDLEMODE to no-idle for the duration of the transfer,
3946 * because DSS interrupts are not capable of waking up the CPU and the
3947 * framedone interrupt could be delayed for quite a long time. I think
3948 * the same goes for any DSS interrupts, but for some reason I have not
3949 * seen the problem anywhere else than here.
3950 */
3951 dispc_disable_sidle();
3952
3953 dsi_perf_mark_start(dsidev);
3954
3955 r = schedule_delayed_work(&dsi->framedone_timeout_work,
3956 msecs_to_jiffies(250));
3957 BUG_ON(r == 0);
3958
3959 dss_mgr_set_timings(mgr, &dsi->timings);
3960
3961 dss_mgr_start_update(mgr);
3962
3963 if (dsi->te_enabled) {
3964 /* disable LP_RX_TO, so that we can receive TE. Time to wait
3965 * for TE is longer than the timer allows */
3966 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
3967
3968 dsi_vc_send_bta(dsidev, channel);
3969
3970 #ifdef DSI_CATCH_MISSING_TE
3971 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
3972 #endif
3973 }
3974 }
3975
3976 #ifdef DSI_CATCH_MISSING_TE
dsi_te_timeout(struct timer_list * unused)3977 static void dsi_te_timeout(struct timer_list *unused)
3978 {
3979 DSSERR("TE not received for 250ms!\n");
3980 }
3981 #endif
3982
dsi_handle_framedone(struct platform_device * dsidev,int error)3983 static void dsi_handle_framedone(struct platform_device *dsidev, int error)
3984 {
3985 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3986
3987 /* SIDLEMODE back to smart-idle */
3988 dispc_enable_sidle();
3989
3990 if (dsi->te_enabled) {
3991 /* enable LP_RX_TO again after the TE */
3992 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
3993 }
3994
3995 dsi->framedone_callback(error, dsi->framedone_data);
3996
3997 if (!error)
3998 dsi_perf_show(dsidev, "DISPC");
3999 }
4000
dsi_framedone_timeout_work_callback(struct work_struct * work)4001 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
4002 {
4003 struct dsi_data *dsi = container_of(work, struct dsi_data,
4004 framedone_timeout_work.work);
4005 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4006 * 250ms which would conflict with this timeout work. What should be
4007 * done is first cancel the transfer on the HW, and then cancel the
4008 * possibly scheduled framedone work. However, cancelling the transfer
4009 * on the HW is buggy, and would probably require resetting the whole
4010 * DSI */
4011
4012 DSSERR("Framedone not received for 250ms!\n");
4013
4014 dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
4015 }
4016
dsi_framedone_irq_callback(void * data)4017 static void dsi_framedone_irq_callback(void *data)
4018 {
4019 struct platform_device *dsidev = (struct platform_device *) data;
4020 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4021
4022 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4023 * turns itself off. However, DSI still has the pixels in its buffers,
4024 * and is sending the data.
4025 */
4026
4027 cancel_delayed_work(&dsi->framedone_timeout_work);
4028
4029 dsi_handle_framedone(dsidev, 0);
4030 }
4031
dsi_update(struct omap_dss_device * dssdev,int channel,void (* callback)(int,void *),void * data)4032 static int dsi_update(struct omap_dss_device *dssdev, int channel,
4033 void (*callback)(int, void *), void *data)
4034 {
4035 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4036 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4037
4038 dsi_perf_mark_setup(dsidev);
4039
4040 dsi->update_channel = channel;
4041
4042 dsi->framedone_callback = callback;
4043 dsi->framedone_data = data;
4044
4045 #ifdef DSI_PERF_MEASURE
4046 dsi->update_bytes = dsi->timings.x_res * dsi->timings.y_res *
4047 dsi_get_pixel_size(dsi->pix_fmt) / 8;
4048 #endif
4049 dsi_update_screen_dispc(dsidev);
4050
4051 return 0;
4052 }
4053
4054 /* Display funcs */
4055
dsi_configure_dispc_clocks(struct platform_device * dsidev)4056 static int dsi_configure_dispc_clocks(struct platform_device *dsidev)
4057 {
4058 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4059 struct dispc_clock_info dispc_cinfo;
4060 int r;
4061 unsigned long fck;
4062
4063 fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
4064
4065 dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div;
4066 dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div;
4067
4068 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
4069 if (r) {
4070 DSSERR("Failed to calc dispc clocks\n");
4071 return r;
4072 }
4073
4074 dsi->mgr_config.clock_info = dispc_cinfo;
4075
4076 return 0;
4077 }
4078
dsi_display_init_dispc(struct platform_device * dsidev,struct omap_overlay_manager * mgr)4079 static int dsi_display_init_dispc(struct platform_device *dsidev,
4080 struct omap_overlay_manager *mgr)
4081 {
4082 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4083 int r;
4084
4085 dss_select_lcd_clk_source(mgr->id, dsi->module_id == 0 ?
4086 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
4087 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC);
4088
4089 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) {
4090 r = dss_mgr_register_framedone_handler(mgr,
4091 dsi_framedone_irq_callback, dsidev);
4092 if (r) {
4093 DSSERR("can't register FRAMEDONE handler\n");
4094 goto err;
4095 }
4096
4097 dsi->mgr_config.stallmode = true;
4098 dsi->mgr_config.fifohandcheck = true;
4099 } else {
4100 dsi->mgr_config.stallmode = false;
4101 dsi->mgr_config.fifohandcheck = false;
4102 }
4103
4104 /*
4105 * override interlace, logic level and edge related parameters in
4106 * omap_video_timings with default values
4107 */
4108 dsi->timings.interlace = false;
4109 dsi->timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4110 dsi->timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4111 dsi->timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
4112 dsi->timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH;
4113 dsi->timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE;
4114
4115 dss_mgr_set_timings(mgr, &dsi->timings);
4116
4117 r = dsi_configure_dispc_clocks(dsidev);
4118 if (r)
4119 goto err1;
4120
4121 dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
4122 dsi->mgr_config.video_port_width =
4123 dsi_get_pixel_size(dsi->pix_fmt);
4124 dsi->mgr_config.lcden_sig_polarity = 0;
4125
4126 dss_mgr_set_lcd_config(mgr, &dsi->mgr_config);
4127
4128 return 0;
4129 err1:
4130 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4131 dss_mgr_unregister_framedone_handler(mgr,
4132 dsi_framedone_irq_callback, dsidev);
4133 err:
4134 dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
4135 return r;
4136 }
4137
dsi_display_uninit_dispc(struct platform_device * dsidev,struct omap_overlay_manager * mgr)4138 static void dsi_display_uninit_dispc(struct platform_device *dsidev,
4139 struct omap_overlay_manager *mgr)
4140 {
4141 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4142
4143 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4144 dss_mgr_unregister_framedone_handler(mgr,
4145 dsi_framedone_irq_callback, dsidev);
4146
4147 dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
4148 }
4149
dsi_configure_dsi_clocks(struct platform_device * dsidev)4150 static int dsi_configure_dsi_clocks(struct platform_device *dsidev)
4151 {
4152 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4153 struct dss_pll_clock_info cinfo;
4154 int r;
4155
4156 cinfo = dsi->user_dsi_cinfo;
4157
4158 r = dss_pll_set_config(&dsi->pll, &cinfo);
4159 if (r) {
4160 DSSERR("Failed to set dsi clocks\n");
4161 return r;
4162 }
4163
4164 return 0;
4165 }
4166
dsi_display_init_dsi(struct platform_device * dsidev)4167 static int dsi_display_init_dsi(struct platform_device *dsidev)
4168 {
4169 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4170 int r;
4171
4172 r = dss_pll_enable(&dsi->pll);
4173 if (r)
4174 goto err0;
4175
4176 r = dsi_configure_dsi_clocks(dsidev);
4177 if (r)
4178 goto err1;
4179
4180 dss_select_dsi_clk_source(dsi->module_id, dsi->module_id == 0 ?
4181 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
4182 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI);
4183
4184 DSSDBG("PLL OK\n");
4185
4186 r = dsi_cio_init(dsidev);
4187 if (r)
4188 goto err2;
4189
4190 _dsi_print_reset_status(dsidev);
4191
4192 dsi_proto_timings(dsidev);
4193 dsi_set_lp_clk_divisor(dsidev);
4194
4195 if (1)
4196 _dsi_print_reset_status(dsidev);
4197
4198 r = dsi_proto_config(dsidev);
4199 if (r)
4200 goto err3;
4201
4202 /* enable interface */
4203 dsi_vc_enable(dsidev, 0, 1);
4204 dsi_vc_enable(dsidev, 1, 1);
4205 dsi_vc_enable(dsidev, 2, 1);
4206 dsi_vc_enable(dsidev, 3, 1);
4207 dsi_if_enable(dsidev, 1);
4208 dsi_force_tx_stop_mode_io(dsidev);
4209
4210 return 0;
4211 err3:
4212 dsi_cio_uninit(dsidev);
4213 err2:
4214 dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4215 err1:
4216 dss_pll_disable(&dsi->pll);
4217 err0:
4218 return r;
4219 }
4220
dsi_display_uninit_dsi(struct platform_device * dsidev,bool disconnect_lanes,bool enter_ulps)4221 static void dsi_display_uninit_dsi(struct platform_device *dsidev,
4222 bool disconnect_lanes, bool enter_ulps)
4223 {
4224 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4225
4226 if (enter_ulps && !dsi->ulps_enabled)
4227 dsi_enter_ulps(dsidev);
4228
4229 /* disable interface */
4230 dsi_if_enable(dsidev, 0);
4231 dsi_vc_enable(dsidev, 0, 0);
4232 dsi_vc_enable(dsidev, 1, 0);
4233 dsi_vc_enable(dsidev, 2, 0);
4234 dsi_vc_enable(dsidev, 3, 0);
4235
4236 dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4237 dsi_cio_uninit(dsidev);
4238 dsi_pll_uninit(dsidev, disconnect_lanes);
4239 }
4240
dsi_display_enable(struct omap_dss_device * dssdev)4241 static int dsi_display_enable(struct omap_dss_device *dssdev)
4242 {
4243 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4244 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4245 int r = 0;
4246
4247 DSSDBG("dsi_display_enable\n");
4248
4249 WARN_ON(!dsi_bus_is_locked(dsidev));
4250
4251 mutex_lock(&dsi->lock);
4252
4253 r = dsi_runtime_get(dsidev);
4254 if (r)
4255 goto err_get_dsi;
4256
4257 _dsi_initialize_irq(dsidev);
4258
4259 r = dsi_display_init_dsi(dsidev);
4260 if (r)
4261 goto err_init_dsi;
4262
4263 mutex_unlock(&dsi->lock);
4264
4265 return 0;
4266
4267 err_init_dsi:
4268 dsi_runtime_put(dsidev);
4269 err_get_dsi:
4270 mutex_unlock(&dsi->lock);
4271 DSSDBG("dsi_display_enable FAILED\n");
4272 return r;
4273 }
4274
dsi_display_disable(struct omap_dss_device * dssdev,bool disconnect_lanes,bool enter_ulps)4275 static void dsi_display_disable(struct omap_dss_device *dssdev,
4276 bool disconnect_lanes, bool enter_ulps)
4277 {
4278 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4279 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4280
4281 DSSDBG("dsi_display_disable\n");
4282
4283 WARN_ON(!dsi_bus_is_locked(dsidev));
4284
4285 mutex_lock(&dsi->lock);
4286
4287 dsi_sync_vc(dsidev, 0);
4288 dsi_sync_vc(dsidev, 1);
4289 dsi_sync_vc(dsidev, 2);
4290 dsi_sync_vc(dsidev, 3);
4291
4292 dsi_display_uninit_dsi(dsidev, disconnect_lanes, enter_ulps);
4293
4294 dsi_runtime_put(dsidev);
4295
4296 mutex_unlock(&dsi->lock);
4297 }
4298
dsi_enable_te(struct omap_dss_device * dssdev,bool enable)4299 static int dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4300 {
4301 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4302 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4303
4304 dsi->te_enabled = enable;
4305 return 0;
4306 }
4307
4308 #ifdef PRINT_VERBOSE_VM_TIMINGS
print_dsi_vm(const char * str,const struct omap_dss_dsi_videomode_timings * t)4309 static void print_dsi_vm(const char *str,
4310 const struct omap_dss_dsi_videomode_timings *t)
4311 {
4312 unsigned long byteclk = t->hsclk / 4;
4313 int bl, wc, pps, tot;
4314
4315 wc = DIV_ROUND_UP(t->hact * t->bitspp, 8);
4316 pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */
4317 bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp;
4318 tot = bl + pps;
4319
4320 #define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk))
4321
4322 pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, "
4323 "%u/%u/%u/%u/%u/%u = %u + %u = %u\n",
4324 str,
4325 byteclk,
4326 t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp,
4327 bl, pps, tot,
4328 TO_DSI_T(t->hss),
4329 TO_DSI_T(t->hsa),
4330 TO_DSI_T(t->hse),
4331 TO_DSI_T(t->hbp),
4332 TO_DSI_T(pps),
4333 TO_DSI_T(t->hfp),
4334
4335 TO_DSI_T(bl),
4336 TO_DSI_T(pps),
4337
4338 TO_DSI_T(tot));
4339 #undef TO_DSI_T
4340 }
4341
print_dispc_vm(const char * str,const struct omap_video_timings * t)4342 static void print_dispc_vm(const char *str, const struct omap_video_timings *t)
4343 {
4344 unsigned long pck = t->pixelclock;
4345 int hact, bl, tot;
4346
4347 hact = t->x_res;
4348 bl = t->hsw + t->hbp + t->hfp;
4349 tot = hact + bl;
4350
4351 #define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck))
4352
4353 pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, "
4354 "%u/%u/%u/%u = %u + %u = %u\n",
4355 str,
4356 pck,
4357 t->hsw, t->hbp, hact, t->hfp,
4358 bl, hact, tot,
4359 TO_DISPC_T(t->hsw),
4360 TO_DISPC_T(t->hbp),
4361 TO_DISPC_T(hact),
4362 TO_DISPC_T(t->hfp),
4363 TO_DISPC_T(bl),
4364 TO_DISPC_T(hact),
4365 TO_DISPC_T(tot));
4366 #undef TO_DISPC_T
4367 }
4368
4369 /* note: this is not quite accurate */
print_dsi_dispc_vm(const char * str,const struct omap_dss_dsi_videomode_timings * t)4370 static void print_dsi_dispc_vm(const char *str,
4371 const struct omap_dss_dsi_videomode_timings *t)
4372 {
4373 struct omap_video_timings vm = { 0 };
4374 unsigned long byteclk = t->hsclk / 4;
4375 unsigned long pck;
4376 u64 dsi_tput;
4377 int dsi_hact, dsi_htot;
4378
4379 dsi_tput = (u64)byteclk * t->ndl * 8;
4380 pck = (u32)div64_u64(dsi_tput, t->bitspp);
4381 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl);
4382 dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp;
4383
4384 vm.pixelclock = pck;
4385 vm.hsw = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk);
4386 vm.hbp = div64_u64((u64)t->hbp * pck, byteclk);
4387 vm.hfp = div64_u64((u64)t->hfp * pck, byteclk);
4388 vm.x_res = t->hact;
4389
4390 print_dispc_vm(str, &vm);
4391 }
4392 #endif /* PRINT_VERBOSE_VM_TIMINGS */
4393
dsi_cm_calc_dispc_cb(int lckd,int pckd,unsigned long lck,unsigned long pck,void * data)4394 static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4395 unsigned long pck, void *data)
4396 {
4397 struct dsi_clk_calc_ctx *ctx = data;
4398 struct omap_video_timings *t = &ctx->dispc_vm;
4399
4400 ctx->dispc_cinfo.lck_div = lckd;
4401 ctx->dispc_cinfo.pck_div = pckd;
4402 ctx->dispc_cinfo.lck = lck;
4403 ctx->dispc_cinfo.pck = pck;
4404
4405 *t = *ctx->config->timings;
4406 t->pixelclock = pck;
4407 t->x_res = ctx->config->timings->x_res;
4408 t->y_res = ctx->config->timings->y_res;
4409 t->hsw = t->hfp = t->hbp = t->vsw = 1;
4410 t->vfp = t->vbp = 0;
4411
4412 return true;
4413 }
4414
dsi_cm_calc_hsdiv_cb(int m_dispc,unsigned long dispc,void * data)4415 static bool dsi_cm_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
4416 void *data)
4417 {
4418 struct dsi_clk_calc_ctx *ctx = data;
4419
4420 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc;
4421 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc;
4422
4423 return dispc_div_calc(dispc, ctx->req_pck_min, ctx->req_pck_max,
4424 dsi_cm_calc_dispc_cb, ctx);
4425 }
4426
dsi_cm_calc_pll_cb(int n,int m,unsigned long fint,unsigned long clkdco,void * data)4427 static bool dsi_cm_calc_pll_cb(int n, int m, unsigned long fint,
4428 unsigned long clkdco, void *data)
4429 {
4430 struct dsi_clk_calc_ctx *ctx = data;
4431
4432 ctx->dsi_cinfo.n = n;
4433 ctx->dsi_cinfo.m = m;
4434 ctx->dsi_cinfo.fint = fint;
4435 ctx->dsi_cinfo.clkdco = clkdco;
4436
4437 return dss_pll_hsdiv_calc(ctx->pll, clkdco, ctx->req_pck_min,
4438 dss_feat_get_param_max(FEAT_PARAM_DSS_FCK),
4439 dsi_cm_calc_hsdiv_cb, ctx);
4440 }
4441
dsi_cm_calc(struct dsi_data * dsi,const struct omap_dss_dsi_config * cfg,struct dsi_clk_calc_ctx * ctx)4442 static bool dsi_cm_calc(struct dsi_data *dsi,
4443 const struct omap_dss_dsi_config *cfg,
4444 struct dsi_clk_calc_ctx *ctx)
4445 {
4446 unsigned long clkin;
4447 int bitspp, ndl;
4448 unsigned long pll_min, pll_max;
4449 unsigned long pck, txbyteclk;
4450
4451 clkin = clk_get_rate(dsi->pll.clkin);
4452 bitspp = dsi_get_pixel_size(cfg->pixel_format);
4453 ndl = dsi->num_lanes_used - 1;
4454
4455 /*
4456 * Here we should calculate minimum txbyteclk to be able to send the
4457 * frame in time, and also to handle TE. That's not very simple, though,
4458 * especially as we go to LP between each pixel packet due to HW
4459 * "feature". So let's just estimate very roughly and multiply by 1.5.
4460 */
4461 pck = cfg->timings->pixelclock;
4462 pck = pck * 3 / 2;
4463 txbyteclk = pck * bitspp / 8 / ndl;
4464
4465 memset(ctx, 0, sizeof(*ctx));
4466 ctx->dsidev = dsi->pdev;
4467 ctx->pll = &dsi->pll;
4468 ctx->config = cfg;
4469 ctx->req_pck_min = pck;
4470 ctx->req_pck_nom = pck;
4471 ctx->req_pck_max = pck * 3 / 2;
4472
4473 pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4);
4474 pll_max = cfg->hs_clk_max * 4;
4475
4476 return dss_pll_calc(ctx->pll, clkin,
4477 pll_min, pll_max,
4478 dsi_cm_calc_pll_cb, ctx);
4479 }
4480
dsi_vm_calc_blanking(struct dsi_clk_calc_ctx * ctx)4481 static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
4482 {
4483 struct dsi_data *dsi = dsi_get_dsidrv_data(ctx->dsidev);
4484 const struct omap_dss_dsi_config *cfg = ctx->config;
4485 int bitspp = dsi_get_pixel_size(cfg->pixel_format);
4486 int ndl = dsi->num_lanes_used - 1;
4487 unsigned long hsclk = ctx->dsi_cinfo.clkdco / 4;
4488 unsigned long byteclk = hsclk / 4;
4489
4490 unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max;
4491 int xres;
4492 int panel_htot, panel_hbl; /* pixels */
4493 int dispc_htot, dispc_hbl; /* pixels */
4494 int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */
4495 int hfp, hsa, hbp;
4496 const struct omap_video_timings *req_vm;
4497 struct omap_video_timings *dispc_vm;
4498 struct omap_dss_dsi_videomode_timings *dsi_vm;
4499 u64 dsi_tput, dispc_tput;
4500
4501 dsi_tput = (u64)byteclk * ndl * 8;
4502
4503 req_vm = cfg->timings;
4504 req_pck_min = ctx->req_pck_min;
4505 req_pck_max = ctx->req_pck_max;
4506 req_pck_nom = ctx->req_pck_nom;
4507
4508 dispc_pck = ctx->dispc_cinfo.pck;
4509 dispc_tput = (u64)dispc_pck * bitspp;
4510
4511 xres = req_vm->x_res;
4512
4513 panel_hbl = req_vm->hfp + req_vm->hbp + req_vm->hsw;
4514 panel_htot = xres + panel_hbl;
4515
4516 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl);
4517
4518 /*
4519 * When there are no line buffers, DISPC and DSI must have the
4520 * same tput. Otherwise DISPC tput needs to be higher than DSI's.
4521 */
4522 if (dsi->line_buffer_size < xres * bitspp / 8) {
4523 if (dispc_tput != dsi_tput)
4524 return false;
4525 } else {
4526 if (dispc_tput < dsi_tput)
4527 return false;
4528 }
4529
4530 /* DSI tput must be over the min requirement */
4531 if (dsi_tput < (u64)bitspp * req_pck_min)
4532 return false;
4533
4534 /* When non-burst mode, DSI tput must be below max requirement. */
4535 if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) {
4536 if (dsi_tput > (u64)bitspp * req_pck_max)
4537 return false;
4538 }
4539
4540 hss = DIV_ROUND_UP(4, ndl);
4541
4542 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4543 if (ndl == 3 && req_vm->hsw == 0)
4544 hse = 1;
4545 else
4546 hse = DIV_ROUND_UP(4, ndl);
4547 } else {
4548 hse = 0;
4549 }
4550
4551 /* DSI htot to match the panel's nominal pck */
4552 dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom);
4553
4554 /* fail if there would be no time for blanking */
4555 if (dsi_htot < hss + hse + dsi_hact)
4556 return false;
4557
4558 /* total DSI blanking needed to achieve panel's TL */
4559 dsi_hbl = dsi_htot - dsi_hact;
4560
4561 /* DISPC htot to match the DSI TL */
4562 dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk);
4563
4564 /* verify that the DSI and DISPC TLs are the same */
4565 if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk)
4566 return false;
4567
4568 dispc_hbl = dispc_htot - xres;
4569
4570 /* setup DSI videomode */
4571
4572 dsi_vm = &ctx->dsi_vm;
4573 memset(dsi_vm, 0, sizeof(*dsi_vm));
4574
4575 dsi_vm->hsclk = hsclk;
4576
4577 dsi_vm->ndl = ndl;
4578 dsi_vm->bitspp = bitspp;
4579
4580 if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) {
4581 hsa = 0;
4582 } else if (ndl == 3 && req_vm->hsw == 0) {
4583 hsa = 0;
4584 } else {
4585 hsa = div64_u64((u64)req_vm->hsw * byteclk, req_pck_nom);
4586 hsa = max(hsa - hse, 1);
4587 }
4588
4589 hbp = div64_u64((u64)req_vm->hbp * byteclk, req_pck_nom);
4590 hbp = max(hbp, 1);
4591
4592 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4593 if (hfp < 1) {
4594 int t;
4595 /* we need to take cycles from hbp */
4596
4597 t = 1 - hfp;
4598 hbp = max(hbp - t, 1);
4599 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4600
4601 if (hfp < 1 && hsa > 0) {
4602 /* we need to take cycles from hsa */
4603 t = 1 - hfp;
4604 hsa = max(hsa - t, 1);
4605 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4606 }
4607 }
4608
4609 if (hfp < 1)
4610 return false;
4611
4612 dsi_vm->hss = hss;
4613 dsi_vm->hsa = hsa;
4614 dsi_vm->hse = hse;
4615 dsi_vm->hbp = hbp;
4616 dsi_vm->hact = xres;
4617 dsi_vm->hfp = hfp;
4618
4619 dsi_vm->vsa = req_vm->vsw;
4620 dsi_vm->vbp = req_vm->vbp;
4621 dsi_vm->vact = req_vm->y_res;
4622 dsi_vm->vfp = req_vm->vfp;
4623
4624 dsi_vm->trans_mode = cfg->trans_mode;
4625
4626 dsi_vm->blanking_mode = 0;
4627 dsi_vm->hsa_blanking_mode = 1;
4628 dsi_vm->hfp_blanking_mode = 1;
4629 dsi_vm->hbp_blanking_mode = 1;
4630
4631 dsi_vm->ddr_clk_always_on = cfg->ddr_clk_always_on;
4632 dsi_vm->window_sync = 4;
4633
4634 /* setup DISPC videomode */
4635
4636 dispc_vm = &ctx->dispc_vm;
4637 *dispc_vm = *req_vm;
4638 dispc_vm->pixelclock = dispc_pck;
4639
4640 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4641 hsa = div64_u64((u64)req_vm->hsw * dispc_pck,
4642 req_pck_nom);
4643 hsa = max(hsa, 1);
4644 } else {
4645 hsa = 1;
4646 }
4647
4648 hbp = div64_u64((u64)req_vm->hbp * dispc_pck, req_pck_nom);
4649 hbp = max(hbp, 1);
4650
4651 hfp = dispc_hbl - hsa - hbp;
4652 if (hfp < 1) {
4653 int t;
4654 /* we need to take cycles from hbp */
4655
4656 t = 1 - hfp;
4657 hbp = max(hbp - t, 1);
4658 hfp = dispc_hbl - hsa - hbp;
4659
4660 if (hfp < 1) {
4661 /* we need to take cycles from hsa */
4662 t = 1 - hfp;
4663 hsa = max(hsa - t, 1);
4664 hfp = dispc_hbl - hsa - hbp;
4665 }
4666 }
4667
4668 if (hfp < 1)
4669 return false;
4670
4671 dispc_vm->hfp = hfp;
4672 dispc_vm->hsw = hsa;
4673 dispc_vm->hbp = hbp;
4674
4675 return true;
4676 }
4677
4678
dsi_vm_calc_dispc_cb(int lckd,int pckd,unsigned long lck,unsigned long pck,void * data)4679 static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4680 unsigned long pck, void *data)
4681 {
4682 struct dsi_clk_calc_ctx *ctx = data;
4683
4684 ctx->dispc_cinfo.lck_div = lckd;
4685 ctx->dispc_cinfo.pck_div = pckd;
4686 ctx->dispc_cinfo.lck = lck;
4687 ctx->dispc_cinfo.pck = pck;
4688
4689 if (dsi_vm_calc_blanking(ctx) == false)
4690 return false;
4691
4692 #ifdef PRINT_VERBOSE_VM_TIMINGS
4693 print_dispc_vm("dispc", &ctx->dispc_vm);
4694 print_dsi_vm("dsi ", &ctx->dsi_vm);
4695 print_dispc_vm("req ", ctx->config->timings);
4696 print_dsi_dispc_vm("act ", &ctx->dsi_vm);
4697 #endif
4698
4699 return true;
4700 }
4701
dsi_vm_calc_hsdiv_cb(int m_dispc,unsigned long dispc,void * data)4702 static bool dsi_vm_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
4703 void *data)
4704 {
4705 struct dsi_clk_calc_ctx *ctx = data;
4706 unsigned long pck_max;
4707
4708 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc;
4709 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc;
4710
4711 /*
4712 * In burst mode we can let the dispc pck be arbitrarily high, but it
4713 * limits our scaling abilities. So for now, don't aim too high.
4714 */
4715
4716 if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE)
4717 pck_max = ctx->req_pck_max + 10000000;
4718 else
4719 pck_max = ctx->req_pck_max;
4720
4721 return dispc_div_calc(dispc, ctx->req_pck_min, pck_max,
4722 dsi_vm_calc_dispc_cb, ctx);
4723 }
4724
dsi_vm_calc_pll_cb(int n,int m,unsigned long fint,unsigned long clkdco,void * data)4725 static bool dsi_vm_calc_pll_cb(int n, int m, unsigned long fint,
4726 unsigned long clkdco, void *data)
4727 {
4728 struct dsi_clk_calc_ctx *ctx = data;
4729
4730 ctx->dsi_cinfo.n = n;
4731 ctx->dsi_cinfo.m = m;
4732 ctx->dsi_cinfo.fint = fint;
4733 ctx->dsi_cinfo.clkdco = clkdco;
4734
4735 return dss_pll_hsdiv_calc(ctx->pll, clkdco, ctx->req_pck_min,
4736 dss_feat_get_param_max(FEAT_PARAM_DSS_FCK),
4737 dsi_vm_calc_hsdiv_cb, ctx);
4738 }
4739
dsi_vm_calc(struct dsi_data * dsi,const struct omap_dss_dsi_config * cfg,struct dsi_clk_calc_ctx * ctx)4740 static bool dsi_vm_calc(struct dsi_data *dsi,
4741 const struct omap_dss_dsi_config *cfg,
4742 struct dsi_clk_calc_ctx *ctx)
4743 {
4744 const struct omap_video_timings *t = cfg->timings;
4745 unsigned long clkin;
4746 unsigned long pll_min;
4747 unsigned long pll_max;
4748 int ndl = dsi->num_lanes_used - 1;
4749 int bitspp = dsi_get_pixel_size(cfg->pixel_format);
4750 unsigned long byteclk_min;
4751
4752 clkin = clk_get_rate(dsi->pll.clkin);
4753
4754 memset(ctx, 0, sizeof(*ctx));
4755 ctx->dsidev = dsi->pdev;
4756 ctx->pll = &dsi->pll;
4757 ctx->config = cfg;
4758
4759 /* these limits should come from the panel driver */
4760 ctx->req_pck_min = t->pixelclock - 1000;
4761 ctx->req_pck_nom = t->pixelclock;
4762 ctx->req_pck_max = t->pixelclock + 1000;
4763
4764 byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8);
4765 pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4);
4766
4767 if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) {
4768 pll_max = cfg->hs_clk_max * 4;
4769 } else {
4770 unsigned long byteclk_max;
4771 byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp,
4772 ndl * 8);
4773
4774 pll_max = byteclk_max * 4 * 4;
4775 }
4776
4777 return dss_pll_calc(ctx->pll, clkin,
4778 pll_min, pll_max,
4779 dsi_vm_calc_pll_cb, ctx);
4780 }
4781
dsi_set_config(struct omap_dss_device * dssdev,const struct omap_dss_dsi_config * config)4782 static int dsi_set_config(struct omap_dss_device *dssdev,
4783 const struct omap_dss_dsi_config *config)
4784 {
4785 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4786 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4787 struct dsi_clk_calc_ctx ctx;
4788 bool ok;
4789 int r;
4790
4791 mutex_lock(&dsi->lock);
4792
4793 dsi->pix_fmt = config->pixel_format;
4794 dsi->mode = config->mode;
4795
4796 if (config->mode == OMAP_DSS_DSI_VIDEO_MODE)
4797 ok = dsi_vm_calc(dsi, config, &ctx);
4798 else
4799 ok = dsi_cm_calc(dsi, config, &ctx);
4800
4801 if (!ok) {
4802 DSSERR("failed to find suitable DSI clock settings\n");
4803 r = -EINVAL;
4804 goto err;
4805 }
4806
4807 dsi_pll_calc_dsi_fck(&ctx.dsi_cinfo);
4808
4809 r = dsi_lp_clock_calc(ctx.dsi_cinfo.clkout[HSDIV_DSI],
4810 config->lp_clk_min, config->lp_clk_max, &dsi->user_lp_cinfo);
4811 if (r) {
4812 DSSERR("failed to find suitable DSI LP clock settings\n");
4813 goto err;
4814 }
4815
4816 dsi->user_dsi_cinfo = ctx.dsi_cinfo;
4817 dsi->user_dispc_cinfo = ctx.dispc_cinfo;
4818
4819 dsi->timings = ctx.dispc_vm;
4820 dsi->vm_timings = ctx.dsi_vm;
4821
4822 mutex_unlock(&dsi->lock);
4823
4824 return 0;
4825 err:
4826 mutex_unlock(&dsi->lock);
4827
4828 return r;
4829 }
4830
4831 /*
4832 * Return a hardcoded channel for the DSI output. This should work for
4833 * current use cases, but this can be later expanded to either resolve
4834 * the channel in some more dynamic manner, or get the channel as a user
4835 * parameter.
4836 */
dsi_get_channel(int module_id)4837 static enum omap_channel dsi_get_channel(int module_id)
4838 {
4839 switch (omapdss_get_version()) {
4840 case OMAPDSS_VER_OMAP24xx:
4841 case OMAPDSS_VER_AM43xx:
4842 DSSWARN("DSI not supported\n");
4843 return OMAP_DSS_CHANNEL_LCD;
4844
4845 case OMAPDSS_VER_OMAP34xx_ES1:
4846 case OMAPDSS_VER_OMAP34xx_ES3:
4847 case OMAPDSS_VER_OMAP3630:
4848 case OMAPDSS_VER_AM35xx:
4849 return OMAP_DSS_CHANNEL_LCD;
4850
4851 case OMAPDSS_VER_OMAP4430_ES1:
4852 case OMAPDSS_VER_OMAP4430_ES2:
4853 case OMAPDSS_VER_OMAP4:
4854 switch (module_id) {
4855 case 0:
4856 return OMAP_DSS_CHANNEL_LCD;
4857 case 1:
4858 return OMAP_DSS_CHANNEL_LCD2;
4859 default:
4860 DSSWARN("unsupported module id\n");
4861 return OMAP_DSS_CHANNEL_LCD;
4862 }
4863
4864 case OMAPDSS_VER_OMAP5:
4865 switch (module_id) {
4866 case 0:
4867 return OMAP_DSS_CHANNEL_LCD;
4868 case 1:
4869 return OMAP_DSS_CHANNEL_LCD3;
4870 default:
4871 DSSWARN("unsupported module id\n");
4872 return OMAP_DSS_CHANNEL_LCD;
4873 }
4874
4875 default:
4876 DSSWARN("unsupported DSS version\n");
4877 return OMAP_DSS_CHANNEL_LCD;
4878 }
4879 }
4880
dsi_request_vc(struct omap_dss_device * dssdev,int * channel)4881 static int dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
4882 {
4883 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4884 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4885 int i;
4886
4887 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4888 if (!dsi->vc[i].dssdev) {
4889 dsi->vc[i].dssdev = dssdev;
4890 *channel = i;
4891 return 0;
4892 }
4893 }
4894
4895 DSSERR("cannot get VC for display %s", dssdev->name);
4896 return -ENOSPC;
4897 }
4898
dsi_set_vc_id(struct omap_dss_device * dssdev,int channel,int vc_id)4899 static int dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
4900 {
4901 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4902 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4903
4904 if (vc_id < 0 || vc_id > 3) {
4905 DSSERR("VC ID out of range\n");
4906 return -EINVAL;
4907 }
4908
4909 if (channel < 0 || channel > 3) {
4910 DSSERR("Virtual Channel out of range\n");
4911 return -EINVAL;
4912 }
4913
4914 if (dsi->vc[channel].dssdev != dssdev) {
4915 DSSERR("Virtual Channel not allocated to display %s\n",
4916 dssdev->name);
4917 return -EINVAL;
4918 }
4919
4920 dsi->vc[channel].vc_id = vc_id;
4921
4922 return 0;
4923 }
4924
dsi_release_vc(struct omap_dss_device * dssdev,int channel)4925 static void dsi_release_vc(struct omap_dss_device *dssdev, int channel)
4926 {
4927 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4928 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4929
4930 if ((channel >= 0 && channel <= 3) &&
4931 dsi->vc[channel].dssdev == dssdev) {
4932 dsi->vc[channel].dssdev = NULL;
4933 dsi->vc[channel].vc_id = 0;
4934 }
4935 }
4936
4937
dsi_get_clocks(struct platform_device * dsidev)4938 static int dsi_get_clocks(struct platform_device *dsidev)
4939 {
4940 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4941 struct clk *clk;
4942
4943 clk = devm_clk_get(&dsidev->dev, "fck");
4944 if (IS_ERR(clk)) {
4945 DSSERR("can't get fck\n");
4946 return PTR_ERR(clk);
4947 }
4948
4949 dsi->dss_clk = clk;
4950
4951 return 0;
4952 }
4953
dsi_connect(struct omap_dss_device * dssdev,struct omap_dss_device * dst)4954 static int dsi_connect(struct omap_dss_device *dssdev,
4955 struct omap_dss_device *dst)
4956 {
4957 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4958 struct omap_overlay_manager *mgr;
4959 int r;
4960
4961 r = dsi_regulator_init(dsidev);
4962 if (r)
4963 return r;
4964
4965 mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
4966 if (!mgr)
4967 return -ENODEV;
4968
4969 r = dss_mgr_connect(mgr, dssdev);
4970 if (r)
4971 return r;
4972
4973 r = omapdss_output_set_device(dssdev, dst);
4974 if (r) {
4975 DSSERR("failed to connect output to new device: %s\n",
4976 dssdev->name);
4977 dss_mgr_disconnect(mgr, dssdev);
4978 return r;
4979 }
4980
4981 return 0;
4982 }
4983
dsi_disconnect(struct omap_dss_device * dssdev,struct omap_dss_device * dst)4984 static void dsi_disconnect(struct omap_dss_device *dssdev,
4985 struct omap_dss_device *dst)
4986 {
4987 WARN_ON(dst != dssdev->dst);
4988
4989 if (dst != dssdev->dst)
4990 return;
4991
4992 omapdss_output_unset_device(dssdev);
4993
4994 if (dssdev->manager)
4995 dss_mgr_disconnect(dssdev->manager, dssdev);
4996 }
4997
4998 static const struct omapdss_dsi_ops dsi_ops = {
4999 .connect = dsi_connect,
5000 .disconnect = dsi_disconnect,
5001
5002 .bus_lock = dsi_bus_lock,
5003 .bus_unlock = dsi_bus_unlock,
5004
5005 .enable = dsi_display_enable,
5006 .disable = dsi_display_disable,
5007
5008 .enable_hs = dsi_vc_enable_hs,
5009
5010 .configure_pins = dsi_configure_pins,
5011 .set_config = dsi_set_config,
5012
5013 .enable_video_output = dsi_enable_video_output,
5014 .disable_video_output = dsi_disable_video_output,
5015
5016 .update = dsi_update,
5017
5018 .enable_te = dsi_enable_te,
5019
5020 .request_vc = dsi_request_vc,
5021 .set_vc_id = dsi_set_vc_id,
5022 .release_vc = dsi_release_vc,
5023
5024 .dcs_write = dsi_vc_dcs_write,
5025 .dcs_write_nosync = dsi_vc_dcs_write_nosync,
5026 .dcs_read = dsi_vc_dcs_read,
5027
5028 .gen_write = dsi_vc_generic_write,
5029 .gen_write_nosync = dsi_vc_generic_write_nosync,
5030 .gen_read = dsi_vc_generic_read,
5031
5032 .bta_sync = dsi_vc_send_bta_sync,
5033
5034 .set_max_rx_packet_size = dsi_vc_set_max_rx_packet_size,
5035 };
5036
dsi_init_output(struct platform_device * dsidev)5037 static void dsi_init_output(struct platform_device *dsidev)
5038 {
5039 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5040 struct omap_dss_device *out = &dsi->output;
5041
5042 out->dev = &dsidev->dev;
5043 out->id = dsi->module_id == 0 ?
5044 OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2;
5045
5046 out->output_type = OMAP_DISPLAY_TYPE_DSI;
5047 out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1";
5048 out->dispc_channel = dsi_get_channel(dsi->module_id);
5049 out->ops.dsi = &dsi_ops;
5050 out->owner = THIS_MODULE;
5051
5052 omapdss_register_output(out);
5053 }
5054
dsi_uninit_output(struct platform_device * dsidev)5055 static void dsi_uninit_output(struct platform_device *dsidev)
5056 {
5057 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5058 struct omap_dss_device *out = &dsi->output;
5059
5060 omapdss_unregister_output(out);
5061 }
5062
dsi_probe_of(struct platform_device * pdev)5063 static int dsi_probe_of(struct platform_device *pdev)
5064 {
5065 struct device_node *node = pdev->dev.of_node;
5066 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5067 struct property *prop;
5068 u32 lane_arr[10];
5069 int len, num_pins;
5070 int r, i;
5071 struct device_node *ep;
5072 struct omap_dsi_pin_config pin_cfg;
5073
5074 ep = omapdss_of_get_first_endpoint(node);
5075 if (!ep)
5076 return 0;
5077
5078 prop = of_find_property(ep, "lanes", &len);
5079 if (prop == NULL) {
5080 dev_err(&pdev->dev, "failed to find lane data\n");
5081 r = -EINVAL;
5082 goto err;
5083 }
5084
5085 num_pins = len / sizeof(u32);
5086
5087 if (num_pins < 4 || num_pins % 2 != 0 ||
5088 num_pins > dsi->num_lanes_supported * 2) {
5089 dev_err(&pdev->dev, "bad number of lanes\n");
5090 r = -EINVAL;
5091 goto err;
5092 }
5093
5094 r = of_property_read_u32_array(ep, "lanes", lane_arr, num_pins);
5095 if (r) {
5096 dev_err(&pdev->dev, "failed to read lane data\n");
5097 goto err;
5098 }
5099
5100 pin_cfg.num_pins = num_pins;
5101 for (i = 0; i < num_pins; ++i)
5102 pin_cfg.pins[i] = (int)lane_arr[i];
5103
5104 r = dsi_configure_pins(&dsi->output, &pin_cfg);
5105 if (r) {
5106 dev_err(&pdev->dev, "failed to configure pins");
5107 goto err;
5108 }
5109
5110 of_node_put(ep);
5111
5112 return 0;
5113
5114 err:
5115 of_node_put(ep);
5116 return r;
5117 }
5118
5119 static const struct dss_pll_ops dsi_pll_ops = {
5120 .enable = dsi_pll_enable,
5121 .disable = dsi_pll_disable,
5122 .set_config = dss_pll_write_config_type_a,
5123 };
5124
5125 static const struct dss_pll_hw dss_omap3_dsi_pll_hw = {
5126 .n_max = (1 << 7) - 1,
5127 .m_max = (1 << 11) - 1,
5128 .mX_max = (1 << 4) - 1,
5129 .fint_min = 750000,
5130 .fint_max = 2100000,
5131 .clkdco_low = 1000000000,
5132 .clkdco_max = 1800000000,
5133
5134 .n_msb = 7,
5135 .n_lsb = 1,
5136 .m_msb = 18,
5137 .m_lsb = 8,
5138
5139 .mX_msb[0] = 22,
5140 .mX_lsb[0] = 19,
5141 .mX_msb[1] = 26,
5142 .mX_lsb[1] = 23,
5143
5144 .has_stopmode = true,
5145 .has_freqsel = true,
5146 .has_selfreqdco = false,
5147 .has_refsel = false,
5148 };
5149
5150 static const struct dss_pll_hw dss_omap4_dsi_pll_hw = {
5151 .n_max = (1 << 8) - 1,
5152 .m_max = (1 << 12) - 1,
5153 .mX_max = (1 << 5) - 1,
5154 .fint_min = 500000,
5155 .fint_max = 2500000,
5156 .clkdco_low = 1000000000,
5157 .clkdco_max = 1800000000,
5158
5159 .n_msb = 8,
5160 .n_lsb = 1,
5161 .m_msb = 20,
5162 .m_lsb = 9,
5163
5164 .mX_msb[0] = 25,
5165 .mX_lsb[0] = 21,
5166 .mX_msb[1] = 30,
5167 .mX_lsb[1] = 26,
5168
5169 .has_stopmode = true,
5170 .has_freqsel = false,
5171 .has_selfreqdco = false,
5172 .has_refsel = false,
5173 };
5174
5175 static const struct dss_pll_hw dss_omap5_dsi_pll_hw = {
5176 .n_max = (1 << 8) - 1,
5177 .m_max = (1 << 12) - 1,
5178 .mX_max = (1 << 5) - 1,
5179 .fint_min = 150000,
5180 .fint_max = 52000000,
5181 .clkdco_low = 1000000000,
5182 .clkdco_max = 1800000000,
5183
5184 .n_msb = 8,
5185 .n_lsb = 1,
5186 .m_msb = 20,
5187 .m_lsb = 9,
5188
5189 .mX_msb[0] = 25,
5190 .mX_lsb[0] = 21,
5191 .mX_msb[1] = 30,
5192 .mX_lsb[1] = 26,
5193
5194 .has_stopmode = true,
5195 .has_freqsel = false,
5196 .has_selfreqdco = true,
5197 .has_refsel = true,
5198 };
5199
dsi_init_pll_data(struct platform_device * dsidev)5200 static int dsi_init_pll_data(struct platform_device *dsidev)
5201 {
5202 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5203 struct dss_pll *pll = &dsi->pll;
5204 struct clk *clk;
5205 int r;
5206
5207 clk = devm_clk_get(&dsidev->dev, "sys_clk");
5208 if (IS_ERR(clk)) {
5209 DSSERR("can't get sys_clk\n");
5210 return PTR_ERR(clk);
5211 }
5212
5213 pll->name = dsi->module_id == 0 ? "dsi0" : "dsi1";
5214 pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2;
5215 pll->clkin = clk;
5216 pll->base = dsi->pll_base;
5217
5218 switch (omapdss_get_version()) {
5219 case OMAPDSS_VER_OMAP34xx_ES1:
5220 case OMAPDSS_VER_OMAP34xx_ES3:
5221 case OMAPDSS_VER_OMAP3630:
5222 case OMAPDSS_VER_AM35xx:
5223 pll->hw = &dss_omap3_dsi_pll_hw;
5224 break;
5225
5226 case OMAPDSS_VER_OMAP4430_ES1:
5227 case OMAPDSS_VER_OMAP4430_ES2:
5228 case OMAPDSS_VER_OMAP4:
5229 pll->hw = &dss_omap4_dsi_pll_hw;
5230 break;
5231
5232 case OMAPDSS_VER_OMAP5:
5233 pll->hw = &dss_omap5_dsi_pll_hw;
5234 break;
5235
5236 default:
5237 return -ENODEV;
5238 }
5239
5240 pll->ops = &dsi_pll_ops;
5241
5242 r = dss_pll_register(pll);
5243 if (r)
5244 return r;
5245
5246 return 0;
5247 }
5248
5249 /* DSI1 HW IP initialisation */
dsi_bind(struct device * dev,struct device * master,void * data)5250 static int dsi_bind(struct device *dev, struct device *master, void *data)
5251 {
5252 struct platform_device *dsidev = to_platform_device(dev);
5253 u32 rev;
5254 int r, i;
5255 struct dsi_data *dsi;
5256 struct resource *dsi_mem;
5257 struct resource *res;
5258 struct resource temp_res;
5259
5260 dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL);
5261 if (!dsi)
5262 return -ENOMEM;
5263
5264 dsi->pdev = dsidev;
5265 platform_set_drvdata(dsidev, dsi);
5266
5267 spin_lock_init(&dsi->irq_lock);
5268 spin_lock_init(&dsi->errors_lock);
5269 dsi->errors = 0;
5270
5271 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
5272 spin_lock_init(&dsi->irq_stats_lock);
5273 dsi->irq_stats.last_reset = jiffies;
5274 #endif
5275
5276 mutex_init(&dsi->lock);
5277 sema_init(&dsi->bus_lock, 1);
5278
5279 INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work,
5280 dsi_framedone_timeout_work_callback);
5281
5282 #ifdef DSI_CATCH_MISSING_TE
5283 timer_setup(&dsi->te_timer, dsi_te_timeout, 0);
5284 #endif
5285
5286 res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "proto");
5287 if (!res) {
5288 res = platform_get_resource(dsidev, IORESOURCE_MEM, 0);
5289 if (!res) {
5290 DSSERR("can't get IORESOURCE_MEM DSI\n");
5291 return -EINVAL;
5292 }
5293
5294 temp_res.start = res->start;
5295 temp_res.end = temp_res.start + DSI_PROTO_SZ - 1;
5296 res = &temp_res;
5297 }
5298
5299 dsi_mem = res;
5300
5301 dsi->proto_base = devm_ioremap(&dsidev->dev, res->start,
5302 resource_size(res));
5303 if (!dsi->proto_base) {
5304 DSSERR("can't ioremap DSI protocol engine\n");
5305 return -ENOMEM;
5306 }
5307
5308 res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "phy");
5309 if (!res) {
5310 res = platform_get_resource(dsidev, IORESOURCE_MEM, 0);
5311 if (!res) {
5312 DSSERR("can't get IORESOURCE_MEM DSI\n");
5313 return -EINVAL;
5314 }
5315
5316 temp_res.start = res->start + DSI_PHY_OFFSET;
5317 temp_res.end = temp_res.start + DSI_PHY_SZ - 1;
5318 res = &temp_res;
5319 }
5320
5321 dsi->phy_base = devm_ioremap(&dsidev->dev, res->start,
5322 resource_size(res));
5323 if (!dsi->phy_base) {
5324 DSSERR("can't ioremap DSI PHY\n");
5325 return -ENOMEM;
5326 }
5327
5328 res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "pll");
5329 if (!res) {
5330 res = platform_get_resource(dsidev, IORESOURCE_MEM, 0);
5331 if (!res) {
5332 DSSERR("can't get IORESOURCE_MEM DSI\n");
5333 return -EINVAL;
5334 }
5335
5336 temp_res.start = res->start + DSI_PLL_OFFSET;
5337 temp_res.end = temp_res.start + DSI_PLL_SZ - 1;
5338 res = &temp_res;
5339 }
5340
5341 dsi->pll_base = devm_ioremap(&dsidev->dev, res->start,
5342 resource_size(res));
5343 if (!dsi->pll_base) {
5344 DSSERR("can't ioremap DSI PLL\n");
5345 return -ENOMEM;
5346 }
5347
5348 dsi->irq = platform_get_irq(dsi->pdev, 0);
5349 if (dsi->irq < 0) {
5350 DSSERR("platform_get_irq failed\n");
5351 return -ENODEV;
5352 }
5353
5354 r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler,
5355 IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev);
5356 if (r < 0) {
5357 DSSERR("request_irq failed\n");
5358 return r;
5359 }
5360
5361 if (dsidev->dev.of_node) {
5362 const struct of_device_id *match;
5363 const struct dsi_module_id_data *d;
5364
5365 match = of_match_node(dsi_of_match, dsidev->dev.of_node);
5366 if (!match) {
5367 DSSERR("unsupported DSI module\n");
5368 return -ENODEV;
5369 }
5370
5371 d = match->data;
5372
5373 while (d->address != 0 && d->address != dsi_mem->start)
5374 d++;
5375
5376 if (d->address == 0) {
5377 DSSERR("unsupported DSI module\n");
5378 return -ENODEV;
5379 }
5380
5381 dsi->module_id = d->id;
5382 } else {
5383 dsi->module_id = dsidev->id;
5384 }
5385
5386 /* DSI VCs initialization */
5387 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
5388 dsi->vc[i].source = DSI_VC_SOURCE_L4;
5389 dsi->vc[i].dssdev = NULL;
5390 dsi->vc[i].vc_id = 0;
5391 }
5392
5393 r = dsi_get_clocks(dsidev);
5394 if (r)
5395 return r;
5396
5397 dsi_init_pll_data(dsidev);
5398
5399 pm_runtime_enable(&dsidev->dev);
5400
5401 r = dsi_runtime_get(dsidev);
5402 if (r)
5403 goto err_runtime_get;
5404
5405 rev = dsi_read_reg(dsidev, DSI_REVISION);
5406 dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
5407 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
5408
5409 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
5410 * of data to 3 by default */
5411 if (dss_has_feature(FEAT_DSI_GNQ))
5412 /* NB_DATA_LANES */
5413 dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9);
5414 else
5415 dsi->num_lanes_supported = 3;
5416
5417 dsi->line_buffer_size = dsi_get_line_buf_size(dsidev);
5418
5419 dsi_init_output(dsidev);
5420
5421 if (dsidev->dev.of_node) {
5422 r = dsi_probe_of(dsidev);
5423 if (r) {
5424 DSSERR("Invalid DSI DT data\n");
5425 goto err_probe_of;
5426 }
5427
5428 r = of_platform_populate(dsidev->dev.of_node, NULL, NULL,
5429 &dsidev->dev);
5430 if (r)
5431 DSSERR("Failed to populate DSI child devices: %d\n", r);
5432 }
5433
5434 dsi_runtime_put(dsidev);
5435
5436 if (dsi->module_id == 0)
5437 dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs);
5438 else if (dsi->module_id == 1)
5439 dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs);
5440
5441 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
5442 if (dsi->module_id == 0)
5443 dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs);
5444 else if (dsi->module_id == 1)
5445 dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs);
5446 #endif
5447
5448 return 0;
5449
5450 err_probe_of:
5451 dsi_uninit_output(dsidev);
5452 dsi_runtime_put(dsidev);
5453
5454 err_runtime_get:
5455 pm_runtime_disable(&dsidev->dev);
5456 return r;
5457 }
5458
dsi_unbind(struct device * dev,struct device * master,void * data)5459 static void dsi_unbind(struct device *dev, struct device *master, void *data)
5460 {
5461 struct platform_device *dsidev = to_platform_device(dev);
5462 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5463
5464 of_platform_depopulate(&dsidev->dev);
5465
5466 WARN_ON(dsi->scp_clk_refcount > 0);
5467
5468 dss_pll_unregister(&dsi->pll);
5469
5470 dsi_uninit_output(dsidev);
5471
5472 pm_runtime_disable(&dsidev->dev);
5473
5474 if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) {
5475 regulator_disable(dsi->vdds_dsi_reg);
5476 dsi->vdds_dsi_enabled = false;
5477 }
5478 }
5479
5480 static const struct component_ops dsi_component_ops = {
5481 .bind = dsi_bind,
5482 .unbind = dsi_unbind,
5483 };
5484
dsi_probe(struct platform_device * pdev)5485 static int dsi_probe(struct platform_device *pdev)
5486 {
5487 return component_add(&pdev->dev, &dsi_component_ops);
5488 }
5489
dsi_remove(struct platform_device * pdev)5490 static int dsi_remove(struct platform_device *pdev)
5491 {
5492 component_del(&pdev->dev, &dsi_component_ops);
5493 return 0;
5494 }
5495
dsi_runtime_suspend(struct device * dev)5496 static int dsi_runtime_suspend(struct device *dev)
5497 {
5498 struct platform_device *pdev = to_platform_device(dev);
5499 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5500
5501 dsi->is_enabled = false;
5502 /* ensure the irq handler sees the is_enabled value */
5503 smp_wmb();
5504 /* wait for current handler to finish before turning the DSI off */
5505 synchronize_irq(dsi->irq);
5506
5507 dispc_runtime_put();
5508
5509 return 0;
5510 }
5511
dsi_runtime_resume(struct device * dev)5512 static int dsi_runtime_resume(struct device *dev)
5513 {
5514 struct platform_device *pdev = to_platform_device(dev);
5515 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5516 int r;
5517
5518 r = dispc_runtime_get();
5519 if (r)
5520 return r;
5521
5522 dsi->is_enabled = true;
5523 /* ensure the irq handler sees the is_enabled value */
5524 smp_wmb();
5525
5526 return 0;
5527 }
5528
5529 static const struct dev_pm_ops dsi_pm_ops = {
5530 .runtime_suspend = dsi_runtime_suspend,
5531 .runtime_resume = dsi_runtime_resume,
5532 };
5533
5534 static const struct dsi_module_id_data dsi_of_data_omap3[] = {
5535 { .address = 0x4804fc00, .id = 0, },
5536 { },
5537 };
5538
5539 static const struct dsi_module_id_data dsi_of_data_omap4[] = {
5540 { .address = 0x58004000, .id = 0, },
5541 { .address = 0x58005000, .id = 1, },
5542 { },
5543 };
5544
5545 static const struct dsi_module_id_data dsi_of_data_omap5[] = {
5546 { .address = 0x58004000, .id = 0, },
5547 { .address = 0x58009000, .id = 1, },
5548 { },
5549 };
5550
5551 static const struct of_device_id dsi_of_match[] = {
5552 { .compatible = "ti,omap3-dsi", .data = dsi_of_data_omap3, },
5553 { .compatible = "ti,omap4-dsi", .data = dsi_of_data_omap4, },
5554 { .compatible = "ti,omap5-dsi", .data = dsi_of_data_omap5, },
5555 {},
5556 };
5557
5558 static struct platform_driver omap_dsihw_driver = {
5559 .probe = dsi_probe,
5560 .remove = dsi_remove,
5561 .driver = {
5562 .name = "omapdss_dsi",
5563 .pm = &dsi_pm_ops,
5564 .of_match_table = dsi_of_match,
5565 .suppress_bind_attrs = true,
5566 },
5567 };
5568
dsi_init_platform_driver(void)5569 int __init dsi_init_platform_driver(void)
5570 {
5571 return platform_driver_register(&omap_dsihw_driver);
5572 }
5573
dsi_uninit_platform_driver(void)5574 void dsi_uninit_platform_driver(void)
5575 {
5576 platform_driver_unregister(&omap_dsihw_driver);
5577 }
5578
