1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (C) 2012-2018 ARM Limited or its affiliates. */ 3 4 #ifndef _CC_CRYPTO_CTX_H_ 5 #define _CC_CRYPTO_CTX_H_ 6 7 #include <linux/types.h> 8 9 #define CC_DRV_DES_IV_SIZE 8 10 #define CC_DRV_DES_BLOCK_SIZE 8 11 12 #define CC_DRV_DES_ONE_KEY_SIZE 8 13 #define CC_DRV_DES_DOUBLE_KEY_SIZE 16 14 #define CC_DRV_DES_TRIPLE_KEY_SIZE 24 15 #define CC_DRV_DES_KEY_SIZE_MAX CC_DRV_DES_TRIPLE_KEY_SIZE 16 17 #define CC_AES_IV_SIZE 16 18 #define CC_AES_IV_SIZE_WORDS (CC_AES_IV_SIZE >> 2) 19 20 #define CC_AES_BLOCK_SIZE 16 21 #define CC_AES_BLOCK_SIZE_WORDS 4 22 23 #define CC_AES_128_BIT_KEY_SIZE 16 24 #define CC_AES_128_BIT_KEY_SIZE_WORDS (CC_AES_128_BIT_KEY_SIZE >> 2) 25 #define CC_AES_192_BIT_KEY_SIZE 24 26 #define CC_AES_192_BIT_KEY_SIZE_WORDS (CC_AES_192_BIT_KEY_SIZE >> 2) 27 #define CC_AES_256_BIT_KEY_SIZE 32 28 #define CC_AES_256_BIT_KEY_SIZE_WORDS (CC_AES_256_BIT_KEY_SIZE >> 2) 29 #define CC_AES_KEY_SIZE_MAX CC_AES_256_BIT_KEY_SIZE 30 #define CC_AES_KEY_SIZE_WORDS_MAX (CC_AES_KEY_SIZE_MAX >> 2) 31 32 #define CC_MD5_DIGEST_SIZE 16 33 #define CC_SHA1_DIGEST_SIZE 20 34 #define CC_SHA224_DIGEST_SIZE 28 35 #define CC_SHA256_DIGEST_SIZE 32 36 #define CC_SHA256_DIGEST_SIZE_IN_WORDS 8 37 #define CC_SHA384_DIGEST_SIZE 48 38 #define CC_SHA512_DIGEST_SIZE 64 39 40 #define CC_SHA1_BLOCK_SIZE 64 41 #define CC_SHA1_BLOCK_SIZE_IN_WORDS 16 42 #define CC_MD5_BLOCK_SIZE 64 43 #define CC_MD5_BLOCK_SIZE_IN_WORDS 16 44 #define CC_SHA224_BLOCK_SIZE 64 45 #define CC_SHA256_BLOCK_SIZE 64 46 #define CC_SHA256_BLOCK_SIZE_IN_WORDS 16 47 #define CC_SHA1_224_256_BLOCK_SIZE 64 48 #define CC_SHA384_BLOCK_SIZE 128 49 #define CC_SHA512_BLOCK_SIZE 128 50 51 #define CC_DIGEST_SIZE_MAX CC_SHA512_DIGEST_SIZE 52 #define CC_HASH_BLOCK_SIZE_MAX CC_SHA512_BLOCK_SIZE /*1024b*/ 53 54 #define CC_HMAC_BLOCK_SIZE_MAX CC_HASH_BLOCK_SIZE_MAX 55 56 #define CC_DRV_ALG_MAX_BLOCK_SIZE CC_HASH_BLOCK_SIZE_MAX 57 58 enum drv_engine_type { 59 DRV_ENGINE_NULL = 0, 60 DRV_ENGINE_AES = 1, 61 DRV_ENGINE_DES = 2, 62 DRV_ENGINE_HASH = 3, 63 DRV_ENGINE_RC4 = 4, 64 DRV_ENGINE_DOUT = 5, 65 DRV_ENGINE_RESERVE32B = S32_MAX, 66 }; 67 68 enum drv_crypto_alg { 69 DRV_CRYPTO_ALG_NULL = -1, 70 DRV_CRYPTO_ALG_AES = 0, 71 DRV_CRYPTO_ALG_DES = 1, 72 DRV_CRYPTO_ALG_HASH = 2, 73 DRV_CRYPTO_ALG_C2 = 3, 74 DRV_CRYPTO_ALG_HMAC = 4, 75 DRV_CRYPTO_ALG_AEAD = 5, 76 DRV_CRYPTO_ALG_BYPASS = 6, 77 DRV_CRYPTO_ALG_NUM = 7, 78 DRV_CRYPTO_ALG_RESERVE32B = S32_MAX 79 }; 80 81 enum drv_crypto_direction { 82 DRV_CRYPTO_DIRECTION_NULL = -1, 83 DRV_CRYPTO_DIRECTION_ENCRYPT = 0, 84 DRV_CRYPTO_DIRECTION_DECRYPT = 1, 85 DRV_CRYPTO_DIRECTION_DECRYPT_ENCRYPT = 3, 86 DRV_CRYPTO_DIRECTION_RESERVE32B = S32_MAX 87 }; 88 89 enum drv_cipher_mode { 90 DRV_CIPHER_NULL_MODE = -1, 91 DRV_CIPHER_ECB = 0, 92 DRV_CIPHER_CBC = 1, 93 DRV_CIPHER_CTR = 2, 94 DRV_CIPHER_CBC_MAC = 3, 95 DRV_CIPHER_XTS = 4, 96 DRV_CIPHER_XCBC_MAC = 5, 97 DRV_CIPHER_OFB = 6, 98 DRV_CIPHER_CMAC = 7, 99 DRV_CIPHER_CCM = 8, 100 DRV_CIPHER_CBC_CTS = 11, 101 DRV_CIPHER_GCTR = 12, 102 DRV_CIPHER_ESSIV = 13, 103 DRV_CIPHER_BITLOCKER = 14, 104 DRV_CIPHER_RESERVE32B = S32_MAX 105 }; 106 107 enum drv_hash_mode { 108 DRV_HASH_NULL = -1, 109 DRV_HASH_SHA1 = 0, 110 DRV_HASH_SHA256 = 1, 111 DRV_HASH_SHA224 = 2, 112 DRV_HASH_SHA512 = 3, 113 DRV_HASH_SHA384 = 4, 114 DRV_HASH_MD5 = 5, 115 DRV_HASH_CBC_MAC = 6, 116 DRV_HASH_XCBC_MAC = 7, 117 DRV_HASH_CMAC = 8, 118 DRV_HASH_MODE_NUM = 9, 119 DRV_HASH_RESERVE32B = S32_MAX 120 }; 121 122 enum drv_hash_hw_mode { 123 DRV_HASH_HW_MD5 = 0, 124 DRV_HASH_HW_SHA1 = 1, 125 DRV_HASH_HW_SHA256 = 2, 126 DRV_HASH_HW_SHA224 = 10, 127 DRV_HASH_HW_SHA512 = 4, 128 DRV_HASH_HW_SHA384 = 12, 129 DRV_HASH_HW_GHASH = 6, 130 DRV_HASH_HW_RESERVE32B = S32_MAX 131 }; 132 133 #endif /* _CC_CRYPTO_CTX_H_ */ 134
