1 /*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/module.h>
35 #include <linux/vga_switcheroo.h>
36 #include <drm/drmP.h>
37 #include <drm/drm_edid.h>
38 #include <drm/drm_encoder.h>
39 #include <drm/drm_displayid.h>
40 #include <drm/drm_scdc_helper.h>
41
42 #include "drm_crtc_internal.h"
43
44 #define version_greater(edid, maj, min) \
45 (((edid)->version > (maj)) || \
46 ((edid)->version == (maj) && (edid)->revision > (min)))
47
48 #define EDID_EST_TIMINGS 16
49 #define EDID_STD_TIMINGS 8
50 #define EDID_DETAILED_TIMINGS 4
51
52 /*
53 * EDID blocks out in the wild have a variety of bugs, try to collect
54 * them here (note that userspace may work around broken monitors first,
55 * but fixes should make their way here so that the kernel "just works"
56 * on as many displays as possible).
57 */
58
59 /* First detailed mode wrong, use largest 60Hz mode */
60 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
61 /* Reported 135MHz pixel clock is too high, needs adjustment */
62 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
63 /* Prefer the largest mode at 75 Hz */
64 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
65 /* Detail timing is in cm not mm */
66 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
67 /* Detailed timing descriptors have bogus size values, so just take the
68 * maximum size and use that.
69 */
70 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
71 /* Monitor forgot to set the first detailed is preferred bit. */
72 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
73 /* use +hsync +vsync for detailed mode */
74 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
75 /* Force reduced-blanking timings for detailed modes */
76 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
77 /* Force 8bpc */
78 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
79 /* Force 12bpc */
80 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
81 /* Force 6bpc */
82 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
83 /* Force 10bpc */
84 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
85 /* Non desktop display (i.e. HMD) */
86 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
87
88 struct detailed_mode_closure {
89 struct drm_connector *connector;
90 struct edid *edid;
91 bool preferred;
92 u32 quirks;
93 int modes;
94 };
95
96 #define LEVEL_DMT 0
97 #define LEVEL_GTF 1
98 #define LEVEL_GTF2 2
99 #define LEVEL_CVT 3
100
101 static const struct edid_quirk {
102 char vendor[4];
103 int product_id;
104 u32 quirks;
105 } edid_quirk_list[] = {
106 /* Acer AL1706 */
107 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
108 /* Acer F51 */
109 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
110 /* Unknown Acer */
111 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
112
113 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
114 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
115
116 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
117 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC },
118
119 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
120 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
121
122 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
123 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC },
124
125 /* Belinea 10 15 55 */
126 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
127 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
128
129 /* Envision Peripherals, Inc. EN-7100e */
130 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
131 /* Envision EN2028 */
132 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
133
134 /* Funai Electronics PM36B */
135 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
136 EDID_QUIRK_DETAILED_IN_CM },
137
138 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
139 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
140
141 /* LG Philips LCD LP154W01-A5 */
142 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
143 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
144
145 /* Philips 107p5 CRT */
146 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
147
148 /* Proview AY765C */
149 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
150
151 /* Samsung SyncMaster 205BW. Note: irony */
152 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
153 /* Samsung SyncMaster 22[5-6]BW */
154 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
155 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
156
157 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
158 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
159
160 /* ViewSonic VA2026w */
161 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
162
163 /* Medion MD 30217 PG */
164 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
165
166 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
167 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
168
169 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
170 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
171
172 /* HTC Vive and Vive Pro VR Headsets */
173 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
174 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP },
175
176 /* Oculus Rift DK1, DK2, and CV1 VR Headsets */
177 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP },
178 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP },
179 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP },
180
181 /* Windows Mixed Reality Headsets */
182 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP },
183 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP },
184 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP },
185 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP },
186 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP },
187 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP },
188 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP },
189 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP },
190
191 /* Sony PlayStation VR Headset */
192 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP },
193 };
194
195 /*
196 * Autogenerated from the DMT spec.
197 * This table is copied from xfree86/modes/xf86EdidModes.c.
198 */
199 static const struct drm_display_mode drm_dmt_modes[] = {
200 /* 0x01 - 640x350@85Hz */
201 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
202 736, 832, 0, 350, 382, 385, 445, 0,
203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
204 /* 0x02 - 640x400@85Hz */
205 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
206 736, 832, 0, 400, 401, 404, 445, 0,
207 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
208 /* 0x03 - 720x400@85Hz */
209 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
210 828, 936, 0, 400, 401, 404, 446, 0,
211 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
212 /* 0x04 - 640x480@60Hz */
213 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
214 752, 800, 0, 480, 490, 492, 525, 0,
215 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
216 /* 0x05 - 640x480@72Hz */
217 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
218 704, 832, 0, 480, 489, 492, 520, 0,
219 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
220 /* 0x06 - 640x480@75Hz */
221 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
222 720, 840, 0, 480, 481, 484, 500, 0,
223 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
224 /* 0x07 - 640x480@85Hz */
225 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
226 752, 832, 0, 480, 481, 484, 509, 0,
227 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
228 /* 0x08 - 800x600@56Hz */
229 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
230 896, 1024, 0, 600, 601, 603, 625, 0,
231 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
232 /* 0x09 - 800x600@60Hz */
233 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
234 968, 1056, 0, 600, 601, 605, 628, 0,
235 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
236 /* 0x0a - 800x600@72Hz */
237 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
238 976, 1040, 0, 600, 637, 643, 666, 0,
239 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
240 /* 0x0b - 800x600@75Hz */
241 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
242 896, 1056, 0, 600, 601, 604, 625, 0,
243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
244 /* 0x0c - 800x600@85Hz */
245 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
246 896, 1048, 0, 600, 601, 604, 631, 0,
247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
248 /* 0x0d - 800x600@120Hz RB */
249 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
250 880, 960, 0, 600, 603, 607, 636, 0,
251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
252 /* 0x0e - 848x480@60Hz */
253 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
254 976, 1088, 0, 480, 486, 494, 517, 0,
255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
256 /* 0x0f - 1024x768@43Hz, interlace */
257 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
258 1208, 1264, 0, 768, 768, 776, 817, 0,
259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
260 DRM_MODE_FLAG_INTERLACE) },
261 /* 0x10 - 1024x768@60Hz */
262 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
263 1184, 1344, 0, 768, 771, 777, 806, 0,
264 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
265 /* 0x11 - 1024x768@70Hz */
266 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
267 1184, 1328, 0, 768, 771, 777, 806, 0,
268 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
269 /* 0x12 - 1024x768@75Hz */
270 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
271 1136, 1312, 0, 768, 769, 772, 800, 0,
272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
273 /* 0x13 - 1024x768@85Hz */
274 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
275 1168, 1376, 0, 768, 769, 772, 808, 0,
276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
277 /* 0x14 - 1024x768@120Hz RB */
278 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
279 1104, 1184, 0, 768, 771, 775, 813, 0,
280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
281 /* 0x15 - 1152x864@75Hz */
282 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
283 1344, 1600, 0, 864, 865, 868, 900, 0,
284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
285 /* 0x55 - 1280x720@60Hz */
286 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
287 1430, 1650, 0, 720, 725, 730, 750, 0,
288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
289 /* 0x16 - 1280x768@60Hz RB */
290 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
291 1360, 1440, 0, 768, 771, 778, 790, 0,
292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
293 /* 0x17 - 1280x768@60Hz */
294 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
295 1472, 1664, 0, 768, 771, 778, 798, 0,
296 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
297 /* 0x18 - 1280x768@75Hz */
298 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
299 1488, 1696, 0, 768, 771, 778, 805, 0,
300 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
301 /* 0x19 - 1280x768@85Hz */
302 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
303 1496, 1712, 0, 768, 771, 778, 809, 0,
304 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
305 /* 0x1a - 1280x768@120Hz RB */
306 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
307 1360, 1440, 0, 768, 771, 778, 813, 0,
308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
309 /* 0x1b - 1280x800@60Hz RB */
310 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
311 1360, 1440, 0, 800, 803, 809, 823, 0,
312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
313 /* 0x1c - 1280x800@60Hz */
314 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
315 1480, 1680, 0, 800, 803, 809, 831, 0,
316 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
317 /* 0x1d - 1280x800@75Hz */
318 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
319 1488, 1696, 0, 800, 803, 809, 838, 0,
320 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
321 /* 0x1e - 1280x800@85Hz */
322 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
323 1496, 1712, 0, 800, 803, 809, 843, 0,
324 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
325 /* 0x1f - 1280x800@120Hz RB */
326 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
327 1360, 1440, 0, 800, 803, 809, 847, 0,
328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
329 /* 0x20 - 1280x960@60Hz */
330 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
331 1488, 1800, 0, 960, 961, 964, 1000, 0,
332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
333 /* 0x21 - 1280x960@85Hz */
334 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
335 1504, 1728, 0, 960, 961, 964, 1011, 0,
336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
337 /* 0x22 - 1280x960@120Hz RB */
338 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
339 1360, 1440, 0, 960, 963, 967, 1017, 0,
340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
341 /* 0x23 - 1280x1024@60Hz */
342 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
343 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
345 /* 0x24 - 1280x1024@75Hz */
346 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
347 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
349 /* 0x25 - 1280x1024@85Hz */
350 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
351 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
353 /* 0x26 - 1280x1024@120Hz RB */
354 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
355 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
357 /* 0x27 - 1360x768@60Hz */
358 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
359 1536, 1792, 0, 768, 771, 777, 795, 0,
360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
361 /* 0x28 - 1360x768@120Hz RB */
362 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
363 1440, 1520, 0, 768, 771, 776, 813, 0,
364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
365 /* 0x51 - 1366x768@60Hz */
366 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
367 1579, 1792, 0, 768, 771, 774, 798, 0,
368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
369 /* 0x56 - 1366x768@60Hz */
370 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
371 1436, 1500, 0, 768, 769, 772, 800, 0,
372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
373 /* 0x29 - 1400x1050@60Hz RB */
374 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
375 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
377 /* 0x2a - 1400x1050@60Hz */
378 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
379 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
380 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
381 /* 0x2b - 1400x1050@75Hz */
382 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
383 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
384 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
385 /* 0x2c - 1400x1050@85Hz */
386 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
387 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
388 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
389 /* 0x2d - 1400x1050@120Hz RB */
390 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
391 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
393 /* 0x2e - 1440x900@60Hz RB */
394 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
395 1520, 1600, 0, 900, 903, 909, 926, 0,
396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
397 /* 0x2f - 1440x900@60Hz */
398 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
399 1672, 1904, 0, 900, 903, 909, 934, 0,
400 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
401 /* 0x30 - 1440x900@75Hz */
402 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
403 1688, 1936, 0, 900, 903, 909, 942, 0,
404 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
405 /* 0x31 - 1440x900@85Hz */
406 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
407 1696, 1952, 0, 900, 903, 909, 948, 0,
408 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
409 /* 0x32 - 1440x900@120Hz RB */
410 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
411 1520, 1600, 0, 900, 903, 909, 953, 0,
412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
413 /* 0x53 - 1600x900@60Hz */
414 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
415 1704, 1800, 0, 900, 901, 904, 1000, 0,
416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
417 /* 0x33 - 1600x1200@60Hz */
418 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
419 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
421 /* 0x34 - 1600x1200@65Hz */
422 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
423 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
424 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
425 /* 0x35 - 1600x1200@70Hz */
426 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
427 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
428 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
429 /* 0x36 - 1600x1200@75Hz */
430 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
431 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
432 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
433 /* 0x37 - 1600x1200@85Hz */
434 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
435 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
437 /* 0x38 - 1600x1200@120Hz RB */
438 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
439 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
441 /* 0x39 - 1680x1050@60Hz RB */
442 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
443 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
445 /* 0x3a - 1680x1050@60Hz */
446 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
447 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
448 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
449 /* 0x3b - 1680x1050@75Hz */
450 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
451 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
452 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
453 /* 0x3c - 1680x1050@85Hz */
454 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
455 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
456 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
457 /* 0x3d - 1680x1050@120Hz RB */
458 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
459 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
461 /* 0x3e - 1792x1344@60Hz */
462 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
463 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
464 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
465 /* 0x3f - 1792x1344@75Hz */
466 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
467 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
468 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
469 /* 0x40 - 1792x1344@120Hz RB */
470 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
471 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
473 /* 0x41 - 1856x1392@60Hz */
474 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
475 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
476 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
477 /* 0x42 - 1856x1392@75Hz */
478 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
479 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
480 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
481 /* 0x43 - 1856x1392@120Hz RB */
482 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
483 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
485 /* 0x52 - 1920x1080@60Hz */
486 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
487 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
488 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
489 /* 0x44 - 1920x1200@60Hz RB */
490 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
491 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
492 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
493 /* 0x45 - 1920x1200@60Hz */
494 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
495 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
496 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
497 /* 0x46 - 1920x1200@75Hz */
498 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
499 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
500 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
501 /* 0x47 - 1920x1200@85Hz */
502 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
503 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
504 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
505 /* 0x48 - 1920x1200@120Hz RB */
506 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
507 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
509 /* 0x49 - 1920x1440@60Hz */
510 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
511 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
512 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
513 /* 0x4a - 1920x1440@75Hz */
514 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
515 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
516 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
517 /* 0x4b - 1920x1440@120Hz RB */
518 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
519 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
521 /* 0x54 - 2048x1152@60Hz */
522 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
523 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
524 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
525 /* 0x4c - 2560x1600@60Hz RB */
526 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
527 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
529 /* 0x4d - 2560x1600@60Hz */
530 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
531 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
532 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
533 /* 0x4e - 2560x1600@75Hz */
534 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
535 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
536 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
537 /* 0x4f - 2560x1600@85Hz */
538 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
539 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
541 /* 0x50 - 2560x1600@120Hz RB */
542 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
543 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
544 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
545 /* 0x57 - 4096x2160@60Hz RB */
546 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
547 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
549 /* 0x58 - 4096x2160@59.94Hz RB */
550 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
551 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
553 };
554
555 /*
556 * These more or less come from the DMT spec. The 720x400 modes are
557 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
558 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
559 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
560 * mode.
561 *
562 * The DMT modes have been fact-checked; the rest are mild guesses.
563 */
564 static const struct drm_display_mode edid_est_modes[] = {
565 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
566 968, 1056, 0, 600, 601, 605, 628, 0,
567 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
568 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
569 896, 1024, 0, 600, 601, 603, 625, 0,
570 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
571 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
572 720, 840, 0, 480, 481, 484, 500, 0,
573 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
574 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
575 704, 832, 0, 480, 489, 492, 520, 0,
576 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
577 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
578 768, 864, 0, 480, 483, 486, 525, 0,
579 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
580 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
581 752, 800, 0, 480, 490, 492, 525, 0,
582 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
583 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
584 846, 900, 0, 400, 421, 423, 449, 0,
585 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
586 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
587 846, 900, 0, 400, 412, 414, 449, 0,
588 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
589 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
590 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
592 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
593 1136, 1312, 0, 768, 769, 772, 800, 0,
594 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
595 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
596 1184, 1328, 0, 768, 771, 777, 806, 0,
597 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
598 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
599 1184, 1344, 0, 768, 771, 777, 806, 0,
600 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
601 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
602 1208, 1264, 0, 768, 768, 776, 817, 0,
603 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
604 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
605 928, 1152, 0, 624, 625, 628, 667, 0,
606 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
607 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
608 896, 1056, 0, 600, 601, 604, 625, 0,
609 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
610 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
611 976, 1040, 0, 600, 637, 643, 666, 0,
612 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
613 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
614 1344, 1600, 0, 864, 865, 868, 900, 0,
615 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
616 };
617
618 struct minimode {
619 short w;
620 short h;
621 short r;
622 short rb;
623 };
624
625 static const struct minimode est3_modes[] = {
626 /* byte 6 */
627 { 640, 350, 85, 0 },
628 { 640, 400, 85, 0 },
629 { 720, 400, 85, 0 },
630 { 640, 480, 85, 0 },
631 { 848, 480, 60, 0 },
632 { 800, 600, 85, 0 },
633 { 1024, 768, 85, 0 },
634 { 1152, 864, 75, 0 },
635 /* byte 7 */
636 { 1280, 768, 60, 1 },
637 { 1280, 768, 60, 0 },
638 { 1280, 768, 75, 0 },
639 { 1280, 768, 85, 0 },
640 { 1280, 960, 60, 0 },
641 { 1280, 960, 85, 0 },
642 { 1280, 1024, 60, 0 },
643 { 1280, 1024, 85, 0 },
644 /* byte 8 */
645 { 1360, 768, 60, 0 },
646 { 1440, 900, 60, 1 },
647 { 1440, 900, 60, 0 },
648 { 1440, 900, 75, 0 },
649 { 1440, 900, 85, 0 },
650 { 1400, 1050, 60, 1 },
651 { 1400, 1050, 60, 0 },
652 { 1400, 1050, 75, 0 },
653 /* byte 9 */
654 { 1400, 1050, 85, 0 },
655 { 1680, 1050, 60, 1 },
656 { 1680, 1050, 60, 0 },
657 { 1680, 1050, 75, 0 },
658 { 1680, 1050, 85, 0 },
659 { 1600, 1200, 60, 0 },
660 { 1600, 1200, 65, 0 },
661 { 1600, 1200, 70, 0 },
662 /* byte 10 */
663 { 1600, 1200, 75, 0 },
664 { 1600, 1200, 85, 0 },
665 { 1792, 1344, 60, 0 },
666 { 1792, 1344, 75, 0 },
667 { 1856, 1392, 60, 0 },
668 { 1856, 1392, 75, 0 },
669 { 1920, 1200, 60, 1 },
670 { 1920, 1200, 60, 0 },
671 /* byte 11 */
672 { 1920, 1200, 75, 0 },
673 { 1920, 1200, 85, 0 },
674 { 1920, 1440, 60, 0 },
675 { 1920, 1440, 75, 0 },
676 };
677
678 static const struct minimode extra_modes[] = {
679 { 1024, 576, 60, 0 },
680 { 1366, 768, 60, 0 },
681 { 1600, 900, 60, 0 },
682 { 1680, 945, 60, 0 },
683 { 1920, 1080, 60, 0 },
684 { 2048, 1152, 60, 0 },
685 { 2048, 1536, 60, 0 },
686 };
687
688 /*
689 * Probably taken from CEA-861 spec.
690 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
691 *
692 * Index using the VIC.
693 */
694 static const struct drm_display_mode edid_cea_modes[] = {
695 /* 0 - dummy, VICs start at 1 */
696 { },
697 /* 1 - 640x480@60Hz 4:3 */
698 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
699 752, 800, 0, 480, 490, 492, 525, 0,
700 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
701 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
702 /* 2 - 720x480@60Hz 4:3 */
703 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
704 798, 858, 0, 480, 489, 495, 525, 0,
705 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
706 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
707 /* 3 - 720x480@60Hz 16:9 */
708 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
709 798, 858, 0, 480, 489, 495, 525, 0,
710 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
711 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
712 /* 4 - 1280x720@60Hz 16:9 */
713 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
714 1430, 1650, 0, 720, 725, 730, 750, 0,
715 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
716 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
717 /* 5 - 1920x1080i@60Hz 16:9 */
718 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
719 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
720 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
721 DRM_MODE_FLAG_INTERLACE),
722 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
723 /* 6 - 720(1440)x480i@60Hz 4:3 */
724 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
725 801, 858, 0, 480, 488, 494, 525, 0,
726 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
727 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
728 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
729 /* 7 - 720(1440)x480i@60Hz 16:9 */
730 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
731 801, 858, 0, 480, 488, 494, 525, 0,
732 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
733 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
734 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
735 /* 8 - 720(1440)x240@60Hz 4:3 */
736 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
737 801, 858, 0, 240, 244, 247, 262, 0,
738 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
739 DRM_MODE_FLAG_DBLCLK),
740 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
741 /* 9 - 720(1440)x240@60Hz 16:9 */
742 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
743 801, 858, 0, 240, 244, 247, 262, 0,
744 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
745 DRM_MODE_FLAG_DBLCLK),
746 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
747 /* 10 - 2880x480i@60Hz 4:3 */
748 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
749 3204, 3432, 0, 480, 488, 494, 525, 0,
750 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
751 DRM_MODE_FLAG_INTERLACE),
752 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
753 /* 11 - 2880x480i@60Hz 16:9 */
754 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
755 3204, 3432, 0, 480, 488, 494, 525, 0,
756 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
757 DRM_MODE_FLAG_INTERLACE),
758 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
759 /* 12 - 2880x240@60Hz 4:3 */
760 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
761 3204, 3432, 0, 240, 244, 247, 262, 0,
762 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
763 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
764 /* 13 - 2880x240@60Hz 16:9 */
765 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
766 3204, 3432, 0, 240, 244, 247, 262, 0,
767 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
768 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
769 /* 14 - 1440x480@60Hz 4:3 */
770 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
771 1596, 1716, 0, 480, 489, 495, 525, 0,
772 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
773 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
774 /* 15 - 1440x480@60Hz 16:9 */
775 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
776 1596, 1716, 0, 480, 489, 495, 525, 0,
777 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
778 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
779 /* 16 - 1920x1080@60Hz 16:9 */
780 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
781 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
782 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
783 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
784 /* 17 - 720x576@50Hz 4:3 */
785 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
786 796, 864, 0, 576, 581, 586, 625, 0,
787 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
788 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
789 /* 18 - 720x576@50Hz 16:9 */
790 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
791 796, 864, 0, 576, 581, 586, 625, 0,
792 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
793 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
794 /* 19 - 1280x720@50Hz 16:9 */
795 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
796 1760, 1980, 0, 720, 725, 730, 750, 0,
797 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
798 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
799 /* 20 - 1920x1080i@50Hz 16:9 */
800 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
801 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
802 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
803 DRM_MODE_FLAG_INTERLACE),
804 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
805 /* 21 - 720(1440)x576i@50Hz 4:3 */
806 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
807 795, 864, 0, 576, 580, 586, 625, 0,
808 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
809 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
810 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
811 /* 22 - 720(1440)x576i@50Hz 16:9 */
812 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
813 795, 864, 0, 576, 580, 586, 625, 0,
814 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
815 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
816 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
817 /* 23 - 720(1440)x288@50Hz 4:3 */
818 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
819 795, 864, 0, 288, 290, 293, 312, 0,
820 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
821 DRM_MODE_FLAG_DBLCLK),
822 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
823 /* 24 - 720(1440)x288@50Hz 16:9 */
824 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
825 795, 864, 0, 288, 290, 293, 312, 0,
826 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
827 DRM_MODE_FLAG_DBLCLK),
828 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
829 /* 25 - 2880x576i@50Hz 4:3 */
830 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
831 3180, 3456, 0, 576, 580, 586, 625, 0,
832 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
833 DRM_MODE_FLAG_INTERLACE),
834 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
835 /* 26 - 2880x576i@50Hz 16:9 */
836 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
837 3180, 3456, 0, 576, 580, 586, 625, 0,
838 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
839 DRM_MODE_FLAG_INTERLACE),
840 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
841 /* 27 - 2880x288@50Hz 4:3 */
842 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
843 3180, 3456, 0, 288, 290, 293, 312, 0,
844 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
845 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
846 /* 28 - 2880x288@50Hz 16:9 */
847 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
848 3180, 3456, 0, 288, 290, 293, 312, 0,
849 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
850 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
851 /* 29 - 1440x576@50Hz 4:3 */
852 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
853 1592, 1728, 0, 576, 581, 586, 625, 0,
854 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
855 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
856 /* 30 - 1440x576@50Hz 16:9 */
857 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
858 1592, 1728, 0, 576, 581, 586, 625, 0,
859 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
860 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
861 /* 31 - 1920x1080@50Hz 16:9 */
862 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
863 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
864 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
865 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
866 /* 32 - 1920x1080@24Hz 16:9 */
867 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
868 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
869 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
870 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
871 /* 33 - 1920x1080@25Hz 16:9 */
872 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
873 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
874 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
875 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
876 /* 34 - 1920x1080@30Hz 16:9 */
877 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
878 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
879 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
880 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
881 /* 35 - 2880x480@60Hz 4:3 */
882 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
883 3192, 3432, 0, 480, 489, 495, 525, 0,
884 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
885 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
886 /* 36 - 2880x480@60Hz 16:9 */
887 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
888 3192, 3432, 0, 480, 489, 495, 525, 0,
889 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
890 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
891 /* 37 - 2880x576@50Hz 4:3 */
892 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
893 3184, 3456, 0, 576, 581, 586, 625, 0,
894 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
895 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
896 /* 38 - 2880x576@50Hz 16:9 */
897 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
898 3184, 3456, 0, 576, 581, 586, 625, 0,
899 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
900 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
901 /* 39 - 1920x1080i@50Hz 16:9 */
902 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
903 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
904 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
905 DRM_MODE_FLAG_INTERLACE),
906 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
907 /* 40 - 1920x1080i@100Hz 16:9 */
908 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
909 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
910 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
911 DRM_MODE_FLAG_INTERLACE),
912 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
913 /* 41 - 1280x720@100Hz 16:9 */
914 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
915 1760, 1980, 0, 720, 725, 730, 750, 0,
916 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
917 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
918 /* 42 - 720x576@100Hz 4:3 */
919 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
920 796, 864, 0, 576, 581, 586, 625, 0,
921 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
922 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
923 /* 43 - 720x576@100Hz 16:9 */
924 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
925 796, 864, 0, 576, 581, 586, 625, 0,
926 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
927 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
928 /* 44 - 720(1440)x576i@100Hz 4:3 */
929 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
930 795, 864, 0, 576, 580, 586, 625, 0,
931 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
932 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
933 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
934 /* 45 - 720(1440)x576i@100Hz 16:9 */
935 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
936 795, 864, 0, 576, 580, 586, 625, 0,
937 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
938 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
939 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
940 /* 46 - 1920x1080i@120Hz 16:9 */
941 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
942 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
943 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
944 DRM_MODE_FLAG_INTERLACE),
945 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
946 /* 47 - 1280x720@120Hz 16:9 */
947 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
948 1430, 1650, 0, 720, 725, 730, 750, 0,
949 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
950 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
951 /* 48 - 720x480@120Hz 4:3 */
952 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
953 798, 858, 0, 480, 489, 495, 525, 0,
954 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
955 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
956 /* 49 - 720x480@120Hz 16:9 */
957 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
958 798, 858, 0, 480, 489, 495, 525, 0,
959 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
960 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
961 /* 50 - 720(1440)x480i@120Hz 4:3 */
962 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
963 801, 858, 0, 480, 488, 494, 525, 0,
964 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
965 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
966 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
967 /* 51 - 720(1440)x480i@120Hz 16:9 */
968 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
969 801, 858, 0, 480, 488, 494, 525, 0,
970 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
971 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
972 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
973 /* 52 - 720x576@200Hz 4:3 */
974 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
975 796, 864, 0, 576, 581, 586, 625, 0,
976 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
977 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
978 /* 53 - 720x576@200Hz 16:9 */
979 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
980 796, 864, 0, 576, 581, 586, 625, 0,
981 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
982 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
983 /* 54 - 720(1440)x576i@200Hz 4:3 */
984 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
985 795, 864, 0, 576, 580, 586, 625, 0,
986 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
987 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
988 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
989 /* 55 - 720(1440)x576i@200Hz 16:9 */
990 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
991 795, 864, 0, 576, 580, 586, 625, 0,
992 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
993 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
994 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
995 /* 56 - 720x480@240Hz 4:3 */
996 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
997 798, 858, 0, 480, 489, 495, 525, 0,
998 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
999 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1000 /* 57 - 720x480@240Hz 16:9 */
1001 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1002 798, 858, 0, 480, 489, 495, 525, 0,
1003 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1004 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1005 /* 58 - 720(1440)x480i@240Hz 4:3 */
1006 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1007 801, 858, 0, 480, 488, 494, 525, 0,
1008 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1009 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1010 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1011 /* 59 - 720(1440)x480i@240Hz 16:9 */
1012 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1013 801, 858, 0, 480, 488, 494, 525, 0,
1014 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1015 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1016 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1017 /* 60 - 1280x720@24Hz 16:9 */
1018 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1019 3080, 3300, 0, 720, 725, 730, 750, 0,
1020 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1021 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1022 /* 61 - 1280x720@25Hz 16:9 */
1023 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1024 3740, 3960, 0, 720, 725, 730, 750, 0,
1025 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1026 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1027 /* 62 - 1280x720@30Hz 16:9 */
1028 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1029 3080, 3300, 0, 720, 725, 730, 750, 0,
1030 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1031 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1032 /* 63 - 1920x1080@120Hz 16:9 */
1033 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1034 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1035 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1036 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1037 /* 64 - 1920x1080@100Hz 16:9 */
1038 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1039 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1040 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1041 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1042 /* 65 - 1280x720@24Hz 64:27 */
1043 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1044 3080, 3300, 0, 720, 725, 730, 750, 0,
1045 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1046 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1047 /* 66 - 1280x720@25Hz 64:27 */
1048 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1049 3740, 3960, 0, 720, 725, 730, 750, 0,
1050 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1051 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1052 /* 67 - 1280x720@30Hz 64:27 */
1053 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1054 3080, 3300, 0, 720, 725, 730, 750, 0,
1055 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1056 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1057 /* 68 - 1280x720@50Hz 64:27 */
1058 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1059 1760, 1980, 0, 720, 725, 730, 750, 0,
1060 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1061 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1062 /* 69 - 1280x720@60Hz 64:27 */
1063 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1064 1430, 1650, 0, 720, 725, 730, 750, 0,
1065 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1066 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1067 /* 70 - 1280x720@100Hz 64:27 */
1068 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1069 1760, 1980, 0, 720, 725, 730, 750, 0,
1070 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1071 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1072 /* 71 - 1280x720@120Hz 64:27 */
1073 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1074 1430, 1650, 0, 720, 725, 730, 750, 0,
1075 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1076 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1077 /* 72 - 1920x1080@24Hz 64:27 */
1078 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1079 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1080 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1081 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1082 /* 73 - 1920x1080@25Hz 64:27 */
1083 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1084 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1085 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1086 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1087 /* 74 - 1920x1080@30Hz 64:27 */
1088 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1089 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1090 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1091 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1092 /* 75 - 1920x1080@50Hz 64:27 */
1093 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1094 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1095 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1096 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1097 /* 76 - 1920x1080@60Hz 64:27 */
1098 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1099 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1100 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1101 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1102 /* 77 - 1920x1080@100Hz 64:27 */
1103 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1104 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1105 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1106 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1107 /* 78 - 1920x1080@120Hz 64:27 */
1108 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1109 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1110 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1111 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1112 /* 79 - 1680x720@24Hz 64:27 */
1113 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1114 3080, 3300, 0, 720, 725, 730, 750, 0,
1115 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1116 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1117 /* 80 - 1680x720@25Hz 64:27 */
1118 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1119 2948, 3168, 0, 720, 725, 730, 750, 0,
1120 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1121 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1122 /* 81 - 1680x720@30Hz 64:27 */
1123 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1124 2420, 2640, 0, 720, 725, 730, 750, 0,
1125 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1126 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1127 /* 82 - 1680x720@50Hz 64:27 */
1128 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1129 1980, 2200, 0, 720, 725, 730, 750, 0,
1130 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1131 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1132 /* 83 - 1680x720@60Hz 64:27 */
1133 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1134 1980, 2200, 0, 720, 725, 730, 750, 0,
1135 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1136 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1137 /* 84 - 1680x720@100Hz 64:27 */
1138 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1139 1780, 2000, 0, 720, 725, 730, 825, 0,
1140 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1141 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1142 /* 85 - 1680x720@120Hz 64:27 */
1143 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1144 1780, 2000, 0, 720, 725, 730, 825, 0,
1145 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1146 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1147 /* 86 - 2560x1080@24Hz 64:27 */
1148 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1149 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1150 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1151 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1152 /* 87 - 2560x1080@25Hz 64:27 */
1153 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1154 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1155 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1156 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1157 /* 88 - 2560x1080@30Hz 64:27 */
1158 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1159 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1160 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1161 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1162 /* 89 - 2560x1080@50Hz 64:27 */
1163 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1164 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1165 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1166 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1167 /* 90 - 2560x1080@60Hz 64:27 */
1168 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1169 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1170 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1171 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1172 /* 91 - 2560x1080@100Hz 64:27 */
1173 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1174 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1175 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1176 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1177 /* 92 - 2560x1080@120Hz 64:27 */
1178 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1179 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1180 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1181 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1182 /* 93 - 3840x2160@24Hz 16:9 */
1183 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1184 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1186 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1187 /* 94 - 3840x2160@25Hz 16:9 */
1188 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1189 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1191 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1192 /* 95 - 3840x2160@30Hz 16:9 */
1193 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1194 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1196 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1197 /* 96 - 3840x2160@50Hz 16:9 */
1198 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1199 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1201 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1202 /* 97 - 3840x2160@60Hz 16:9 */
1203 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1204 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1206 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1207 /* 98 - 4096x2160@24Hz 256:135 */
1208 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1209 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1211 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1212 /* 99 - 4096x2160@25Hz 256:135 */
1213 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1214 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1216 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1217 /* 100 - 4096x2160@30Hz 256:135 */
1218 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1219 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1221 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1222 /* 101 - 4096x2160@50Hz 256:135 */
1223 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1224 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1225 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1226 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1227 /* 102 - 4096x2160@60Hz 256:135 */
1228 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1229 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1231 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1232 /* 103 - 3840x2160@24Hz 64:27 */
1233 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1234 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1235 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1236 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1237 /* 104 - 3840x2160@25Hz 64:27 */
1238 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1239 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1241 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1242 /* 105 - 3840x2160@30Hz 64:27 */
1243 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1244 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1246 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1247 /* 106 - 3840x2160@50Hz 64:27 */
1248 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1249 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1251 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1252 /* 107 - 3840x2160@60Hz 64:27 */
1253 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1254 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1256 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1257 };
1258
1259 /*
1260 * HDMI 1.4 4k modes. Index using the VIC.
1261 */
1262 static const struct drm_display_mode edid_4k_modes[] = {
1263 /* 0 - dummy, VICs start at 1 */
1264 { },
1265 /* 1 - 3840x2160@30Hz */
1266 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1267 3840, 4016, 4104, 4400, 0,
1268 2160, 2168, 2178, 2250, 0,
1269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1270 .vrefresh = 30, },
1271 /* 2 - 3840x2160@25Hz */
1272 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1273 3840, 4896, 4984, 5280, 0,
1274 2160, 2168, 2178, 2250, 0,
1275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1276 .vrefresh = 25, },
1277 /* 3 - 3840x2160@24Hz */
1278 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1279 3840, 5116, 5204, 5500, 0,
1280 2160, 2168, 2178, 2250, 0,
1281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1282 .vrefresh = 24, },
1283 /* 4 - 4096x2160@24Hz (SMPTE) */
1284 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1285 4096, 5116, 5204, 5500, 0,
1286 2160, 2168, 2178, 2250, 0,
1287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1288 .vrefresh = 24, },
1289 };
1290
1291 /*** DDC fetch and block validation ***/
1292
1293 static const u8 edid_header[] = {
1294 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1295 };
1296
1297 /**
1298 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1299 * @raw_edid: pointer to raw base EDID block
1300 *
1301 * Sanity check the header of the base EDID block.
1302 *
1303 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1304 */
drm_edid_header_is_valid(const u8 * raw_edid)1305 int drm_edid_header_is_valid(const u8 *raw_edid)
1306 {
1307 int i, score = 0;
1308
1309 for (i = 0; i < sizeof(edid_header); i++)
1310 if (raw_edid[i] == edid_header[i])
1311 score++;
1312
1313 return score;
1314 }
1315 EXPORT_SYMBOL(drm_edid_header_is_valid);
1316
1317 static int edid_fixup __read_mostly = 6;
1318 module_param_named(edid_fixup, edid_fixup, int, 0400);
1319 MODULE_PARM_DESC(edid_fixup,
1320 "Minimum number of valid EDID header bytes (0-8, default 6)");
1321
1322 static void drm_get_displayid(struct drm_connector *connector,
1323 struct edid *edid);
1324
drm_edid_block_checksum(const u8 * raw_edid)1325 static int drm_edid_block_checksum(const u8 *raw_edid)
1326 {
1327 int i;
1328 u8 csum = 0;
1329 for (i = 0; i < EDID_LENGTH; i++)
1330 csum += raw_edid[i];
1331
1332 return csum;
1333 }
1334
drm_edid_is_zero(const u8 * in_edid,int length)1335 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1336 {
1337 if (memchr_inv(in_edid, 0, length))
1338 return false;
1339
1340 return true;
1341 }
1342
1343 /**
1344 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1345 * @raw_edid: pointer to raw EDID block
1346 * @block: type of block to validate (0 for base, extension otherwise)
1347 * @print_bad_edid: if true, dump bad EDID blocks to the console
1348 * @edid_corrupt: if true, the header or checksum is invalid
1349 *
1350 * Validate a base or extension EDID block and optionally dump bad blocks to
1351 * the console.
1352 *
1353 * Return: True if the block is valid, false otherwise.
1354 */
drm_edid_block_valid(u8 * raw_edid,int block,bool print_bad_edid,bool * edid_corrupt)1355 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1356 bool *edid_corrupt)
1357 {
1358 u8 csum;
1359 struct edid *edid = (struct edid *)raw_edid;
1360
1361 if (WARN_ON(!raw_edid))
1362 return false;
1363
1364 if (edid_fixup > 8 || edid_fixup < 0)
1365 edid_fixup = 6;
1366
1367 if (block == 0) {
1368 int score = drm_edid_header_is_valid(raw_edid);
1369 if (score == 8) {
1370 if (edid_corrupt)
1371 *edid_corrupt = false;
1372 } else if (score >= edid_fixup) {
1373 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1374 * The corrupt flag needs to be set here otherwise, the
1375 * fix-up code here will correct the problem, the
1376 * checksum is correct and the test fails
1377 */
1378 if (edid_corrupt)
1379 *edid_corrupt = true;
1380 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1381 memcpy(raw_edid, edid_header, sizeof(edid_header));
1382 } else {
1383 if (edid_corrupt)
1384 *edid_corrupt = true;
1385 goto bad;
1386 }
1387 }
1388
1389 csum = drm_edid_block_checksum(raw_edid);
1390 if (csum) {
1391 if (edid_corrupt)
1392 *edid_corrupt = true;
1393
1394 /* allow CEA to slide through, switches mangle this */
1395 if (raw_edid[0] == CEA_EXT) {
1396 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1397 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1398 } else {
1399 if (print_bad_edid)
1400 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1401
1402 goto bad;
1403 }
1404 }
1405
1406 /* per-block-type checks */
1407 switch (raw_edid[0]) {
1408 case 0: /* base */
1409 if (edid->version != 1) {
1410 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
1411 goto bad;
1412 }
1413
1414 if (edid->revision > 4)
1415 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1416 break;
1417
1418 default:
1419 break;
1420 }
1421
1422 return true;
1423
1424 bad:
1425 if (print_bad_edid) {
1426 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1427 pr_notice("EDID block is all zeroes\n");
1428 } else {
1429 pr_notice("Raw EDID:\n");
1430 print_hex_dump(KERN_NOTICE,
1431 " \t", DUMP_PREFIX_NONE, 16, 1,
1432 raw_edid, EDID_LENGTH, false);
1433 }
1434 }
1435 return false;
1436 }
1437 EXPORT_SYMBOL(drm_edid_block_valid);
1438
1439 /**
1440 * drm_edid_is_valid - sanity check EDID data
1441 * @edid: EDID data
1442 *
1443 * Sanity-check an entire EDID record (including extensions)
1444 *
1445 * Return: True if the EDID data is valid, false otherwise.
1446 */
drm_edid_is_valid(struct edid * edid)1447 bool drm_edid_is_valid(struct edid *edid)
1448 {
1449 int i;
1450 u8 *raw = (u8 *)edid;
1451
1452 if (!edid)
1453 return false;
1454
1455 for (i = 0; i <= edid->extensions; i++)
1456 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1457 return false;
1458
1459 return true;
1460 }
1461 EXPORT_SYMBOL(drm_edid_is_valid);
1462
1463 #define DDC_SEGMENT_ADDR 0x30
1464 /**
1465 * drm_do_probe_ddc_edid() - get EDID information via I2C
1466 * @data: I2C device adapter
1467 * @buf: EDID data buffer to be filled
1468 * @block: 128 byte EDID block to start fetching from
1469 * @len: EDID data buffer length to fetch
1470 *
1471 * Try to fetch EDID information by calling I2C driver functions.
1472 *
1473 * Return: 0 on success or -1 on failure.
1474 */
1475 static int
drm_do_probe_ddc_edid(void * data,u8 * buf,unsigned int block,size_t len)1476 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1477 {
1478 struct i2c_adapter *adapter = data;
1479 unsigned char start = block * EDID_LENGTH;
1480 unsigned char segment = block >> 1;
1481 unsigned char xfers = segment ? 3 : 2;
1482 int ret, retries = 5;
1483
1484 /*
1485 * The core I2C driver will automatically retry the transfer if the
1486 * adapter reports EAGAIN. However, we find that bit-banging transfers
1487 * are susceptible to errors under a heavily loaded machine and
1488 * generate spurious NAKs and timeouts. Retrying the transfer
1489 * of the individual block a few times seems to overcome this.
1490 */
1491 do {
1492 struct i2c_msg msgs[] = {
1493 {
1494 .addr = DDC_SEGMENT_ADDR,
1495 .flags = 0,
1496 .len = 1,
1497 .buf = &segment,
1498 }, {
1499 .addr = DDC_ADDR,
1500 .flags = 0,
1501 .len = 1,
1502 .buf = &start,
1503 }, {
1504 .addr = DDC_ADDR,
1505 .flags = I2C_M_RD,
1506 .len = len,
1507 .buf = buf,
1508 }
1509 };
1510
1511 /*
1512 * Avoid sending the segment addr to not upset non-compliant
1513 * DDC monitors.
1514 */
1515 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1516
1517 if (ret == -ENXIO) {
1518 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1519 adapter->name);
1520 break;
1521 }
1522 } while (ret != xfers && --retries);
1523
1524 return ret == xfers ? 0 : -1;
1525 }
1526
connector_bad_edid(struct drm_connector * connector,u8 * edid,int num_blocks)1527 static void connector_bad_edid(struct drm_connector *connector,
1528 u8 *edid, int num_blocks)
1529 {
1530 int i;
1531
1532 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
1533 return;
1534
1535 dev_warn(connector->dev->dev,
1536 "%s: EDID is invalid:\n",
1537 connector->name);
1538 for (i = 0; i < num_blocks; i++) {
1539 u8 *block = edid + i * EDID_LENGTH;
1540 char prefix[20];
1541
1542 if (drm_edid_is_zero(block, EDID_LENGTH))
1543 sprintf(prefix, "\t[%02x] ZERO ", i);
1544 else if (!drm_edid_block_valid(block, i, false, NULL))
1545 sprintf(prefix, "\t[%02x] BAD ", i);
1546 else
1547 sprintf(prefix, "\t[%02x] GOOD ", i);
1548
1549 print_hex_dump(KERN_WARNING,
1550 prefix, DUMP_PREFIX_NONE, 16, 1,
1551 block, EDID_LENGTH, false);
1552 }
1553 }
1554
1555 /**
1556 * drm_do_get_edid - get EDID data using a custom EDID block read function
1557 * @connector: connector we're probing
1558 * @get_edid_block: EDID block read function
1559 * @data: private data passed to the block read function
1560 *
1561 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1562 * exposes a different interface to read EDID blocks this function can be used
1563 * to get EDID data using a custom block read function.
1564 *
1565 * As in the general case the DDC bus is accessible by the kernel at the I2C
1566 * level, drivers must make all reasonable efforts to expose it as an I2C
1567 * adapter and use drm_get_edid() instead of abusing this function.
1568 *
1569 * The EDID may be overridden using debugfs override_edid or firmare EDID
1570 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1571 * order. Having either of them bypasses actual EDID reads.
1572 *
1573 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1574 */
drm_do_get_edid(struct drm_connector * connector,int (* get_edid_block)(void * data,u8 * buf,unsigned int block,size_t len),void * data)1575 struct edid *drm_do_get_edid(struct drm_connector *connector,
1576 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1577 size_t len),
1578 void *data)
1579 {
1580 int i, j = 0, valid_extensions = 0;
1581 u8 *edid, *new;
1582 struct edid *override = NULL;
1583
1584 if (connector->override_edid)
1585 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1586
1587 if (!override)
1588 override = drm_load_edid_firmware(connector);
1589
1590 if (!IS_ERR_OR_NULL(override))
1591 return override;
1592
1593 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1594 return NULL;
1595
1596 /* base block fetch */
1597 for (i = 0; i < 4; i++) {
1598 if (get_edid_block(data, edid, 0, EDID_LENGTH))
1599 goto out;
1600 if (drm_edid_block_valid(edid, 0, false,
1601 &connector->edid_corrupt))
1602 break;
1603 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1604 connector->null_edid_counter++;
1605 goto carp;
1606 }
1607 }
1608 if (i == 4)
1609 goto carp;
1610
1611 /* if there's no extensions, we're done */
1612 valid_extensions = edid[0x7e];
1613 if (valid_extensions == 0)
1614 return (struct edid *)edid;
1615
1616 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1617 if (!new)
1618 goto out;
1619 edid = new;
1620
1621 for (j = 1; j <= edid[0x7e]; j++) {
1622 u8 *block = edid + j * EDID_LENGTH;
1623
1624 for (i = 0; i < 4; i++) {
1625 if (get_edid_block(data, block, j, EDID_LENGTH))
1626 goto out;
1627 if (drm_edid_block_valid(block, j, false, NULL))
1628 break;
1629 }
1630
1631 if (i == 4)
1632 valid_extensions--;
1633 }
1634
1635 if (valid_extensions != edid[0x7e]) {
1636 u8 *base;
1637
1638 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1639
1640 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1641 edid[0x7e] = valid_extensions;
1642
1643 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
1644 GFP_KERNEL);
1645 if (!new)
1646 goto out;
1647
1648 base = new;
1649 for (i = 0; i <= edid[0x7e]; i++) {
1650 u8 *block = edid + i * EDID_LENGTH;
1651
1652 if (!drm_edid_block_valid(block, i, false, NULL))
1653 continue;
1654
1655 memcpy(base, block, EDID_LENGTH);
1656 base += EDID_LENGTH;
1657 }
1658
1659 kfree(edid);
1660 edid = new;
1661 }
1662
1663 return (struct edid *)edid;
1664
1665 carp:
1666 connector_bad_edid(connector, edid, 1);
1667 out:
1668 kfree(edid);
1669 return NULL;
1670 }
1671 EXPORT_SYMBOL_GPL(drm_do_get_edid);
1672
1673 /**
1674 * drm_probe_ddc() - probe DDC presence
1675 * @adapter: I2C adapter to probe
1676 *
1677 * Return: True on success, false on failure.
1678 */
1679 bool
drm_probe_ddc(struct i2c_adapter * adapter)1680 drm_probe_ddc(struct i2c_adapter *adapter)
1681 {
1682 unsigned char out;
1683
1684 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1685 }
1686 EXPORT_SYMBOL(drm_probe_ddc);
1687
1688 /**
1689 * drm_get_edid - get EDID data, if available
1690 * @connector: connector we're probing
1691 * @adapter: I2C adapter to use for DDC
1692 *
1693 * Poke the given I2C channel to grab EDID data if possible. If found,
1694 * attach it to the connector.
1695 *
1696 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1697 */
drm_get_edid(struct drm_connector * connector,struct i2c_adapter * adapter)1698 struct edid *drm_get_edid(struct drm_connector *connector,
1699 struct i2c_adapter *adapter)
1700 {
1701 struct edid *edid;
1702
1703 if (connector->force == DRM_FORCE_OFF)
1704 return NULL;
1705
1706 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
1707 return NULL;
1708
1709 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1710 if (edid)
1711 drm_get_displayid(connector, edid);
1712 return edid;
1713 }
1714 EXPORT_SYMBOL(drm_get_edid);
1715
1716 /**
1717 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1718 * @connector: connector we're probing
1719 * @adapter: I2C adapter to use for DDC
1720 *
1721 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1722 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1723 * switch DDC to the GPU which is retrieving EDID.
1724 *
1725 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1726 */
drm_get_edid_switcheroo(struct drm_connector * connector,struct i2c_adapter * adapter)1727 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1728 struct i2c_adapter *adapter)
1729 {
1730 struct pci_dev *pdev = connector->dev->pdev;
1731 struct edid *edid;
1732
1733 vga_switcheroo_lock_ddc(pdev);
1734 edid = drm_get_edid(connector, adapter);
1735 vga_switcheroo_unlock_ddc(pdev);
1736
1737 return edid;
1738 }
1739 EXPORT_SYMBOL(drm_get_edid_switcheroo);
1740
1741 /**
1742 * drm_edid_duplicate - duplicate an EDID and the extensions
1743 * @edid: EDID to duplicate
1744 *
1745 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1746 */
drm_edid_duplicate(const struct edid * edid)1747 struct edid *drm_edid_duplicate(const struct edid *edid)
1748 {
1749 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1750 }
1751 EXPORT_SYMBOL(drm_edid_duplicate);
1752
1753 /*** EDID parsing ***/
1754
1755 /**
1756 * edid_vendor - match a string against EDID's obfuscated vendor field
1757 * @edid: EDID to match
1758 * @vendor: vendor string
1759 *
1760 * Returns true if @vendor is in @edid, false otherwise
1761 */
edid_vendor(const struct edid * edid,const char * vendor)1762 static bool edid_vendor(const struct edid *edid, const char *vendor)
1763 {
1764 char edid_vendor[3];
1765
1766 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1767 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1768 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1769 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1770
1771 return !strncmp(edid_vendor, vendor, 3);
1772 }
1773
1774 /**
1775 * edid_get_quirks - return quirk flags for a given EDID
1776 * @edid: EDID to process
1777 *
1778 * This tells subsequent routines what fixes they need to apply.
1779 */
edid_get_quirks(const struct edid * edid)1780 static u32 edid_get_quirks(const struct edid *edid)
1781 {
1782 const struct edid_quirk *quirk;
1783 int i;
1784
1785 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1786 quirk = &edid_quirk_list[i];
1787
1788 if (edid_vendor(edid, quirk->vendor) &&
1789 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1790 return quirk->quirks;
1791 }
1792
1793 return 0;
1794 }
1795
1796 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1797 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1798
1799 /**
1800 * edid_fixup_preferred - set preferred modes based on quirk list
1801 * @connector: has mode list to fix up
1802 * @quirks: quirks list
1803 *
1804 * Walk the mode list for @connector, clearing the preferred status
1805 * on existing modes and setting it anew for the right mode ala @quirks.
1806 */
edid_fixup_preferred(struct drm_connector * connector,u32 quirks)1807 static void edid_fixup_preferred(struct drm_connector *connector,
1808 u32 quirks)
1809 {
1810 struct drm_display_mode *t, *cur_mode, *preferred_mode;
1811 int target_refresh = 0;
1812 int cur_vrefresh, preferred_vrefresh;
1813
1814 if (list_empty(&connector->probed_modes))
1815 return;
1816
1817 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1818 target_refresh = 60;
1819 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1820 target_refresh = 75;
1821
1822 preferred_mode = list_first_entry(&connector->probed_modes,
1823 struct drm_display_mode, head);
1824
1825 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1826 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1827
1828 if (cur_mode == preferred_mode)
1829 continue;
1830
1831 /* Largest mode is preferred */
1832 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1833 preferred_mode = cur_mode;
1834
1835 cur_vrefresh = cur_mode->vrefresh ?
1836 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1837 preferred_vrefresh = preferred_mode->vrefresh ?
1838 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1839 /* At a given size, try to get closest to target refresh */
1840 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1841 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1842 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1843 preferred_mode = cur_mode;
1844 }
1845 }
1846
1847 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1848 }
1849
1850 static bool
mode_is_rb(const struct drm_display_mode * mode)1851 mode_is_rb(const struct drm_display_mode *mode)
1852 {
1853 return (mode->htotal - mode->hdisplay == 160) &&
1854 (mode->hsync_end - mode->hdisplay == 80) &&
1855 (mode->hsync_end - mode->hsync_start == 32) &&
1856 (mode->vsync_start - mode->vdisplay == 3);
1857 }
1858
1859 /*
1860 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1861 * @dev: Device to duplicate against
1862 * @hsize: Mode width
1863 * @vsize: Mode height
1864 * @fresh: Mode refresh rate
1865 * @rb: Mode reduced-blanking-ness
1866 *
1867 * Walk the DMT mode list looking for a match for the given parameters.
1868 *
1869 * Return: A newly allocated copy of the mode, or NULL if not found.
1870 */
drm_mode_find_dmt(struct drm_device * dev,int hsize,int vsize,int fresh,bool rb)1871 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1872 int hsize, int vsize, int fresh,
1873 bool rb)
1874 {
1875 int i;
1876
1877 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1878 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1879 if (hsize != ptr->hdisplay)
1880 continue;
1881 if (vsize != ptr->vdisplay)
1882 continue;
1883 if (fresh != drm_mode_vrefresh(ptr))
1884 continue;
1885 if (rb != mode_is_rb(ptr))
1886 continue;
1887
1888 return drm_mode_duplicate(dev, ptr);
1889 }
1890
1891 return NULL;
1892 }
1893 EXPORT_SYMBOL(drm_mode_find_dmt);
1894
1895 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1896
1897 static void
cea_for_each_detailed_block(u8 * ext,detailed_cb * cb,void * closure)1898 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1899 {
1900 int i, n = 0;
1901 u8 d = ext[0x02];
1902 u8 *det_base = ext + d;
1903
1904 n = (127 - d) / 18;
1905 for (i = 0; i < n; i++)
1906 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1907 }
1908
1909 static void
vtb_for_each_detailed_block(u8 * ext,detailed_cb * cb,void * closure)1910 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1911 {
1912 unsigned int i, n = min((int)ext[0x02], 6);
1913 u8 *det_base = ext + 5;
1914
1915 if (ext[0x01] != 1)
1916 return; /* unknown version */
1917
1918 for (i = 0; i < n; i++)
1919 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1920 }
1921
1922 static void
drm_for_each_detailed_block(u8 * raw_edid,detailed_cb * cb,void * closure)1923 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1924 {
1925 int i;
1926 struct edid *edid = (struct edid *)raw_edid;
1927
1928 if (edid == NULL)
1929 return;
1930
1931 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1932 cb(&(edid->detailed_timings[i]), closure);
1933
1934 for (i = 1; i <= raw_edid[0x7e]; i++) {
1935 u8 *ext = raw_edid + (i * EDID_LENGTH);
1936 switch (*ext) {
1937 case CEA_EXT:
1938 cea_for_each_detailed_block(ext, cb, closure);
1939 break;
1940 case VTB_EXT:
1941 vtb_for_each_detailed_block(ext, cb, closure);
1942 break;
1943 default:
1944 break;
1945 }
1946 }
1947 }
1948
1949 static void
is_rb(struct detailed_timing * t,void * data)1950 is_rb(struct detailed_timing *t, void *data)
1951 {
1952 u8 *r = (u8 *)t;
1953 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1954 if (r[15] & 0x10)
1955 *(bool *)data = true;
1956 }
1957
1958 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1959 static bool
drm_monitor_supports_rb(struct edid * edid)1960 drm_monitor_supports_rb(struct edid *edid)
1961 {
1962 if (edid->revision >= 4) {
1963 bool ret = false;
1964 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1965 return ret;
1966 }
1967
1968 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1969 }
1970
1971 static void
find_gtf2(struct detailed_timing * t,void * data)1972 find_gtf2(struct detailed_timing *t, void *data)
1973 {
1974 u8 *r = (u8 *)t;
1975 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1976 *(u8 **)data = r;
1977 }
1978
1979 /* Secondary GTF curve kicks in above some break frequency */
1980 static int
drm_gtf2_hbreak(struct edid * edid)1981 drm_gtf2_hbreak(struct edid *edid)
1982 {
1983 u8 *r = NULL;
1984 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1985 return r ? (r[12] * 2) : 0;
1986 }
1987
1988 static int
drm_gtf2_2c(struct edid * edid)1989 drm_gtf2_2c(struct edid *edid)
1990 {
1991 u8 *r = NULL;
1992 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1993 return r ? r[13] : 0;
1994 }
1995
1996 static int
drm_gtf2_m(struct edid * edid)1997 drm_gtf2_m(struct edid *edid)
1998 {
1999 u8 *r = NULL;
2000 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2001 return r ? (r[15] << 8) + r[14] : 0;
2002 }
2003
2004 static int
drm_gtf2_k(struct edid * edid)2005 drm_gtf2_k(struct edid *edid)
2006 {
2007 u8 *r = NULL;
2008 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2009 return r ? r[16] : 0;
2010 }
2011
2012 static int
drm_gtf2_2j(struct edid * edid)2013 drm_gtf2_2j(struct edid *edid)
2014 {
2015 u8 *r = NULL;
2016 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2017 return r ? r[17] : 0;
2018 }
2019
2020 /**
2021 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2022 * @edid: EDID block to scan
2023 */
standard_timing_level(struct edid * edid)2024 static int standard_timing_level(struct edid *edid)
2025 {
2026 if (edid->revision >= 2) {
2027 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2028 return LEVEL_CVT;
2029 if (drm_gtf2_hbreak(edid))
2030 return LEVEL_GTF2;
2031 return LEVEL_GTF;
2032 }
2033 return LEVEL_DMT;
2034 }
2035
2036 /*
2037 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2038 * monitors fill with ascii space (0x20) instead.
2039 */
2040 static int
bad_std_timing(u8 a,u8 b)2041 bad_std_timing(u8 a, u8 b)
2042 {
2043 return (a == 0x00 && b == 0x00) ||
2044 (a == 0x01 && b == 0x01) ||
2045 (a == 0x20 && b == 0x20);
2046 }
2047
2048 /**
2049 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
2050 * @connector: connector of for the EDID block
2051 * @edid: EDID block to scan
2052 * @t: standard timing params
2053 *
2054 * Take the standard timing params (in this case width, aspect, and refresh)
2055 * and convert them into a real mode using CVT/GTF/DMT.
2056 */
2057 static struct drm_display_mode *
drm_mode_std(struct drm_connector * connector,struct edid * edid,struct std_timing * t)2058 drm_mode_std(struct drm_connector *connector, struct edid *edid,
2059 struct std_timing *t)
2060 {
2061 struct drm_device *dev = connector->dev;
2062 struct drm_display_mode *m, *mode = NULL;
2063 int hsize, vsize;
2064 int vrefresh_rate;
2065 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2066 >> EDID_TIMING_ASPECT_SHIFT;
2067 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2068 >> EDID_TIMING_VFREQ_SHIFT;
2069 int timing_level = standard_timing_level(edid);
2070
2071 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2072 return NULL;
2073
2074 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2075 hsize = t->hsize * 8 + 248;
2076 /* vrefresh_rate = vfreq + 60 */
2077 vrefresh_rate = vfreq + 60;
2078 /* the vdisplay is calculated based on the aspect ratio */
2079 if (aspect_ratio == 0) {
2080 if (edid->revision < 3)
2081 vsize = hsize;
2082 else
2083 vsize = (hsize * 10) / 16;
2084 } else if (aspect_ratio == 1)
2085 vsize = (hsize * 3) / 4;
2086 else if (aspect_ratio == 2)
2087 vsize = (hsize * 4) / 5;
2088 else
2089 vsize = (hsize * 9) / 16;
2090
2091 /* HDTV hack, part 1 */
2092 if (vrefresh_rate == 60 &&
2093 ((hsize == 1360 && vsize == 765) ||
2094 (hsize == 1368 && vsize == 769))) {
2095 hsize = 1366;
2096 vsize = 768;
2097 }
2098
2099 /*
2100 * If this connector already has a mode for this size and refresh
2101 * rate (because it came from detailed or CVT info), use that
2102 * instead. This way we don't have to guess at interlace or
2103 * reduced blanking.
2104 */
2105 list_for_each_entry(m, &connector->probed_modes, head)
2106 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2107 drm_mode_vrefresh(m) == vrefresh_rate)
2108 return NULL;
2109
2110 /* HDTV hack, part 2 */
2111 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2112 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
2113 false);
2114 if (!mode)
2115 return NULL;
2116 mode->hdisplay = 1366;
2117 mode->hsync_start = mode->hsync_start - 1;
2118 mode->hsync_end = mode->hsync_end - 1;
2119 return mode;
2120 }
2121
2122 /* check whether it can be found in default mode table */
2123 if (drm_monitor_supports_rb(edid)) {
2124 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2125 true);
2126 if (mode)
2127 return mode;
2128 }
2129 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2130 if (mode)
2131 return mode;
2132
2133 /* okay, generate it */
2134 switch (timing_level) {
2135 case LEVEL_DMT:
2136 break;
2137 case LEVEL_GTF:
2138 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2139 break;
2140 case LEVEL_GTF2:
2141 /*
2142 * This is potentially wrong if there's ever a monitor with
2143 * more than one ranges section, each claiming a different
2144 * secondary GTF curve. Please don't do that.
2145 */
2146 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2147 if (!mode)
2148 return NULL;
2149 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2150 drm_mode_destroy(dev, mode);
2151 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2152 vrefresh_rate, 0, 0,
2153 drm_gtf2_m(edid),
2154 drm_gtf2_2c(edid),
2155 drm_gtf2_k(edid),
2156 drm_gtf2_2j(edid));
2157 }
2158 break;
2159 case LEVEL_CVT:
2160 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2161 false);
2162 break;
2163 }
2164 return mode;
2165 }
2166
2167 /*
2168 * EDID is delightfully ambiguous about how interlaced modes are to be
2169 * encoded. Our internal representation is of frame height, but some
2170 * HDTV detailed timings are encoded as field height.
2171 *
2172 * The format list here is from CEA, in frame size. Technically we
2173 * should be checking refresh rate too. Whatever.
2174 */
2175 static void
drm_mode_do_interlace_quirk(struct drm_display_mode * mode,struct detailed_pixel_timing * pt)2176 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2177 struct detailed_pixel_timing *pt)
2178 {
2179 int i;
2180 static const struct {
2181 int w, h;
2182 } cea_interlaced[] = {
2183 { 1920, 1080 },
2184 { 720, 480 },
2185 { 1440, 480 },
2186 { 2880, 480 },
2187 { 720, 576 },
2188 { 1440, 576 },
2189 { 2880, 576 },
2190 };
2191
2192 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2193 return;
2194
2195 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2196 if ((mode->hdisplay == cea_interlaced[i].w) &&
2197 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2198 mode->vdisplay *= 2;
2199 mode->vsync_start *= 2;
2200 mode->vsync_end *= 2;
2201 mode->vtotal *= 2;
2202 mode->vtotal |= 1;
2203 }
2204 }
2205
2206 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2207 }
2208
2209 /**
2210 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2211 * @dev: DRM device (needed to create new mode)
2212 * @edid: EDID block
2213 * @timing: EDID detailed timing info
2214 * @quirks: quirks to apply
2215 *
2216 * An EDID detailed timing block contains enough info for us to create and
2217 * return a new struct drm_display_mode.
2218 */
drm_mode_detailed(struct drm_device * dev,struct edid * edid,struct detailed_timing * timing,u32 quirks)2219 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2220 struct edid *edid,
2221 struct detailed_timing *timing,
2222 u32 quirks)
2223 {
2224 struct drm_display_mode *mode;
2225 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2226 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2227 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2228 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2229 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2230 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2231 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2232 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2233 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2234
2235 /* ignore tiny modes */
2236 if (hactive < 64 || vactive < 64)
2237 return NULL;
2238
2239 if (pt->misc & DRM_EDID_PT_STEREO) {
2240 DRM_DEBUG_KMS("stereo mode not supported\n");
2241 return NULL;
2242 }
2243 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2244 DRM_DEBUG_KMS("composite sync not supported\n");
2245 }
2246
2247 /* it is incorrect if hsync/vsync width is zero */
2248 if (!hsync_pulse_width || !vsync_pulse_width) {
2249 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2250 "Wrong Hsync/Vsync pulse width\n");
2251 return NULL;
2252 }
2253
2254 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2255 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2256 if (!mode)
2257 return NULL;
2258
2259 goto set_size;
2260 }
2261
2262 mode = drm_mode_create(dev);
2263 if (!mode)
2264 return NULL;
2265
2266 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2267 timing->pixel_clock = cpu_to_le16(1088);
2268
2269 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2270
2271 mode->hdisplay = hactive;
2272 mode->hsync_start = mode->hdisplay + hsync_offset;
2273 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2274 mode->htotal = mode->hdisplay + hblank;
2275
2276 mode->vdisplay = vactive;
2277 mode->vsync_start = mode->vdisplay + vsync_offset;
2278 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2279 mode->vtotal = mode->vdisplay + vblank;
2280
2281 /* Some EDIDs have bogus h/vtotal values */
2282 if (mode->hsync_end > mode->htotal)
2283 mode->htotal = mode->hsync_end + 1;
2284 if (mode->vsync_end > mode->vtotal)
2285 mode->vtotal = mode->vsync_end + 1;
2286
2287 drm_mode_do_interlace_quirk(mode, pt);
2288
2289 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2290 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2291 }
2292
2293 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2294 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2295 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2296 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2297
2298 set_size:
2299 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2300 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2301
2302 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2303 mode->width_mm *= 10;
2304 mode->height_mm *= 10;
2305 }
2306
2307 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2308 mode->width_mm = edid->width_cm * 10;
2309 mode->height_mm = edid->height_cm * 10;
2310 }
2311
2312 mode->type = DRM_MODE_TYPE_DRIVER;
2313 mode->vrefresh = drm_mode_vrefresh(mode);
2314 drm_mode_set_name(mode);
2315
2316 return mode;
2317 }
2318
2319 static bool
mode_in_hsync_range(const struct drm_display_mode * mode,struct edid * edid,u8 * t)2320 mode_in_hsync_range(const struct drm_display_mode *mode,
2321 struct edid *edid, u8 *t)
2322 {
2323 int hsync, hmin, hmax;
2324
2325 hmin = t[7];
2326 if (edid->revision >= 4)
2327 hmin += ((t[4] & 0x04) ? 255 : 0);
2328 hmax = t[8];
2329 if (edid->revision >= 4)
2330 hmax += ((t[4] & 0x08) ? 255 : 0);
2331 hsync = drm_mode_hsync(mode);
2332
2333 return (hsync <= hmax && hsync >= hmin);
2334 }
2335
2336 static bool
mode_in_vsync_range(const struct drm_display_mode * mode,struct edid * edid,u8 * t)2337 mode_in_vsync_range(const struct drm_display_mode *mode,
2338 struct edid *edid, u8 *t)
2339 {
2340 int vsync, vmin, vmax;
2341
2342 vmin = t[5];
2343 if (edid->revision >= 4)
2344 vmin += ((t[4] & 0x01) ? 255 : 0);
2345 vmax = t[6];
2346 if (edid->revision >= 4)
2347 vmax += ((t[4] & 0x02) ? 255 : 0);
2348 vsync = drm_mode_vrefresh(mode);
2349
2350 return (vsync <= vmax && vsync >= vmin);
2351 }
2352
2353 static u32
range_pixel_clock(struct edid * edid,u8 * t)2354 range_pixel_clock(struct edid *edid, u8 *t)
2355 {
2356 /* unspecified */
2357 if (t[9] == 0 || t[9] == 255)
2358 return 0;
2359
2360 /* 1.4 with CVT support gives us real precision, yay */
2361 if (edid->revision >= 4 && t[10] == 0x04)
2362 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2363
2364 /* 1.3 is pathetic, so fuzz up a bit */
2365 return t[9] * 10000 + 5001;
2366 }
2367
2368 static bool
mode_in_range(const struct drm_display_mode * mode,struct edid * edid,struct detailed_timing * timing)2369 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2370 struct detailed_timing *timing)
2371 {
2372 u32 max_clock;
2373 u8 *t = (u8 *)timing;
2374
2375 if (!mode_in_hsync_range(mode, edid, t))
2376 return false;
2377
2378 if (!mode_in_vsync_range(mode, edid, t))
2379 return false;
2380
2381 if ((max_clock = range_pixel_clock(edid, t)))
2382 if (mode->clock > max_clock)
2383 return false;
2384
2385 /* 1.4 max horizontal check */
2386 if (edid->revision >= 4 && t[10] == 0x04)
2387 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2388 return false;
2389
2390 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2391 return false;
2392
2393 return true;
2394 }
2395
valid_inferred_mode(const struct drm_connector * connector,const struct drm_display_mode * mode)2396 static bool valid_inferred_mode(const struct drm_connector *connector,
2397 const struct drm_display_mode *mode)
2398 {
2399 const struct drm_display_mode *m;
2400 bool ok = false;
2401
2402 list_for_each_entry(m, &connector->probed_modes, head) {
2403 if (mode->hdisplay == m->hdisplay &&
2404 mode->vdisplay == m->vdisplay &&
2405 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2406 return false; /* duplicated */
2407 if (mode->hdisplay <= m->hdisplay &&
2408 mode->vdisplay <= m->vdisplay)
2409 ok = true;
2410 }
2411 return ok;
2412 }
2413
2414 static int
drm_dmt_modes_for_range(struct drm_connector * connector,struct edid * edid,struct detailed_timing * timing)2415 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2416 struct detailed_timing *timing)
2417 {
2418 int i, modes = 0;
2419 struct drm_display_mode *newmode;
2420 struct drm_device *dev = connector->dev;
2421
2422 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2423 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2424 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2425 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2426 if (newmode) {
2427 drm_mode_probed_add(connector, newmode);
2428 modes++;
2429 }
2430 }
2431 }
2432
2433 return modes;
2434 }
2435
2436 /* fix up 1366x768 mode from 1368x768;
2437 * GFT/CVT can't express 1366 width which isn't dividable by 8
2438 */
drm_mode_fixup_1366x768(struct drm_display_mode * mode)2439 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2440 {
2441 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2442 mode->hdisplay = 1366;
2443 mode->hsync_start--;
2444 mode->hsync_end--;
2445 drm_mode_set_name(mode);
2446 }
2447 }
2448
2449 static int
drm_gtf_modes_for_range(struct drm_connector * connector,struct edid * edid,struct detailed_timing * timing)2450 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2451 struct detailed_timing *timing)
2452 {
2453 int i, modes = 0;
2454 struct drm_display_mode *newmode;
2455 struct drm_device *dev = connector->dev;
2456
2457 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2458 const struct minimode *m = &extra_modes[i];
2459 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2460 if (!newmode)
2461 return modes;
2462
2463 drm_mode_fixup_1366x768(newmode);
2464 if (!mode_in_range(newmode, edid, timing) ||
2465 !valid_inferred_mode(connector, newmode)) {
2466 drm_mode_destroy(dev, newmode);
2467 continue;
2468 }
2469
2470 drm_mode_probed_add(connector, newmode);
2471 modes++;
2472 }
2473
2474 return modes;
2475 }
2476
2477 static int
drm_cvt_modes_for_range(struct drm_connector * connector,struct edid * edid,struct detailed_timing * timing)2478 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2479 struct detailed_timing *timing)
2480 {
2481 int i, modes = 0;
2482 struct drm_display_mode *newmode;
2483 struct drm_device *dev = connector->dev;
2484 bool rb = drm_monitor_supports_rb(edid);
2485
2486 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2487 const struct minimode *m = &extra_modes[i];
2488 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2489 if (!newmode)
2490 return modes;
2491
2492 drm_mode_fixup_1366x768(newmode);
2493 if (!mode_in_range(newmode, edid, timing) ||
2494 !valid_inferred_mode(connector, newmode)) {
2495 drm_mode_destroy(dev, newmode);
2496 continue;
2497 }
2498
2499 drm_mode_probed_add(connector, newmode);
2500 modes++;
2501 }
2502
2503 return modes;
2504 }
2505
2506 static void
do_inferred_modes(struct detailed_timing * timing,void * c)2507 do_inferred_modes(struct detailed_timing *timing, void *c)
2508 {
2509 struct detailed_mode_closure *closure = c;
2510 struct detailed_non_pixel *data = &timing->data.other_data;
2511 struct detailed_data_monitor_range *range = &data->data.range;
2512
2513 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2514 return;
2515
2516 closure->modes += drm_dmt_modes_for_range(closure->connector,
2517 closure->edid,
2518 timing);
2519
2520 if (!version_greater(closure->edid, 1, 1))
2521 return; /* GTF not defined yet */
2522
2523 switch (range->flags) {
2524 case 0x02: /* secondary gtf, XXX could do more */
2525 case 0x00: /* default gtf */
2526 closure->modes += drm_gtf_modes_for_range(closure->connector,
2527 closure->edid,
2528 timing);
2529 break;
2530 case 0x04: /* cvt, only in 1.4+ */
2531 if (!version_greater(closure->edid, 1, 3))
2532 break;
2533
2534 closure->modes += drm_cvt_modes_for_range(closure->connector,
2535 closure->edid,
2536 timing);
2537 break;
2538 case 0x01: /* just the ranges, no formula */
2539 default:
2540 break;
2541 }
2542 }
2543
2544 static int
add_inferred_modes(struct drm_connector * connector,struct edid * edid)2545 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2546 {
2547 struct detailed_mode_closure closure = {
2548 .connector = connector,
2549 .edid = edid,
2550 };
2551
2552 if (version_greater(edid, 1, 0))
2553 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2554 &closure);
2555
2556 return closure.modes;
2557 }
2558
2559 static int
drm_est3_modes(struct drm_connector * connector,struct detailed_timing * timing)2560 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2561 {
2562 int i, j, m, modes = 0;
2563 struct drm_display_mode *mode;
2564 u8 *est = ((u8 *)timing) + 6;
2565
2566 for (i = 0; i < 6; i++) {
2567 for (j = 7; j >= 0; j--) {
2568 m = (i * 8) + (7 - j);
2569 if (m >= ARRAY_SIZE(est3_modes))
2570 break;
2571 if (est[i] & (1 << j)) {
2572 mode = drm_mode_find_dmt(connector->dev,
2573 est3_modes[m].w,
2574 est3_modes[m].h,
2575 est3_modes[m].r,
2576 est3_modes[m].rb);
2577 if (mode) {
2578 drm_mode_probed_add(connector, mode);
2579 modes++;
2580 }
2581 }
2582 }
2583 }
2584
2585 return modes;
2586 }
2587
2588 static void
do_established_modes(struct detailed_timing * timing,void * c)2589 do_established_modes(struct detailed_timing *timing, void *c)
2590 {
2591 struct detailed_mode_closure *closure = c;
2592 struct detailed_non_pixel *data = &timing->data.other_data;
2593
2594 if (data->type == EDID_DETAIL_EST_TIMINGS)
2595 closure->modes += drm_est3_modes(closure->connector, timing);
2596 }
2597
2598 /**
2599 * add_established_modes - get est. modes from EDID and add them
2600 * @connector: connector to add mode(s) to
2601 * @edid: EDID block to scan
2602 *
2603 * Each EDID block contains a bitmap of the supported "established modes" list
2604 * (defined above). Tease them out and add them to the global modes list.
2605 */
2606 static int
add_established_modes(struct drm_connector * connector,struct edid * edid)2607 add_established_modes(struct drm_connector *connector, struct edid *edid)
2608 {
2609 struct drm_device *dev = connector->dev;
2610 unsigned long est_bits = edid->established_timings.t1 |
2611 (edid->established_timings.t2 << 8) |
2612 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2613 int i, modes = 0;
2614 struct detailed_mode_closure closure = {
2615 .connector = connector,
2616 .edid = edid,
2617 };
2618
2619 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2620 if (est_bits & (1<<i)) {
2621 struct drm_display_mode *newmode;
2622 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2623 if (newmode) {
2624 drm_mode_probed_add(connector, newmode);
2625 modes++;
2626 }
2627 }
2628 }
2629
2630 if (version_greater(edid, 1, 0))
2631 drm_for_each_detailed_block((u8 *)edid,
2632 do_established_modes, &closure);
2633
2634 return modes + closure.modes;
2635 }
2636
2637 static void
do_standard_modes(struct detailed_timing * timing,void * c)2638 do_standard_modes(struct detailed_timing *timing, void *c)
2639 {
2640 struct detailed_mode_closure *closure = c;
2641 struct detailed_non_pixel *data = &timing->data.other_data;
2642 struct drm_connector *connector = closure->connector;
2643 struct edid *edid = closure->edid;
2644
2645 if (data->type == EDID_DETAIL_STD_MODES) {
2646 int i;
2647 for (i = 0; i < 6; i++) {
2648 struct std_timing *std;
2649 struct drm_display_mode *newmode;
2650
2651 std = &data->data.timings[i];
2652 newmode = drm_mode_std(connector, edid, std);
2653 if (newmode) {
2654 drm_mode_probed_add(connector, newmode);
2655 closure->modes++;
2656 }
2657 }
2658 }
2659 }
2660
2661 /**
2662 * add_standard_modes - get std. modes from EDID and add them
2663 * @connector: connector to add mode(s) to
2664 * @edid: EDID block to scan
2665 *
2666 * Standard modes can be calculated using the appropriate standard (DMT,
2667 * GTF or CVT. Grab them from @edid and add them to the list.
2668 */
2669 static int
add_standard_modes(struct drm_connector * connector,struct edid * edid)2670 add_standard_modes(struct drm_connector *connector, struct edid *edid)
2671 {
2672 int i, modes = 0;
2673 struct detailed_mode_closure closure = {
2674 .connector = connector,
2675 .edid = edid,
2676 };
2677
2678 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2679 struct drm_display_mode *newmode;
2680
2681 newmode = drm_mode_std(connector, edid,
2682 &edid->standard_timings[i]);
2683 if (newmode) {
2684 drm_mode_probed_add(connector, newmode);
2685 modes++;
2686 }
2687 }
2688
2689 if (version_greater(edid, 1, 0))
2690 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2691 &closure);
2692
2693 /* XXX should also look for standard codes in VTB blocks */
2694
2695 return modes + closure.modes;
2696 }
2697
drm_cvt_modes(struct drm_connector * connector,struct detailed_timing * timing)2698 static int drm_cvt_modes(struct drm_connector *connector,
2699 struct detailed_timing *timing)
2700 {
2701 int i, j, modes = 0;
2702 struct drm_display_mode *newmode;
2703 struct drm_device *dev = connector->dev;
2704 struct cvt_timing *cvt;
2705 const int rates[] = { 60, 85, 75, 60, 50 };
2706 const u8 empty[3] = { 0, 0, 0 };
2707
2708 for (i = 0; i < 4; i++) {
2709 int uninitialized_var(width), height;
2710 cvt = &(timing->data.other_data.data.cvt[i]);
2711
2712 if (!memcmp(cvt->code, empty, 3))
2713 continue;
2714
2715 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2716 switch (cvt->code[1] & 0x0c) {
2717 case 0x00:
2718 width = height * 4 / 3;
2719 break;
2720 case 0x04:
2721 width = height * 16 / 9;
2722 break;
2723 case 0x08:
2724 width = height * 16 / 10;
2725 break;
2726 case 0x0c:
2727 width = height * 15 / 9;
2728 break;
2729 }
2730
2731 for (j = 1; j < 5; j++) {
2732 if (cvt->code[2] & (1 << j)) {
2733 newmode = drm_cvt_mode(dev, width, height,
2734 rates[j], j == 0,
2735 false, false);
2736 if (newmode) {
2737 drm_mode_probed_add(connector, newmode);
2738 modes++;
2739 }
2740 }
2741 }
2742 }
2743
2744 return modes;
2745 }
2746
2747 static void
do_cvt_mode(struct detailed_timing * timing,void * c)2748 do_cvt_mode(struct detailed_timing *timing, void *c)
2749 {
2750 struct detailed_mode_closure *closure = c;
2751 struct detailed_non_pixel *data = &timing->data.other_data;
2752
2753 if (data->type == EDID_DETAIL_CVT_3BYTE)
2754 closure->modes += drm_cvt_modes(closure->connector, timing);
2755 }
2756
2757 static int
add_cvt_modes(struct drm_connector * connector,struct edid * edid)2758 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2759 {
2760 struct detailed_mode_closure closure = {
2761 .connector = connector,
2762 .edid = edid,
2763 };
2764
2765 if (version_greater(edid, 1, 2))
2766 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2767
2768 /* XXX should also look for CVT codes in VTB blocks */
2769
2770 return closure.modes;
2771 }
2772
2773 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2774
2775 static void
do_detailed_mode(struct detailed_timing * timing,void * c)2776 do_detailed_mode(struct detailed_timing *timing, void *c)
2777 {
2778 struct detailed_mode_closure *closure = c;
2779 struct drm_display_mode *newmode;
2780
2781 if (timing->pixel_clock) {
2782 newmode = drm_mode_detailed(closure->connector->dev,
2783 closure->edid, timing,
2784 closure->quirks);
2785 if (!newmode)
2786 return;
2787
2788 if (closure->preferred)
2789 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2790
2791 /*
2792 * Detailed modes are limited to 10kHz pixel clock resolution,
2793 * so fix up anything that looks like CEA/HDMI mode, but the clock
2794 * is just slightly off.
2795 */
2796 fixup_detailed_cea_mode_clock(newmode);
2797
2798 drm_mode_probed_add(closure->connector, newmode);
2799 closure->modes++;
2800 closure->preferred = false;
2801 }
2802 }
2803
2804 /*
2805 * add_detailed_modes - Add modes from detailed timings
2806 * @connector: attached connector
2807 * @edid: EDID block to scan
2808 * @quirks: quirks to apply
2809 */
2810 static int
add_detailed_modes(struct drm_connector * connector,struct edid * edid,u32 quirks)2811 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2812 u32 quirks)
2813 {
2814 struct detailed_mode_closure closure = {
2815 .connector = connector,
2816 .edid = edid,
2817 .preferred = true,
2818 .quirks = quirks,
2819 };
2820
2821 if (closure.preferred && !version_greater(edid, 1, 3))
2822 closure.preferred =
2823 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2824
2825 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2826
2827 return closure.modes;
2828 }
2829
2830 #define AUDIO_BLOCK 0x01
2831 #define VIDEO_BLOCK 0x02
2832 #define VENDOR_BLOCK 0x03
2833 #define SPEAKER_BLOCK 0x04
2834 #define USE_EXTENDED_TAG 0x07
2835 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00
2836 #define EXT_VIDEO_DATA_BLOCK_420 0x0E
2837 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
2838 #define EDID_BASIC_AUDIO (1 << 6)
2839 #define EDID_CEA_YCRCB444 (1 << 5)
2840 #define EDID_CEA_YCRCB422 (1 << 4)
2841 #define EDID_CEA_VCDB_QS (1 << 6)
2842
2843 /*
2844 * Search EDID for CEA extension block.
2845 */
drm_find_edid_extension(const struct edid * edid,int ext_id)2846 static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id)
2847 {
2848 u8 *edid_ext = NULL;
2849 int i;
2850
2851 /* No EDID or EDID extensions */
2852 if (edid == NULL || edid->extensions == 0)
2853 return NULL;
2854
2855 /* Find CEA extension */
2856 for (i = 0; i < edid->extensions; i++) {
2857 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2858 if (edid_ext[0] == ext_id)
2859 break;
2860 }
2861
2862 if (i == edid->extensions)
2863 return NULL;
2864
2865 return edid_ext;
2866 }
2867
drm_find_cea_extension(const struct edid * edid)2868 static u8 *drm_find_cea_extension(const struct edid *edid)
2869 {
2870 return drm_find_edid_extension(edid, CEA_EXT);
2871 }
2872
drm_find_displayid_extension(const struct edid * edid)2873 static u8 *drm_find_displayid_extension(const struct edid *edid)
2874 {
2875 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2876 }
2877
2878 /*
2879 * Calculate the alternate clock for the CEA mode
2880 * (60Hz vs. 59.94Hz etc.)
2881 */
2882 static unsigned int
cea_mode_alternate_clock(const struct drm_display_mode * cea_mode)2883 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2884 {
2885 unsigned int clock = cea_mode->clock;
2886
2887 if (cea_mode->vrefresh % 6 != 0)
2888 return clock;
2889
2890 /*
2891 * edid_cea_modes contains the 59.94Hz
2892 * variant for 240 and 480 line modes,
2893 * and the 60Hz variant otherwise.
2894 */
2895 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2896 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
2897 else
2898 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
2899
2900 return clock;
2901 }
2902
2903 static bool
cea_mode_alternate_timings(u8 vic,struct drm_display_mode * mode)2904 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
2905 {
2906 /*
2907 * For certain VICs the spec allows the vertical
2908 * front porch to vary by one or two lines.
2909 *
2910 * cea_modes[] stores the variant with the shortest
2911 * vertical front porch. We can adjust the mode to
2912 * get the other variants by simply increasing the
2913 * vertical front porch length.
2914 */
2915 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 ||
2916 edid_cea_modes[9].vtotal != 262 ||
2917 edid_cea_modes[12].vtotal != 262 ||
2918 edid_cea_modes[13].vtotal != 262 ||
2919 edid_cea_modes[23].vtotal != 312 ||
2920 edid_cea_modes[24].vtotal != 312 ||
2921 edid_cea_modes[27].vtotal != 312 ||
2922 edid_cea_modes[28].vtotal != 312);
2923
2924 if (((vic == 8 || vic == 9 ||
2925 vic == 12 || vic == 13) && mode->vtotal < 263) ||
2926 ((vic == 23 || vic == 24 ||
2927 vic == 27 || vic == 28) && mode->vtotal < 314)) {
2928 mode->vsync_start++;
2929 mode->vsync_end++;
2930 mode->vtotal++;
2931
2932 return true;
2933 }
2934
2935 return false;
2936 }
2937
drm_match_cea_mode_clock_tolerance(const struct drm_display_mode * to_match,unsigned int clock_tolerance)2938 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
2939 unsigned int clock_tolerance)
2940 {
2941 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
2942 u8 vic;
2943
2944 if (!to_match->clock)
2945 return 0;
2946
2947 if (to_match->picture_aspect_ratio)
2948 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
2949
2950 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2951 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2952 unsigned int clock1, clock2;
2953
2954 /* Check both 60Hz and 59.94Hz */
2955 clock1 = cea_mode.clock;
2956 clock2 = cea_mode_alternate_clock(&cea_mode);
2957
2958 if (abs(to_match->clock - clock1) > clock_tolerance &&
2959 abs(to_match->clock - clock2) > clock_tolerance)
2960 continue;
2961
2962 do {
2963 if (drm_mode_match(to_match, &cea_mode, match_flags))
2964 return vic;
2965 } while (cea_mode_alternate_timings(vic, &cea_mode));
2966 }
2967
2968 return 0;
2969 }
2970
2971 /**
2972 * drm_match_cea_mode - look for a CEA mode matching given mode
2973 * @to_match: display mode
2974 *
2975 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
2976 * mode.
2977 */
drm_match_cea_mode(const struct drm_display_mode * to_match)2978 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
2979 {
2980 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
2981 u8 vic;
2982
2983 if (!to_match->clock)
2984 return 0;
2985
2986 if (to_match->picture_aspect_ratio)
2987 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
2988
2989 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2990 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2991 unsigned int clock1, clock2;
2992
2993 /* Check both 60Hz and 59.94Hz */
2994 clock1 = cea_mode.clock;
2995 clock2 = cea_mode_alternate_clock(&cea_mode);
2996
2997 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
2998 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
2999 continue;
3000
3001 do {
3002 if (drm_mode_match(to_match, &cea_mode, match_flags))
3003 return vic;
3004 } while (cea_mode_alternate_timings(vic, &cea_mode));
3005 }
3006
3007 return 0;
3008 }
3009 EXPORT_SYMBOL(drm_match_cea_mode);
3010
drm_valid_cea_vic(u8 vic)3011 static bool drm_valid_cea_vic(u8 vic)
3012 {
3013 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
3014 }
3015
3016 /**
3017 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
3018 * the input VIC from the CEA mode list
3019 * @video_code: ID given to each of the CEA modes
3020 *
3021 * Returns picture aspect ratio
3022 */
drm_get_cea_aspect_ratio(const u8 video_code)3023 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
3024 {
3025 return edid_cea_modes[video_code].picture_aspect_ratio;
3026 }
3027 EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
3028
3029 /*
3030 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3031 * specific block).
3032 *
3033 * It's almost like cea_mode_alternate_clock(), we just need to add an
3034 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
3035 * one.
3036 */
3037 static unsigned int
hdmi_mode_alternate_clock(const struct drm_display_mode * hdmi_mode)3038 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3039 {
3040 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
3041 return hdmi_mode->clock;
3042
3043 return cea_mode_alternate_clock(hdmi_mode);
3044 }
3045
drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode * to_match,unsigned int clock_tolerance)3046 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3047 unsigned int clock_tolerance)
3048 {
3049 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3050 u8 vic;
3051
3052 if (!to_match->clock)
3053 return 0;
3054
3055 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3056 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3057 unsigned int clock1, clock2;
3058
3059 /* Make sure to also match alternate clocks */
3060 clock1 = hdmi_mode->clock;
3061 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3062
3063 if (abs(to_match->clock - clock1) > clock_tolerance &&
3064 abs(to_match->clock - clock2) > clock_tolerance)
3065 continue;
3066
3067 if (drm_mode_match(to_match, hdmi_mode, match_flags))
3068 return vic;
3069 }
3070
3071 return 0;
3072 }
3073
3074 /*
3075 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3076 * @to_match: display mode
3077 *
3078 * An HDMI mode is one defined in the HDMI vendor specific block.
3079 *
3080 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3081 */
drm_match_hdmi_mode(const struct drm_display_mode * to_match)3082 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3083 {
3084 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3085 u8 vic;
3086
3087 if (!to_match->clock)
3088 return 0;
3089
3090 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3091 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3092 unsigned int clock1, clock2;
3093
3094 /* Make sure to also match alternate clocks */
3095 clock1 = hdmi_mode->clock;
3096 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3097
3098 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3099 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3100 drm_mode_match(to_match, hdmi_mode, match_flags))
3101 return vic;
3102 }
3103 return 0;
3104 }
3105
drm_valid_hdmi_vic(u8 vic)3106 static bool drm_valid_hdmi_vic(u8 vic)
3107 {
3108 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3109 }
3110
3111 static int
add_alternate_cea_modes(struct drm_connector * connector,struct edid * edid)3112 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3113 {
3114 struct drm_device *dev = connector->dev;
3115 struct drm_display_mode *mode, *tmp;
3116 LIST_HEAD(list);
3117 int modes = 0;
3118
3119 /* Don't add CEA modes if the CEA extension block is missing */
3120 if (!drm_find_cea_extension(edid))
3121 return 0;
3122
3123 /*
3124 * Go through all probed modes and create a new mode
3125 * with the alternate clock for certain CEA modes.
3126 */
3127 list_for_each_entry(mode, &connector->probed_modes, head) {
3128 const struct drm_display_mode *cea_mode = NULL;
3129 struct drm_display_mode *newmode;
3130 u8 vic = drm_match_cea_mode(mode);
3131 unsigned int clock1, clock2;
3132
3133 if (drm_valid_cea_vic(vic)) {
3134 cea_mode = &edid_cea_modes[vic];
3135 clock2 = cea_mode_alternate_clock(cea_mode);
3136 } else {
3137 vic = drm_match_hdmi_mode(mode);
3138 if (drm_valid_hdmi_vic(vic)) {
3139 cea_mode = &edid_4k_modes[vic];
3140 clock2 = hdmi_mode_alternate_clock(cea_mode);
3141 }
3142 }
3143
3144 if (!cea_mode)
3145 continue;
3146
3147 clock1 = cea_mode->clock;
3148
3149 if (clock1 == clock2)
3150 continue;
3151
3152 if (mode->clock != clock1 && mode->clock != clock2)
3153 continue;
3154
3155 newmode = drm_mode_duplicate(dev, cea_mode);
3156 if (!newmode)
3157 continue;
3158
3159 /* Carry over the stereo flags */
3160 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3161
3162 /*
3163 * The current mode could be either variant. Make
3164 * sure to pick the "other" clock for the new mode.
3165 */
3166 if (mode->clock != clock1)
3167 newmode->clock = clock1;
3168 else
3169 newmode->clock = clock2;
3170
3171 list_add_tail(&newmode->head, &list);
3172 }
3173
3174 list_for_each_entry_safe(mode, tmp, &list, head) {
3175 list_del(&mode->head);
3176 drm_mode_probed_add(connector, mode);
3177 modes++;
3178 }
3179
3180 return modes;
3181 }
3182
svd_to_vic(u8 svd)3183 static u8 svd_to_vic(u8 svd)
3184 {
3185 /* 0-6 bit vic, 7th bit native mode indicator */
3186 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3187 return svd & 127;
3188
3189 return svd;
3190 }
3191
3192 static struct drm_display_mode *
drm_display_mode_from_vic_index(struct drm_connector * connector,const u8 * video_db,u8 video_len,u8 video_index)3193 drm_display_mode_from_vic_index(struct drm_connector *connector,
3194 const u8 *video_db, u8 video_len,
3195 u8 video_index)
3196 {
3197 struct drm_device *dev = connector->dev;
3198 struct drm_display_mode *newmode;
3199 u8 vic;
3200
3201 if (video_db == NULL || video_index >= video_len)
3202 return NULL;
3203
3204 /* CEA modes are numbered 1..127 */
3205 vic = svd_to_vic(video_db[video_index]);
3206 if (!drm_valid_cea_vic(vic))
3207 return NULL;
3208
3209 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3210 if (!newmode)
3211 return NULL;
3212
3213 newmode->vrefresh = 0;
3214
3215 return newmode;
3216 }
3217
3218 /*
3219 * do_y420vdb_modes - Parse YCBCR 420 only modes
3220 * @connector: connector corresponding to the HDMI sink
3221 * @svds: start of the data block of CEA YCBCR 420 VDB
3222 * @len: length of the CEA YCBCR 420 VDB
3223 *
3224 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3225 * which contains modes which can be supported in YCBCR 420
3226 * output format only.
3227 */
do_y420vdb_modes(struct drm_connector * connector,const u8 * svds,u8 svds_len)3228 static int do_y420vdb_modes(struct drm_connector *connector,
3229 const u8 *svds, u8 svds_len)
3230 {
3231 int modes = 0, i;
3232 struct drm_device *dev = connector->dev;
3233 struct drm_display_info *info = &connector->display_info;
3234 struct drm_hdmi_info *hdmi = &info->hdmi;
3235
3236 for (i = 0; i < svds_len; i++) {
3237 u8 vic = svd_to_vic(svds[i]);
3238 struct drm_display_mode *newmode;
3239
3240 if (!drm_valid_cea_vic(vic))
3241 continue;
3242
3243 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3244 if (!newmode)
3245 break;
3246 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3247 drm_mode_probed_add(connector, newmode);
3248 modes++;
3249 }
3250
3251 if (modes > 0)
3252 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3253 return modes;
3254 }
3255
3256 /*
3257 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3258 * @connector: connector corresponding to the HDMI sink
3259 * @vic: CEA vic for the video mode to be added in the map
3260 *
3261 * Makes an entry for a videomode in the YCBCR 420 bitmap
3262 */
3263 static void
drm_add_cmdb_modes(struct drm_connector * connector,u8 svd)3264 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3265 {
3266 u8 vic = svd_to_vic(svd);
3267 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3268
3269 if (!drm_valid_cea_vic(vic))
3270 return;
3271
3272 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3273 }
3274
3275 static int
do_cea_modes(struct drm_connector * connector,const u8 * db,u8 len)3276 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3277 {
3278 int i, modes = 0;
3279 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3280
3281 for (i = 0; i < len; i++) {
3282 struct drm_display_mode *mode;
3283 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3284 if (mode) {
3285 /*
3286 * YCBCR420 capability block contains a bitmap which
3287 * gives the index of CEA modes from CEA VDB, which
3288 * can support YCBCR 420 sampling output also (apart
3289 * from RGB/YCBCR444 etc).
3290 * For example, if the bit 0 in bitmap is set,
3291 * first mode in VDB can support YCBCR420 output too.
3292 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3293 */
3294 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3295 drm_add_cmdb_modes(connector, db[i]);
3296
3297 drm_mode_probed_add(connector, mode);
3298 modes++;
3299 }
3300 }
3301
3302 return modes;
3303 }
3304
3305 struct stereo_mandatory_mode {
3306 int width, height, vrefresh;
3307 unsigned int flags;
3308 };
3309
3310 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3311 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3312 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3313 { 1920, 1080, 50,
3314 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3315 { 1920, 1080, 60,
3316 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3317 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3318 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3319 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3320 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3321 };
3322
3323 static bool
stereo_match_mandatory(const struct drm_display_mode * mode,const struct stereo_mandatory_mode * stereo_mode)3324 stereo_match_mandatory(const struct drm_display_mode *mode,
3325 const struct stereo_mandatory_mode *stereo_mode)
3326 {
3327 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3328
3329 return mode->hdisplay == stereo_mode->width &&
3330 mode->vdisplay == stereo_mode->height &&
3331 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3332 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3333 }
3334
add_hdmi_mandatory_stereo_modes(struct drm_connector * connector)3335 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3336 {
3337 struct drm_device *dev = connector->dev;
3338 const struct drm_display_mode *mode;
3339 struct list_head stereo_modes;
3340 int modes = 0, i;
3341
3342 INIT_LIST_HEAD(&stereo_modes);
3343
3344 list_for_each_entry(mode, &connector->probed_modes, head) {
3345 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3346 const struct stereo_mandatory_mode *mandatory;
3347 struct drm_display_mode *new_mode;
3348
3349 if (!stereo_match_mandatory(mode,
3350 &stereo_mandatory_modes[i]))
3351 continue;
3352
3353 mandatory = &stereo_mandatory_modes[i];
3354 new_mode = drm_mode_duplicate(dev, mode);
3355 if (!new_mode)
3356 continue;
3357
3358 new_mode->flags |= mandatory->flags;
3359 list_add_tail(&new_mode->head, &stereo_modes);
3360 modes++;
3361 }
3362 }
3363
3364 list_splice_tail(&stereo_modes, &connector->probed_modes);
3365
3366 return modes;
3367 }
3368
add_hdmi_mode(struct drm_connector * connector,u8 vic)3369 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3370 {
3371 struct drm_device *dev = connector->dev;
3372 struct drm_display_mode *newmode;
3373
3374 if (!drm_valid_hdmi_vic(vic)) {
3375 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3376 return 0;
3377 }
3378
3379 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3380 if (!newmode)
3381 return 0;
3382
3383 drm_mode_probed_add(connector, newmode);
3384
3385 return 1;
3386 }
3387
add_3d_struct_modes(struct drm_connector * connector,u16 structure,const u8 * video_db,u8 video_len,u8 video_index)3388 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3389 const u8 *video_db, u8 video_len, u8 video_index)
3390 {
3391 struct drm_display_mode *newmode;
3392 int modes = 0;
3393
3394 if (structure & (1 << 0)) {
3395 newmode = drm_display_mode_from_vic_index(connector, video_db,
3396 video_len,
3397 video_index);
3398 if (newmode) {
3399 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3400 drm_mode_probed_add(connector, newmode);
3401 modes++;
3402 }
3403 }
3404 if (structure & (1 << 6)) {
3405 newmode = drm_display_mode_from_vic_index(connector, video_db,
3406 video_len,
3407 video_index);
3408 if (newmode) {
3409 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3410 drm_mode_probed_add(connector, newmode);
3411 modes++;
3412 }
3413 }
3414 if (structure & (1 << 8)) {
3415 newmode = drm_display_mode_from_vic_index(connector, video_db,
3416 video_len,
3417 video_index);
3418 if (newmode) {
3419 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3420 drm_mode_probed_add(connector, newmode);
3421 modes++;
3422 }
3423 }
3424
3425 return modes;
3426 }
3427
3428 /*
3429 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3430 * @connector: connector corresponding to the HDMI sink
3431 * @db: start of the CEA vendor specific block
3432 * @len: length of the CEA block payload, ie. one can access up to db[len]
3433 *
3434 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3435 * also adds the stereo 3d modes when applicable.
3436 */
3437 static int
do_hdmi_vsdb_modes(struct drm_connector * connector,const u8 * db,u8 len,const u8 * video_db,u8 video_len)3438 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3439 const u8 *video_db, u8 video_len)
3440 {
3441 struct drm_display_info *info = &connector->display_info;
3442 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3443 u8 vic_len, hdmi_3d_len = 0;
3444 u16 mask;
3445 u16 structure_all;
3446
3447 if (len < 8)
3448 goto out;
3449
3450 /* no HDMI_Video_Present */
3451 if (!(db[8] & (1 << 5)))
3452 goto out;
3453
3454 /* Latency_Fields_Present */
3455 if (db[8] & (1 << 7))
3456 offset += 2;
3457
3458 /* I_Latency_Fields_Present */
3459 if (db[8] & (1 << 6))
3460 offset += 2;
3461
3462 /* the declared length is not long enough for the 2 first bytes
3463 * of additional video format capabilities */
3464 if (len < (8 + offset + 2))
3465 goto out;
3466
3467 /* 3D_Present */
3468 offset++;
3469 if (db[8 + offset] & (1 << 7)) {
3470 modes += add_hdmi_mandatory_stereo_modes(connector);
3471
3472 /* 3D_Multi_present */
3473 multi_present = (db[8 + offset] & 0x60) >> 5;
3474 }
3475
3476 offset++;
3477 vic_len = db[8 + offset] >> 5;
3478 hdmi_3d_len = db[8 + offset] & 0x1f;
3479
3480 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3481 u8 vic;
3482
3483 vic = db[9 + offset + i];
3484 modes += add_hdmi_mode(connector, vic);
3485 }
3486 offset += 1 + vic_len;
3487
3488 if (multi_present == 1)
3489 multi_len = 2;
3490 else if (multi_present == 2)
3491 multi_len = 4;
3492 else
3493 multi_len = 0;
3494
3495 if (len < (8 + offset + hdmi_3d_len - 1))
3496 goto out;
3497
3498 if (hdmi_3d_len < multi_len)
3499 goto out;
3500
3501 if (multi_present == 1 || multi_present == 2) {
3502 /* 3D_Structure_ALL */
3503 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3504
3505 /* check if 3D_MASK is present */
3506 if (multi_present == 2)
3507 mask = (db[10 + offset] << 8) | db[11 + offset];
3508 else
3509 mask = 0xffff;
3510
3511 for (i = 0; i < 16; i++) {
3512 if (mask & (1 << i))
3513 modes += add_3d_struct_modes(connector,
3514 structure_all,
3515 video_db,
3516 video_len, i);
3517 }
3518 }
3519
3520 offset += multi_len;
3521
3522 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3523 int vic_index;
3524 struct drm_display_mode *newmode = NULL;
3525 unsigned int newflag = 0;
3526 bool detail_present;
3527
3528 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3529
3530 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3531 break;
3532
3533 /* 2D_VIC_order_X */
3534 vic_index = db[8 + offset + i] >> 4;
3535
3536 /* 3D_Structure_X */
3537 switch (db[8 + offset + i] & 0x0f) {
3538 case 0:
3539 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3540 break;
3541 case 6:
3542 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3543 break;
3544 case 8:
3545 /* 3D_Detail_X */
3546 if ((db[9 + offset + i] >> 4) == 1)
3547 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3548 break;
3549 }
3550
3551 if (newflag != 0) {
3552 newmode = drm_display_mode_from_vic_index(connector,
3553 video_db,
3554 video_len,
3555 vic_index);
3556
3557 if (newmode) {
3558 newmode->flags |= newflag;
3559 drm_mode_probed_add(connector, newmode);
3560 modes++;
3561 }
3562 }
3563
3564 if (detail_present)
3565 i++;
3566 }
3567
3568 out:
3569 if (modes > 0)
3570 info->has_hdmi_infoframe = true;
3571 return modes;
3572 }
3573
3574 static int
cea_db_payload_len(const u8 * db)3575 cea_db_payload_len(const u8 *db)
3576 {
3577 return db[0] & 0x1f;
3578 }
3579
3580 static int
cea_db_extended_tag(const u8 * db)3581 cea_db_extended_tag(const u8 *db)
3582 {
3583 return db[1];
3584 }
3585
3586 static int
cea_db_tag(const u8 * db)3587 cea_db_tag(const u8 *db)
3588 {
3589 return db[0] >> 5;
3590 }
3591
3592 static int
cea_revision(const u8 * cea)3593 cea_revision(const u8 *cea)
3594 {
3595 return cea[1];
3596 }
3597
3598 static int
cea_db_offsets(const u8 * cea,int * start,int * end)3599 cea_db_offsets(const u8 *cea, int *start, int *end)
3600 {
3601 /* Data block offset in CEA extension block */
3602 *start = 4;
3603 *end = cea[2];
3604 if (*end == 0)
3605 *end = 127;
3606 if (*end < 4 || *end > 127)
3607 return -ERANGE;
3608 return 0;
3609 }
3610
cea_db_is_hdmi_vsdb(const u8 * db)3611 static bool cea_db_is_hdmi_vsdb(const u8 *db)
3612 {
3613 int hdmi_id;
3614
3615 if (cea_db_tag(db) != VENDOR_BLOCK)
3616 return false;
3617
3618 if (cea_db_payload_len(db) < 5)
3619 return false;
3620
3621 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3622
3623 return hdmi_id == HDMI_IEEE_OUI;
3624 }
3625
cea_db_is_hdmi_forum_vsdb(const u8 * db)3626 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
3627 {
3628 unsigned int oui;
3629
3630 if (cea_db_tag(db) != VENDOR_BLOCK)
3631 return false;
3632
3633 if (cea_db_payload_len(db) < 7)
3634 return false;
3635
3636 oui = db[3] << 16 | db[2] << 8 | db[1];
3637
3638 return oui == HDMI_FORUM_IEEE_OUI;
3639 }
3640
cea_db_is_y420cmdb(const u8 * db)3641 static bool cea_db_is_y420cmdb(const u8 *db)
3642 {
3643 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3644 return false;
3645
3646 if (!cea_db_payload_len(db))
3647 return false;
3648
3649 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
3650 return false;
3651
3652 return true;
3653 }
3654
cea_db_is_y420vdb(const u8 * db)3655 static bool cea_db_is_y420vdb(const u8 *db)
3656 {
3657 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3658 return false;
3659
3660 if (!cea_db_payload_len(db))
3661 return false;
3662
3663 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
3664 return false;
3665
3666 return true;
3667 }
3668
3669 #define for_each_cea_db(cea, i, start, end) \
3670 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3671
drm_parse_y420cmdb_bitmap(struct drm_connector * connector,const u8 * db)3672 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
3673 const u8 *db)
3674 {
3675 struct drm_display_info *info = &connector->display_info;
3676 struct drm_hdmi_info *hdmi = &info->hdmi;
3677 u8 map_len = cea_db_payload_len(db) - 1;
3678 u8 count;
3679 u64 map = 0;
3680
3681 if (map_len == 0) {
3682 /* All CEA modes support ycbcr420 sampling also.*/
3683 hdmi->y420_cmdb_map = U64_MAX;
3684 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3685 return;
3686 }
3687
3688 /*
3689 * This map indicates which of the existing CEA block modes
3690 * from VDB can support YCBCR420 output too. So if bit=0 is
3691 * set, first mode from VDB can support YCBCR420 output too.
3692 * We will parse and keep this map, before parsing VDB itself
3693 * to avoid going through the same block again and again.
3694 *
3695 * Spec is not clear about max possible size of this block.
3696 * Clamping max bitmap block size at 8 bytes. Every byte can
3697 * address 8 CEA modes, in this way this map can address
3698 * 8*8 = first 64 SVDs.
3699 */
3700 if (WARN_ON_ONCE(map_len > 8))
3701 map_len = 8;
3702
3703 for (count = 0; count < map_len; count++)
3704 map |= (u64)db[2 + count] << (8 * count);
3705
3706 if (map)
3707 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3708
3709 hdmi->y420_cmdb_map = map;
3710 }
3711
3712 static int
add_cea_modes(struct drm_connector * connector,struct edid * edid)3713 add_cea_modes(struct drm_connector *connector, struct edid *edid)
3714 {
3715 const u8 *cea = drm_find_cea_extension(edid);
3716 const u8 *db, *hdmi = NULL, *video = NULL;
3717 u8 dbl, hdmi_len, video_len = 0;
3718 int modes = 0;
3719
3720 if (cea && cea_revision(cea) >= 3) {
3721 int i, start, end;
3722
3723 if (cea_db_offsets(cea, &start, &end))
3724 return 0;
3725
3726 for_each_cea_db(cea, i, start, end) {
3727 db = &cea[i];
3728 dbl = cea_db_payload_len(db);
3729
3730 if (cea_db_tag(db) == VIDEO_BLOCK) {
3731 video = db + 1;
3732 video_len = dbl;
3733 modes += do_cea_modes(connector, video, dbl);
3734 } else if (cea_db_is_hdmi_vsdb(db)) {
3735 hdmi = db;
3736 hdmi_len = dbl;
3737 } else if (cea_db_is_y420vdb(db)) {
3738 const u8 *vdb420 = &db[2];
3739
3740 /* Add 4:2:0(only) modes present in EDID */
3741 modes += do_y420vdb_modes(connector,
3742 vdb420,
3743 dbl - 1);
3744 }
3745 }
3746 }
3747
3748 /*
3749 * We parse the HDMI VSDB after having added the cea modes as we will
3750 * be patching their flags when the sink supports stereo 3D.
3751 */
3752 if (hdmi)
3753 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3754 video_len);
3755
3756 return modes;
3757 }
3758
fixup_detailed_cea_mode_clock(struct drm_display_mode * mode)3759 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3760 {
3761 const struct drm_display_mode *cea_mode;
3762 int clock1, clock2, clock;
3763 u8 vic;
3764 const char *type;
3765
3766 /*
3767 * allow 5kHz clock difference either way to account for
3768 * the 10kHz clock resolution limit of detailed timings.
3769 */
3770 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3771 if (drm_valid_cea_vic(vic)) {
3772 type = "CEA";
3773 cea_mode = &edid_cea_modes[vic];
3774 clock1 = cea_mode->clock;
3775 clock2 = cea_mode_alternate_clock(cea_mode);
3776 } else {
3777 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3778 if (drm_valid_hdmi_vic(vic)) {
3779 type = "HDMI";
3780 cea_mode = &edid_4k_modes[vic];
3781 clock1 = cea_mode->clock;
3782 clock2 = hdmi_mode_alternate_clock(cea_mode);
3783 } else {
3784 return;
3785 }
3786 }
3787
3788 /* pick whichever is closest */
3789 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3790 clock = clock1;
3791 else
3792 clock = clock2;
3793
3794 if (mode->clock == clock)
3795 return;
3796
3797 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3798 type, vic, mode->clock, clock);
3799 mode->clock = clock;
3800 }
3801
3802 static void
drm_parse_hdmi_vsdb_audio(struct drm_connector * connector,const u8 * db)3803 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
3804 {
3805 u8 len = cea_db_payload_len(db);
3806
3807 if (len >= 6 && (db[6] & (1 << 7)))
3808 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
3809 if (len >= 8) {
3810 connector->latency_present[0] = db[8] >> 7;
3811 connector->latency_present[1] = (db[8] >> 6) & 1;
3812 }
3813 if (len >= 9)
3814 connector->video_latency[0] = db[9];
3815 if (len >= 10)
3816 connector->audio_latency[0] = db[10];
3817 if (len >= 11)
3818 connector->video_latency[1] = db[11];
3819 if (len >= 12)
3820 connector->audio_latency[1] = db[12];
3821
3822 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
3823 "video latency %d %d, "
3824 "audio latency %d %d\n",
3825 connector->latency_present[0],
3826 connector->latency_present[1],
3827 connector->video_latency[0],
3828 connector->video_latency[1],
3829 connector->audio_latency[0],
3830 connector->audio_latency[1]);
3831 }
3832
3833 static void
monitor_name(struct detailed_timing * t,void * data)3834 monitor_name(struct detailed_timing *t, void *data)
3835 {
3836 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3837 *(u8 **)data = t->data.other_data.data.str.str;
3838 }
3839
get_monitor_name(struct edid * edid,char name[13])3840 static int get_monitor_name(struct edid *edid, char name[13])
3841 {
3842 char *edid_name = NULL;
3843 int mnl;
3844
3845 if (!edid || !name)
3846 return 0;
3847
3848 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
3849 for (mnl = 0; edid_name && mnl < 13; mnl++) {
3850 if (edid_name[mnl] == 0x0a)
3851 break;
3852
3853 name[mnl] = edid_name[mnl];
3854 }
3855
3856 return mnl;
3857 }
3858
3859 /**
3860 * drm_edid_get_monitor_name - fetch the monitor name from the edid
3861 * @edid: monitor EDID information
3862 * @name: pointer to a character array to hold the name of the monitor
3863 * @bufsize: The size of the name buffer (should be at least 14 chars.)
3864 *
3865 */
drm_edid_get_monitor_name(struct edid * edid,char * name,int bufsize)3866 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
3867 {
3868 int name_length;
3869 char buf[13];
3870
3871 if (bufsize <= 0)
3872 return;
3873
3874 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
3875 memcpy(name, buf, name_length);
3876 name[name_length] = '\0';
3877 }
3878 EXPORT_SYMBOL(drm_edid_get_monitor_name);
3879
clear_eld(struct drm_connector * connector)3880 static void clear_eld(struct drm_connector *connector)
3881 {
3882 memset(connector->eld, 0, sizeof(connector->eld));
3883
3884 connector->latency_present[0] = false;
3885 connector->latency_present[1] = false;
3886 connector->video_latency[0] = 0;
3887 connector->audio_latency[0] = 0;
3888 connector->video_latency[1] = 0;
3889 connector->audio_latency[1] = 0;
3890 }
3891
3892 /*
3893 * drm_edid_to_eld - build ELD from EDID
3894 * @connector: connector corresponding to the HDMI/DP sink
3895 * @edid: EDID to parse
3896 *
3897 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3898 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
3899 */
drm_edid_to_eld(struct drm_connector * connector,struct edid * edid)3900 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3901 {
3902 uint8_t *eld = connector->eld;
3903 u8 *cea;
3904 u8 *db;
3905 int total_sad_count = 0;
3906 int mnl;
3907 int dbl;
3908
3909 clear_eld(connector);
3910
3911 if (!edid)
3912 return;
3913
3914 cea = drm_find_cea_extension(edid);
3915 if (!cea) {
3916 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3917 return;
3918 }
3919
3920 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
3921 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
3922
3923 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
3924 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
3925
3926 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
3927
3928 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
3929 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
3930 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
3931 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
3932
3933 if (cea_revision(cea) >= 3) {
3934 int i, start, end;
3935
3936 if (cea_db_offsets(cea, &start, &end)) {
3937 start = 0;
3938 end = 0;
3939 }
3940
3941 for_each_cea_db(cea, i, start, end) {
3942 db = &cea[i];
3943 dbl = cea_db_payload_len(db);
3944
3945 switch (cea_db_tag(db)) {
3946 int sad_count;
3947
3948 case AUDIO_BLOCK:
3949 /* Audio Data Block, contains SADs */
3950 sad_count = min(dbl / 3, 15 - total_sad_count);
3951 if (sad_count >= 1)
3952 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
3953 &db[1], sad_count * 3);
3954 total_sad_count += sad_count;
3955 break;
3956 case SPEAKER_BLOCK:
3957 /* Speaker Allocation Data Block */
3958 if (dbl >= 1)
3959 eld[DRM_ELD_SPEAKER] = db[1];
3960 break;
3961 case VENDOR_BLOCK:
3962 /* HDMI Vendor-Specific Data Block */
3963 if (cea_db_is_hdmi_vsdb(db))
3964 drm_parse_hdmi_vsdb_audio(connector, db);
3965 break;
3966 default:
3967 break;
3968 }
3969 }
3970 }
3971 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
3972
3973 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
3974 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3975 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
3976 else
3977 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
3978
3979 eld[DRM_ELD_BASELINE_ELD_LEN] =
3980 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
3981
3982 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
3983 drm_eld_size(eld), total_sad_count);
3984 }
3985
3986 /**
3987 * drm_edid_to_sad - extracts SADs from EDID
3988 * @edid: EDID to parse
3989 * @sads: pointer that will be set to the extracted SADs
3990 *
3991 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
3992 *
3993 * Note: The returned pointer needs to be freed using kfree().
3994 *
3995 * Return: The number of found SADs or negative number on error.
3996 */
drm_edid_to_sad(struct edid * edid,struct cea_sad ** sads)3997 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3998 {
3999 int count = 0;
4000 int i, start, end, dbl;
4001 u8 *cea;
4002
4003 cea = drm_find_cea_extension(edid);
4004 if (!cea) {
4005 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4006 return -ENOENT;
4007 }
4008
4009 if (cea_revision(cea) < 3) {
4010 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4011 return -ENOTSUPP;
4012 }
4013
4014 if (cea_db_offsets(cea, &start, &end)) {
4015 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4016 return -EPROTO;
4017 }
4018
4019 for_each_cea_db(cea, i, start, end) {
4020 u8 *db = &cea[i];
4021
4022 if (cea_db_tag(db) == AUDIO_BLOCK) {
4023 int j;
4024 dbl = cea_db_payload_len(db);
4025
4026 count = dbl / 3; /* SAD is 3B */
4027 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4028 if (!*sads)
4029 return -ENOMEM;
4030 for (j = 0; j < count; j++) {
4031 u8 *sad = &db[1 + j * 3];
4032
4033 (*sads)[j].format = (sad[0] & 0x78) >> 3;
4034 (*sads)[j].channels = sad[0] & 0x7;
4035 (*sads)[j].freq = sad[1] & 0x7F;
4036 (*sads)[j].byte2 = sad[2];
4037 }
4038 break;
4039 }
4040 }
4041
4042 return count;
4043 }
4044 EXPORT_SYMBOL(drm_edid_to_sad);
4045
4046 /**
4047 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4048 * @edid: EDID to parse
4049 * @sadb: pointer to the speaker block
4050 *
4051 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
4052 *
4053 * Note: The returned pointer needs to be freed using kfree().
4054 *
4055 * Return: The number of found Speaker Allocation Blocks or negative number on
4056 * error.
4057 */
drm_edid_to_speaker_allocation(struct edid * edid,u8 ** sadb)4058 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4059 {
4060 int count = 0;
4061 int i, start, end, dbl;
4062 const u8 *cea;
4063
4064 cea = drm_find_cea_extension(edid);
4065 if (!cea) {
4066 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4067 return -ENOENT;
4068 }
4069
4070 if (cea_revision(cea) < 3) {
4071 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4072 return -ENOTSUPP;
4073 }
4074
4075 if (cea_db_offsets(cea, &start, &end)) {
4076 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4077 return -EPROTO;
4078 }
4079
4080 for_each_cea_db(cea, i, start, end) {
4081 const u8 *db = &cea[i];
4082
4083 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4084 dbl = cea_db_payload_len(db);
4085
4086 /* Speaker Allocation Data Block */
4087 if (dbl == 3) {
4088 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4089 if (!*sadb)
4090 return -ENOMEM;
4091 count = dbl;
4092 break;
4093 }
4094 }
4095 }
4096
4097 return count;
4098 }
4099 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4100
4101 /**
4102 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
4103 * @connector: connector associated with the HDMI/DP sink
4104 * @mode: the display mode
4105 *
4106 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4107 * the sink doesn't support audio or video.
4108 */
drm_av_sync_delay(struct drm_connector * connector,const struct drm_display_mode * mode)4109 int drm_av_sync_delay(struct drm_connector *connector,
4110 const struct drm_display_mode *mode)
4111 {
4112 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4113 int a, v;
4114
4115 if (!connector->latency_present[0])
4116 return 0;
4117 if (!connector->latency_present[1])
4118 i = 0;
4119
4120 a = connector->audio_latency[i];
4121 v = connector->video_latency[i];
4122
4123 /*
4124 * HDMI/DP sink doesn't support audio or video?
4125 */
4126 if (a == 255 || v == 255)
4127 return 0;
4128
4129 /*
4130 * Convert raw EDID values to millisecond.
4131 * Treat unknown latency as 0ms.
4132 */
4133 if (a)
4134 a = min(2 * (a - 1), 500);
4135 if (v)
4136 v = min(2 * (v - 1), 500);
4137
4138 return max(v - a, 0);
4139 }
4140 EXPORT_SYMBOL(drm_av_sync_delay);
4141
4142 /**
4143 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
4144 * @edid: monitor EDID information
4145 *
4146 * Parse the CEA extension according to CEA-861-B.
4147 *
4148 * Return: True if the monitor is HDMI, false if not or unknown.
4149 */
drm_detect_hdmi_monitor(struct edid * edid)4150 bool drm_detect_hdmi_monitor(struct edid *edid)
4151 {
4152 u8 *edid_ext;
4153 int i;
4154 int start_offset, end_offset;
4155
4156 edid_ext = drm_find_cea_extension(edid);
4157 if (!edid_ext)
4158 return false;
4159
4160 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4161 return false;
4162
4163 /*
4164 * Because HDMI identifier is in Vendor Specific Block,
4165 * search it from all data blocks of CEA extension.
4166 */
4167 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4168 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4169 return true;
4170 }
4171
4172 return false;
4173 }
4174 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4175
4176 /**
4177 * drm_detect_monitor_audio - check monitor audio capability
4178 * @edid: EDID block to scan
4179 *
4180 * Monitor should have CEA extension block.
4181 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4182 * audio' only. If there is any audio extension block and supported
4183 * audio format, assume at least 'basic audio' support, even if 'basic
4184 * audio' is not defined in EDID.
4185 *
4186 * Return: True if the monitor supports audio, false otherwise.
4187 */
drm_detect_monitor_audio(struct edid * edid)4188 bool drm_detect_monitor_audio(struct edid *edid)
4189 {
4190 u8 *edid_ext;
4191 int i, j;
4192 bool has_audio = false;
4193 int start_offset, end_offset;
4194
4195 edid_ext = drm_find_cea_extension(edid);
4196 if (!edid_ext)
4197 goto end;
4198
4199 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4200
4201 if (has_audio) {
4202 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4203 goto end;
4204 }
4205
4206 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4207 goto end;
4208
4209 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4210 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
4211 has_audio = true;
4212 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
4213 DRM_DEBUG_KMS("CEA audio format %d\n",
4214 (edid_ext[i + j] >> 3) & 0xf);
4215 goto end;
4216 }
4217 }
4218 end:
4219 return has_audio;
4220 }
4221 EXPORT_SYMBOL(drm_detect_monitor_audio);
4222
4223 /**
4224 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
4225 * @edid: EDID block to scan
4226 *
4227 * Check whether the monitor reports the RGB quantization range selection
4228 * as supported. The AVI infoframe can then be used to inform the monitor
4229 * which quantization range (full or limited) is used.
4230 *
4231 * Return: True if the RGB quantization range is selectable, false otherwise.
4232 */
drm_rgb_quant_range_selectable(struct edid * edid)4233 bool drm_rgb_quant_range_selectable(struct edid *edid)
4234 {
4235 u8 *edid_ext;
4236 int i, start, end;
4237
4238 edid_ext = drm_find_cea_extension(edid);
4239 if (!edid_ext)
4240 return false;
4241
4242 if (cea_db_offsets(edid_ext, &start, &end))
4243 return false;
4244
4245 for_each_cea_db(edid_ext, i, start, end) {
4246 if (cea_db_tag(&edid_ext[i]) == USE_EXTENDED_TAG &&
4247 cea_db_payload_len(&edid_ext[i]) == 2 &&
4248 cea_db_extended_tag(&edid_ext[i]) ==
4249 EXT_VIDEO_CAPABILITY_BLOCK) {
4250 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
4251 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
4252 }
4253 }
4254
4255 return false;
4256 }
4257 EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
4258
4259 /**
4260 * drm_default_rgb_quant_range - default RGB quantization range
4261 * @mode: display mode
4262 *
4263 * Determine the default RGB quantization range for the mode,
4264 * as specified in CEA-861.
4265 *
4266 * Return: The default RGB quantization range for the mode
4267 */
4268 enum hdmi_quantization_range
drm_default_rgb_quant_range(const struct drm_display_mode * mode)4269 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4270 {
4271 /* All CEA modes other than VIC 1 use limited quantization range. */
4272 return drm_match_cea_mode(mode) > 1 ?
4273 HDMI_QUANTIZATION_RANGE_LIMITED :
4274 HDMI_QUANTIZATION_RANGE_FULL;
4275 }
4276 EXPORT_SYMBOL(drm_default_rgb_quant_range);
4277
drm_parse_ycbcr420_deep_color_info(struct drm_connector * connector,const u8 * db)4278 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4279 const u8 *db)
4280 {
4281 u8 dc_mask;
4282 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4283
4284 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
4285 hdmi->y420_dc_modes = dc_mask;
4286 }
4287
drm_parse_hdmi_forum_vsdb(struct drm_connector * connector,const u8 * hf_vsdb)4288 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4289 const u8 *hf_vsdb)
4290 {
4291 struct drm_display_info *display = &connector->display_info;
4292 struct drm_hdmi_info *hdmi = &display->hdmi;
4293
4294 display->has_hdmi_infoframe = true;
4295
4296 if (hf_vsdb[6] & 0x80) {
4297 hdmi->scdc.supported = true;
4298 if (hf_vsdb[6] & 0x40)
4299 hdmi->scdc.read_request = true;
4300 }
4301
4302 /*
4303 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4304 * And as per the spec, three factors confirm this:
4305 * * Availability of a HF-VSDB block in EDID (check)
4306 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4307 * * SCDC support available (let's check)
4308 * Lets check it out.
4309 */
4310
4311 if (hf_vsdb[5]) {
4312 /* max clock is 5000 KHz times block value */
4313 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4314 struct drm_scdc *scdc = &hdmi->scdc;
4315
4316 if (max_tmds_clock > 340000) {
4317 display->max_tmds_clock = max_tmds_clock;
4318 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4319 display->max_tmds_clock);
4320 }
4321
4322 if (scdc->supported) {
4323 scdc->scrambling.supported = true;
4324
4325 /* Few sinks support scrambling for cloks < 340M */
4326 if ((hf_vsdb[6] & 0x8))
4327 scdc->scrambling.low_rates = true;
4328 }
4329 }
4330
4331 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
4332 }
4333
drm_parse_hdmi_deep_color_info(struct drm_connector * connector,const u8 * hdmi)4334 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4335 const u8 *hdmi)
4336 {
4337 struct drm_display_info *info = &connector->display_info;
4338 unsigned int dc_bpc = 0;
4339
4340 /* HDMI supports at least 8 bpc */
4341 info->bpc = 8;
4342
4343 if (cea_db_payload_len(hdmi) < 6)
4344 return;
4345
4346 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4347 dc_bpc = 10;
4348 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4349 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4350 connector->name);
4351 }
4352
4353 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4354 dc_bpc = 12;
4355 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4356 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4357 connector->name);
4358 }
4359
4360 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4361 dc_bpc = 16;
4362 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4363 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4364 connector->name);
4365 }
4366
4367 if (dc_bpc == 0) {
4368 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4369 connector->name);
4370 return;
4371 }
4372
4373 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4374 connector->name, dc_bpc);
4375 info->bpc = dc_bpc;
4376
4377 /*
4378 * Deep color support mandates RGB444 support for all video
4379 * modes and forbids YCRCB422 support for all video modes per
4380 * HDMI 1.3 spec.
4381 */
4382 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4383
4384 /* YCRCB444 is optional according to spec. */
4385 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4386 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4387 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4388 connector->name);
4389 }
4390
4391 /*
4392 * Spec says that if any deep color mode is supported at all,
4393 * then deep color 36 bit must be supported.
4394 */
4395 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4396 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4397 connector->name);
4398 }
4399 }
4400
4401 static void
drm_parse_hdmi_vsdb_video(struct drm_connector * connector,const u8 * db)4402 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4403 {
4404 struct drm_display_info *info = &connector->display_info;
4405 u8 len = cea_db_payload_len(db);
4406
4407 if (len >= 6)
4408 info->dvi_dual = db[6] & 1;
4409 if (len >= 7)
4410 info->max_tmds_clock = db[7] * 5000;
4411
4412 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4413 "max TMDS clock %d kHz\n",
4414 info->dvi_dual,
4415 info->max_tmds_clock);
4416
4417 drm_parse_hdmi_deep_color_info(connector, db);
4418 }
4419
drm_parse_cea_ext(struct drm_connector * connector,const struct edid * edid)4420 static void drm_parse_cea_ext(struct drm_connector *connector,
4421 const struct edid *edid)
4422 {
4423 struct drm_display_info *info = &connector->display_info;
4424 const u8 *edid_ext;
4425 int i, start, end;
4426
4427 edid_ext = drm_find_cea_extension(edid);
4428 if (!edid_ext)
4429 return;
4430
4431 info->cea_rev = edid_ext[1];
4432
4433 /* The existence of a CEA block should imply RGB support */
4434 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4435 if (edid_ext[3] & EDID_CEA_YCRCB444)
4436 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4437 if (edid_ext[3] & EDID_CEA_YCRCB422)
4438 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4439
4440 if (cea_db_offsets(edid_ext, &start, &end))
4441 return;
4442
4443 for_each_cea_db(edid_ext, i, start, end) {
4444 const u8 *db = &edid_ext[i];
4445
4446 if (cea_db_is_hdmi_vsdb(db))
4447 drm_parse_hdmi_vsdb_video(connector, db);
4448 if (cea_db_is_hdmi_forum_vsdb(db))
4449 drm_parse_hdmi_forum_vsdb(connector, db);
4450 if (cea_db_is_y420cmdb(db))
4451 drm_parse_y420cmdb_bitmap(connector, db);
4452 }
4453 }
4454
4455 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
4456 * all of the values which would have been set from EDID
4457 */
4458 void
drm_reset_display_info(struct drm_connector * connector)4459 drm_reset_display_info(struct drm_connector *connector)
4460 {
4461 struct drm_display_info *info = &connector->display_info;
4462
4463 info->width_mm = 0;
4464 info->height_mm = 0;
4465
4466 info->bpc = 0;
4467 info->color_formats = 0;
4468 info->cea_rev = 0;
4469 info->max_tmds_clock = 0;
4470 info->dvi_dual = false;
4471 info->has_hdmi_infoframe = false;
4472 memset(&info->hdmi, 0, sizeof(info->hdmi));
4473
4474 info->non_desktop = 0;
4475 }
4476
drm_add_display_info(struct drm_connector * connector,const struct edid * edid)4477 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
4478 {
4479 struct drm_display_info *info = &connector->display_info;
4480
4481 u32 quirks = edid_get_quirks(edid);
4482
4483 drm_reset_display_info(connector);
4484
4485 info->width_mm = edid->width_cm * 10;
4486 info->height_mm = edid->height_cm * 10;
4487
4488 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
4489
4490 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
4491
4492 if (edid->revision < 3)
4493 return quirks;
4494
4495 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
4496 return quirks;
4497
4498 drm_parse_cea_ext(connector, edid);
4499
4500 /*
4501 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
4502 *
4503 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
4504 * tells us to assume 8 bpc color depth if the EDID doesn't have
4505 * extensions which tell otherwise.
4506 */
4507 if ((info->bpc == 0) && (edid->revision < 4) &&
4508 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) {
4509 info->bpc = 8;
4510 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4511 connector->name, info->bpc);
4512 }
4513
4514 /* Only defined for 1.4 with digital displays */
4515 if (edid->revision < 4)
4516 return quirks;
4517
4518 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
4519 case DRM_EDID_DIGITAL_DEPTH_6:
4520 info->bpc = 6;
4521 break;
4522 case DRM_EDID_DIGITAL_DEPTH_8:
4523 info->bpc = 8;
4524 break;
4525 case DRM_EDID_DIGITAL_DEPTH_10:
4526 info->bpc = 10;
4527 break;
4528 case DRM_EDID_DIGITAL_DEPTH_12:
4529 info->bpc = 12;
4530 break;
4531 case DRM_EDID_DIGITAL_DEPTH_14:
4532 info->bpc = 14;
4533 break;
4534 case DRM_EDID_DIGITAL_DEPTH_16:
4535 info->bpc = 16;
4536 break;
4537 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
4538 default:
4539 info->bpc = 0;
4540 break;
4541 }
4542
4543 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
4544 connector->name, info->bpc);
4545
4546 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
4547 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
4548 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4549 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
4550 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4551 return quirks;
4552 }
4553
validate_displayid(u8 * displayid,int length,int idx)4554 static int validate_displayid(u8 *displayid, int length, int idx)
4555 {
4556 int i;
4557 u8 csum = 0;
4558 struct displayid_hdr *base;
4559
4560 base = (struct displayid_hdr *)&displayid[idx];
4561
4562 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4563 base->rev, base->bytes, base->prod_id, base->ext_count);
4564
4565 if (base->bytes + 5 > length - idx)
4566 return -EINVAL;
4567 for (i = idx; i <= base->bytes + 5; i++) {
4568 csum += displayid[i];
4569 }
4570 if (csum) {
4571 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
4572 return -EINVAL;
4573 }
4574 return 0;
4575 }
4576
drm_mode_displayid_detailed(struct drm_device * dev,struct displayid_detailed_timings_1 * timings)4577 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
4578 struct displayid_detailed_timings_1 *timings)
4579 {
4580 struct drm_display_mode *mode;
4581 unsigned pixel_clock = (timings->pixel_clock[0] |
4582 (timings->pixel_clock[1] << 8) |
4583 (timings->pixel_clock[2] << 16));
4584 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
4585 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
4586 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
4587 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
4588 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
4589 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
4590 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4591 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4592 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4593 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4594 mode = drm_mode_create(dev);
4595 if (!mode)
4596 return NULL;
4597
4598 mode->clock = pixel_clock * 10;
4599 mode->hdisplay = hactive;
4600 mode->hsync_start = mode->hdisplay + hsync;
4601 mode->hsync_end = mode->hsync_start + hsync_width;
4602 mode->htotal = mode->hdisplay + hblank;
4603
4604 mode->vdisplay = vactive;
4605 mode->vsync_start = mode->vdisplay + vsync;
4606 mode->vsync_end = mode->vsync_start + vsync_width;
4607 mode->vtotal = mode->vdisplay + vblank;
4608
4609 mode->flags = 0;
4610 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4611 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4612 mode->type = DRM_MODE_TYPE_DRIVER;
4613
4614 if (timings->flags & 0x80)
4615 mode->type |= DRM_MODE_TYPE_PREFERRED;
4616 mode->vrefresh = drm_mode_vrefresh(mode);
4617 drm_mode_set_name(mode);
4618
4619 return mode;
4620 }
4621
add_displayid_detailed_1_modes(struct drm_connector * connector,struct displayid_block * block)4622 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4623 struct displayid_block *block)
4624 {
4625 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4626 int i;
4627 int num_timings;
4628 struct drm_display_mode *newmode;
4629 int num_modes = 0;
4630 /* blocks must be multiple of 20 bytes length */
4631 if (block->num_bytes % 20)
4632 return 0;
4633
4634 num_timings = block->num_bytes / 20;
4635 for (i = 0; i < num_timings; i++) {
4636 struct displayid_detailed_timings_1 *timings = &det->timings[i];
4637
4638 newmode = drm_mode_displayid_detailed(connector->dev, timings);
4639 if (!newmode)
4640 continue;
4641
4642 drm_mode_probed_add(connector, newmode);
4643 num_modes++;
4644 }
4645 return num_modes;
4646 }
4647
add_displayid_detailed_modes(struct drm_connector * connector,struct edid * edid)4648 static int add_displayid_detailed_modes(struct drm_connector *connector,
4649 struct edid *edid)
4650 {
4651 u8 *displayid;
4652 int ret;
4653 int idx = 1;
4654 int length = EDID_LENGTH;
4655 struct displayid_block *block;
4656 int num_modes = 0;
4657
4658 displayid = drm_find_displayid_extension(edid);
4659 if (!displayid)
4660 return 0;
4661
4662 ret = validate_displayid(displayid, length, idx);
4663 if (ret)
4664 return 0;
4665
4666 idx += sizeof(struct displayid_hdr);
4667 while (block = (struct displayid_block *)&displayid[idx],
4668 idx + sizeof(struct displayid_block) <= length &&
4669 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4670 block->num_bytes > 0) {
4671 idx += block->num_bytes + sizeof(struct displayid_block);
4672 switch (block->tag) {
4673 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4674 num_modes += add_displayid_detailed_1_modes(connector, block);
4675 break;
4676 }
4677 }
4678 return num_modes;
4679 }
4680
4681 /**
4682 * drm_add_edid_modes - add modes from EDID data, if available
4683 * @connector: connector we're probing
4684 * @edid: EDID data
4685 *
4686 * Add the specified modes to the connector's mode list. Also fills out the
4687 * &drm_display_info structure and ELD in @connector with any information which
4688 * can be derived from the edid.
4689 *
4690 * Return: The number of modes added or 0 if we couldn't find any.
4691 */
drm_add_edid_modes(struct drm_connector * connector,struct edid * edid)4692 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4693 {
4694 int num_modes = 0;
4695 u32 quirks;
4696
4697 if (edid == NULL) {
4698 clear_eld(connector);
4699 return 0;
4700 }
4701 if (!drm_edid_is_valid(edid)) {
4702 clear_eld(connector);
4703 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
4704 connector->name);
4705 return 0;
4706 }
4707
4708 drm_edid_to_eld(connector, edid);
4709
4710 /*
4711 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
4712 * To avoid multiple parsing of same block, lets parse that map
4713 * from sink info, before parsing CEA modes.
4714 */
4715 quirks = drm_add_display_info(connector, edid);
4716
4717 /*
4718 * EDID spec says modes should be preferred in this order:
4719 * - preferred detailed mode
4720 * - other detailed modes from base block
4721 * - detailed modes from extension blocks
4722 * - CVT 3-byte code modes
4723 * - standard timing codes
4724 * - established timing codes
4725 * - modes inferred from GTF or CVT range information
4726 *
4727 * We get this pretty much right.
4728 *
4729 * XXX order for additional mode types in extension blocks?
4730 */
4731 num_modes += add_detailed_modes(connector, edid, quirks);
4732 num_modes += add_cvt_modes(connector, edid);
4733 num_modes += add_standard_modes(connector, edid);
4734 num_modes += add_established_modes(connector, edid);
4735 num_modes += add_cea_modes(connector, edid);
4736 num_modes += add_alternate_cea_modes(connector, edid);
4737 num_modes += add_displayid_detailed_modes(connector, edid);
4738 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4739 num_modes += add_inferred_modes(connector, edid);
4740
4741 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4742 edid_fixup_preferred(connector, quirks);
4743
4744 if (quirks & EDID_QUIRK_FORCE_6BPC)
4745 connector->display_info.bpc = 6;
4746
4747 if (quirks & EDID_QUIRK_FORCE_8BPC)
4748 connector->display_info.bpc = 8;
4749
4750 if (quirks & EDID_QUIRK_FORCE_10BPC)
4751 connector->display_info.bpc = 10;
4752
4753 if (quirks & EDID_QUIRK_FORCE_12BPC)
4754 connector->display_info.bpc = 12;
4755
4756 return num_modes;
4757 }
4758 EXPORT_SYMBOL(drm_add_edid_modes);
4759
4760 /**
4761 * drm_add_modes_noedid - add modes for the connectors without EDID
4762 * @connector: connector we're probing
4763 * @hdisplay: the horizontal display limit
4764 * @vdisplay: the vertical display limit
4765 *
4766 * Add the specified modes to the connector's mode list. Only when the
4767 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4768 *
4769 * Return: The number of modes added or 0 if we couldn't find any.
4770 */
drm_add_modes_noedid(struct drm_connector * connector,int hdisplay,int vdisplay)4771 int drm_add_modes_noedid(struct drm_connector *connector,
4772 int hdisplay, int vdisplay)
4773 {
4774 int i, count, num_modes = 0;
4775 struct drm_display_mode *mode;
4776 struct drm_device *dev = connector->dev;
4777
4778 count = ARRAY_SIZE(drm_dmt_modes);
4779 if (hdisplay < 0)
4780 hdisplay = 0;
4781 if (vdisplay < 0)
4782 vdisplay = 0;
4783
4784 for (i = 0; i < count; i++) {
4785 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
4786 if (hdisplay && vdisplay) {
4787 /*
4788 * Only when two are valid, they will be used to check
4789 * whether the mode should be added to the mode list of
4790 * the connector.
4791 */
4792 if (ptr->hdisplay > hdisplay ||
4793 ptr->vdisplay > vdisplay)
4794 continue;
4795 }
4796 if (drm_mode_vrefresh(ptr) > 61)
4797 continue;
4798 mode = drm_mode_duplicate(dev, ptr);
4799 if (mode) {
4800 drm_mode_probed_add(connector, mode);
4801 num_modes++;
4802 }
4803 }
4804 return num_modes;
4805 }
4806 EXPORT_SYMBOL(drm_add_modes_noedid);
4807
4808 /**
4809 * drm_set_preferred_mode - Sets the preferred mode of a connector
4810 * @connector: connector whose mode list should be processed
4811 * @hpref: horizontal resolution of preferred mode
4812 * @vpref: vertical resolution of preferred mode
4813 *
4814 * Marks a mode as preferred if it matches the resolution specified by @hpref
4815 * and @vpref.
4816 */
drm_set_preferred_mode(struct drm_connector * connector,int hpref,int vpref)4817 void drm_set_preferred_mode(struct drm_connector *connector,
4818 int hpref, int vpref)
4819 {
4820 struct drm_display_mode *mode;
4821
4822 list_for_each_entry(mode, &connector->probed_modes, head) {
4823 if (mode->hdisplay == hpref &&
4824 mode->vdisplay == vpref)
4825 mode->type |= DRM_MODE_TYPE_PREFERRED;
4826 }
4827 }
4828 EXPORT_SYMBOL(drm_set_preferred_mode);
4829
4830 /**
4831 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4832 * data from a DRM display mode
4833 * @frame: HDMI AVI infoframe
4834 * @mode: DRM display mode
4835 * @is_hdmi2_sink: Sink is HDMI 2.0 compliant
4836 *
4837 * Return: 0 on success or a negative error code on failure.
4838 */
4839 int
drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe * frame,const struct drm_display_mode * mode,bool is_hdmi2_sink)4840 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
4841 const struct drm_display_mode *mode,
4842 bool is_hdmi2_sink)
4843 {
4844 enum hdmi_picture_aspect picture_aspect;
4845 int err;
4846
4847 if (!frame || !mode)
4848 return -EINVAL;
4849
4850 err = hdmi_avi_infoframe_init(frame);
4851 if (err < 0)
4852 return err;
4853
4854 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
4855 frame->pixel_repeat = 1;
4856
4857 frame->video_code = drm_match_cea_mode(mode);
4858
4859 /*
4860 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
4861 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
4862 * have to make sure we dont break HDMI 1.4 sinks.
4863 */
4864 if (!is_hdmi2_sink && frame->video_code > 64)
4865 frame->video_code = 0;
4866
4867 /*
4868 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
4869 * we should send its VIC in vendor infoframes, else send the
4870 * VIC in AVI infoframes. Lets check if this mode is present in
4871 * HDMI 1.4b 4K modes
4872 */
4873 if (frame->video_code) {
4874 u8 vendor_if_vic = drm_match_hdmi_mode(mode);
4875 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK;
4876
4877 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d)
4878 frame->video_code = 0;
4879 }
4880
4881 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4882
4883 /*
4884 * As some drivers don't support atomic, we can't use connector state.
4885 * So just initialize the frame with default values, just the same way
4886 * as it's done with other properties here.
4887 */
4888 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
4889 frame->itc = 0;
4890
4891 /*
4892 * Populate picture aspect ratio from either
4893 * user input (if specified) or from the CEA mode list.
4894 */
4895 picture_aspect = mode->picture_aspect_ratio;
4896 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE)
4897 picture_aspect = drm_get_cea_aspect_ratio(frame->video_code);
4898
4899 /*
4900 * The infoframe can't convey anything but none, 4:3
4901 * and 16:9, so if the user has asked for anything else
4902 * we can only satisfy it by specifying the right VIC.
4903 */
4904 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
4905 if (picture_aspect !=
4906 drm_get_cea_aspect_ratio(frame->video_code))
4907 return -EINVAL;
4908 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4909 }
4910
4911 frame->picture_aspect = picture_aspect;
4912 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
4913 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
4914
4915 return 0;
4916 }
4917 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
4918
4919 /**
4920 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
4921 * quantization range information
4922 * @frame: HDMI AVI infoframe
4923 * @mode: DRM display mode
4924 * @rgb_quant_range: RGB quantization range (Q)
4925 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS)
4926 * @is_hdmi2_sink: HDMI 2.0 sink, which has different default recommendations
4927 *
4928 * Note that @is_hdmi2_sink can be derived by looking at the
4929 * &drm_scdc.supported flag stored in &drm_hdmi_info.scdc,
4930 * &drm_display_info.hdmi, which can be found in &drm_connector.display_info.
4931 */
4932 void
drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe * frame,const struct drm_display_mode * mode,enum hdmi_quantization_range rgb_quant_range,bool rgb_quant_range_selectable,bool is_hdmi2_sink)4933 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
4934 const struct drm_display_mode *mode,
4935 enum hdmi_quantization_range rgb_quant_range,
4936 bool rgb_quant_range_selectable,
4937 bool is_hdmi2_sink)
4938 {
4939 /*
4940 * CEA-861:
4941 * "A Source shall not send a non-zero Q value that does not correspond
4942 * to the default RGB Quantization Range for the transmitted Picture
4943 * unless the Sink indicates support for the Q bit in a Video
4944 * Capabilities Data Block."
4945 *
4946 * HDMI 2.0 recommends sending non-zero Q when it does match the
4947 * default RGB quantization range for the mode, even when QS=0.
4948 */
4949 if (rgb_quant_range_selectable ||
4950 rgb_quant_range == drm_default_rgb_quant_range(mode))
4951 frame->quantization_range = rgb_quant_range;
4952 else
4953 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
4954
4955 /*
4956 * CEA-861-F:
4957 * "When transmitting any RGB colorimetry, the Source should set the
4958 * YQ-field to match the RGB Quantization Range being transmitted
4959 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
4960 * set YQ=1) and the Sink shall ignore the YQ-field."
4961 *
4962 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
4963 * by non-zero YQ when receiving RGB. There doesn't seem to be any
4964 * good way to tell which version of CEA-861 the sink supports, so
4965 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
4966 * on on CEA-861-F.
4967 */
4968 if (!is_hdmi2_sink ||
4969 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
4970 frame->ycc_quantization_range =
4971 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
4972 else
4973 frame->ycc_quantization_range =
4974 HDMI_YCC_QUANTIZATION_RANGE_FULL;
4975 }
4976 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
4977
4978 static enum hdmi_3d_structure
s3d_structure_from_display_mode(const struct drm_display_mode * mode)4979 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
4980 {
4981 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
4982
4983 switch (layout) {
4984 case DRM_MODE_FLAG_3D_FRAME_PACKING:
4985 return HDMI_3D_STRUCTURE_FRAME_PACKING;
4986 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
4987 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
4988 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
4989 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
4990 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
4991 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
4992 case DRM_MODE_FLAG_3D_L_DEPTH:
4993 return HDMI_3D_STRUCTURE_L_DEPTH;
4994 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
4995 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
4996 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
4997 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
4998 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
4999 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
5000 default:
5001 return HDMI_3D_STRUCTURE_INVALID;
5002 }
5003 }
5004
5005 /**
5006 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
5007 * data from a DRM display mode
5008 * @frame: HDMI vendor infoframe
5009 * @connector: the connector
5010 * @mode: DRM display mode
5011 *
5012 * Note that there's is a need to send HDMI vendor infoframes only when using a
5013 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
5014 * function will return -EINVAL, error that can be safely ignored.
5015 *
5016 * Return: 0 on success or a negative error code on failure.
5017 */
5018 int
drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe * frame,struct drm_connector * connector,const struct drm_display_mode * mode)5019 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
5020 struct drm_connector *connector,
5021 const struct drm_display_mode *mode)
5022 {
5023 /*
5024 * FIXME: sil-sii8620 doesn't have a connector around when
5025 * we need one, so we have to be prepared for a NULL connector.
5026 */
5027 bool has_hdmi_infoframe = connector ?
5028 connector->display_info.has_hdmi_infoframe : false;
5029 int err;
5030 u32 s3d_flags;
5031 u8 vic;
5032
5033 if (!frame || !mode)
5034 return -EINVAL;
5035
5036 if (!has_hdmi_infoframe)
5037 return -EINVAL;
5038
5039 vic = drm_match_hdmi_mode(mode);
5040 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
5041
5042 /*
5043 * Even if it's not absolutely necessary to send the infoframe
5044 * (ie.vic==0 and s3d_struct==0) we will still send it if we
5045 * know that the sink can handle it. This is based on a
5046 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
5047 * have trouble realizing that they shuld switch from 3D to 2D
5048 * mode if the source simply stops sending the infoframe when
5049 * it wants to switch from 3D to 2D.
5050 */
5051
5052 if (vic && s3d_flags)
5053 return -EINVAL;
5054
5055 err = hdmi_vendor_infoframe_init(frame);
5056 if (err < 0)
5057 return err;
5058
5059 frame->vic = vic;
5060 frame->s3d_struct = s3d_structure_from_display_mode(mode);
5061
5062 return 0;
5063 }
5064 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
5065
drm_parse_tiled_block(struct drm_connector * connector,struct displayid_block * block)5066 static int drm_parse_tiled_block(struct drm_connector *connector,
5067 struct displayid_block *block)
5068 {
5069 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5070 u16 w, h;
5071 u8 tile_v_loc, tile_h_loc;
5072 u8 num_v_tile, num_h_tile;
5073 struct drm_tile_group *tg;
5074
5075 w = tile->tile_size[0] | tile->tile_size[1] << 8;
5076 h = tile->tile_size[2] | tile->tile_size[3] << 8;
5077
5078 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
5079 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
5080 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
5081 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
5082
5083 connector->has_tile = true;
5084 if (tile->tile_cap & 0x80)
5085 connector->tile_is_single_monitor = true;
5086
5087 connector->num_h_tile = num_h_tile + 1;
5088 connector->num_v_tile = num_v_tile + 1;
5089 connector->tile_h_loc = tile_h_loc;
5090 connector->tile_v_loc = tile_v_loc;
5091 connector->tile_h_size = w + 1;
5092 connector->tile_v_size = h + 1;
5093
5094 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
5095 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
5096 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
5097 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
5098 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5099
5100 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
5101 if (!tg) {
5102 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5103 }
5104 if (!tg)
5105 return -ENOMEM;
5106
5107 if (connector->tile_group != tg) {
5108 /* if we haven't got a pointer,
5109 take the reference, drop ref to old tile group */
5110 if (connector->tile_group) {
5111 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5112 }
5113 connector->tile_group = tg;
5114 } else
5115 /* if same tile group, then release the ref we just took. */
5116 drm_mode_put_tile_group(connector->dev, tg);
5117 return 0;
5118 }
5119
drm_parse_display_id(struct drm_connector * connector,u8 * displayid,int length,bool is_edid_extension)5120 static int drm_parse_display_id(struct drm_connector *connector,
5121 u8 *displayid, int length,
5122 bool is_edid_extension)
5123 {
5124 /* if this is an EDID extension the first byte will be 0x70 */
5125 int idx = 0;
5126 struct displayid_block *block;
5127 int ret;
5128
5129 if (is_edid_extension)
5130 idx = 1;
5131
5132 ret = validate_displayid(displayid, length, idx);
5133 if (ret)
5134 return ret;
5135
5136 idx += sizeof(struct displayid_hdr);
5137 while (block = (struct displayid_block *)&displayid[idx],
5138 idx + sizeof(struct displayid_block) <= length &&
5139 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
5140 block->num_bytes > 0) {
5141 idx += block->num_bytes + sizeof(struct displayid_block);
5142 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5143 block->tag, block->rev, block->num_bytes);
5144
5145 switch (block->tag) {
5146 case DATA_BLOCK_TILED_DISPLAY:
5147 ret = drm_parse_tiled_block(connector, block);
5148 if (ret)
5149 return ret;
5150 break;
5151 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5152 /* handled in mode gathering code. */
5153 break;
5154 default:
5155 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
5156 break;
5157 }
5158 }
5159 return 0;
5160 }
5161
drm_get_displayid(struct drm_connector * connector,struct edid * edid)5162 static void drm_get_displayid(struct drm_connector *connector,
5163 struct edid *edid)
5164 {
5165 void *displayid = NULL;
5166 int ret;
5167 connector->has_tile = false;
5168 displayid = drm_find_displayid_extension(edid);
5169 if (!displayid) {
5170 /* drop reference to any tile group we had */
5171 goto out_drop_ref;
5172 }
5173
5174 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
5175 if (ret < 0)
5176 goto out_drop_ref;
5177 if (!connector->has_tile)
5178 goto out_drop_ref;
5179 return;
5180 out_drop_ref:
5181 if (connector->tile_group) {
5182 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5183 connector->tile_group = NULL;
5184 }
5185 return;
5186 }
5187
