1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * DRA7 Clock init 4 * 5 * Copyright (C) 2013 Texas Instruments, Inc. 6 * 7 * Tero Kristo (t-kristo@ti.com) 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/list.h> 12 #include <linux/clk.h> 13 #include <linux/clkdev.h> 14 #include <linux/clk/ti.h> 15 #include <dt-bindings/clock/dra7.h> 16 17 #include "clock.h" 18 19 #define DRA7_DPLL_GMAC_DEFFREQ 1000000000 20 #define DRA7_DPLL_USB_DEFFREQ 960000000 21 22 static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = { 23 { DRA7_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" }, 24 { 0 }, 25 }; 26 27 static const char * const dra7_mcasp1_aux_gfclk_mux_parents[] __initconst = { 28 "per_abe_x1_gfclk2_div", 29 "video1_clk2_div", 30 "video2_clk2_div", 31 "hdmi_clk2_div", 32 NULL, 33 }; 34 35 static const char * const dra7_mcasp1_ahclkx_mux_parents[] __initconst = { 36 "abe_24m_fclk", 37 "abe_sys_clk_div", 38 "func_24m_clk", 39 "atl_clkin3_ck", 40 "atl_clkin2_ck", 41 "atl_clkin1_ck", 42 "atl_clkin0_ck", 43 "sys_clkin2", 44 "ref_clkin0_ck", 45 "ref_clkin1_ck", 46 "ref_clkin2_ck", 47 "ref_clkin3_ck", 48 "mlb_clk", 49 "mlbp_clk", 50 NULL, 51 }; 52 53 static const struct omap_clkctrl_bit_data dra7_mcasp1_bit_data[] __initconst = { 54 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 55 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 56 { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 57 { 0 }, 58 }; 59 60 static const char * const dra7_timer5_gfclk_mux_parents[] __initconst = { 61 "timer_sys_clk_div", 62 "sys_32k_ck", 63 "sys_clkin2", 64 "ref_clkin0_ck", 65 "ref_clkin1_ck", 66 "ref_clkin2_ck", 67 "ref_clkin3_ck", 68 "abe_giclk_div", 69 "video1_div_clk", 70 "video2_div_clk", 71 "hdmi_div_clk", 72 "clkoutmux0_clk_mux", 73 NULL, 74 }; 75 76 static const struct omap_clkctrl_bit_data dra7_timer5_bit_data[] __initconst = { 77 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL }, 78 { 0 }, 79 }; 80 81 static const struct omap_clkctrl_bit_data dra7_timer6_bit_data[] __initconst = { 82 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL }, 83 { 0 }, 84 }; 85 86 static const struct omap_clkctrl_bit_data dra7_timer7_bit_data[] __initconst = { 87 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL }, 88 { 0 }, 89 }; 90 91 static const struct omap_clkctrl_bit_data dra7_timer8_bit_data[] __initconst = { 92 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL }, 93 { 0 }, 94 }; 95 96 static const char * const dra7_uart6_gfclk_mux_parents[] __initconst = { 97 "func_48m_fclk", 98 "dpll_per_m2x2_ck", 99 NULL, 100 }; 101 102 static const struct omap_clkctrl_bit_data dra7_uart6_bit_data[] __initconst = { 103 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 104 { 0 }, 105 }; 106 107 static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = { 108 { DRA7_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0010:22" }, 109 { DRA7_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0018:24" }, 110 { DRA7_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0020:24" }, 111 { DRA7_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0028:24" }, 112 { DRA7_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0030:24" }, 113 { DRA7_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 114 { DRA7_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0040:24" }, 115 { 0 }, 116 }; 117 118 static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = { 119 { DRA7_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, 120 { 0 }, 121 }; 122 123 static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = { 124 { DRA7_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" }, 125 { DRA7_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" }, 126 { 0 }, 127 }; 128 129 static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = { 130 { DRA7_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" }, 131 { DRA7_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 132 { DRA7_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" }, 133 { DRA7_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 134 { DRA7_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 135 { DRA7_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" }, 136 { DRA7_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" }, 137 { 0 }, 138 }; 139 140 static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = { 141 { DRA7_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" }, 142 { 0 }, 143 }; 144 145 static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = { 146 { DRA7_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" }, 147 { 0 }, 148 }; 149 150 static const char * const dra7_atl_dpll_clk_mux_parents[] __initconst = { 151 "sys_32k_ck", 152 "video1_clkin_ck", 153 "video2_clkin_ck", 154 "hdmi_clkin_ck", 155 NULL, 156 }; 157 158 static const char * const dra7_atl_gfclk_mux_parents[] __initconst = { 159 "l3_iclk_div", 160 "dpll_abe_m2_ck", 161 "atl_cm:clk:0000:24", 162 NULL, 163 }; 164 165 static const struct omap_clkctrl_bit_data dra7_atl_bit_data[] __initconst = { 166 { 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL }, 167 { 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL }, 168 { 0 }, 169 }; 170 171 static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = { 172 { DRA7_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl_cm:clk:0000:26" }, 173 { 0 }, 174 }; 175 176 static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = { 177 { DRA7_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" }, 178 { DRA7_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" }, 179 { DRA7_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" }, 180 { DRA7_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" }, 181 { DRA7_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" }, 182 { DRA7_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" }, 183 { DRA7_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" }, 184 { DRA7_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" }, 185 { DRA7_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" }, 186 { DRA7_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" }, 187 { DRA7_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" }, 188 { DRA7_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" }, 189 { DRA7_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" }, 190 { DRA7_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" }, 191 { DRA7_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" }, 192 { 0 }, 193 }; 194 195 static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = { 196 { DRA7_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 197 { DRA7_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 198 { 0 }, 199 }; 200 201 static const char * const dra7_dss_dss_clk_parents[] __initconst = { 202 "dpll_per_h12x2_ck", 203 NULL, 204 }; 205 206 static const char * const dra7_dss_48mhz_clk_parents[] __initconst = { 207 "func_48m_fclk", 208 NULL, 209 }; 210 211 static const char * const dra7_dss_hdmi_clk_parents[] __initconst = { 212 "hdmi_dpll_clk_mux", 213 NULL, 214 }; 215 216 static const char * const dra7_dss_32khz_clk_parents[] __initconst = { 217 "sys_32k_ck", 218 NULL, 219 }; 220 221 static const char * const dra7_dss_video1_clk_parents[] __initconst = { 222 "video1_dpll_clk_mux", 223 NULL, 224 }; 225 226 static const char * const dra7_dss_video2_clk_parents[] __initconst = { 227 "video2_dpll_clk_mux", 228 NULL, 229 }; 230 231 static const struct omap_clkctrl_bit_data dra7_dss_core_bit_data[] __initconst = { 232 { 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL }, 233 { 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL }, 234 { 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL }, 235 { 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 236 { 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL }, 237 { 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL }, 238 { 0 }, 239 }; 240 241 static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = { 242 { DRA7_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" }, 243 { DRA7_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" }, 244 { 0 }, 245 }; 246 247 static const char * const dra7_mmc1_fclk_mux_parents[] __initconst = { 248 "func_128m_clk", 249 "dpll_per_m2x2_ck", 250 NULL, 251 }; 252 253 static const char * const dra7_mmc1_fclk_div_parents[] __initconst = { 254 "l3init_cm:clk:0008:24", 255 NULL, 256 }; 257 258 static const struct omap_clkctrl_div_data dra7_mmc1_fclk_div_data __initconst = { 259 .max_div = 4, 260 .flags = CLK_DIVIDER_POWER_OF_TWO, 261 }; 262 263 static const struct omap_clkctrl_bit_data dra7_mmc1_bit_data[] __initconst = { 264 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 265 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL }, 266 { 25, TI_CLK_DIVIDER, dra7_mmc1_fclk_div_parents, &dra7_mmc1_fclk_div_data }, 267 { 0 }, 268 }; 269 270 static const char * const dra7_mmc2_fclk_div_parents[] __initconst = { 271 "l3init_cm:clk:0010:24", 272 NULL, 273 }; 274 275 static const struct omap_clkctrl_div_data dra7_mmc2_fclk_div_data __initconst = { 276 .max_div = 4, 277 .flags = CLK_DIVIDER_POWER_OF_TWO, 278 }; 279 280 static const struct omap_clkctrl_bit_data dra7_mmc2_bit_data[] __initconst = { 281 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 282 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL }, 283 { 25, TI_CLK_DIVIDER, dra7_mmc2_fclk_div_parents, &dra7_mmc2_fclk_div_data }, 284 { 0 }, 285 }; 286 287 static const char * const dra7_usb_otg_ss2_refclk960m_parents[] __initconst = { 288 "l3init_960m_gfclk", 289 NULL, 290 }; 291 292 static const struct omap_clkctrl_bit_data dra7_usb_otg_ss2_bit_data[] __initconst = { 293 { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL }, 294 { 0 }, 295 }; 296 297 static const char * const dra7_sata_ref_clk_parents[] __initconst = { 298 "sys_clkin1", 299 NULL, 300 }; 301 302 static const struct omap_clkctrl_bit_data dra7_sata_bit_data[] __initconst = { 303 { 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL }, 304 { 0 }, 305 }; 306 307 static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = { 308 "apll_pcie_ck", 309 NULL, 310 }; 311 312 static const char * const dra7_optfclk_pciephy1_div_clk_parents[] __initconst = { 313 "optfclk_pciephy_div", 314 NULL, 315 }; 316 317 static const struct omap_clkctrl_bit_data dra7_pcie1_bit_data[] __initconst = { 318 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 319 { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL }, 320 { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL }, 321 { 0 }, 322 }; 323 324 static const struct omap_clkctrl_bit_data dra7_pcie2_bit_data[] __initconst = { 325 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 326 { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL }, 327 { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL }, 328 { 0 }, 329 }; 330 331 static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = { 332 "dpll_gmac_h11x2_ck", 333 "rmii_clk_ck", 334 NULL, 335 }; 336 337 static const char * const dra7_gmac_rft_clk_mux_parents[] __initconst = { 338 "video1_clkin_ck", 339 "video2_clkin_ck", 340 "dpll_abe_m2_ck", 341 "hdmi_clkin_ck", 342 "l3_iclk_div", 343 NULL, 344 }; 345 346 static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = { 347 { 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL }, 348 { 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL }, 349 { 0 }, 350 }; 351 352 static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = { 353 { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL }, 354 { 0 }, 355 }; 356 357 static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = { 358 { DRA7_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" }, 359 { DRA7_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" }, 360 { DRA7_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, 361 { DRA7_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, 362 { DRA7_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_DRA74 | CLKF_SOC_DRA76, "dpll_core_h13x2_ck" }, 363 { DRA7_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" }, 364 { DRA7_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" }, 365 { DRA7_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" }, 366 { DRA7_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "dpll_gmac_ck", "gmac_clkdm" }, 367 { DRA7_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" }, 368 { DRA7_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" }, 369 { DRA7_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, 370 { 0 }, 371 }; 372 373 static const char * const dra7_timer10_gfclk_mux_parents[] __initconst = { 374 "timer_sys_clk_div", 375 "sys_32k_ck", 376 "sys_clkin2", 377 "ref_clkin0_ck", 378 "ref_clkin1_ck", 379 "ref_clkin2_ck", 380 "ref_clkin3_ck", 381 "abe_giclk_div", 382 "video1_div_clk", 383 "video2_div_clk", 384 "hdmi_div_clk", 385 NULL, 386 }; 387 388 static const struct omap_clkctrl_bit_data dra7_timer10_bit_data[] __initconst = { 389 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 390 { 0 }, 391 }; 392 393 static const struct omap_clkctrl_bit_data dra7_timer11_bit_data[] __initconst = { 394 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 395 { 0 }, 396 }; 397 398 static const struct omap_clkctrl_bit_data dra7_timer2_bit_data[] __initconst = { 399 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 400 { 0 }, 401 }; 402 403 static const struct omap_clkctrl_bit_data dra7_timer3_bit_data[] __initconst = { 404 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 405 { 0 }, 406 }; 407 408 static const struct omap_clkctrl_bit_data dra7_timer4_bit_data[] __initconst = { 409 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 410 { 0 }, 411 }; 412 413 static const struct omap_clkctrl_bit_data dra7_timer9_bit_data[] __initconst = { 414 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 415 { 0 }, 416 }; 417 418 static const struct omap_clkctrl_bit_data dra7_gpio2_bit_data[] __initconst = { 419 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 420 { 0 }, 421 }; 422 423 static const struct omap_clkctrl_bit_data dra7_gpio3_bit_data[] __initconst = { 424 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 425 { 0 }, 426 }; 427 428 static const struct omap_clkctrl_bit_data dra7_gpio4_bit_data[] __initconst = { 429 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 430 { 0 }, 431 }; 432 433 static const struct omap_clkctrl_bit_data dra7_gpio5_bit_data[] __initconst = { 434 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 435 { 0 }, 436 }; 437 438 static const struct omap_clkctrl_bit_data dra7_gpio6_bit_data[] __initconst = { 439 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 440 { 0 }, 441 }; 442 443 static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = { 444 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 445 { 0 }, 446 }; 447 448 static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = { 449 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 450 { 0 }, 451 }; 452 453 static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = { 454 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 455 { 0 }, 456 }; 457 458 static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = { 459 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 460 { 0 }, 461 }; 462 463 static const struct omap_clkctrl_bit_data dra7_gpio8_bit_data[] __initconst = { 464 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 465 { 0 }, 466 }; 467 468 static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = { 469 "l4per_cm:clk:0120:24", 470 NULL, 471 }; 472 473 static const struct omap_clkctrl_div_data dra7_mmc3_gfclk_div_data __initconst = { 474 .max_div = 4, 475 .flags = CLK_DIVIDER_POWER_OF_TWO, 476 }; 477 478 static const struct omap_clkctrl_bit_data dra7_mmc3_bit_data[] __initconst = { 479 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 480 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 481 { 25, TI_CLK_DIVIDER, dra7_mmc3_gfclk_div_parents, &dra7_mmc3_gfclk_div_data }, 482 { 0 }, 483 }; 484 485 static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = { 486 "l4per_cm:clk:0128:24", 487 NULL, 488 }; 489 490 static const struct omap_clkctrl_div_data dra7_mmc4_gfclk_div_data __initconst = { 491 .max_div = 4, 492 .flags = CLK_DIVIDER_POWER_OF_TWO, 493 }; 494 495 static const struct omap_clkctrl_bit_data dra7_mmc4_bit_data[] __initconst = { 496 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 497 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 498 { 25, TI_CLK_DIVIDER, dra7_mmc4_gfclk_div_parents, &dra7_mmc4_gfclk_div_data }, 499 { 0 }, 500 }; 501 502 static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = { 503 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 504 { 0 }, 505 }; 506 507 static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = { 508 "func_128m_clk", 509 "dpll_per_h13x2_ck", 510 NULL, 511 }; 512 513 static const char * const dra7_qspi_gfclk_div_parents[] __initconst = { 514 "l4per_cm:clk:0138:24", 515 NULL, 516 }; 517 518 static const struct omap_clkctrl_div_data dra7_qspi_gfclk_div_data __initconst = { 519 .max_div = 4, 520 .flags = CLK_DIVIDER_POWER_OF_TWO, 521 }; 522 523 static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = { 524 { 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL }, 525 { 25, TI_CLK_DIVIDER, dra7_qspi_gfclk_div_parents, &dra7_qspi_gfclk_div_data }, 526 { 0 }, 527 }; 528 529 static const struct omap_clkctrl_bit_data dra7_uart1_bit_data[] __initconst = { 530 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 531 { 0 }, 532 }; 533 534 static const struct omap_clkctrl_bit_data dra7_uart2_bit_data[] __initconst = { 535 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 536 { 0 }, 537 }; 538 539 static const struct omap_clkctrl_bit_data dra7_uart3_bit_data[] __initconst = { 540 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 541 { 0 }, 542 }; 543 544 static const struct omap_clkctrl_bit_data dra7_uart4_bit_data[] __initconst = { 545 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 546 { 0 }, 547 }; 548 549 static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = { 550 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 551 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 552 { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 553 { 0 }, 554 }; 555 556 static const struct omap_clkctrl_bit_data dra7_mcasp3_bit_data[] __initconst = { 557 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 558 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 559 { 0 }, 560 }; 561 562 static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = { 563 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 564 { 0 }, 565 }; 566 567 static const struct omap_clkctrl_bit_data dra7_mcasp5_bit_data[] __initconst = { 568 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 569 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 570 { 0 }, 571 }; 572 573 static const struct omap_clkctrl_bit_data dra7_mcasp8_bit_data[] __initconst = { 574 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 575 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 576 { 0 }, 577 }; 578 579 static const struct omap_clkctrl_bit_data dra7_mcasp4_bit_data[] __initconst = { 580 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 581 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 582 { 0 }, 583 }; 584 585 static const struct omap_clkctrl_bit_data dra7_uart7_bit_data[] __initconst = { 586 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 587 { 0 }, 588 }; 589 590 static const struct omap_clkctrl_bit_data dra7_uart8_bit_data[] __initconst = { 591 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 592 { 0 }, 593 }; 594 595 static const struct omap_clkctrl_bit_data dra7_uart9_bit_data[] __initconst = { 596 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 597 { 0 }, 598 }; 599 600 static const struct omap_clkctrl_bit_data dra7_mcasp6_bit_data[] __initconst = { 601 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 602 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 603 { 0 }, 604 }; 605 606 static const struct omap_clkctrl_bit_data dra7_mcasp7_bit_data[] __initconst = { 607 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 608 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 609 { 0 }, 610 }; 611 612 static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = { 613 { DRA7_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per2_clkdm" }, 614 { DRA7_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per3_clkdm" }, 615 { DRA7_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" }, 616 { DRA7_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" }, 617 { DRA7_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0038:24" }, 618 { DRA7_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0040:24" }, 619 { DRA7_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0048:24" }, 620 { DRA7_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0050:24" }, 621 { DRA7_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" }, 622 { DRA7_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 623 { DRA7_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 624 { DRA7_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 625 { DRA7_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 626 { DRA7_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 627 { DRA7_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" }, 628 { DRA7_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" }, 629 { DRA7_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" }, 630 { DRA7_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 631 { DRA7_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 632 { DRA7_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 633 { DRA7_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 634 { DRA7_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" }, 635 { DRA7_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" }, 636 { DRA7_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00c8:24", "l4per3_clkdm" }, 637 { DRA7_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d0:24", "l4per3_clkdm" }, 638 { DRA7_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d8:24", "l4per3_clkdm" }, 639 { DRA7_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 640 { DRA7_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 641 { DRA7_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 642 { DRA7_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 643 { DRA7_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 644 { DRA7_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 645 { DRA7_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0120:25" }, 646 { DRA7_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0128:25" }, 647 { DRA7_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0130:24", "l4per3_clkdm" }, 648 { DRA7_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0138:25", "l4per2_clkdm" }, 649 { DRA7_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0140:24" }, 650 { DRA7_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0148:24" }, 651 { DRA7_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0150:24" }, 652 { DRA7_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0158:24" }, 653 { DRA7_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0160:22", "l4per2_clkdm" }, 654 { DRA7_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0168:22", "l4per2_clkdm" }, 655 { DRA7_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0170:24" }, 656 { DRA7_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0178:22", "l4per2_clkdm" }, 657 { DRA7_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0190:24", "l4per2_clkdm" }, 658 { DRA7_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0198:22", "l4per2_clkdm" }, 659 { DRA7_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" }, 660 { DRA7_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" }, 661 { DRA7_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" }, 662 { DRA7_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l3_iclk_div", "l4sec_clkdm" }, 663 { DRA7_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" }, 664 { DRA7_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01d0:24", "l4per2_clkdm" }, 665 { DRA7_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e0:24", "l4per2_clkdm" }, 666 { DRA7_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e8:24", "l4per2_clkdm" }, 667 { DRA7_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1", "l4per2_clkdm" }, 668 { DRA7_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0204:22", "l4per2_clkdm" }, 669 { DRA7_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0208:22", "l4per2_clkdm" }, 670 { 0 }, 671 }; 672 673 static const struct omap_clkctrl_bit_data dra7_gpio1_bit_data[] __initconst = { 674 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 675 { 0 }, 676 }; 677 678 static const struct omap_clkctrl_bit_data dra7_timer1_bit_data[] __initconst = { 679 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 680 { 0 }, 681 }; 682 683 static const struct omap_clkctrl_bit_data dra7_uart10_bit_data[] __initconst = { 684 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 685 { 0 }, 686 }; 687 688 static const char * const dra7_dcan1_sys_clk_mux_parents[] __initconst = { 689 "sys_clkin1", 690 "sys_clkin2", 691 NULL, 692 }; 693 694 static const struct omap_clkctrl_bit_data dra7_dcan1_bit_data[] __initconst = { 695 { 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL }, 696 { 0 }, 697 }; 698 699 static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = { 700 { DRA7_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, 701 { DRA7_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, 702 { DRA7_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" }, 703 { DRA7_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" }, 704 { DRA7_TIMER12_CLKCTRL, NULL, CLKF_SOC_NONSEC, "secure_32k_clk_src_ck" }, 705 { DRA7_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, 706 { DRA7_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0060:24" }, 707 { DRA7_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0068:24" }, 708 { DRA7_ADC_CLKCTRL, NULL, CLKF_SW_SUP, "mcan_clk"}, 709 { 0 }, 710 }; 711 712 const struct omap_clkctrl_data dra7_clkctrl_compat_data[] __initconst = { 713 { 0x4a005320, dra7_mpu_clkctrl_regs }, 714 { 0x4a005540, dra7_ipu_clkctrl_regs }, 715 { 0x4a005740, dra7_rtc_clkctrl_regs }, 716 { 0x4a008620, dra7_coreaon_clkctrl_regs }, 717 { 0x4a008720, dra7_l3main1_clkctrl_regs }, 718 { 0x4a008a20, dra7_dma_clkctrl_regs }, 719 { 0x4a008b20, dra7_emif_clkctrl_regs }, 720 { 0x4a008c00, dra7_atl_clkctrl_regs }, 721 { 0x4a008d20, dra7_l4cfg_clkctrl_regs }, 722 { 0x4a008e20, dra7_l3instr_clkctrl_regs }, 723 { 0x4a009120, dra7_dss_clkctrl_regs }, 724 { 0x4a009320, dra7_l3init_clkctrl_regs }, 725 { 0x4a009700, dra7_l4per_clkctrl_regs }, 726 { 0x4ae07820, dra7_wkupaon_clkctrl_regs }, 727 { 0 }, 728 }; 729 730 struct ti_dt_clk dra7xx_compat_clks[] = { 731 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), 732 DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"), 733 DT_CLK(NULL, "sys_clkin", "sys_clkin1"), 734 DT_CLK(NULL, "atl_dpll_clk_mux", "atl_cm:0000:24"), 735 DT_CLK(NULL, "atl_gfclk_mux", "atl_cm:0000:26"), 736 DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon_cm:0068:24"), 737 DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"), 738 DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"), 739 DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"), 740 DT_CLK(NULL, "dss_hdmi_clk", "dss_cm:0000:10"), 741 DT_CLK(NULL, "dss_video1_clk", "dss_cm:0000:12"), 742 DT_CLK(NULL, "dss_video2_clk", "dss_cm:0000:13"), 743 DT_CLK(NULL, "gmac_rft_clk_mux", "l3init_cm:00b0:25"), 744 DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"), 745 DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0060:8"), 746 DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0068:8"), 747 DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0070:8"), 748 DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0078:8"), 749 DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0080:8"), 750 DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:0110:8"), 751 DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:0118:8"), 752 DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu_cm:0010:28"), 753 DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu_cm:0010:24"), 754 DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu_cm:0010:22"), 755 DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per_cm:0160:28"), 756 DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per_cm:0160:24"), 757 DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per_cm:0160:22"), 758 DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per_cm:0168:24"), 759 DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per_cm:0168:22"), 760 DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per_cm:0198:24"), 761 DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per_cm:0198:22"), 762 DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per_cm:0178:24"), 763 DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per_cm:0178:22"), 764 DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per_cm:0204:24"), 765 DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per_cm:0204:22"), 766 DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per_cm:0208:24"), 767 DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per_cm:0208:22"), 768 DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per_cm:0190:22"), 769 DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per_cm:0190:24"), 770 DT_CLK(NULL, "mmc1_clk32k", "l3init_cm:0008:8"), 771 DT_CLK(NULL, "mmc1_fclk_div", "l3init_cm:0008:25"), 772 DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"), 773 DT_CLK(NULL, "mmc2_clk32k", "l3init_cm:0010:8"), 774 DT_CLK(NULL, "mmc2_fclk_div", "l3init_cm:0010:25"), 775 DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"), 776 DT_CLK(NULL, "mmc3_clk32k", "l4per_cm:0120:8"), 777 DT_CLK(NULL, "mmc3_gfclk_div", "l4per_cm:0120:25"), 778 DT_CLK(NULL, "mmc3_gfclk_mux", "l4per_cm:0120:24"), 779 DT_CLK(NULL, "mmc4_clk32k", "l4per_cm:0128:8"), 780 DT_CLK(NULL, "mmc4_gfclk_div", "l4per_cm:0128:25"), 781 DT_CLK(NULL, "mmc4_gfclk_mux", "l4per_cm:0128:24"), 782 DT_CLK(NULL, "optfclk_pciephy1_32khz", "l3init_cm:0090:8"), 783 DT_CLK(NULL, "optfclk_pciephy1_clk", "l3init_cm:0090:9"), 784 DT_CLK(NULL, "optfclk_pciephy1_div_clk", "l3init_cm:0090:10"), 785 DT_CLK(NULL, "optfclk_pciephy2_32khz", "l3init_cm:0098:8"), 786 DT_CLK(NULL, "optfclk_pciephy2_clk", "l3init_cm:0098:9"), 787 DT_CLK(NULL, "optfclk_pciephy2_div_clk", "l3init_cm:0098:10"), 788 DT_CLK(NULL, "qspi_gfclk_div", "l4per_cm:0138:25"), 789 DT_CLK(NULL, "qspi_gfclk_mux", "l4per_cm:0138:24"), 790 DT_CLK(NULL, "rmii_50mhz_clk_mux", "l3init_cm:00b0:24"), 791 DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"), 792 DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0028:24"), 793 DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0030:24"), 794 DT_CLK(NULL, "timer13_gfclk_mux", "l4per_cm:00c8:24"), 795 DT_CLK(NULL, "timer14_gfclk_mux", "l4per_cm:00d0:24"), 796 DT_CLK(NULL, "timer15_gfclk_mux", "l4per_cm:00d8:24"), 797 DT_CLK(NULL, "timer16_gfclk_mux", "l4per_cm:0130:24"), 798 DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"), 799 DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0038:24"), 800 DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0040:24"), 801 DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0048:24"), 802 DT_CLK(NULL, "timer5_gfclk_mux", "ipu_cm:0018:24"), 803 DT_CLK(NULL, "timer6_gfclk_mux", "ipu_cm:0020:24"), 804 DT_CLK(NULL, "timer7_gfclk_mux", "ipu_cm:0028:24"), 805 DT_CLK(NULL, "timer8_gfclk_mux", "ipu_cm:0030:24"), 806 DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0050:24"), 807 DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon_cm:0060:24"), 808 DT_CLK(NULL, "uart1_gfclk_mux", "l4per_cm:0140:24"), 809 DT_CLK(NULL, "uart2_gfclk_mux", "l4per_cm:0148:24"), 810 DT_CLK(NULL, "uart3_gfclk_mux", "l4per_cm:0150:24"), 811 DT_CLK(NULL, "uart4_gfclk_mux", "l4per_cm:0158:24"), 812 DT_CLK(NULL, "uart5_gfclk_mux", "l4per_cm:0170:24"), 813 DT_CLK(NULL, "uart6_gfclk_mux", "ipu_cm:0040:24"), 814 DT_CLK(NULL, "uart7_gfclk_mux", "l4per_cm:01d0:24"), 815 DT_CLK(NULL, "uart8_gfclk_mux", "l4per_cm:01e0:24"), 816 DT_CLK(NULL, "uart9_gfclk_mux", "l4per_cm:01e8:24"), 817 DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init_cm:00d0:8"), 818 DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init_cm:0020:8"), 819 { .node_name = NULL }, 820 }; 821
