1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved
4 */
5
6 #include "dpu_hw_mdss.h"
7 #include "dpu_hwio.h"
8 #include "dpu_hw_catalog.h"
9 #include "dpu_hw_wb.h"
10 #include "dpu_formats.h"
11 #include "dpu_kms.h"
12
13 #define WB_DST_FORMAT 0x000
14 #define WB_DST_OP_MODE 0x004
15 #define WB_DST_PACK_PATTERN 0x008
16 #define WB_DST0_ADDR 0x00C
17 #define WB_DST1_ADDR 0x010
18 #define WB_DST2_ADDR 0x014
19 #define WB_DST3_ADDR 0x018
20 #define WB_DST_YSTRIDE0 0x01C
21 #define WB_DST_YSTRIDE1 0x020
22 #define WB_DST_YSTRIDE1 0x020
23 #define WB_DST_DITHER_BITDEPTH 0x024
24 #define WB_DST_MATRIX_ROW0 0x030
25 #define WB_DST_MATRIX_ROW1 0x034
26 #define WB_DST_MATRIX_ROW2 0x038
27 #define WB_DST_MATRIX_ROW3 0x03C
28 #define WB_DST_WRITE_CONFIG 0x048
29 #define WB_ROTATION_DNSCALER 0x050
30 #define WB_ROTATOR_PIPE_DOWNSCALER 0x054
31 #define WB_N16_INIT_PHASE_X_C03 0x060
32 #define WB_N16_INIT_PHASE_X_C12 0x064
33 #define WB_N16_INIT_PHASE_Y_C03 0x068
34 #define WB_N16_INIT_PHASE_Y_C12 0x06C
35 #define WB_OUT_SIZE 0x074
36 #define WB_ALPHA_X_VALUE 0x078
37 #define WB_DANGER_LUT 0x084
38 #define WB_SAFE_LUT 0x088
39 #define WB_QOS_CTRL 0x090
40 #define WB_CREQ_LUT_0 0x098
41 #define WB_CREQ_LUT_1 0x09C
42 #define WB_UBWC_STATIC_CTRL 0x144
43 #define WB_MUX 0x150
44 #define WB_CROP_CTRL 0x154
45 #define WB_CROP_OFFSET 0x158
46 #define WB_CSC_BASE 0x260
47 #define WB_DST_ADDR_SW_STATUS 0x2B0
48 #define WB_CDP_CNTL 0x2B4
49 #define WB_OUT_IMAGE_SIZE 0x2C0
50 #define WB_OUT_XY 0x2C4
51
dpu_hw_wb_setup_outaddress(struct dpu_hw_wb * ctx,struct dpu_hw_wb_cfg * data)52 static void dpu_hw_wb_setup_outaddress(struct dpu_hw_wb *ctx,
53 struct dpu_hw_wb_cfg *data)
54 {
55 struct dpu_hw_blk_reg_map *c = &ctx->hw;
56
57 DPU_REG_WRITE(c, WB_DST0_ADDR, data->dest.plane_addr[0]);
58 DPU_REG_WRITE(c, WB_DST1_ADDR, data->dest.plane_addr[1]);
59 DPU_REG_WRITE(c, WB_DST2_ADDR, data->dest.plane_addr[2]);
60 DPU_REG_WRITE(c, WB_DST3_ADDR, data->dest.plane_addr[3]);
61 }
62
dpu_hw_wb_setup_format(struct dpu_hw_wb * ctx,struct dpu_hw_wb_cfg * data)63 static void dpu_hw_wb_setup_format(struct dpu_hw_wb *ctx,
64 struct dpu_hw_wb_cfg *data)
65 {
66 struct dpu_hw_blk_reg_map *c = &ctx->hw;
67 const struct dpu_format *fmt = data->dest.format;
68 u32 dst_format, pattern, ystride0, ystride1, outsize, chroma_samp;
69 u32 write_config = 0;
70 u32 opmode = 0;
71 u32 dst_addr_sw = 0;
72
73 chroma_samp = fmt->chroma_sample;
74
75 dst_format = (chroma_samp << 23) |
76 (fmt->fetch_planes << 19) |
77 (fmt->bits[C3_ALPHA] << 6) |
78 (fmt->bits[C2_R_Cr] << 4) |
79 (fmt->bits[C1_B_Cb] << 2) |
80 (fmt->bits[C0_G_Y] << 0);
81
82 if (fmt->bits[C3_ALPHA] || fmt->alpha_enable) {
83 dst_format |= BIT(8); /* DSTC3_EN */
84 if (!fmt->alpha_enable ||
85 !(ctx->caps->features & BIT(DPU_WB_PIPE_ALPHA)))
86 dst_format |= BIT(14); /* DST_ALPHA_X */
87 }
88
89 pattern = (fmt->element[3] << 24) |
90 (fmt->element[2] << 16) |
91 (fmt->element[1] << 8) |
92 (fmt->element[0] << 0);
93
94 dst_format |= (fmt->unpack_align_msb << 18) |
95 (fmt->unpack_tight << 17) |
96 ((fmt->unpack_count - 1) << 12) |
97 ((fmt->bpp - 1) << 9);
98
99 ystride0 = data->dest.plane_pitch[0] |
100 (data->dest.plane_pitch[1] << 16);
101 ystride1 = data->dest.plane_pitch[2] |
102 (data->dest.plane_pitch[3] << 16);
103
104 if (drm_rect_height(&data->roi) && drm_rect_width(&data->roi))
105 outsize = (drm_rect_height(&data->roi) << 16) | drm_rect_width(&data->roi);
106 else
107 outsize = (data->dest.height << 16) | data->dest.width;
108
109 DPU_REG_WRITE(c, WB_ALPHA_X_VALUE, 0xFF);
110 DPU_REG_WRITE(c, WB_DST_FORMAT, dst_format);
111 DPU_REG_WRITE(c, WB_DST_OP_MODE, opmode);
112 DPU_REG_WRITE(c, WB_DST_PACK_PATTERN, pattern);
113 DPU_REG_WRITE(c, WB_DST_YSTRIDE0, ystride0);
114 DPU_REG_WRITE(c, WB_DST_YSTRIDE1, ystride1);
115 DPU_REG_WRITE(c, WB_OUT_SIZE, outsize);
116 DPU_REG_WRITE(c, WB_DST_WRITE_CONFIG, write_config);
117 DPU_REG_WRITE(c, WB_DST_ADDR_SW_STATUS, dst_addr_sw);
118 }
119
dpu_hw_wb_roi(struct dpu_hw_wb * ctx,struct dpu_hw_wb_cfg * wb)120 static void dpu_hw_wb_roi(struct dpu_hw_wb *ctx, struct dpu_hw_wb_cfg *wb)
121 {
122 struct dpu_hw_blk_reg_map *c = &ctx->hw;
123 u32 image_size, out_size, out_xy;
124
125 image_size = (wb->dest.height << 16) | wb->dest.width;
126 out_xy = 0;
127 out_size = (drm_rect_height(&wb->roi) << 16) | drm_rect_width(&wb->roi);
128
129 DPU_REG_WRITE(c, WB_OUT_IMAGE_SIZE, image_size);
130 DPU_REG_WRITE(c, WB_OUT_XY, out_xy);
131 DPU_REG_WRITE(c, WB_OUT_SIZE, out_size);
132 }
133
dpu_hw_wb_setup_qos_lut(struct dpu_hw_wb * ctx,struct dpu_hw_qos_cfg * cfg)134 static void dpu_hw_wb_setup_qos_lut(struct dpu_hw_wb *ctx,
135 struct dpu_hw_qos_cfg *cfg)
136 {
137 if (!ctx || !cfg)
138 return;
139
140 _dpu_hw_setup_qos_lut(&ctx->hw, WB_DANGER_LUT,
141 test_bit(DPU_WB_QOS_8LVL, &ctx->caps->features),
142 cfg);
143 }
144
dpu_hw_wb_setup_cdp(struct dpu_hw_wb * ctx,const struct dpu_format * fmt,bool enable)145 static void dpu_hw_wb_setup_cdp(struct dpu_hw_wb *ctx,
146 const struct dpu_format *fmt,
147 bool enable)
148 {
149 if (!ctx)
150 return;
151
152 dpu_setup_cdp(&ctx->hw, WB_CDP_CNTL, fmt, enable);
153 }
154
dpu_hw_wb_bind_pingpong_blk(struct dpu_hw_wb * ctx,const enum dpu_pingpong pp)155 static void dpu_hw_wb_bind_pingpong_blk(
156 struct dpu_hw_wb *ctx,
157 const enum dpu_pingpong pp)
158 {
159 struct dpu_hw_blk_reg_map *c;
160 int mux_cfg;
161
162 if (!ctx)
163 return;
164
165 c = &ctx->hw;
166
167 mux_cfg = DPU_REG_READ(c, WB_MUX);
168 mux_cfg &= ~0xf;
169
170 if (pp)
171 mux_cfg |= (pp - PINGPONG_0) & 0x7;
172 else
173 mux_cfg |= 0xf;
174
175 DPU_REG_WRITE(c, WB_MUX, mux_cfg);
176 }
177
_setup_wb_ops(struct dpu_hw_wb_ops * ops,unsigned long features)178 static void _setup_wb_ops(struct dpu_hw_wb_ops *ops,
179 unsigned long features)
180 {
181 ops->setup_outaddress = dpu_hw_wb_setup_outaddress;
182 ops->setup_outformat = dpu_hw_wb_setup_format;
183
184 if (test_bit(DPU_WB_XY_ROI_OFFSET, &features))
185 ops->setup_roi = dpu_hw_wb_roi;
186
187 if (test_bit(DPU_WB_QOS, &features))
188 ops->setup_qos_lut = dpu_hw_wb_setup_qos_lut;
189
190 if (test_bit(DPU_WB_CDP, &features))
191 ops->setup_cdp = dpu_hw_wb_setup_cdp;
192
193 if (test_bit(DPU_WB_INPUT_CTRL, &features))
194 ops->bind_pingpong_blk = dpu_hw_wb_bind_pingpong_blk;
195 }
196
dpu_hw_wb_init(const struct dpu_wb_cfg * cfg,void __iomem * addr)197 struct dpu_hw_wb *dpu_hw_wb_init(const struct dpu_wb_cfg *cfg,
198 void __iomem *addr)
199 {
200 struct dpu_hw_wb *c;
201
202 if (!addr)
203 return ERR_PTR(-EINVAL);
204
205 c = kzalloc(sizeof(*c), GFP_KERNEL);
206 if (!c)
207 return ERR_PTR(-ENOMEM);
208
209 c->hw.blk_addr = addr + cfg->base;
210 c->hw.log_mask = DPU_DBG_MASK_WB;
211
212 /* Assign ops */
213 c->idx = cfg->id;
214 c->caps = cfg;
215 _setup_wb_ops(&c->ops, c->caps->features);
216
217 return c;
218 }
219
dpu_hw_wb_destroy(struct dpu_hw_wb * hw_wb)220 void dpu_hw_wb_destroy(struct dpu_hw_wb *hw_wb)
221 {
222 kfree(hw_wb);
223 }
224
