1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
3 */
4
5 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
6 #include "dpu_encoder_phys.h"
7 #include "dpu_hw_interrupts.h"
8 #include "dpu_core_irq.h"
9 #include "dpu_formats.h"
10 #include "dpu_trace.h"
11
12 #define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \
13 (e) && (e)->parent ? \
14 (e)->parent->base.id : -1, \
15 (e) && (e)->hw_intf ? \
16 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
17
18 #define DPU_ERROR_VIDENC(e, fmt, ...) DPU_ERROR("enc%d intf%d " fmt, \
19 (e) && (e)->parent ? \
20 (e)->parent->base.id : -1, \
21 (e) && (e)->hw_intf ? \
22 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
23
24 #define to_dpu_encoder_phys_vid(x) \
25 container_of(x, struct dpu_encoder_phys_vid, base)
26
dpu_encoder_phys_vid_is_master(struct dpu_encoder_phys * phys_enc)27 static bool dpu_encoder_phys_vid_is_master(
28 struct dpu_encoder_phys *phys_enc)
29 {
30 bool ret = false;
31
32 if (phys_enc->split_role != ENC_ROLE_SLAVE)
33 ret = true;
34
35 return ret;
36 }
37
drm_mode_to_intf_timing_params(const struct dpu_encoder_phys * phys_enc,const struct drm_display_mode * mode,struct intf_timing_params * timing)38 static void drm_mode_to_intf_timing_params(
39 const struct dpu_encoder_phys *phys_enc,
40 const struct drm_display_mode *mode,
41 struct intf_timing_params *timing)
42 {
43 memset(timing, 0, sizeof(*timing));
44
45 if ((mode->htotal < mode->hsync_end)
46 || (mode->hsync_start < mode->hdisplay)
47 || (mode->vtotal < mode->vsync_end)
48 || (mode->vsync_start < mode->vdisplay)
49 || (mode->hsync_end < mode->hsync_start)
50 || (mode->vsync_end < mode->vsync_start)) {
51 DPU_ERROR(
52 "invalid params - hstart:%d,hend:%d,htot:%d,hdisplay:%d\n",
53 mode->hsync_start, mode->hsync_end,
54 mode->htotal, mode->hdisplay);
55 DPU_ERROR("vstart:%d,vend:%d,vtot:%d,vdisplay:%d\n",
56 mode->vsync_start, mode->vsync_end,
57 mode->vtotal, mode->vdisplay);
58 return;
59 }
60
61 /*
62 * https://www.kernel.org/doc/htmldocs/drm/ch02s05.html
63 * Active Region Front Porch Sync Back Porch
64 * <-----------------><------------><-----><----------->
65 * <- [hv]display --->
66 * <--------- [hv]sync_start ------>
67 * <----------------- [hv]sync_end ------->
68 * <---------------------------- [hv]total ------------->
69 */
70 timing->width = mode->hdisplay; /* active width */
71 timing->height = mode->vdisplay; /* active height */
72 timing->xres = timing->width;
73 timing->yres = timing->height;
74 timing->h_back_porch = mode->htotal - mode->hsync_end;
75 timing->h_front_porch = mode->hsync_start - mode->hdisplay;
76 timing->v_back_porch = mode->vtotal - mode->vsync_end;
77 timing->v_front_porch = mode->vsync_start - mode->vdisplay;
78 timing->hsync_pulse_width = mode->hsync_end - mode->hsync_start;
79 timing->vsync_pulse_width = mode->vsync_end - mode->vsync_start;
80 timing->hsync_polarity = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0;
81 timing->vsync_polarity = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
82 timing->border_clr = 0;
83 timing->underflow_clr = 0xff;
84 timing->hsync_skew = mode->hskew;
85
86 /* DSI controller cannot handle active-low sync signals. */
87 if (phys_enc->hw_intf->cap->type == INTF_DSI) {
88 timing->hsync_polarity = 0;
89 timing->vsync_polarity = 0;
90 }
91
92 /*
93 * For edp only:
94 * DISPLAY_V_START = (VBP * HCYCLE) + HBP
95 * DISPLAY_V_END = (VBP + VACTIVE) * HCYCLE - 1 - HFP
96 */
97 /*
98 * if (vid_enc->hw->cap->type == INTF_EDP) {
99 * display_v_start += mode->htotal - mode->hsync_start;
100 * display_v_end -= mode->hsync_start - mode->hdisplay;
101 * }
102 */
103 }
104
get_horizontal_total(const struct intf_timing_params * timing)105 static u32 get_horizontal_total(const struct intf_timing_params *timing)
106 {
107 u32 active = timing->xres;
108 u32 inactive =
109 timing->h_back_porch + timing->h_front_porch +
110 timing->hsync_pulse_width;
111 return active + inactive;
112 }
113
get_vertical_total(const struct intf_timing_params * timing)114 static u32 get_vertical_total(const struct intf_timing_params *timing)
115 {
116 u32 active = timing->yres;
117 u32 inactive =
118 timing->v_back_porch + timing->v_front_porch +
119 timing->vsync_pulse_width;
120 return active + inactive;
121 }
122
123 /*
124 * programmable_fetch_get_num_lines:
125 * Number of fetch lines in vertical front porch
126 * @timing: Pointer to the intf timing information for the requested mode
127 *
128 * Returns the number of fetch lines in vertical front porch at which mdp
129 * can start fetching the next frame.
130 *
131 * Number of needed prefetch lines is anything that cannot be absorbed in the
132 * start of frame time (back porch + vsync pulse width).
133 *
134 * Some panels have very large VFP, however we only need a total number of
135 * lines based on the chip worst case latencies.
136 */
programmable_fetch_get_num_lines(struct dpu_encoder_phys * phys_enc,const struct intf_timing_params * timing)137 static u32 programmable_fetch_get_num_lines(
138 struct dpu_encoder_phys *phys_enc,
139 const struct intf_timing_params *timing)
140 {
141 u32 worst_case_needed_lines =
142 phys_enc->hw_intf->cap->prog_fetch_lines_worst_case;
143 u32 start_of_frame_lines =
144 timing->v_back_porch + timing->vsync_pulse_width;
145 u32 needed_vfp_lines = worst_case_needed_lines - start_of_frame_lines;
146 u32 actual_vfp_lines = 0;
147
148 /* Fetch must be outside active lines, otherwise undefined. */
149 if (start_of_frame_lines >= worst_case_needed_lines) {
150 DPU_DEBUG_VIDENC(phys_enc,
151 "prog fetch is not needed, large vbp+vsw\n");
152 actual_vfp_lines = 0;
153 } else if (timing->v_front_porch < needed_vfp_lines) {
154 /* Warn fetch needed, but not enough porch in panel config */
155 pr_warn_once
156 ("low vbp+vfp may lead to perf issues in some cases\n");
157 DPU_DEBUG_VIDENC(phys_enc,
158 "less vfp than fetch req, using entire vfp\n");
159 actual_vfp_lines = timing->v_front_porch;
160 } else {
161 DPU_DEBUG_VIDENC(phys_enc, "room in vfp for needed prefetch\n");
162 actual_vfp_lines = needed_vfp_lines;
163 }
164
165 DPU_DEBUG_VIDENC(phys_enc,
166 "v_front_porch %u v_back_porch %u vsync_pulse_width %u\n",
167 timing->v_front_porch, timing->v_back_porch,
168 timing->vsync_pulse_width);
169 DPU_DEBUG_VIDENC(phys_enc,
170 "wc_lines %u needed_vfp_lines %u actual_vfp_lines %u\n",
171 worst_case_needed_lines, needed_vfp_lines, actual_vfp_lines);
172
173 return actual_vfp_lines;
174 }
175
176 /*
177 * programmable_fetch_config: Programs HW to prefetch lines by offsetting
178 * the start of fetch into the vertical front porch for cases where the
179 * vsync pulse width and vertical back porch time is insufficient
180 *
181 * Gets # of lines to pre-fetch, then calculate VSYNC counter value.
182 * HW layer requires VSYNC counter of first pixel of tgt VFP line.
183 *
184 * @timing: Pointer to the intf timing information for the requested mode
185 */
programmable_fetch_config(struct dpu_encoder_phys * phys_enc,const struct intf_timing_params * timing)186 static void programmable_fetch_config(struct dpu_encoder_phys *phys_enc,
187 const struct intf_timing_params *timing)
188 {
189 struct intf_prog_fetch f = { 0 };
190 u32 vfp_fetch_lines = 0;
191 u32 horiz_total = 0;
192 u32 vert_total = 0;
193 u32 vfp_fetch_start_vsync_counter = 0;
194 unsigned long lock_flags;
195
196 if (WARN_ON_ONCE(!phys_enc->hw_intf->ops.setup_prg_fetch))
197 return;
198
199 vfp_fetch_lines = programmable_fetch_get_num_lines(phys_enc, timing);
200 if (vfp_fetch_lines) {
201 vert_total = get_vertical_total(timing);
202 horiz_total = get_horizontal_total(timing);
203 vfp_fetch_start_vsync_counter =
204 (vert_total - vfp_fetch_lines) * horiz_total + 1;
205 f.enable = 1;
206 f.fetch_start = vfp_fetch_start_vsync_counter;
207 }
208
209 DPU_DEBUG_VIDENC(phys_enc,
210 "vfp_fetch_lines %u vfp_fetch_start_vsync_counter %u\n",
211 vfp_fetch_lines, vfp_fetch_start_vsync_counter);
212
213 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
214 phys_enc->hw_intf->ops.setup_prg_fetch(phys_enc->hw_intf, &f);
215 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
216 }
217
dpu_encoder_phys_vid_mode_fixup(struct dpu_encoder_phys * phys_enc,const struct drm_display_mode * mode,struct drm_display_mode * adj_mode)218 static bool dpu_encoder_phys_vid_mode_fixup(
219 struct dpu_encoder_phys *phys_enc,
220 const struct drm_display_mode *mode,
221 struct drm_display_mode *adj_mode)
222 {
223 if (phys_enc)
224 DPU_DEBUG_VIDENC(phys_enc, "\n");
225
226 /*
227 * Modifying mode has consequences when the mode comes back to us
228 */
229 return true;
230 }
231
dpu_encoder_phys_vid_setup_timing_engine(struct dpu_encoder_phys * phys_enc)232 static void dpu_encoder_phys_vid_setup_timing_engine(
233 struct dpu_encoder_phys *phys_enc)
234 {
235 struct drm_display_mode mode;
236 struct intf_timing_params timing_params = { 0 };
237 const struct dpu_format *fmt = NULL;
238 u32 fmt_fourcc = DRM_FORMAT_RGB888;
239 unsigned long lock_flags;
240 struct dpu_hw_intf_cfg intf_cfg = { 0 };
241
242 if (!phys_enc || !phys_enc->hw_ctl->ops.setup_intf_cfg) {
243 DPU_ERROR("invalid encoder %d\n", phys_enc != 0);
244 return;
245 }
246
247 mode = phys_enc->cached_mode;
248 if (!phys_enc->hw_intf->ops.setup_timing_gen) {
249 DPU_ERROR("timing engine setup is not supported\n");
250 return;
251 }
252
253 DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n");
254 drm_mode_debug_printmodeline(&mode);
255
256 if (phys_enc->split_role != ENC_ROLE_SOLO) {
257 mode.hdisplay >>= 1;
258 mode.htotal >>= 1;
259 mode.hsync_start >>= 1;
260 mode.hsync_end >>= 1;
261
262 DPU_DEBUG_VIDENC(phys_enc,
263 "split_role %d, halve horizontal %d %d %d %d\n",
264 phys_enc->split_role,
265 mode.hdisplay, mode.htotal,
266 mode.hsync_start, mode.hsync_end);
267 }
268
269 drm_mode_to_intf_timing_params(phys_enc, &mode, &timing_params);
270
271 fmt = dpu_get_dpu_format(fmt_fourcc);
272 DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc);
273
274 intf_cfg.intf = phys_enc->hw_intf->idx;
275 intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID;
276 intf_cfg.stream_sel = 0; /* Don't care value for video mode */
277 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
278
279 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
280 phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,
281 &timing_params, fmt);
282 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
283 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
284
285 programmable_fetch_config(phys_enc, &timing_params);
286 }
287
dpu_encoder_phys_vid_vblank_irq(void * arg,int irq_idx)288 static void dpu_encoder_phys_vid_vblank_irq(void *arg, int irq_idx)
289 {
290 struct dpu_encoder_phys *phys_enc = arg;
291 struct dpu_hw_ctl *hw_ctl;
292 unsigned long lock_flags;
293 u32 flush_register = 0;
294 int new_cnt = -1, old_cnt = -1;
295
296 if (!phys_enc)
297 return;
298
299 hw_ctl = phys_enc->hw_ctl;
300 if (!hw_ctl)
301 return;
302
303 DPU_ATRACE_BEGIN("vblank_irq");
304
305 if (phys_enc->parent_ops->handle_vblank_virt)
306 phys_enc->parent_ops->handle_vblank_virt(phys_enc->parent,
307 phys_enc);
308
309 old_cnt = atomic_read(&phys_enc->pending_kickoff_cnt);
310
311 /*
312 * only decrement the pending flush count if we've actually flushed
313 * hardware. due to sw irq latency, vblank may have already happened
314 * so we need to double-check with hw that it accepted the flush bits
315 */
316 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
317 if (hw_ctl && hw_ctl->ops.get_flush_register)
318 flush_register = hw_ctl->ops.get_flush_register(hw_ctl);
319
320 if (!(flush_register & hw_ctl->ops.get_pending_flush(hw_ctl)))
321 new_cnt = atomic_add_unless(&phys_enc->pending_kickoff_cnt,
322 -1, 0);
323 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
324
325 /* Signal any waiting atomic commit thread */
326 wake_up_all(&phys_enc->pending_kickoff_wq);
327
328 phys_enc->parent_ops->handle_frame_done(phys_enc->parent, phys_enc,
329 DPU_ENCODER_FRAME_EVENT_DONE);
330
331 DPU_ATRACE_END("vblank_irq");
332 }
333
dpu_encoder_phys_vid_underrun_irq(void * arg,int irq_idx)334 static void dpu_encoder_phys_vid_underrun_irq(void *arg, int irq_idx)
335 {
336 struct dpu_encoder_phys *phys_enc = arg;
337
338 if (!phys_enc)
339 return;
340
341 if (phys_enc->parent_ops->handle_underrun_virt)
342 phys_enc->parent_ops->handle_underrun_virt(phys_enc->parent,
343 phys_enc);
344 }
345
dpu_encoder_phys_vid_needs_single_flush(struct dpu_encoder_phys * phys_enc)346 static bool dpu_encoder_phys_vid_needs_single_flush(
347 struct dpu_encoder_phys *phys_enc)
348 {
349 return phys_enc->split_role != ENC_ROLE_SOLO;
350 }
351
_dpu_encoder_phys_vid_setup_irq_hw_idx(struct dpu_encoder_phys * phys_enc)352 static void _dpu_encoder_phys_vid_setup_irq_hw_idx(
353 struct dpu_encoder_phys *phys_enc)
354 {
355 struct dpu_encoder_irq *irq;
356
357 /*
358 * Initialize irq->hw_idx only when irq is not registered.
359 * Prevent invalidating irq->irq_idx as modeset may be
360 * called many times during dfps.
361 */
362
363 irq = &phys_enc->irq[INTR_IDX_VSYNC];
364 if (irq->irq_idx < 0)
365 irq->hw_idx = phys_enc->intf_idx;
366
367 irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
368 if (irq->irq_idx < 0)
369 irq->hw_idx = phys_enc->intf_idx;
370 }
371
dpu_encoder_phys_vid_mode_set(struct dpu_encoder_phys * phys_enc,struct drm_display_mode * mode,struct drm_display_mode * adj_mode)372 static void dpu_encoder_phys_vid_mode_set(
373 struct dpu_encoder_phys *phys_enc,
374 struct drm_display_mode *mode,
375 struct drm_display_mode *adj_mode)
376 {
377 if (!phys_enc || !phys_enc->dpu_kms) {
378 DPU_ERROR("invalid encoder/kms\n");
379 return;
380 }
381
382 if (adj_mode) {
383 phys_enc->cached_mode = *adj_mode;
384 drm_mode_debug_printmodeline(adj_mode);
385 DPU_DEBUG_VIDENC(phys_enc, "caching mode:\n");
386 }
387
388 _dpu_encoder_phys_vid_setup_irq_hw_idx(phys_enc);
389 }
390
dpu_encoder_phys_vid_control_vblank_irq(struct dpu_encoder_phys * phys_enc,bool enable)391 static int dpu_encoder_phys_vid_control_vblank_irq(
392 struct dpu_encoder_phys *phys_enc,
393 bool enable)
394 {
395 int ret = 0;
396 int refcount;
397
398 if (!phys_enc) {
399 DPU_ERROR("invalid encoder\n");
400 return -EINVAL;
401 }
402
403 refcount = atomic_read(&phys_enc->vblank_refcount);
404
405 /* Slave encoders don't report vblank */
406 if (!dpu_encoder_phys_vid_is_master(phys_enc))
407 goto end;
408
409 /* protect against negative */
410 if (!enable && refcount == 0) {
411 ret = -EINVAL;
412 goto end;
413 }
414
415 DRM_DEBUG_KMS("id:%u enable=%d/%d\n", DRMID(phys_enc->parent), enable,
416 atomic_read(&phys_enc->vblank_refcount));
417
418 if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1)
419 ret = dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_VSYNC);
420 else if (!enable && atomic_dec_return(&phys_enc->vblank_refcount) == 0)
421 ret = dpu_encoder_helper_unregister_irq(phys_enc,
422 INTR_IDX_VSYNC);
423
424 end:
425 if (ret) {
426 DRM_ERROR("failed: id:%u intf:%d ret:%d enable:%d refcnt:%d\n",
427 DRMID(phys_enc->parent),
428 phys_enc->hw_intf->idx - INTF_0, ret, enable,
429 refcount);
430 }
431 return ret;
432 }
433
dpu_encoder_phys_vid_enable(struct dpu_encoder_phys * phys_enc)434 static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
435 {
436 struct dpu_hw_ctl *ctl;
437 u32 flush_mask = 0;
438
439 ctl = phys_enc->hw_ctl;
440
441 DPU_DEBUG_VIDENC(phys_enc, "\n");
442
443 if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing))
444 return;
445
446 dpu_encoder_helper_split_config(phys_enc, phys_enc->hw_intf->idx);
447
448 dpu_encoder_phys_vid_setup_timing_engine(phys_enc);
449
450 /*
451 * For single flush cases (dual-ctl or pp-split), skip setting the
452 * flush bit for the slave intf, since both intfs use same ctl
453 * and HW will only flush the master.
454 */
455 if (dpu_encoder_phys_vid_needs_single_flush(phys_enc) &&
456 !dpu_encoder_phys_vid_is_master(phys_enc))
457 goto skip_flush;
458
459 ctl->ops.get_bitmask_intf(ctl, &flush_mask, phys_enc->hw_intf->idx);
460 ctl->ops.update_pending_flush(ctl, flush_mask);
461
462 skip_flush:
463 DPU_DEBUG_VIDENC(phys_enc,
464 "update pending flush ctl %d flush_mask %x\n",
465 ctl->idx - CTL_0, flush_mask);
466
467 /* ctl_flush & timing engine enable will be triggered by framework */
468 if (phys_enc->enable_state == DPU_ENC_DISABLED)
469 phys_enc->enable_state = DPU_ENC_ENABLING;
470 }
471
dpu_encoder_phys_vid_destroy(struct dpu_encoder_phys * phys_enc)472 static void dpu_encoder_phys_vid_destroy(struct dpu_encoder_phys *phys_enc)
473 {
474 if (!phys_enc) {
475 DPU_ERROR("invalid encoder\n");
476 return;
477 }
478
479 DPU_DEBUG_VIDENC(phys_enc, "\n");
480 kfree(phys_enc);
481 }
482
dpu_encoder_phys_vid_get_hw_resources(struct dpu_encoder_phys * phys_enc,struct dpu_encoder_hw_resources * hw_res)483 static void dpu_encoder_phys_vid_get_hw_resources(
484 struct dpu_encoder_phys *phys_enc,
485 struct dpu_encoder_hw_resources *hw_res)
486 {
487 hw_res->intfs[phys_enc->intf_idx - INTF_0] = INTF_MODE_VIDEO;
488 }
489
dpu_encoder_phys_vid_wait_for_vblank(struct dpu_encoder_phys * phys_enc)490 static int dpu_encoder_phys_vid_wait_for_vblank(
491 struct dpu_encoder_phys *phys_enc)
492 {
493 struct dpu_encoder_wait_info wait_info;
494 int ret;
495
496 if (!phys_enc) {
497 pr_err("invalid encoder\n");
498 return -EINVAL;
499 }
500
501 wait_info.wq = &phys_enc->pending_kickoff_wq;
502 wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt;
503 wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
504
505 if (!dpu_encoder_phys_vid_is_master(phys_enc)) {
506 return 0;
507 }
508
509 /* Wait for kickoff to complete */
510 ret = dpu_encoder_helper_wait_for_irq(phys_enc, INTR_IDX_VSYNC,
511 &wait_info);
512
513 if (ret == -ETIMEDOUT) {
514 dpu_encoder_helper_report_irq_timeout(phys_enc, INTR_IDX_VSYNC);
515 }
516
517 return ret;
518 }
519
dpu_encoder_phys_vid_wait_for_commit_done(struct dpu_encoder_phys * phys_enc)520 static int dpu_encoder_phys_vid_wait_for_commit_done(
521 struct dpu_encoder_phys *phys_enc)
522 {
523 struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl;
524 int ret;
525
526 if (!hw_ctl)
527 return 0;
528
529 ret = wait_event_timeout(phys_enc->pending_kickoff_wq,
530 (hw_ctl->ops.get_flush_register(hw_ctl) == 0),
531 msecs_to_jiffies(50));
532 if (ret <= 0) {
533 DPU_ERROR("vblank timeout\n");
534 return -ETIMEDOUT;
535 }
536
537 return 0;
538 }
539
dpu_encoder_phys_vid_prepare_for_kickoff(struct dpu_encoder_phys * phys_enc)540 static void dpu_encoder_phys_vid_prepare_for_kickoff(
541 struct dpu_encoder_phys *phys_enc)
542 {
543 struct dpu_hw_ctl *ctl;
544 int rc;
545
546 if (!phys_enc) {
547 DPU_ERROR("invalid encoder/parameters\n");
548 return;
549 }
550
551 ctl = phys_enc->hw_ctl;
552 if (!ctl || !ctl->ops.wait_reset_status)
553 return;
554
555 /*
556 * hw supports hardware initiated ctl reset, so before we kickoff a new
557 * frame, need to check and wait for hw initiated ctl reset completion
558 */
559 rc = ctl->ops.wait_reset_status(ctl);
560 if (rc) {
561 DPU_ERROR_VIDENC(phys_enc, "ctl %d reset failure: %d\n",
562 ctl->idx, rc);
563 dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_VSYNC);
564 }
565 }
566
dpu_encoder_phys_vid_disable(struct dpu_encoder_phys * phys_enc)567 static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc)
568 {
569 struct msm_drm_private *priv;
570 unsigned long lock_flags;
571 int ret;
572
573 if (!phys_enc || !phys_enc->parent || !phys_enc->parent->dev ||
574 !phys_enc->parent->dev->dev_private) {
575 DPU_ERROR("invalid encoder/device\n");
576 return;
577 }
578 priv = phys_enc->parent->dev->dev_private;
579
580 if (!phys_enc->hw_intf || !phys_enc->hw_ctl) {
581 DPU_ERROR("invalid hw_intf %d hw_ctl %d\n",
582 phys_enc->hw_intf != 0, phys_enc->hw_ctl != 0);
583 return;
584 }
585
586 if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing))
587 return;
588
589 if (phys_enc->enable_state == DPU_ENC_DISABLED) {
590 DPU_ERROR("already disabled\n");
591 return;
592 }
593
594 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
595 phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 0);
596 if (dpu_encoder_phys_vid_is_master(phys_enc))
597 dpu_encoder_phys_inc_pending(phys_enc);
598 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
599
600 /*
601 * Wait for a vsync so we know the ENABLE=0 latched before
602 * the (connector) source of the vsync's gets disabled,
603 * otherwise we end up in a funny state if we re-enable
604 * before the disable latches, which results that some of
605 * the settings changes for the new modeset (like new
606 * scanout buffer) don't latch properly..
607 */
608 if (dpu_encoder_phys_vid_is_master(phys_enc)) {
609 ret = dpu_encoder_phys_vid_wait_for_vblank(phys_enc);
610 if (ret) {
611 atomic_set(&phys_enc->pending_kickoff_cnt, 0);
612 DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n",
613 DRMID(phys_enc->parent),
614 phys_enc->hw_intf->idx - INTF_0, ret);
615 }
616 }
617
618 phys_enc->enable_state = DPU_ENC_DISABLED;
619 }
620
dpu_encoder_phys_vid_handle_post_kickoff(struct dpu_encoder_phys * phys_enc)621 static void dpu_encoder_phys_vid_handle_post_kickoff(
622 struct dpu_encoder_phys *phys_enc)
623 {
624 unsigned long lock_flags;
625
626 /*
627 * Video mode must flush CTL before enabling timing engine
628 * Video encoders need to turn on their interfaces now
629 */
630 if (phys_enc->enable_state == DPU_ENC_ENABLING) {
631 trace_dpu_enc_phys_vid_post_kickoff(DRMID(phys_enc->parent),
632 phys_enc->hw_intf->idx - INTF_0);
633 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
634 phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 1);
635 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
636 phys_enc->enable_state = DPU_ENC_ENABLED;
637 }
638 }
639
dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys * phys_enc,bool enable)640 static void dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys *phys_enc,
641 bool enable)
642 {
643 int ret;
644
645 if (!phys_enc)
646 return;
647
648 trace_dpu_enc_phys_vid_irq_ctrl(DRMID(phys_enc->parent),
649 phys_enc->hw_intf->idx - INTF_0,
650 enable,
651 atomic_read(&phys_enc->vblank_refcount));
652
653 if (enable) {
654 ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true);
655 if (ret)
656 return;
657
658 dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_UNDERRUN);
659 } else {
660 dpu_encoder_phys_vid_control_vblank_irq(phys_enc, false);
661 dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_UNDERRUN);
662 }
663 }
664
dpu_encoder_phys_vid_get_line_count(struct dpu_encoder_phys * phys_enc)665 static int dpu_encoder_phys_vid_get_line_count(
666 struct dpu_encoder_phys *phys_enc)
667 {
668 if (!phys_enc)
669 return -EINVAL;
670
671 if (!dpu_encoder_phys_vid_is_master(phys_enc))
672 return -EINVAL;
673
674 if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_line_count)
675 return -EINVAL;
676
677 return phys_enc->hw_intf->ops.get_line_count(phys_enc->hw_intf);
678 }
679
dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops * ops)680 static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops)
681 {
682 ops->is_master = dpu_encoder_phys_vid_is_master;
683 ops->mode_set = dpu_encoder_phys_vid_mode_set;
684 ops->mode_fixup = dpu_encoder_phys_vid_mode_fixup;
685 ops->enable = dpu_encoder_phys_vid_enable;
686 ops->disable = dpu_encoder_phys_vid_disable;
687 ops->destroy = dpu_encoder_phys_vid_destroy;
688 ops->get_hw_resources = dpu_encoder_phys_vid_get_hw_resources;
689 ops->control_vblank_irq = dpu_encoder_phys_vid_control_vblank_irq;
690 ops->wait_for_commit_done = dpu_encoder_phys_vid_wait_for_commit_done;
691 ops->wait_for_vblank = dpu_encoder_phys_vid_wait_for_vblank;
692 ops->wait_for_tx_complete = dpu_encoder_phys_vid_wait_for_vblank;
693 ops->irq_control = dpu_encoder_phys_vid_irq_control;
694 ops->prepare_for_kickoff = dpu_encoder_phys_vid_prepare_for_kickoff;
695 ops->handle_post_kickoff = dpu_encoder_phys_vid_handle_post_kickoff;
696 ops->needs_single_flush = dpu_encoder_phys_vid_needs_single_flush;
697 ops->get_line_count = dpu_encoder_phys_vid_get_line_count;
698 }
699
dpu_encoder_phys_vid_init(struct dpu_enc_phys_init_params * p)700 struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
701 struct dpu_enc_phys_init_params *p)
702 {
703 struct dpu_encoder_phys *phys_enc = NULL;
704 struct dpu_encoder_irq *irq;
705 int i, ret = 0;
706
707 if (!p) {
708 ret = -EINVAL;
709 goto fail;
710 }
711
712 phys_enc = kzalloc(sizeof(*phys_enc), GFP_KERNEL);
713 if (!phys_enc) {
714 ret = -ENOMEM;
715 goto fail;
716 }
717
718 phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
719 phys_enc->intf_idx = p->intf_idx;
720
721 DPU_DEBUG_VIDENC(phys_enc, "\n");
722
723 dpu_encoder_phys_vid_init_ops(&phys_enc->ops);
724 phys_enc->parent = p->parent;
725 phys_enc->parent_ops = p->parent_ops;
726 phys_enc->dpu_kms = p->dpu_kms;
727 phys_enc->split_role = p->split_role;
728 phys_enc->intf_mode = INTF_MODE_VIDEO;
729 phys_enc->enc_spinlock = p->enc_spinlock;
730 for (i = 0; i < INTR_IDX_MAX; i++) {
731 irq = &phys_enc->irq[i];
732 INIT_LIST_HEAD(&irq->cb.list);
733 irq->irq_idx = -EINVAL;
734 irq->hw_idx = -EINVAL;
735 irq->cb.arg = phys_enc;
736 }
737
738 irq = &phys_enc->irq[INTR_IDX_VSYNC];
739 irq->name = "vsync_irq";
740 irq->intr_type = DPU_IRQ_TYPE_INTF_VSYNC;
741 irq->intr_idx = INTR_IDX_VSYNC;
742 irq->cb.func = dpu_encoder_phys_vid_vblank_irq;
743
744 irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
745 irq->name = "underrun";
746 irq->intr_type = DPU_IRQ_TYPE_INTF_UNDER_RUN;
747 irq->intr_idx = INTR_IDX_UNDERRUN;
748 irq->cb.func = dpu_encoder_phys_vid_underrun_irq;
749
750 atomic_set(&phys_enc->vblank_refcount, 0);
751 atomic_set(&phys_enc->pending_kickoff_cnt, 0);
752 init_waitqueue_head(&phys_enc->pending_kickoff_wq);
753 phys_enc->enable_state = DPU_ENC_DISABLED;
754
755 DPU_DEBUG_VIDENC(phys_enc, "created intf idx:%d\n", p->intf_idx);
756
757 return phys_enc;
758
759 fail:
760 DPU_ERROR("failed to create encoder\n");
761 if (phys_enc)
762 dpu_encoder_phys_vid_destroy(phys_enc);
763
764 return ERR_PTR(ret);
765 }
766
