1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 *
4 * OMAP SRAM detection and management
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
8 *
9 * Copyright (C) 2009-2012 Texas Instruments
10 * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 */
12
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/io.h>
17 #include <linux/set_memory.h>
18
19 #include <asm/fncpy.h>
20 #include <asm/tlb.h>
21 #include <asm/cacheflush.h>
22
23 #include <asm/mach/map.h>
24
25 #include "soc.h"
26 #include "iomap.h"
27 #include "prm2xxx_3xxx.h"
28 #include "sdrc.h"
29 #include "sram.h"
30
31 #define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800)
32 #define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000)
33
34 #define SRAM_BOOTLOADER_SZ 0x00
35
36 #define OMAP24XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68005048)
37 #define OMAP24XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68005050)
38 #define OMAP24XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68005058)
39
40 #define OMAP34XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68012848)
41 #define OMAP34XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68012850)
42 #define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858)
43 #define OMAP34XX_VA_ADDR_MATCH2 OMAP2_L3_IO_ADDRESS(0x68012880)
44 #define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_L3_IO_ADDRESS(0x6C000048)
45
46 #define GP_DEVICE 0x300
47
48 #define ROUND_DOWN(value, boundary) ((value) & (~((boundary) - 1)))
49
50 static unsigned long omap_sram_start;
51 static unsigned long omap_sram_size;
52 static void __iomem *omap_sram_base;
53 static unsigned long omap_sram_skip;
54 static void __iomem *omap_sram_ceil;
55
56 /*
57 * Memory allocator for SRAM: calculates the new ceiling address
58 * for pushing a function using the fncpy API.
59 *
60 * Note that fncpy requires the returned address to be aligned
61 * to an 8-byte boundary.
62 */
omap_sram_push_address(unsigned long size)63 static void *omap_sram_push_address(unsigned long size)
64 {
65 unsigned long available, new_ceil = (unsigned long)omap_sram_ceil;
66
67 available = omap_sram_ceil - (omap_sram_base + omap_sram_skip);
68
69 if (size > available) {
70 pr_err("Not enough space in SRAM\n");
71 return NULL;
72 }
73
74 new_ceil -= size;
75 new_ceil = ROUND_DOWN(new_ceil, FNCPY_ALIGN);
76 omap_sram_ceil = IOMEM(new_ceil);
77
78 return (void __force *)omap_sram_ceil;
79 }
80
omap_sram_push(void * funcp,unsigned long size)81 void *omap_sram_push(void *funcp, unsigned long size)
82 {
83 void *sram;
84 unsigned long base;
85 int pages;
86 void *dst = NULL;
87
88 sram = omap_sram_push_address(size);
89 if (!sram)
90 return NULL;
91
92 base = (unsigned long)sram & PAGE_MASK;
93 pages = PAGE_ALIGN(size) / PAGE_SIZE;
94
95 set_memory_rw(base, pages);
96
97 dst = fncpy(sram, funcp, size);
98
99 set_memory_rox(base, pages);
100
101 return dst;
102 }
103
104 /*
105 * The SRAM context is lost during off-idle and stack
106 * needs to be reset.
107 */
omap_sram_reset(void)108 static void omap_sram_reset(void)
109 {
110 omap_sram_ceil = omap_sram_base + omap_sram_size;
111 }
112
113 /*
114 * Depending on the target RAMFS firewall setup, the public usable amount of
115 * SRAM varies. The default accessible size for all device types is 2k. A GP
116 * device allows ARM11 but not other initiators for full size. This
117 * functionality seems ok until some nice security API happens.
118 */
is_sram_locked(void)119 static int is_sram_locked(void)
120 {
121 if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
122 /* RAMFW: R/W access to all initiators for all qualifier sets */
123 if (cpu_is_omap242x()) {
124 writel_relaxed(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
125 writel_relaxed(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
126 writel_relaxed(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
127 }
128 if (cpu_is_omap34xx()) {
129 writel_relaxed(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
130 writel_relaxed(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
131 writel_relaxed(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
132 writel_relaxed(0x0, OMAP34XX_VA_ADDR_MATCH2);
133 writel_relaxed(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
134 }
135 return 0;
136 } else
137 return 1; /* assume locked with no PPA or security driver */
138 }
139
140 /*
141 * The amount of SRAM depends on the core type.
142 * Note that we cannot try to test for SRAM here because writes
143 * to secure SRAM will hang the system. Also the SRAM is not
144 * yet mapped at this point.
145 */
omap_detect_sram(void)146 static void __init omap_detect_sram(void)
147 {
148 omap_sram_skip = SRAM_BOOTLOADER_SZ;
149 if (is_sram_locked()) {
150 if (cpu_is_omap34xx()) {
151 omap_sram_start = OMAP3_SRAM_PUB_PA;
152 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
153 (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
154 omap_sram_size = 0x7000; /* 28K */
155 omap_sram_skip += SZ_16K;
156 } else {
157 omap_sram_size = 0x8000; /* 32K */
158 }
159 } else {
160 omap_sram_start = OMAP2_SRAM_PUB_PA;
161 omap_sram_size = 0x800; /* 2K */
162 }
163 } else {
164 if (cpu_is_omap34xx()) {
165 omap_sram_start = OMAP3_SRAM_PA;
166 omap_sram_size = 0x10000; /* 64K */
167 } else {
168 omap_sram_start = OMAP2_SRAM_PA;
169 if (cpu_is_omap242x())
170 omap_sram_size = 0xa0000; /* 640K */
171 else if (cpu_is_omap243x())
172 omap_sram_size = 0x10000; /* 64K */
173 }
174 }
175 }
176
177 /*
178 * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
179 */
omap2_map_sram(void)180 static void __init omap2_map_sram(void)
181 {
182 unsigned long base;
183 int pages;
184 int cached = 1;
185
186 if (cpu_is_omap34xx()) {
187 /*
188 * SRAM must be marked as non-cached on OMAP3 since the
189 * CORE DPLL M2 divider change code (in SRAM) runs with the
190 * SDRAM controller disabled, and if it is marked cached,
191 * the ARM may attempt to write cache lines back to SDRAM
192 * which will cause the system to hang.
193 */
194 cached = 0;
195 }
196
197 if (omap_sram_size == 0)
198 return;
199
200 omap_sram_start = ROUND_DOWN(omap_sram_start, PAGE_SIZE);
201 omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size, cached);
202 if (!omap_sram_base) {
203 pr_err("SRAM: Could not map\n");
204 return;
205 }
206
207 omap_sram_reset();
208
209 /*
210 * Looks like we need to preserve some bootloader code at the
211 * beginning of SRAM for jumping to flash for reboot to work...
212 */
213 memset_io(omap_sram_base + omap_sram_skip, 0,
214 omap_sram_size - omap_sram_skip);
215
216 base = (unsigned long)omap_sram_base;
217 pages = PAGE_ALIGN(omap_sram_size) / PAGE_SIZE;
218
219 set_memory_rox(base, pages);
220 }
221
222 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
223 u32 base_cs, u32 force_unlock);
224
omap2_sram_ddr_init(u32 * slow_dll_ctrl,u32 fast_dll_ctrl,u32 base_cs,u32 force_unlock)225 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
226 u32 base_cs, u32 force_unlock)
227 {
228 BUG_ON(!_omap2_sram_ddr_init);
229 _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
230 base_cs, force_unlock);
231 }
232
233 static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
234 u32 mem_type);
235
omap2_sram_reprogram_sdrc(u32 perf_level,u32 dll_val,u32 mem_type)236 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
237 {
238 BUG_ON(!_omap2_sram_reprogram_sdrc);
239 _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
240 }
241
242 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
243
omap2_set_prcm(u32 dpll_ctrl_val,u32 sdrc_rfr_val,int bypass)244 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
245 {
246 BUG_ON(!_omap2_set_prcm);
247 return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
248 }
249
250 #ifdef CONFIG_SOC_OMAP2420
omap242x_sram_init(void)251 static int __init omap242x_sram_init(void)
252 {
253 _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
254 omap242x_sram_ddr_init_sz);
255
256 _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
257 omap242x_sram_reprogram_sdrc_sz);
258
259 _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
260 omap242x_sram_set_prcm_sz);
261
262 return 0;
263 }
264 #else
omap242x_sram_init(void)265 static inline int omap242x_sram_init(void)
266 {
267 return 0;
268 }
269 #endif
270
271 #ifdef CONFIG_SOC_OMAP2430
omap243x_sram_init(void)272 static int __init omap243x_sram_init(void)
273 {
274 _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
275 omap243x_sram_ddr_init_sz);
276
277 _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
278 omap243x_sram_reprogram_sdrc_sz);
279
280 _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
281 omap243x_sram_set_prcm_sz);
282
283 return 0;
284 }
285 #else
omap243x_sram_init(void)286 static inline int omap243x_sram_init(void)
287 {
288 return 0;
289 }
290 #endif
291
292 #ifdef CONFIG_ARCH_OMAP3
293
omap3_sram_restore_context(void)294 void omap3_sram_restore_context(void)
295 {
296 omap_sram_reset();
297
298 omap_push_sram_idle();
299 }
300
omap34xx_sram_init(void)301 static inline int omap34xx_sram_init(void)
302 {
303 omap3_sram_restore_context();
304 return 0;
305 }
306 #else
omap34xx_sram_init(void)307 static inline int omap34xx_sram_init(void)
308 {
309 return 0;
310 }
311 #endif /* CONFIG_ARCH_OMAP3 */
312
omap_sram_init(void)313 int __init omap_sram_init(void)
314 {
315 omap_detect_sram();
316 omap2_map_sram();
317
318 if (cpu_is_omap242x())
319 omap242x_sram_init();
320 else if (cpu_is_omap2430())
321 omap243x_sram_init();
322 else if (cpu_is_omap34xx())
323 omap34xx_sram_init();
324
325 return 0;
326 }
327
