1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 /* FILE POLICY AND INTENDED USAGE:
27 * This file implements retrieval and configuration of eDP panel features such
28 * as PSR and ABM and it also manages specs defined eDP panel power sequences.
29 */
30
31 #include "link_edp_panel_control.h"
32 #include "link_dpcd.h"
33 #include "link_dp_capability.h"
34 #include "dm_helpers.h"
35 #include "dal_asic_id.h"
36 #include "dce/dmub_psr.h"
37 #include "dc/dc_dmub_srv.h"
38 #include "dce/dmub_replay.h"
39 #include "abm.h"
40 #define DC_LOGGER_INIT(logger)
41
42 #define DP_SINK_PR_ENABLE_AND_CONFIGURATION 0x37B
43
44 /* Travis */
45 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
46 /* Nutmeg */
47 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
48
dp_set_panel_mode(struct dc_link * link,enum dp_panel_mode panel_mode)49 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
50 {
51 union dpcd_edp_config edp_config_set;
52 bool panel_mode_edp = false;
53 enum dc_status result;
54
55 memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
56
57 switch (panel_mode) {
58 case DP_PANEL_MODE_EDP:
59 case DP_PANEL_MODE_SPECIAL:
60 panel_mode_edp = true;
61 break;
62
63 default:
64 break;
65 }
66
67 /*set edp panel mode in receiver*/
68 result = core_link_read_dpcd(
69 link,
70 DP_EDP_CONFIGURATION_SET,
71 &edp_config_set.raw,
72 sizeof(edp_config_set.raw));
73
74 if (result == DC_OK &&
75 edp_config_set.bits.PANEL_MODE_EDP
76 != panel_mode_edp) {
77
78 edp_config_set.bits.PANEL_MODE_EDP =
79 panel_mode_edp;
80 result = core_link_write_dpcd(
81 link,
82 DP_EDP_CONFIGURATION_SET,
83 &edp_config_set.raw,
84 sizeof(edp_config_set.raw));
85
86 ASSERT(result == DC_OK);
87 }
88
89 link->panel_mode = panel_mode;
90 DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
91 "eDP panel mode enabled: %d \n",
92 link->link_index,
93 link->dpcd_caps.panel_mode_edp,
94 panel_mode_edp);
95 }
96
dp_get_panel_mode(struct dc_link * link)97 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
98 {
99 /* We need to explicitly check that connector
100 * is not DP. Some Travis_VGA get reported
101 * by video bios as DP.
102 */
103 if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
104
105 switch (link->dpcd_caps.branch_dev_id) {
106 case DP_BRANCH_DEVICE_ID_0022B9:
107 /* alternate scrambler reset is required for Travis
108 * for the case when external chip does not
109 * provide sink device id, alternate scrambler
110 * scheme will be overriden later by querying
111 * Encoder features
112 */
113 if (strncmp(
114 link->dpcd_caps.branch_dev_name,
115 DP_VGA_LVDS_CONVERTER_ID_2,
116 sizeof(
117 link->dpcd_caps.
118 branch_dev_name)) == 0) {
119 return DP_PANEL_MODE_SPECIAL;
120 }
121 break;
122 case DP_BRANCH_DEVICE_ID_00001A:
123 /* alternate scrambler reset is required for Travis
124 * for the case when external chip does not provide
125 * sink device id, alternate scrambler scheme will
126 * be overriden later by querying Encoder feature
127 */
128 if (strncmp(link->dpcd_caps.branch_dev_name,
129 DP_VGA_LVDS_CONVERTER_ID_3,
130 sizeof(
131 link->dpcd_caps.
132 branch_dev_name)) == 0) {
133 return DP_PANEL_MODE_SPECIAL;
134 }
135 break;
136 default:
137 break;
138 }
139 }
140
141 if (link->dpcd_caps.panel_mode_edp &&
142 (link->connector_signal == SIGNAL_TYPE_EDP ||
143 (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
144 link->is_internal_display))) {
145 return DP_PANEL_MODE_EDP;
146 }
147
148 return DP_PANEL_MODE_DEFAULT;
149 }
150
edp_set_backlight_level_nits(struct dc_link * link,bool isHDR,uint32_t backlight_millinits,uint32_t transition_time_in_ms)151 bool edp_set_backlight_level_nits(struct dc_link *link,
152 bool isHDR,
153 uint32_t backlight_millinits,
154 uint32_t transition_time_in_ms)
155 {
156 struct dpcd_source_backlight_set dpcd_backlight_set;
157 uint8_t backlight_control = isHDR ? 1 : 0;
158
159 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
160 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
161 return false;
162
163 // OLEDs have no PWM, they can only use AUX
164 if (link->dpcd_sink_ext_caps.bits.oled == 1)
165 backlight_control = 1;
166
167 *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits;
168 *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;
169
170 link->backlight_settings.backlight_millinits = backlight_millinits;
171
172 if (!link->dpcd_caps.panel_luminance_control) {
173 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
174 (uint8_t *)(&dpcd_backlight_set),
175 sizeof(dpcd_backlight_set)) != DC_OK)
176 return false;
177
178 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,
179 &backlight_control, 1) != DC_OK)
180 return false;
181 } else {
182 const uint8_t backlight_enable = DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE;
183 struct target_luminance_value *target_luminance = NULL;
184
185 //if target luminance value is greater than 24 bits, clip the value to 24 bits
186 if (backlight_millinits > 0xFFFFFF)
187 backlight_millinits = 0xFFFFFF;
188
189 target_luminance = (struct target_luminance_value *)&backlight_millinits;
190
191 if (core_link_write_dpcd(link, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
192 &backlight_enable,
193 sizeof(backlight_enable)) != DC_OK)
194 return false;
195
196 if (core_link_write_dpcd(link, DP_EDP_PANEL_TARGET_LUMINANCE_VALUE,
197 (uint8_t *)(target_luminance),
198 sizeof(struct target_luminance_value)) != DC_OK)
199 return false;
200 }
201
202 return true;
203 }
204
edp_get_backlight_level_nits(struct dc_link * link,uint32_t * backlight_millinits_avg,uint32_t * backlight_millinits_peak)205 bool edp_get_backlight_level_nits(struct dc_link *link,
206 uint32_t *backlight_millinits_avg,
207 uint32_t *backlight_millinits_peak)
208 {
209 union dpcd_source_backlight_get dpcd_backlight_get;
210
211 memset(&dpcd_backlight_get, 0, sizeof(union dpcd_source_backlight_get));
212
213 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
214 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
215 return false;
216
217 if (!core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CURRENT_PEAK,
218 dpcd_backlight_get.raw,
219 sizeof(union dpcd_source_backlight_get)))
220 return false;
221
222 *backlight_millinits_avg =
223 dpcd_backlight_get.bytes.backlight_millinits_avg;
224 *backlight_millinits_peak =
225 dpcd_backlight_get.bytes.backlight_millinits_peak;
226
227 /* On non-supported panels dpcd_read usually succeeds with 0 returned */
228 if (*backlight_millinits_avg == 0 ||
229 *backlight_millinits_avg > *backlight_millinits_peak)
230 return false;
231
232 return true;
233 }
234
edp_backlight_enable_aux(struct dc_link * link,bool enable)235 bool edp_backlight_enable_aux(struct dc_link *link, bool enable)
236 {
237 uint8_t backlight_enable = enable ? 1 : 0;
238
239 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
240 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
241 return false;
242
243 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_ENABLE,
244 &backlight_enable, 1) != DC_OK)
245 return false;
246
247 return true;
248 }
249
250 // we read default from 0x320 because we expect BIOS wrote it there
251 // regular get_backlight_nit reads from panel set at 0x326
read_default_bl_aux(struct dc_link * link,uint32_t * backlight_millinits)252 static bool read_default_bl_aux(struct dc_link *link, uint32_t *backlight_millinits)
253 {
254 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
255 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
256 return false;
257
258 if (!link->dpcd_caps.panel_luminance_control) {
259 if (!core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
260 (uint8_t *)backlight_millinits,
261 sizeof(uint32_t)))
262 return false;
263 } else {
264 //setting to 0 as a precaution, since target_luminance_value is 3 bytes
265 memset(backlight_millinits, 0, sizeof(uint32_t));
266
267 if (!core_link_read_dpcd(link, DP_EDP_PANEL_TARGET_LUMINANCE_VALUE,
268 (uint8_t *)backlight_millinits,
269 sizeof(struct target_luminance_value)))
270 return false;
271 }
272
273 return true;
274 }
275
set_default_brightness_aux(struct dc_link * link)276 bool set_default_brightness_aux(struct dc_link *link)
277 {
278 uint32_t default_backlight;
279
280 if (link && link->dpcd_sink_ext_caps.bits.oled == 1) {
281 if (!read_default_bl_aux(link, &default_backlight))
282 default_backlight = 150000;
283 // if < 5 nits or > 5000, it might be wrong readback
284 if (default_backlight < 5000 || default_backlight > 5000000)
285 default_backlight = 150000; //
286
287 return edp_set_backlight_level_nits(link, true,
288 default_backlight, 0);
289 }
290 return false;
291 }
292
set_cached_brightness_aux(struct dc_link * link)293 bool set_cached_brightness_aux(struct dc_link *link)
294 {
295 if (link->backlight_settings.backlight_millinits)
296 return edp_set_backlight_level_nits(link, true,
297 link->backlight_settings.backlight_millinits, 0);
298 else
299 return set_default_brightness_aux(link);
300 return false;
301 }
302
edp_is_ilr_optimization_required(struct dc_link * link,struct dc_crtc_timing * crtc_timing)303 bool edp_is_ilr_optimization_required(struct dc_link *link,
304 struct dc_crtc_timing *crtc_timing)
305 {
306 struct dc_link_settings link_setting;
307 uint8_t link_bw_set;
308 uint8_t link_rate_set;
309 uint32_t req_bw;
310 union lane_count_set lane_count_set = {0};
311
312 ASSERT(link || crtc_timing); // invalid input
313
314 if (link->dpcd_caps.edp_supported_link_rates_count == 0 ||
315 !link->panel_config.ilr.optimize_edp_link_rate)
316 return false;
317
318
319 // Read DPCD 00100h to find if standard link rates are set
320 core_link_read_dpcd(link, DP_LINK_BW_SET,
321 &link_bw_set, sizeof(link_bw_set));
322
323 if (link_bw_set) {
324 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS used link_bw_set\n");
325 return true;
326 }
327
328 // Read DPCD 00115h to find the edp link rate set used
329 core_link_read_dpcd(link, DP_LINK_RATE_SET,
330 &link_rate_set, sizeof(link_rate_set));
331
332 // Read DPCD 00101h to find out the number of lanes currently set
333 core_link_read_dpcd(link, DP_LANE_COUNT_SET,
334 &lane_count_set.raw, sizeof(lane_count_set));
335
336 req_bw = dc_bandwidth_in_kbps_from_timing(crtc_timing, dc_link_get_highest_encoding_format(link));
337
338 if (!crtc_timing->flags.DSC)
339 edp_decide_link_settings(link, &link_setting, req_bw);
340 else
341 decide_edp_link_settings_with_dsc(link, &link_setting, req_bw, LINK_RATE_UNKNOWN);
342
343 if (link->dpcd_caps.edp_supported_link_rates[link_rate_set] != link_setting.link_rate ||
344 lane_count_set.bits.LANE_COUNT_SET != link_setting.lane_count) {
345 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS link_rate_set not optimal\n");
346 return true;
347 }
348
349 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: No optimization required, VBIOS set optimal link_rate_set\n");
350 return false;
351 }
352
edp_panel_backlight_power_on(struct dc_link * link,bool wait_for_hpd)353 void edp_panel_backlight_power_on(struct dc_link *link, bool wait_for_hpd)
354 {
355 if (link->connector_signal != SIGNAL_TYPE_EDP)
356 return;
357
358 link->dc->hwss.edp_power_control(link, true);
359 if (wait_for_hpd)
360 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
361 if (link->dc->hwss.edp_backlight_control)
362 link->dc->hwss.edp_backlight_control(link, true);
363 }
364
edp_wait_for_t12(struct dc_link * link)365 bool edp_wait_for_t12(struct dc_link *link)
366 {
367 if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->hwss.edp_wait_for_T12) {
368 link->dc->hwss.edp_wait_for_T12(link);
369
370 return true;
371 }
372
373 return false;
374 }
375
edp_add_delay_for_T9(struct dc_link * link)376 void edp_add_delay_for_T9(struct dc_link *link)
377 {
378 if (link && link->panel_config.pps.extra_delay_backlight_off > 0)
379 fsleep(link->panel_config.pps.extra_delay_backlight_off * 1000);
380 }
381
edp_receiver_ready_T9(struct dc_link * link)382 bool edp_receiver_ready_T9(struct dc_link *link)
383 {
384 unsigned int tries = 0;
385 unsigned char sinkstatus = 0;
386 unsigned char edpRev = 0;
387 enum dc_status result = DC_OK;
388
389 result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, &edpRev, sizeof(edpRev));
390
391 /* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
392 if (result == DC_OK && edpRev >= DP_EDP_12) {
393 do {
394 sinkstatus = 1;
395 result = core_link_read_dpcd(link, DP_SINK_STATUS, &sinkstatus, sizeof(sinkstatus));
396 if (sinkstatus == 0)
397 break;
398 if (result != DC_OK)
399 break;
400 udelay(100); //MAx T9
401 } while (++tries < 50);
402 }
403
404 return result;
405 }
406
edp_receiver_ready_T7(struct dc_link * link)407 bool edp_receiver_ready_T7(struct dc_link *link)
408 {
409 unsigned char sinkstatus = 0;
410 unsigned char edpRev = 0;
411 enum dc_status result = DC_OK;
412
413 /* use absolute time stamp to constrain max T7*/
414 unsigned long long enter_timestamp = 0;
415 unsigned long long finish_timestamp = 0;
416 unsigned long long time_taken_in_ns = 0;
417
418 result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, &edpRev, sizeof(edpRev));
419
420 if (result == DC_OK && edpRev >= DP_EDP_12) {
421 /* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
422 enter_timestamp = dm_get_timestamp(link->ctx);
423 do {
424 sinkstatus = 0;
425 result = core_link_read_dpcd(link, DP_SINK_STATUS, &sinkstatus, sizeof(sinkstatus));
426 if (sinkstatus == 1)
427 break;
428 if (result != DC_OK)
429 break;
430 udelay(25);
431 finish_timestamp = dm_get_timestamp(link->ctx);
432 time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp, enter_timestamp);
433 } while (time_taken_in_ns < 50 * 1000000); //MAx T7 is 50ms
434 }
435
436 if (link && link->panel_config.pps.extra_t7_ms > 0)
437 fsleep(link->panel_config.pps.extra_t7_ms * 1000);
438
439 return result;
440 }
441
edp_power_alpm_dpcd_enable(struct dc_link * link,bool enable)442 bool edp_power_alpm_dpcd_enable(struct dc_link *link, bool enable)
443 {
444 bool ret = false;
445 union dpcd_alpm_configuration alpm_config;
446
447 if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
448 memset(&alpm_config, 0, sizeof(alpm_config));
449
450 alpm_config.bits.ENABLE = (enable ? true : false);
451 ret = dm_helpers_dp_write_dpcd(link->ctx, link,
452 DP_RECEIVER_ALPM_CONFIG, &alpm_config.raw,
453 sizeof(alpm_config.raw));
454 }
455 return ret;
456 }
457
get_pipe_from_link(const struct dc_link * link)458 static struct pipe_ctx *get_pipe_from_link(const struct dc_link *link)
459 {
460 int i;
461 struct dc *dc = link->ctx->dc;
462 struct pipe_ctx *pipe_ctx = NULL;
463
464 for (i = 0; i < MAX_PIPES; i++) {
465 if (dc->current_state->res_ctx.pipe_ctx[i].stream) {
466 if (dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {
467 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
468 break;
469 }
470 }
471 }
472
473 return pipe_ctx;
474 }
475
edp_set_backlight_level(const struct dc_link * link,uint32_t backlight_pwm_u16_16,uint32_t frame_ramp)476 bool edp_set_backlight_level(const struct dc_link *link,
477 uint32_t backlight_pwm_u16_16,
478 uint32_t frame_ramp)
479 {
480 struct dc *dc = link->ctx->dc;
481
482 DC_LOGGER_INIT(link->ctx->logger);
483 DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
484 backlight_pwm_u16_16, backlight_pwm_u16_16);
485
486 if (dc_is_embedded_signal(link->connector_signal)) {
487 struct pipe_ctx *pipe_ctx = get_pipe_from_link(link);
488
489 if (pipe_ctx) {
490 /* Disable brightness ramping when the display is blanked
491 * as it can hang the DMCU
492 */
493 if (pipe_ctx->plane_state == NULL)
494 frame_ramp = 0;
495 } else {
496 return false;
497 }
498
499 dc->hwss.set_backlight_level(
500 pipe_ctx,
501 backlight_pwm_u16_16,
502 frame_ramp);
503 }
504 return true;
505 }
506
edp_set_psr_allow_active(struct dc_link * link,const bool * allow_active,bool wait,bool force_static,const unsigned int * power_opts)507 bool edp_set_psr_allow_active(struct dc_link *link, const bool *allow_active,
508 bool wait, bool force_static, const unsigned int *power_opts)
509 {
510 struct dc *dc = link->ctx->dc;
511 struct dmcu *dmcu = dc->res_pool->dmcu;
512 struct dmub_psr *psr = dc->res_pool->psr;
513 unsigned int panel_inst;
514
515 if (psr == NULL && force_static)
516 return false;
517
518 if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
519 return false;
520
521 if ((allow_active != NULL) && (*allow_active == true) && (link->type == dc_connection_none)) {
522 // Don't enter PSR if panel is not connected
523 return false;
524 }
525
526 /* Set power optimization flag */
527 if (power_opts && link->psr_settings.psr_power_opt != *power_opts) {
528 link->psr_settings.psr_power_opt = *power_opts;
529
530 if (psr != NULL && link->psr_settings.psr_feature_enabled && psr->funcs->psr_set_power_opt)
531 psr->funcs->psr_set_power_opt(psr, link->psr_settings.psr_power_opt, panel_inst);
532 }
533
534 if (psr != NULL && link->psr_settings.psr_feature_enabled &&
535 force_static && psr->funcs->psr_force_static)
536 psr->funcs->psr_force_static(psr, panel_inst);
537
538 /* Enable or Disable PSR */
539 if (allow_active && link->psr_settings.psr_allow_active != *allow_active) {
540 link->psr_settings.psr_allow_active = *allow_active;
541
542 if (!link->psr_settings.psr_allow_active)
543 dc_z10_restore(dc);
544
545 if (psr != NULL && link->psr_settings.psr_feature_enabled) {
546 psr->funcs->psr_enable(psr, link->psr_settings.psr_allow_active, wait, panel_inst);
547 } else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) &&
548 link->psr_settings.psr_feature_enabled)
549 dmcu->funcs->set_psr_enable(dmcu, link->psr_settings.psr_allow_active, wait);
550 else
551 return false;
552 }
553 return true;
554 }
555
edp_get_psr_state(const struct dc_link * link,enum dc_psr_state * state)556 bool edp_get_psr_state(const struct dc_link *link, enum dc_psr_state *state)
557 {
558 struct dc *dc = link->ctx->dc;
559 struct dmcu *dmcu = dc->res_pool->dmcu;
560 struct dmub_psr *psr = dc->res_pool->psr;
561 unsigned int panel_inst;
562
563 if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
564 return false;
565
566 if (psr != NULL && link->psr_settings.psr_feature_enabled)
567 psr->funcs->psr_get_state(psr, state, panel_inst);
568 else if (dmcu != NULL && link->psr_settings.psr_feature_enabled)
569 dmcu->funcs->get_psr_state(dmcu, state);
570
571 return true;
572 }
573
574 static inline enum physical_phy_id
transmitter_to_phy_id(struct dc_link * link)575 transmitter_to_phy_id(struct dc_link *link)
576 {
577 struct dc_context *dc_ctx = link->ctx;
578 enum transmitter transmitter_value = link->link_enc->transmitter;
579
580 switch (transmitter_value) {
581 case TRANSMITTER_UNIPHY_A:
582 return PHYLD_0;
583 case TRANSMITTER_UNIPHY_B:
584 return PHYLD_1;
585 case TRANSMITTER_UNIPHY_C:
586 return PHYLD_2;
587 case TRANSMITTER_UNIPHY_D:
588 return PHYLD_3;
589 case TRANSMITTER_UNIPHY_E:
590 return PHYLD_4;
591 case TRANSMITTER_UNIPHY_F:
592 return PHYLD_5;
593 case TRANSMITTER_NUTMEG_CRT:
594 return PHYLD_6;
595 case TRANSMITTER_TRAVIS_CRT:
596 return PHYLD_7;
597 case TRANSMITTER_TRAVIS_LCD:
598 return PHYLD_8;
599 case TRANSMITTER_UNIPHY_G:
600 return PHYLD_9;
601 case TRANSMITTER_COUNT:
602 return PHYLD_COUNT;
603 case TRANSMITTER_UNKNOWN:
604 return PHYLD_UNKNOWN;
605 default:
606 DC_ERROR("Unknown transmitter value %d\n", transmitter_value);
607 return PHYLD_UNKNOWN;
608 }
609 }
610
edp_setup_psr(struct dc_link * link,const struct dc_stream_state * stream,struct psr_config * psr_config,struct psr_context * psr_context)611 bool edp_setup_psr(struct dc_link *link,
612 const struct dc_stream_state *stream, struct psr_config *psr_config,
613 struct psr_context *psr_context)
614 {
615 struct dc *dc;
616 struct dmcu *dmcu;
617 struct dmub_psr *psr;
618 int i;
619 unsigned int panel_inst;
620 /* updateSinkPsrDpcdConfig*/
621 union dpcd_psr_configuration psr_configuration;
622 union dpcd_sink_active_vtotal_control_mode vtotal_control = {0};
623
624 psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
625
626 if (!link)
627 return false;
628
629 dc = link->ctx->dc;
630 dmcu = dc->res_pool->dmcu;
631 psr = dc->res_pool->psr;
632
633 if (!dmcu && !psr)
634 return false;
635
636 if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
637 return false;
638
639
640 memset(&psr_configuration, 0, sizeof(psr_configuration));
641
642 psr_configuration.bits.ENABLE = 1;
643 psr_configuration.bits.CRC_VERIFICATION = 1;
644 psr_configuration.bits.FRAME_CAPTURE_INDICATION =
645 psr_config->psr_frame_capture_indication_req;
646
647 /* Check for PSR v2*/
648 if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
649 /* For PSR v2 selective update.
650 * Indicates whether sink should start capturing
651 * immediately following active scan line,
652 * or starting with the 2nd active scan line.
653 */
654 psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
655 /*For PSR v2, determines whether Sink should generate
656 * IRQ_HPD when CRC mismatch is detected.
657 */
658 psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR = 1;
659 /* For PSR v2, set the bit when the Source device will
660 * be enabling PSR2 operation.
661 */
662 psr_configuration.bits.ENABLE_PSR2 = 1;
663 /* For PSR v2, the Sink device must be able to receive
664 * SU region updates early in the frame time.
665 */
666 psr_configuration.bits.EARLY_TRANSPORT_ENABLE = 1;
667 }
668
669 dm_helpers_dp_write_dpcd(
670 link->ctx,
671 link,
672 368,
673 &psr_configuration.raw,
674 sizeof(psr_configuration.raw));
675
676 if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
677 edp_power_alpm_dpcd_enable(link, true);
678 psr_context->su_granularity_required =
679 psr_config->su_granularity_required;
680 psr_context->su_y_granularity =
681 psr_config->su_y_granularity;
682 psr_context->line_time_in_us = psr_config->line_time_in_us;
683
684 /* linux must be able to expose AMD Source DPCD definition
685 * in order to support FreeSync PSR
686 */
687 if (link->psr_settings.psr_vtotal_control_support) {
688 psr_context->rate_control_caps = psr_config->rate_control_caps;
689 vtotal_control.bits.ENABLE = true;
690 core_link_write_dpcd(link, DP_SINK_PSR_ACTIVE_VTOTAL_CONTROL_MODE,
691 &vtotal_control.raw, sizeof(vtotal_control.raw));
692 }
693 }
694
695 psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
696 psr_context->transmitterId = link->link_enc->transmitter;
697 psr_context->engineId = link->link_enc->preferred_engine;
698
699 for (i = 0; i < MAX_PIPES; i++) {
700 if (dc->current_state->res_ctx.pipe_ctx[i].stream
701 == stream) {
702 /* dmcu -1 for all controller id values,
703 * therefore +1 here
704 */
705 psr_context->controllerId =
706 dc->current_state->res_ctx.
707 pipe_ctx[i].stream_res.tg->inst + 1;
708 break;
709 }
710 }
711
712 /* Hardcoded for now. Can be Pcie or Uniphy (or Unknown)*/
713 psr_context->phyType = PHY_TYPE_UNIPHY;
714 /*PhyId is associated with the transmitter id*/
715 psr_context->smuPhyId = transmitter_to_phy_id(link);
716
717 psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
718 psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->
719 timing.pix_clk_100hz * 100),
720 stream->timing.v_total),
721 stream->timing.h_total);
722
723 psr_context->psrSupportedDisplayConfig = true;
724 psr_context->psrExitLinkTrainingRequired =
725 psr_config->psr_exit_link_training_required;
726 psr_context->sdpTransmitLineNumDeadline =
727 psr_config->psr_sdp_transmit_line_num_deadline;
728 psr_context->psrFrameCaptureIndicationReq =
729 psr_config->psr_frame_capture_indication_req;
730
731 psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */
732
733 psr_context->numberOfControllers =
734 link->dc->res_pool->timing_generator_count;
735
736 psr_context->rfb_update_auto_en = true;
737
738 /* 2 frames before enter PSR. */
739 psr_context->timehyst_frames = 2;
740 /* half a frame
741 * (units in 100 lines, i.e. a value of 1 represents 100 lines)
742 */
743 psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
744 psr_context->aux_repeats = 10;
745
746 psr_context->psr_level.u32all = 0;
747
748 /*skip power down the single pipe since it blocks the cstate*/
749 if (link->ctx->asic_id.chip_family >= FAMILY_RV) {
750 switch (link->ctx->asic_id.chip_family) {
751 case FAMILY_YELLOW_CARP:
752 case AMDGPU_FAMILY_GC_10_3_6:
753 case AMDGPU_FAMILY_GC_11_0_1:
754 if (dc->debug.disable_z10 || dc->debug.psr_skip_crtc_disable)
755 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
756 break;
757 default:
758 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
759 break;
760 }
761 }
762
763 /* SMU will perform additional powerdown sequence.
764 * For unsupported ASICs, set psr_level flag to skip PSR
765 * static screen notification to SMU.
766 * (Always set for DAL2, did not check ASIC)
767 */
768 psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
769 psr_context->allow_multi_disp_optimizations = psr_config->allow_multi_disp_optimizations;
770
771 /* Complete PSR entry before aborting to prevent intermittent
772 * freezes on certain eDPs
773 */
774 psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
775
776 /* Disable ALPM first for compatible non-ALPM panel now */
777 psr_context->psr_level.bits.DISABLE_ALPM = 0;
778 psr_context->psr_level.bits.ALPM_DEFAULT_PD_MODE = 1;
779
780 /* Controls additional delay after remote frame capture before
781 * continuing power down, default = 0
782 */
783 psr_context->frame_delay = 0;
784
785 psr_context->dsc_slice_height = psr_config->dsc_slice_height;
786
787 if (psr) {
788 link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr,
789 link, psr_context, panel_inst);
790 link->psr_settings.psr_power_opt = 0;
791 link->psr_settings.psr_allow_active = 0;
792 } else {
793 link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
794 }
795
796 /* psr_enabled == 0 indicates setup_psr did not succeed, but this
797 * should not happen since firmware should be running at this point
798 */
799 if (link->psr_settings.psr_feature_enabled == 0)
800 ASSERT(0);
801
802 return true;
803
804 }
805
edp_get_psr_residency(const struct dc_link * link,uint32_t * residency)806 void edp_get_psr_residency(const struct dc_link *link, uint32_t *residency)
807 {
808 struct dc *dc = link->ctx->dc;
809 struct dmub_psr *psr = dc->res_pool->psr;
810 unsigned int panel_inst;
811
812 if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
813 return;
814
815 // PSR residency measurements only supported on DMCUB
816 if (psr != NULL && link->psr_settings.psr_feature_enabled)
817 psr->funcs->psr_get_residency(psr, residency, panel_inst);
818 else
819 *residency = 0;
820 }
edp_set_sink_vtotal_in_psr_active(const struct dc_link * link,uint16_t psr_vtotal_idle,uint16_t psr_vtotal_su)821 bool edp_set_sink_vtotal_in_psr_active(const struct dc_link *link, uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su)
822 {
823 struct dc *dc = link->ctx->dc;
824 struct dmub_psr *psr = dc->res_pool->psr;
825
826 if (psr == NULL || !link->psr_settings.psr_feature_enabled || !link->psr_settings.psr_vtotal_control_support)
827 return false;
828
829 psr->funcs->psr_set_sink_vtotal_in_psr_active(psr, psr_vtotal_idle, psr_vtotal_su);
830
831 return true;
832 }
833
edp_set_replay_allow_active(struct dc_link * link,const bool * allow_active,bool wait,bool force_static,const unsigned int * power_opts)834 bool edp_set_replay_allow_active(struct dc_link *link, const bool *allow_active,
835 bool wait, bool force_static, const unsigned int *power_opts)
836 {
837 struct dc *dc = link->ctx->dc;
838 struct dmub_replay *replay = dc->res_pool->replay;
839 unsigned int panel_inst;
840
841 if (replay == NULL && force_static)
842 return false;
843
844 if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
845 return false;
846
847 /* Set power optimization flag */
848 if (power_opts && link->replay_settings.replay_power_opt_active != *power_opts) {
849 if (link->replay_settings.replay_feature_enabled && replay->funcs->replay_set_power_opt) {
850 replay->funcs->replay_set_power_opt(replay, *power_opts, panel_inst);
851 link->replay_settings.replay_power_opt_active = *power_opts;
852 }
853 }
854
855 /* Activate or deactivate Replay */
856 if (allow_active && link->replay_settings.replay_allow_active != *allow_active) {
857 // TODO: Handle mux change case if force_static is set
858 // If force_static is set, just change the replay_allow_active state directly
859 if (replay != NULL && link->replay_settings.replay_feature_enabled)
860 replay->funcs->replay_enable(replay, *allow_active, wait, panel_inst);
861 link->replay_settings.replay_allow_active = *allow_active;
862 }
863
864 return true;
865 }
866
edp_get_replay_state(const struct dc_link * link,uint64_t * state)867 bool edp_get_replay_state(const struct dc_link *link, uint64_t *state)
868 {
869 struct dc *dc = link->ctx->dc;
870 struct dmub_replay *replay = dc->res_pool->replay;
871 unsigned int panel_inst;
872 enum replay_state pr_state = REPLAY_STATE_0;
873
874 if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
875 return false;
876
877 if (replay != NULL && link->replay_settings.replay_feature_enabled)
878 replay->funcs->replay_get_state(replay, &pr_state, panel_inst);
879 *state = pr_state;
880
881 return true;
882 }
883
edp_setup_replay(struct dc_link * link,const struct dc_stream_state * stream)884 bool edp_setup_replay(struct dc_link *link, const struct dc_stream_state *stream)
885 {
886 /* To-do: Setup Replay */
887 struct dc *dc = link->ctx->dc;
888 struct dmub_replay *replay = dc->res_pool->replay;
889 int i;
890 unsigned int panel_inst;
891 struct replay_context replay_context = { 0 };
892 unsigned int lineTimeInNs = 0;
893
894
895 union replay_enable_and_configuration replay_config;
896
897 union dpcd_alpm_configuration alpm_config;
898
899 replay_context.controllerId = CONTROLLER_ID_UNDEFINED;
900
901 if (!link)
902 return false;
903
904 if (!replay)
905 return false;
906
907 if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
908 return false;
909
910 replay_context.aux_inst = link->ddc->ddc_pin->hw_info.ddc_channel;
911 replay_context.digbe_inst = link->link_enc->transmitter;
912 replay_context.digfe_inst = link->link_enc->preferred_engine;
913
914 for (i = 0; i < MAX_PIPES; i++) {
915 if (dc->current_state->res_ctx.pipe_ctx[i].stream
916 == stream) {
917 /* dmcu -1 for all controller id values,
918 * therefore +1 here
919 */
920 replay_context.controllerId =
921 dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst + 1;
922 break;
923 }
924 }
925
926 lineTimeInNs =
927 ((stream->timing.h_total * 1000000) /
928 (stream->timing.pix_clk_100hz / 10)) + 1;
929
930 replay_context.line_time_in_ns = lineTimeInNs;
931
932 if (replay)
933 link->replay_settings.replay_feature_enabled =
934 replay->funcs->replay_copy_settings(replay, link, &replay_context, panel_inst);
935 if (link->replay_settings.replay_feature_enabled) {
936
937 replay_config.bits.FREESYNC_PANEL_REPLAY_MODE = 1;
938 replay_config.bits.TIMING_DESYNC_ERROR_VERIFICATION =
939 link->replay_settings.config.replay_timing_sync_supported;
940 replay_config.bits.STATE_TRANSITION_ERROR_DETECTION = 1;
941 dm_helpers_dp_write_dpcd(link->ctx, link,
942 DP_SINK_PR_ENABLE_AND_CONFIGURATION,
943 (uint8_t *)&(replay_config.raw), sizeof(uint8_t));
944
945 memset(&alpm_config, 0, sizeof(alpm_config));
946 alpm_config.bits.ENABLE = 1;
947 dm_helpers_dp_write_dpcd(
948 link->ctx,
949 link,
950 DP_RECEIVER_ALPM_CONFIG,
951 &alpm_config.raw,
952 sizeof(alpm_config.raw));
953 }
954 return true;
955 }
956
edp_set_coasting_vtotal(struct dc_link * link,uint16_t coasting_vtotal)957 bool edp_set_coasting_vtotal(struct dc_link *link, uint16_t coasting_vtotal)
958 {
959 struct dc *dc = link->ctx->dc;
960 struct dmub_replay *replay = dc->res_pool->replay;
961 unsigned int panel_inst;
962
963 if (!replay)
964 return false;
965
966 if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
967 return false;
968
969 if (coasting_vtotal && link->replay_settings.coasting_vtotal != coasting_vtotal) {
970 replay->funcs->replay_set_coasting_vtotal(replay, coasting_vtotal, panel_inst);
971 link->replay_settings.coasting_vtotal = coasting_vtotal;
972 }
973
974 return true;
975 }
976
edp_replay_residency(const struct dc_link * link,unsigned int * residency,const bool is_start,const bool is_alpm)977 bool edp_replay_residency(const struct dc_link *link,
978 unsigned int *residency, const bool is_start, const bool is_alpm)
979 {
980 struct dc *dc = link->ctx->dc;
981 struct dmub_replay *replay = dc->res_pool->replay;
982 unsigned int panel_inst;
983
984 if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
985 return false;
986
987 if (replay != NULL && link->replay_settings.replay_feature_enabled)
988 replay->funcs->replay_residency(replay, panel_inst, residency, is_start, is_alpm);
989 else
990 *residency = 0;
991
992 return true;
993 }
994
get_abm_from_stream_res(const struct dc_link * link)995 static struct abm *get_abm_from_stream_res(const struct dc_link *link)
996 {
997 int i;
998 struct dc *dc = link->ctx->dc;
999 struct abm *abm = NULL;
1000
1001 for (i = 0; i < MAX_PIPES; i++) {
1002 struct pipe_ctx pipe_ctx = dc->current_state->res_ctx.pipe_ctx[i];
1003 struct dc_stream_state *stream = pipe_ctx.stream;
1004
1005 if (stream && stream->link == link) {
1006 abm = pipe_ctx.stream_res.abm;
1007 break;
1008 }
1009 }
1010 return abm;
1011 }
1012
edp_get_backlight_level(const struct dc_link * link)1013 int edp_get_backlight_level(const struct dc_link *link)
1014 {
1015 struct abm *abm = get_abm_from_stream_res(link);
1016 struct panel_cntl *panel_cntl = link->panel_cntl;
1017 struct dc *dc = link->ctx->dc;
1018 struct dmcu *dmcu = dc->res_pool->dmcu;
1019 bool fw_set_brightness = true;
1020
1021 if (dmcu)
1022 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
1023
1024 if (!fw_set_brightness && panel_cntl->funcs->get_current_backlight)
1025 return panel_cntl->funcs->get_current_backlight(panel_cntl);
1026 else if (abm != NULL && abm->funcs->get_current_backlight != NULL)
1027 return (int) abm->funcs->get_current_backlight(abm);
1028 else
1029 return DC_ERROR_UNEXPECTED;
1030 }
1031
edp_get_target_backlight_pwm(const struct dc_link * link)1032 int edp_get_target_backlight_pwm(const struct dc_link *link)
1033 {
1034 struct abm *abm = get_abm_from_stream_res(link);
1035
1036 if (abm == NULL || abm->funcs->get_target_backlight == NULL)
1037 return DC_ERROR_UNEXPECTED;
1038
1039 return (int) abm->funcs->get_target_backlight(abm);
1040 }
1041
