1 /*
2 * 'traps.c' handles hardware traps and faults after we have saved some
3 * state in 'entry.S'.
4 *
5 * SuperH version: Copyright (C) 1999 Niibe Yutaka
6 * Copyright (C) 2000 Philipp Rumpf
7 * Copyright (C) 2000 David Howells
8 * Copyright (C) 2002 - 2010 Paul Mundt
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details.
13 */
14 #include <linux/kernel.h>
15 #include <linux/ptrace.h>
16 #include <linux/hardirq.h>
17 #include <linux/init.h>
18 #include <linux/spinlock.h>
19 #include <linux/kallsyms.h>
20 #include <linux/io.h>
21 #include <linux/bug.h>
22 #include <linux/debug_locks.h>
23 #include <linux/kdebug.h>
24 #include <linux/limits.h>
25 #include <linux/sysfs.h>
26 #include <linux/uaccess.h>
27 #include <linux/perf_event.h>
28 #include <linux/sched/task_stack.h>
29
30 #include <asm/alignment.h>
31 #include <asm/fpu.h>
32 #include <asm/kprobes.h>
33 #include <asm/traps.h>
34 #include <asm/bl_bit.h>
35
36 #ifdef CONFIG_CPU_SH2
37 # define TRAP_RESERVED_INST 4
38 # define TRAP_ILLEGAL_SLOT_INST 6
39 # define TRAP_ADDRESS_ERROR 9
40 # ifdef CONFIG_CPU_SH2A
41 # define TRAP_UBC 12
42 # define TRAP_FPU_ERROR 13
43 # define TRAP_DIVZERO_ERROR 17
44 # define TRAP_DIVOVF_ERROR 18
45 # endif
46 #else
47 #define TRAP_RESERVED_INST 12
48 #define TRAP_ILLEGAL_SLOT_INST 13
49 #endif
50
sign_extend(unsigned int count,unsigned char * dst)51 static inline void sign_extend(unsigned int count, unsigned char *dst)
52 {
53 #ifdef __LITTLE_ENDIAN__
54 if ((count == 1) && dst[0] & 0x80) {
55 dst[1] = 0xff;
56 dst[2] = 0xff;
57 dst[3] = 0xff;
58 }
59 if ((count == 2) && dst[1] & 0x80) {
60 dst[2] = 0xff;
61 dst[3] = 0xff;
62 }
63 #else
64 if ((count == 1) && dst[3] & 0x80) {
65 dst[2] = 0xff;
66 dst[1] = 0xff;
67 dst[0] = 0xff;
68 }
69 if ((count == 2) && dst[2] & 0x80) {
70 dst[1] = 0xff;
71 dst[0] = 0xff;
72 }
73 #endif
74 }
75
76 static struct mem_access user_mem_access = {
77 copy_from_user,
78 copy_to_user,
79 };
80
81 /*
82 * handle an instruction that does an unaligned memory access by emulating the
83 * desired behaviour
84 * - note that PC _may not_ point to the faulting instruction
85 * (if that instruction is in a branch delay slot)
86 * - return 0 if emulation okay, -EFAULT on existential error
87 */
handle_unaligned_ins(insn_size_t instruction,struct pt_regs * regs,struct mem_access * ma)88 static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs,
89 struct mem_access *ma)
90 {
91 int ret, index, count;
92 unsigned long *rm, *rn;
93 unsigned char *src, *dst;
94 unsigned char __user *srcu, *dstu;
95
96 index = (instruction>>8)&15; /* 0x0F00 */
97 rn = ®s->regs[index];
98
99 index = (instruction>>4)&15; /* 0x00F0 */
100 rm = ®s->regs[index];
101
102 count = 1<<(instruction&3);
103
104 switch (count) {
105 case 1: inc_unaligned_byte_access(); break;
106 case 2: inc_unaligned_word_access(); break;
107 case 4: inc_unaligned_dword_access(); break;
108 case 8: inc_unaligned_multi_access(); break;
109 }
110
111 ret = -EFAULT;
112 switch (instruction>>12) {
113 case 0: /* mov.[bwl] to/from memory via r0+rn */
114 if (instruction & 8) {
115 /* from memory */
116 srcu = (unsigned char __user *)*rm;
117 srcu += regs->regs[0];
118 dst = (unsigned char *)rn;
119 *(unsigned long *)dst = 0;
120
121 #if !defined(__LITTLE_ENDIAN__)
122 dst += 4-count;
123 #endif
124 if (ma->from(dst, srcu, count))
125 goto fetch_fault;
126
127 sign_extend(count, dst);
128 } else {
129 /* to memory */
130 src = (unsigned char *)rm;
131 #if !defined(__LITTLE_ENDIAN__)
132 src += 4-count;
133 #endif
134 dstu = (unsigned char __user *)*rn;
135 dstu += regs->regs[0];
136
137 if (ma->to(dstu, src, count))
138 goto fetch_fault;
139 }
140 ret = 0;
141 break;
142
143 case 1: /* mov.l Rm,@(disp,Rn) */
144 src = (unsigned char*) rm;
145 dstu = (unsigned char __user *)*rn;
146 dstu += (instruction&0x000F)<<2;
147
148 if (ma->to(dstu, src, 4))
149 goto fetch_fault;
150 ret = 0;
151 break;
152
153 case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
154 if (instruction & 4)
155 *rn -= count;
156 src = (unsigned char*) rm;
157 dstu = (unsigned char __user *)*rn;
158 #if !defined(__LITTLE_ENDIAN__)
159 src += 4-count;
160 #endif
161 if (ma->to(dstu, src, count))
162 goto fetch_fault;
163 ret = 0;
164 break;
165
166 case 5: /* mov.l @(disp,Rm),Rn */
167 srcu = (unsigned char __user *)*rm;
168 srcu += (instruction & 0x000F) << 2;
169 dst = (unsigned char *)rn;
170 *(unsigned long *)dst = 0;
171
172 if (ma->from(dst, srcu, 4))
173 goto fetch_fault;
174 ret = 0;
175 break;
176
177 case 6: /* mov.[bwl] from memory, possibly with post-increment */
178 srcu = (unsigned char __user *)*rm;
179 if (instruction & 4)
180 *rm += count;
181 dst = (unsigned char*) rn;
182 *(unsigned long*)dst = 0;
183
184 #if !defined(__LITTLE_ENDIAN__)
185 dst += 4-count;
186 #endif
187 if (ma->from(dst, srcu, count))
188 goto fetch_fault;
189 sign_extend(count, dst);
190 ret = 0;
191 break;
192
193 case 8:
194 switch ((instruction&0xFF00)>>8) {
195 case 0x81: /* mov.w R0,@(disp,Rn) */
196 src = (unsigned char *) ®s->regs[0];
197 #if !defined(__LITTLE_ENDIAN__)
198 src += 2;
199 #endif
200 dstu = (unsigned char __user *)*rm; /* called Rn in the spec */
201 dstu += (instruction & 0x000F) << 1;
202
203 if (ma->to(dstu, src, 2))
204 goto fetch_fault;
205 ret = 0;
206 break;
207
208 case 0x85: /* mov.w @(disp,Rm),R0 */
209 srcu = (unsigned char __user *)*rm;
210 srcu += (instruction & 0x000F) << 1;
211 dst = (unsigned char *) ®s->regs[0];
212 *(unsigned long *)dst = 0;
213
214 #if !defined(__LITTLE_ENDIAN__)
215 dst += 2;
216 #endif
217 if (ma->from(dst, srcu, 2))
218 goto fetch_fault;
219 sign_extend(2, dst);
220 ret = 0;
221 break;
222 }
223 break;
224
225 case 9: /* mov.w @(disp,PC),Rn */
226 srcu = (unsigned char __user *)regs->pc;
227 srcu += 4;
228 srcu += (instruction & 0x00FF) << 1;
229 dst = (unsigned char *)rn;
230 *(unsigned long *)dst = 0;
231
232 #if !defined(__LITTLE_ENDIAN__)
233 dst += 2;
234 #endif
235
236 if (ma->from(dst, srcu, 2))
237 goto fetch_fault;
238 sign_extend(2, dst);
239 ret = 0;
240 break;
241
242 case 0xd: /* mov.l @(disp,PC),Rn */
243 srcu = (unsigned char __user *)(regs->pc & ~0x3);
244 srcu += 4;
245 srcu += (instruction & 0x00FF) << 2;
246 dst = (unsigned char *)rn;
247 *(unsigned long *)dst = 0;
248
249 if (ma->from(dst, srcu, 4))
250 goto fetch_fault;
251 ret = 0;
252 break;
253 }
254 return ret;
255
256 fetch_fault:
257 /* Argh. Address not only misaligned but also non-existent.
258 * Raise an EFAULT and see if it's trapped
259 */
260 die_if_no_fixup("Fault in unaligned fixup", regs, 0);
261 return -EFAULT;
262 }
263
264 /*
265 * emulate the instruction in the delay slot
266 * - fetches the instruction from PC+2
267 */
handle_delayslot(struct pt_regs * regs,insn_size_t old_instruction,struct mem_access * ma)268 static inline int handle_delayslot(struct pt_regs *regs,
269 insn_size_t old_instruction,
270 struct mem_access *ma)
271 {
272 insn_size_t instruction;
273 void __user *addr = (void __user *)(regs->pc +
274 instruction_size(old_instruction));
275
276 if (copy_from_user(&instruction, addr, sizeof(instruction))) {
277 /* the instruction-fetch faulted */
278 if (user_mode(regs))
279 return -EFAULT;
280
281 /* kernel */
282 die("delay-slot-insn faulting in handle_unaligned_delayslot",
283 regs, 0);
284 }
285
286 return handle_unaligned_ins(instruction, regs, ma);
287 }
288
289 /*
290 * handle an instruction that does an unaligned memory access
291 * - have to be careful of branch delay-slot instructions that fault
292 * SH3:
293 * - if the branch would be taken PC points to the branch
294 * - if the branch would not be taken, PC points to delay-slot
295 * SH4:
296 * - PC always points to delayed branch
297 * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
298 */
299
300 /* Macros to determine offset from current PC for branch instructions */
301 /* Explicit type coercion is used to force sign extension where needed */
302 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
303 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
304
handle_unaligned_access(insn_size_t instruction,struct pt_regs * regs,struct mem_access * ma,int expected,unsigned long address)305 int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
306 struct mem_access *ma, int expected,
307 unsigned long address)
308 {
309 u_int rm;
310 int ret, index;
311
312 /*
313 * XXX: We can't handle mixed 16/32-bit instructions yet
314 */
315 if (instruction_size(instruction) != 2)
316 return -EINVAL;
317
318 index = (instruction>>8)&15; /* 0x0F00 */
319 rm = regs->regs[index];
320
321 /*
322 * Log the unexpected fixups, and then pass them on to perf.
323 *
324 * We intentionally don't report the expected cases to perf as
325 * otherwise the trapped I/O case will skew the results too much
326 * to be useful.
327 */
328 if (!expected) {
329 unaligned_fixups_notify(current, instruction, regs);
330 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1,
331 regs, address);
332 }
333
334 ret = -EFAULT;
335 switch (instruction&0xF000) {
336 case 0x0000:
337 if (instruction==0x000B) {
338 /* rts */
339 ret = handle_delayslot(regs, instruction, ma);
340 if (ret==0)
341 regs->pc = regs->pr;
342 }
343 else if ((instruction&0x00FF)==0x0023) {
344 /* braf @Rm */
345 ret = handle_delayslot(regs, instruction, ma);
346 if (ret==0)
347 regs->pc += rm + 4;
348 }
349 else if ((instruction&0x00FF)==0x0003) {
350 /* bsrf @Rm */
351 ret = handle_delayslot(regs, instruction, ma);
352 if (ret==0) {
353 regs->pr = regs->pc + 4;
354 regs->pc += rm + 4;
355 }
356 }
357 else {
358 /* mov.[bwl] to/from memory via r0+rn */
359 goto simple;
360 }
361 break;
362
363 case 0x1000: /* mov.l Rm,@(disp,Rn) */
364 goto simple;
365
366 case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
367 goto simple;
368
369 case 0x4000:
370 if ((instruction&0x00FF)==0x002B) {
371 /* jmp @Rm */
372 ret = handle_delayslot(regs, instruction, ma);
373 if (ret==0)
374 regs->pc = rm;
375 }
376 else if ((instruction&0x00FF)==0x000B) {
377 /* jsr @Rm */
378 ret = handle_delayslot(regs, instruction, ma);
379 if (ret==0) {
380 regs->pr = regs->pc + 4;
381 regs->pc = rm;
382 }
383 }
384 else {
385 /* mov.[bwl] to/from memory via r0+rn */
386 goto simple;
387 }
388 break;
389
390 case 0x5000: /* mov.l @(disp,Rm),Rn */
391 goto simple;
392
393 case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
394 goto simple;
395
396 case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
397 switch (instruction&0x0F00) {
398 case 0x0100: /* mov.w R0,@(disp,Rm) */
399 goto simple;
400 case 0x0500: /* mov.w @(disp,Rm),R0 */
401 goto simple;
402 case 0x0B00: /* bf lab - no delayslot*/
403 ret = 0;
404 break;
405 case 0x0F00: /* bf/s lab */
406 ret = handle_delayslot(regs, instruction, ma);
407 if (ret==0) {
408 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
409 if ((regs->sr & 0x00000001) != 0)
410 regs->pc += 4; /* next after slot */
411 else
412 #endif
413 regs->pc += SH_PC_8BIT_OFFSET(instruction);
414 }
415 break;
416 case 0x0900: /* bt lab - no delayslot */
417 ret = 0;
418 break;
419 case 0x0D00: /* bt/s lab */
420 ret = handle_delayslot(regs, instruction, ma);
421 if (ret==0) {
422 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
423 if ((regs->sr & 0x00000001) == 0)
424 regs->pc += 4; /* next after slot */
425 else
426 #endif
427 regs->pc += SH_PC_8BIT_OFFSET(instruction);
428 }
429 break;
430 }
431 break;
432
433 case 0x9000: /* mov.w @(disp,Rm),Rn */
434 goto simple;
435
436 case 0xA000: /* bra label */
437 ret = handle_delayslot(regs, instruction, ma);
438 if (ret==0)
439 regs->pc += SH_PC_12BIT_OFFSET(instruction);
440 break;
441
442 case 0xB000: /* bsr label */
443 ret = handle_delayslot(regs, instruction, ma);
444 if (ret==0) {
445 regs->pr = regs->pc + 4;
446 regs->pc += SH_PC_12BIT_OFFSET(instruction);
447 }
448 break;
449
450 case 0xD000: /* mov.l @(disp,Rm),Rn */
451 goto simple;
452 }
453 return ret;
454
455 /* handle non-delay-slot instruction */
456 simple:
457 ret = handle_unaligned_ins(instruction, regs, ma);
458 if (ret==0)
459 regs->pc += instruction_size(instruction);
460 return ret;
461 }
462
463 /*
464 * Handle various address error exceptions:
465 * - instruction address error:
466 * misaligned PC
467 * PC >= 0x80000000 in user mode
468 * - data address error (read and write)
469 * misaligned data access
470 * access to >= 0x80000000 is user mode
471 * Unfortuntaly we can't distinguish between instruction address error
472 * and data address errors caused by read accesses.
473 */
do_address_error(struct pt_regs * regs,unsigned long writeaccess,unsigned long address)474 asmlinkage void do_address_error(struct pt_regs *regs,
475 unsigned long writeaccess,
476 unsigned long address)
477 {
478 unsigned long error_code = 0;
479 mm_segment_t oldfs;
480 insn_size_t instruction;
481 int tmp;
482
483 /* Intentional ifdef */
484 #ifdef CONFIG_CPU_HAS_SR_RB
485 error_code = lookup_exception_vector();
486 #endif
487
488 oldfs = get_fs();
489
490 if (user_mode(regs)) {
491 int si_code = BUS_ADRERR;
492 unsigned int user_action;
493
494 local_irq_enable();
495 inc_unaligned_user_access();
496
497 set_fs(USER_DS);
498 if (copy_from_user(&instruction, (insn_size_t *)(regs->pc & ~1),
499 sizeof(instruction))) {
500 set_fs(oldfs);
501 goto uspace_segv;
502 }
503 set_fs(oldfs);
504
505 /* shout about userspace fixups */
506 unaligned_fixups_notify(current, instruction, regs);
507
508 user_action = unaligned_user_action();
509 if (user_action & UM_FIXUP)
510 goto fixup;
511 if (user_action & UM_SIGNAL)
512 goto uspace_segv;
513 else {
514 /* ignore */
515 regs->pc += instruction_size(instruction);
516 return;
517 }
518
519 fixup:
520 /* bad PC is not something we can fix */
521 if (regs->pc & 1) {
522 si_code = BUS_ADRALN;
523 goto uspace_segv;
524 }
525
526 set_fs(USER_DS);
527 tmp = handle_unaligned_access(instruction, regs,
528 &user_mem_access, 0,
529 address);
530 set_fs(oldfs);
531
532 if (tmp == 0)
533 return; /* sorted */
534 uspace_segv:
535 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
536 "access (PC %lx PR %lx)\n", current->comm, regs->pc,
537 regs->pr);
538
539 force_sig_fault(SIGBUS, si_code, (void __user *)address, current);
540 } else {
541 inc_unaligned_kernel_access();
542
543 if (regs->pc & 1)
544 die("unaligned program counter", regs, error_code);
545
546 set_fs(KERNEL_DS);
547 if (copy_from_user(&instruction, (void __user *)(regs->pc),
548 sizeof(instruction))) {
549 /* Argh. Fault on the instruction itself.
550 This should never happen non-SMP
551 */
552 set_fs(oldfs);
553 die("insn faulting in do_address_error", regs, 0);
554 }
555
556 unaligned_fixups_notify(current, instruction, regs);
557
558 handle_unaligned_access(instruction, regs, &user_mem_access,
559 0, address);
560 set_fs(oldfs);
561 }
562 }
563
564 #ifdef CONFIG_SH_DSP
565 /*
566 * SH-DSP support gerg@snapgear.com.
567 */
is_dsp_inst(struct pt_regs * regs)568 int is_dsp_inst(struct pt_regs *regs)
569 {
570 unsigned short inst = 0;
571
572 /*
573 * Safe guard if DSP mode is already enabled or we're lacking
574 * the DSP altogether.
575 */
576 if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
577 return 0;
578
579 get_user(inst, ((unsigned short *) regs->pc));
580
581 inst &= 0xf000;
582
583 /* Check for any type of DSP or support instruction */
584 if ((inst == 0xf000) || (inst == 0x4000))
585 return 1;
586
587 return 0;
588 }
589 #else
590 #define is_dsp_inst(regs) (0)
591 #endif /* CONFIG_SH_DSP */
592
593 #ifdef CONFIG_CPU_SH2A
do_divide_error(unsigned long r4)594 asmlinkage void do_divide_error(unsigned long r4)
595 {
596 int code;
597
598 switch (r4) {
599 case TRAP_DIVZERO_ERROR:
600 code = FPE_INTDIV;
601 break;
602 case TRAP_DIVOVF_ERROR:
603 code = FPE_INTOVF;
604 break;
605 default:
606 /* Let gcc know unhandled cases don't make it past here */
607 return;
608 }
609 force_sig_fault(SIGFPE, code, NULL, current);
610 }
611 #endif
612
do_reserved_inst(void)613 asmlinkage void do_reserved_inst(void)
614 {
615 struct pt_regs *regs = current_pt_regs();
616 unsigned long error_code;
617 struct task_struct *tsk = current;
618
619 #ifdef CONFIG_SH_FPU_EMU
620 unsigned short inst = 0;
621 int err;
622
623 get_user(inst, (unsigned short*)regs->pc);
624
625 err = do_fpu_inst(inst, regs);
626 if (!err) {
627 regs->pc += instruction_size(inst);
628 return;
629 }
630 /* not a FPU inst. */
631 #endif
632
633 #ifdef CONFIG_SH_DSP
634 /* Check if it's a DSP instruction */
635 if (is_dsp_inst(regs)) {
636 /* Enable DSP mode, and restart instruction. */
637 regs->sr |= SR_DSP;
638 /* Save DSP mode */
639 tsk->thread.dsp_status.status |= SR_DSP;
640 return;
641 }
642 #endif
643
644 error_code = lookup_exception_vector();
645
646 local_irq_enable();
647 force_sig(SIGILL, tsk);
648 die_if_no_fixup("reserved instruction", regs, error_code);
649 }
650
651 #ifdef CONFIG_SH_FPU_EMU
emulate_branch(unsigned short inst,struct pt_regs * regs)652 static int emulate_branch(unsigned short inst, struct pt_regs *regs)
653 {
654 /*
655 * bfs: 8fxx: PC+=d*2+4;
656 * bts: 8dxx: PC+=d*2+4;
657 * bra: axxx: PC+=D*2+4;
658 * bsr: bxxx: PC+=D*2+4 after PR=PC+4;
659 * braf:0x23: PC+=Rn*2+4;
660 * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
661 * jmp: 4x2b: PC=Rn;
662 * jsr: 4x0b: PC=Rn after PR=PC+4;
663 * rts: 000b: PC=PR;
664 */
665 if (((inst & 0xf000) == 0xb000) || /* bsr */
666 ((inst & 0xf0ff) == 0x0003) || /* bsrf */
667 ((inst & 0xf0ff) == 0x400b)) /* jsr */
668 regs->pr = regs->pc + 4;
669
670 if ((inst & 0xfd00) == 0x8d00) { /* bfs, bts */
671 regs->pc += SH_PC_8BIT_OFFSET(inst);
672 return 0;
673 }
674
675 if ((inst & 0xe000) == 0xa000) { /* bra, bsr */
676 regs->pc += SH_PC_12BIT_OFFSET(inst);
677 return 0;
678 }
679
680 if ((inst & 0xf0df) == 0x0003) { /* braf, bsrf */
681 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
682 return 0;
683 }
684
685 if ((inst & 0xf0df) == 0x400b) { /* jmp, jsr */
686 regs->pc = regs->regs[(inst & 0x0f00) >> 8];
687 return 0;
688 }
689
690 if ((inst & 0xffff) == 0x000b) { /* rts */
691 regs->pc = regs->pr;
692 return 0;
693 }
694
695 return 1;
696 }
697 #endif
698
do_illegal_slot_inst(void)699 asmlinkage void do_illegal_slot_inst(void)
700 {
701 struct pt_regs *regs = current_pt_regs();
702 unsigned long inst;
703 struct task_struct *tsk = current;
704
705 if (kprobe_handle_illslot(regs->pc) == 0)
706 return;
707
708 #ifdef CONFIG_SH_FPU_EMU
709 get_user(inst, (unsigned short *)regs->pc + 1);
710 if (!do_fpu_inst(inst, regs)) {
711 get_user(inst, (unsigned short *)regs->pc);
712 if (!emulate_branch(inst, regs))
713 return;
714 /* fault in branch.*/
715 }
716 /* not a FPU inst. */
717 #endif
718
719 inst = lookup_exception_vector();
720
721 local_irq_enable();
722 force_sig(SIGILL, tsk);
723 die_if_no_fixup("illegal slot instruction", regs, inst);
724 }
725
do_exception_error(void)726 asmlinkage void do_exception_error(void)
727 {
728 long ex;
729
730 ex = lookup_exception_vector();
731 die_if_kernel("exception", current_pt_regs(), ex);
732 }
733
per_cpu_trap_init(void)734 void per_cpu_trap_init(void)
735 {
736 extern void *vbr_base;
737
738 /* NOTE: The VBR value should be at P1
739 (or P2, virtural "fixed" address space).
740 It's definitely should not in physical address. */
741
742 asm volatile("ldc %0, vbr"
743 : /* no output */
744 : "r" (&vbr_base)
745 : "memory");
746
747 /* disable exception blocking now when the vbr has been setup */
748 clear_bl_bit();
749 }
750
set_exception_table_vec(unsigned int vec,void * handler)751 void *set_exception_table_vec(unsigned int vec, void *handler)
752 {
753 extern void *exception_handling_table[];
754 void *old_handler;
755
756 old_handler = exception_handling_table[vec];
757 exception_handling_table[vec] = handler;
758 return old_handler;
759 }
760
trap_init(void)761 void __init trap_init(void)
762 {
763 set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
764 set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
765
766 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
767 defined(CONFIG_SH_FPU_EMU)
768 /*
769 * For SH-4 lacking an FPU, treat floating point instructions as
770 * reserved. They'll be handled in the math-emu case, or faulted on
771 * otherwise.
772 */
773 set_exception_table_evt(0x800, do_reserved_inst);
774 set_exception_table_evt(0x820, do_illegal_slot_inst);
775 #elif defined(CONFIG_SH_FPU)
776 set_exception_table_evt(0x800, fpu_state_restore_trap_handler);
777 set_exception_table_evt(0x820, fpu_state_restore_trap_handler);
778 #endif
779
780 #ifdef CONFIG_CPU_SH2
781 set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);
782 #endif
783 #ifdef CONFIG_CPU_SH2A
784 set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
785 set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
786 #ifdef CONFIG_SH_FPU
787 set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler);
788 #endif
789 #endif
790
791 #ifdef TRAP_UBC
792 set_exception_table_vec(TRAP_UBC, breakpoint_trap_handler);
793 #endif
794 }
795
