1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_CLK_MGR_H__ 27 #define __DAL_CLK_MGR_H__ 28 29 #include "dc.h" 30 #include "dm_pp_smu.h" 31 32 #define DCN_MINIMUM_DISPCLK_Khz 100000 33 #define DCN_MINIMUM_DPPCLK_Khz 100000 34 35 /* Constants */ 36 #define DDR4_DRAM_WIDTH 64 37 #define WM_A 0 38 #define WM_B 1 39 #define WM_C 2 40 #define WM_D 3 41 #define WM_SET_COUNT 4 42 43 #define DCN_MINIMUM_DISPCLK_Khz 100000 44 #define DCN_MINIMUM_DPPCLK_Khz 100000 45 46 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 47 struct dcn3_clk_internal { 48 int dummy; 49 /*TODO: 50 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk 51 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk 52 uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk 53 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk 54 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider 55 uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow 56 57 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass 58 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass 59 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass 60 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass 61 */ 62 }; 63 64 #endif 65 /* Will these bw structures be ASIC specific? */ 66 67 #define MAX_NUM_DPM_LVL 8 68 #define WM_SET_COUNT 4 69 70 71 struct clk_limit_table_entry { 72 unsigned int voltage; /* milivolts withh 2 fractional bits */ 73 unsigned int dcfclk_mhz; 74 unsigned int fclk_mhz; 75 unsigned int memclk_mhz; 76 unsigned int socclk_mhz; 77 #ifdef CONFIG_DRM_AMD_DC_DCN3_0 78 unsigned int dtbclk_mhz; 79 unsigned int dispclk_mhz; 80 unsigned int dppclk_mhz; 81 unsigned int phyclk_mhz; 82 #endif 83 }; 84 85 /* This table is contiguous */ 86 struct clk_limit_table { 87 struct clk_limit_table_entry entries[MAX_NUM_DPM_LVL]; 88 unsigned int num_entries; 89 }; 90 91 struct wm_range_table_entry { 92 unsigned int wm_inst; 93 unsigned int wm_type; 94 double pstate_latency_us; 95 double sr_exit_time_us; 96 double sr_enter_plus_exit_time_us; 97 bool valid; 98 }; 99 100 #ifdef CONFIG_DRM_AMD_DC_DCN3_0 101 102 struct nv_wm_range_entry { 103 bool valid; 104 105 struct { 106 uint8_t wm_type; 107 uint16_t min_dcfclk; 108 uint16_t max_dcfclk; 109 uint16_t min_uclk; 110 uint16_t max_uclk; 111 } pmfw_breakdown; 112 113 struct { 114 double pstate_latency_us; 115 double sr_exit_time_us; 116 double sr_enter_plus_exit_time_us; 117 } dml_input; 118 }; 119 #endif 120 121 struct clk_log_info { 122 bool enabled; 123 char *pBuf; 124 unsigned int bufSize; 125 unsigned int *sum_chars_printed; 126 }; 127 128 struct clk_state_registers_and_bypass { 129 uint32_t dcfclk; 130 uint32_t dcf_deep_sleep_divider; 131 uint32_t dcf_deep_sleep_allow; 132 uint32_t dprefclk; 133 uint32_t dispclk; 134 uint32_t dppclk; 135 136 uint32_t dppclk_bypass; 137 uint32_t dcfclk_bypass; 138 uint32_t dprefclk_bypass; 139 uint32_t dispclk_bypass; 140 }; 141 142 struct rv1_clk_internal { 143 uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk 144 uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider 145 uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow 146 uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk 147 uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk 148 149 uint32_t CLK0_CLK8_BYPASS_CNTL; //dcfclk bypass 150 uint32_t CLK0_CLK10_BYPASS_CNTL; //dprefclk bypass 151 uint32_t CLK0_CLK11_BYPASS_CNTL; //dispclk bypass 152 }; 153 154 struct rn_clk_internal { 155 uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk 156 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk 157 uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk 158 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk 159 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider 160 uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow 161 162 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass 163 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass 164 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass 165 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass 166 167 }; 168 169 /* For dtn logging and debugging */ 170 struct clk_state_registers { 171 uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk 172 uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider 173 uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow 174 uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk 175 uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk 176 }; 177 178 /* TODO: combine this with the above */ 179 struct clk_bypass { 180 uint32_t dcfclk_bypass; 181 uint32_t dispclk_pypass; 182 uint32_t dprefclk_bypass; 183 }; 184 /* 185 * This table is not contiguous, can have holes, each 186 * entry correspond to one set of WM. For example if 187 * we have 2 DPM and LPDDR, we will WM set A, B and 188 * D occupied, C will be emptry. 189 */ 190 struct wm_table { 191 #ifdef CONFIG_DRM_AMD_DC_DCN3_0 192 union { 193 struct nv_wm_range_entry nv_entries[WM_SET_COUNT]; 194 #endif 195 struct wm_range_table_entry entries[WM_SET_COUNT]; 196 #ifdef CONFIG_DRM_AMD_DC_DCN3_0 197 }; 198 #endif 199 }; 200 201 struct dummy_pstate_entry { 202 unsigned int dram_speed_mts; 203 unsigned int dummy_pstate_latency_us; 204 }; 205 206 struct clk_bw_params { 207 unsigned int vram_type; 208 unsigned int num_channels; 209 struct clk_limit_table clk_table; 210 struct wm_table wm_table; 211 struct dummy_pstate_entry dummy_pstate_table[4]; 212 }; 213 /* Public interfaces */ 214 215 struct clk_states { 216 uint32_t dprefclk_khz; 217 }; 218 219 struct clk_mgr_funcs { 220 /* 221 * This function should set new clocks based on the input "safe_to_lower". 222 * If safe_to_lower == false, then only clocks which are to be increased 223 * should changed. 224 * If safe_to_lower == true, then only clocks which are to be decreased 225 * should be changed. 226 */ 227 void (*update_clocks)(struct clk_mgr *clk_mgr, 228 struct dc_state *context, 229 bool safe_to_lower); 230 231 int (*get_dp_ref_clk_frequency)(struct clk_mgr *clk_mgr); 232 233 void (*set_low_power_state)(struct clk_mgr *clk_mgr); 234 235 void (*init_clocks)(struct clk_mgr *clk_mgr); 236 237 void (*enable_pme_wa) (struct clk_mgr *clk_mgr); 238 void (*get_clock)(struct clk_mgr *clk_mgr, 239 struct dc_state *context, 240 enum dc_clock_type clock_type, 241 struct dc_clock_config *clock_cfg); 242 243 bool (*are_clock_states_equal) (struct dc_clocks *a, 244 struct dc_clocks *b); 245 void (*notify_wm_ranges)(struct clk_mgr *clk_mgr); 246 247 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */ 248 void (*notify_link_rate_change)(struct clk_mgr *clk_mgr, struct dc_link *link); 249 #ifdef CONFIG_DRM_AMD_DC_DCN3_0 250 /* 251 * Send message to PMFW to set hard min memclk frequency 252 * When current_mode = false, set DPM0 253 * When current_mode = true, set required clock for current mode 254 */ 255 void (*set_hard_min_memclk)(struct clk_mgr *clk_mgr, bool current_mode); 256 257 /* Send message to PMFW to set hard max memclk frequency to highest DPM */ 258 void (*set_hard_max_memclk)(struct clk_mgr *clk_mgr); 259 260 /* Get current memclk states from PMFW, update relevant structures */ 261 void (*get_memclk_states_from_smu)(struct clk_mgr *clk_mgr); 262 #endif 263 }; 264 265 struct clk_mgr { 266 struct dc_context *ctx; 267 struct clk_mgr_funcs *funcs; 268 struct dc_clocks clks; 269 bool psr_allow_active_cache; 270 #ifdef CONFIG_DRM_AMD_DC_DCN3_0 271 bool force_smu_not_present; 272 #endif 273 int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes 274 int dentist_vco_freq_khz; 275 struct clk_state_registers_and_bypass boot_snapshot; 276 struct clk_bw_params *bw_params; 277 struct pp_smu_wm_range_sets ranges; 278 }; 279 280 /* forward declarations */ 281 struct dccg; 282 283 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg); 284 285 void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr); 286 287 void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr); 288 289 void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr); 290 291 #endif /* __DAL_CLK_MGR_H__ */ 292
