1 /*
2 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
3 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 */
15 #ifndef __IPU_PRV_H__
16 #define __IPU_PRV_H__
17
18 struct ipu_soc;
19
20 #include <linux/types.h>
21 #include <linux/device.h>
22 #include <linux/clk.h>
23 #include <linux/platform_device.h>
24
25 #include <video/imx-ipu-v3.h>
26
27 #define IPU_MCU_T_DEFAULT 8
28 #define IPU_CM_IDMAC_REG_OFS 0x00008000
29 #define IPU_CM_IC_REG_OFS 0x00020000
30 #define IPU_CM_IRT_REG_OFS 0x00028000
31 #define IPU_CM_CSI0_REG_OFS 0x00030000
32 #define IPU_CM_CSI1_REG_OFS 0x00038000
33 #define IPU_CM_SMFC_REG_OFS 0x00050000
34 #define IPU_CM_DC_REG_OFS 0x00058000
35 #define IPU_CM_DMFC_REG_OFS 0x00060000
36
37 /* Register addresses */
38 /* IPU Common registers */
39 #define IPU_CM_REG(offset) (offset)
40
41 #define IPU_CONF IPU_CM_REG(0)
42
43 #define IPU_SRM_PRI1 IPU_CM_REG(0x00a0)
44 #define IPU_SRM_PRI2 IPU_CM_REG(0x00a4)
45 #define IPU_FS_PROC_FLOW1 IPU_CM_REG(0x00a8)
46 #define IPU_FS_PROC_FLOW2 IPU_CM_REG(0x00ac)
47 #define IPU_FS_PROC_FLOW3 IPU_CM_REG(0x00b0)
48 #define IPU_FS_DISP_FLOW1 IPU_CM_REG(0x00b4)
49 #define IPU_FS_DISP_FLOW2 IPU_CM_REG(0x00b8)
50 #define IPU_SKIP IPU_CM_REG(0x00bc)
51 #define IPU_DISP_ALT_CONF IPU_CM_REG(0x00c0)
52 #define IPU_DISP_GEN IPU_CM_REG(0x00c4)
53 #define IPU_DISP_ALT1 IPU_CM_REG(0x00c8)
54 #define IPU_DISP_ALT2 IPU_CM_REG(0x00cc)
55 #define IPU_DISP_ALT3 IPU_CM_REG(0x00d0)
56 #define IPU_DISP_ALT4 IPU_CM_REG(0x00d4)
57 #define IPU_SNOOP IPU_CM_REG(0x00d8)
58 #define IPU_MEM_RST IPU_CM_REG(0x00dc)
59 #define IPU_PM IPU_CM_REG(0x00e0)
60 #define IPU_GPR IPU_CM_REG(0x00e4)
61 #define IPU_CHA_DB_MODE_SEL(ch) IPU_CM_REG(0x0150 + 4 * ((ch) / 32))
62 #define IPU_ALT_CHA_DB_MODE_SEL(ch) IPU_CM_REG(0x0168 + 4 * ((ch) / 32))
63 #define IPU_CHA_CUR_BUF(ch) IPU_CM_REG(0x023C + 4 * ((ch) / 32))
64 #define IPU_ALT_CUR_BUF0 IPU_CM_REG(0x0244)
65 #define IPU_ALT_CUR_BUF1 IPU_CM_REG(0x0248)
66 #define IPU_SRM_STAT IPU_CM_REG(0x024C)
67 #define IPU_PROC_TASK_STAT IPU_CM_REG(0x0250)
68 #define IPU_DISP_TASK_STAT IPU_CM_REG(0x0254)
69 #define IPU_CHA_BUF0_RDY(ch) IPU_CM_REG(0x0268 + 4 * ((ch) / 32))
70 #define IPU_CHA_BUF1_RDY(ch) IPU_CM_REG(0x0270 + 4 * ((ch) / 32))
71 #define IPU_CHA_BUF2_RDY(ch) IPU_CM_REG(0x0288 + 4 * ((ch) / 32))
72 #define IPU_ALT_CHA_BUF0_RDY(ch) IPU_CM_REG(0x0278 + 4 * ((ch) / 32))
73 #define IPU_ALT_CHA_BUF1_RDY(ch) IPU_CM_REG(0x0280 + 4 * ((ch) / 32))
74
75 #define IPU_INT_CTRL(n) IPU_CM_REG(0x003C + 4 * (n))
76 #define IPU_INT_STAT(n) IPU_CM_REG(0x0200 + 4 * (n))
77
78 /* SRM_PRI2 */
79 #define DP_S_SRM_MODE_MASK (0x3 << 3)
80 #define DP_S_SRM_MODE_NOW (0x3 << 3)
81 #define DP_S_SRM_MODE_NEXT_FRAME (0x1 << 3)
82
83 /* FS_PROC_FLOW1 */
84 #define FS_PRPENC_ROT_SRC_SEL_MASK (0xf << 0)
85 #define FS_PRPENC_ROT_SRC_SEL_ENC (0x7 << 0)
86 #define FS_PRPVF_ROT_SRC_SEL_MASK (0xf << 8)
87 #define FS_PRPVF_ROT_SRC_SEL_VF (0x8 << 8)
88 #define FS_PP_SRC_SEL_MASK (0xf << 12)
89 #define FS_PP_ROT_SRC_SEL_MASK (0xf << 16)
90 #define FS_PP_ROT_SRC_SEL_PP (0x5 << 16)
91 #define FS_VDI1_SRC_SEL_MASK (0x3 << 20)
92 #define FS_VDI3_SRC_SEL_MASK (0x3 << 20)
93 #define FS_PRP_SRC_SEL_MASK (0xf << 24)
94 #define FS_VDI_SRC_SEL_MASK (0x3 << 28)
95 #define FS_VDI_SRC_SEL_CSI_DIRECT (0x1 << 28)
96 #define FS_VDI_SRC_SEL_VDOA (0x2 << 28)
97
98 /* FS_PROC_FLOW2 */
99 #define FS_PRP_ENC_DEST_SEL_MASK (0xf << 0)
100 #define FS_PRP_ENC_DEST_SEL_IRT_ENC (0x1 << 0)
101 #define FS_PRPVF_DEST_SEL_MASK (0xf << 4)
102 #define FS_PRPVF_DEST_SEL_IRT_VF (0x1 << 4)
103 #define FS_PRPVF_ROT_DEST_SEL_MASK (0xf << 8)
104 #define FS_PP_DEST_SEL_MASK (0xf << 12)
105 #define FS_PP_DEST_SEL_IRT_PP (0x3 << 12)
106 #define FS_PP_ROT_DEST_SEL_MASK (0xf << 16)
107 #define FS_PRPENC_ROT_DEST_SEL_MASK (0xf << 20)
108 #define FS_PRP_DEST_SEL_MASK (0xf << 24)
109
110 #define IPU_DI0_COUNTER_RELEASE (1 << 24)
111 #define IPU_DI1_COUNTER_RELEASE (1 << 25)
112
113 #define IPU_IDMAC_REG(offset) (offset)
114
115 #define IDMAC_CONF IPU_IDMAC_REG(0x0000)
116 #define IDMAC_CHA_EN(ch) IPU_IDMAC_REG(0x0004 + 4 * ((ch) / 32))
117 #define IDMAC_SEP_ALPHA IPU_IDMAC_REG(0x000c)
118 #define IDMAC_ALT_SEP_ALPHA IPU_IDMAC_REG(0x0010)
119 #define IDMAC_CHA_PRI(ch) IPU_IDMAC_REG(0x0014 + 4 * ((ch) / 32))
120 #define IDMAC_WM_EN(ch) IPU_IDMAC_REG(0x001c + 4 * ((ch) / 32))
121 #define IDMAC_CH_LOCK_EN_1 IPU_IDMAC_REG(0x0024)
122 #define IDMAC_CH_LOCK_EN_2 IPU_IDMAC_REG(0x0028)
123 #define IDMAC_SUB_ADDR_0 IPU_IDMAC_REG(0x002c)
124 #define IDMAC_SUB_ADDR_1 IPU_IDMAC_REG(0x0030)
125 #define IDMAC_SUB_ADDR_2 IPU_IDMAC_REG(0x0034)
126 #define IDMAC_BAND_EN(ch) IPU_IDMAC_REG(0x0040 + 4 * ((ch) / 32))
127 #define IDMAC_CHA_BUSY(ch) IPU_IDMAC_REG(0x0100 + 4 * ((ch) / 32))
128
129 #define IPU_NUM_IRQS (32 * 15)
130
131 enum ipu_modules {
132 IPU_CONF_CSI0_EN = (1 << 0),
133 IPU_CONF_CSI1_EN = (1 << 1),
134 IPU_CONF_IC_EN = (1 << 2),
135 IPU_CONF_ROT_EN = (1 << 3),
136 IPU_CONF_ISP_EN = (1 << 4),
137 IPU_CONF_DP_EN = (1 << 5),
138 IPU_CONF_DI0_EN = (1 << 6),
139 IPU_CONF_DI1_EN = (1 << 7),
140 IPU_CONF_SMFC_EN = (1 << 8),
141 IPU_CONF_DC_EN = (1 << 9),
142 IPU_CONF_DMFC_EN = (1 << 10),
143
144 IPU_CONF_VDI_EN = (1 << 12),
145
146 IPU_CONF_IDMAC_DIS = (1 << 22),
147
148 IPU_CONF_IC_DMFC_SEL = (1 << 25),
149 IPU_CONF_IC_DMFC_SYNC = (1 << 26),
150 IPU_CONF_VDI_DMFC_SYNC = (1 << 27),
151
152 IPU_CONF_CSI0_DATA_SOURCE = (1 << 28),
153 IPU_CONF_CSI1_DATA_SOURCE = (1 << 29),
154 IPU_CONF_IC_INPUT = (1 << 30),
155 IPU_CONF_CSI_SEL = (1 << 31),
156 };
157
158 struct ipuv3_channel {
159 unsigned int num;
160 struct ipu_soc *ipu;
161 struct list_head list;
162 };
163
164 struct ipu_cpmem;
165 struct ipu_csi;
166 struct ipu_dc_priv;
167 struct ipu_dmfc_priv;
168 struct ipu_di;
169 struct ipu_ic_priv;
170 struct ipu_vdi;
171 struct ipu_image_convert_priv;
172 struct ipu_smfc_priv;
173 struct ipu_pre;
174 struct ipu_prg;
175
176 struct ipu_devtype;
177
178 struct ipu_soc {
179 struct device *dev;
180 const struct ipu_devtype *devtype;
181 enum ipuv3_type ipu_type;
182 spinlock_t lock;
183 struct mutex channel_lock;
184 struct list_head channels;
185
186 void __iomem *cm_reg;
187 void __iomem *idmac_reg;
188
189 int id;
190 int usecount;
191
192 struct clk *clk;
193
194 int irq_sync;
195 int irq_err;
196 struct irq_domain *domain;
197
198 struct ipu_cpmem *cpmem_priv;
199 struct ipu_dc_priv *dc_priv;
200 struct ipu_dp_priv *dp_priv;
201 struct ipu_dmfc_priv *dmfc_priv;
202 struct ipu_di *di_priv[2];
203 struct ipu_csi *csi_priv[2];
204 struct ipu_ic_priv *ic_priv;
205 struct ipu_vdi *vdi_priv;
206 struct ipu_image_convert_priv *image_convert_priv;
207 struct ipu_smfc_priv *smfc_priv;
208 struct ipu_prg *prg_priv;
209 };
210
ipu_idmac_read(struct ipu_soc * ipu,unsigned offset)211 static inline u32 ipu_idmac_read(struct ipu_soc *ipu, unsigned offset)
212 {
213 return readl(ipu->idmac_reg + offset);
214 }
215
ipu_idmac_write(struct ipu_soc * ipu,u32 value,unsigned offset)216 static inline void ipu_idmac_write(struct ipu_soc *ipu, u32 value,
217 unsigned offset)
218 {
219 writel(value, ipu->idmac_reg + offset);
220 }
221
222 void ipu_srm_dp_update(struct ipu_soc *ipu, bool sync);
223
224 int ipu_module_enable(struct ipu_soc *ipu, u32 mask);
225 int ipu_module_disable(struct ipu_soc *ipu, u32 mask);
226
227 bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno);
228
229 int ipu_csi_init(struct ipu_soc *ipu, struct device *dev, int id,
230 unsigned long base, u32 module, struct clk *clk_ipu);
231 void ipu_csi_exit(struct ipu_soc *ipu, int id);
232
233 int ipu_ic_init(struct ipu_soc *ipu, struct device *dev,
234 unsigned long base, unsigned long tpmem_base);
235 void ipu_ic_exit(struct ipu_soc *ipu);
236
237 int ipu_vdi_init(struct ipu_soc *ipu, struct device *dev,
238 unsigned long base, u32 module);
239 void ipu_vdi_exit(struct ipu_soc *ipu);
240
241 int ipu_image_convert_init(struct ipu_soc *ipu, struct device *dev);
242 void ipu_image_convert_exit(struct ipu_soc *ipu);
243
244 int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id,
245 unsigned long base, u32 module, struct clk *ipu_clk);
246 void ipu_di_exit(struct ipu_soc *ipu, int id);
247
248 int ipu_dmfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base,
249 struct clk *ipu_clk);
250 void ipu_dmfc_exit(struct ipu_soc *ipu);
251
252 int ipu_dp_init(struct ipu_soc *ipu, struct device *dev, unsigned long base);
253 void ipu_dp_exit(struct ipu_soc *ipu);
254
255 int ipu_dc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base,
256 unsigned long template_base);
257 void ipu_dc_exit(struct ipu_soc *ipu);
258
259 int ipu_cpmem_init(struct ipu_soc *ipu, struct device *dev, unsigned long base);
260 void ipu_cpmem_exit(struct ipu_soc *ipu);
261
262 int ipu_smfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base);
263 void ipu_smfc_exit(struct ipu_soc *ipu);
264
265 struct ipu_pre *ipu_pre_lookup_by_phandle(struct device *dev, const char *name,
266 int index);
267 int ipu_pre_get_available_count(void);
268 int ipu_pre_get(struct ipu_pre *pre);
269 void ipu_pre_put(struct ipu_pre *pre);
270 u32 ipu_pre_get_baddr(struct ipu_pre *pre);
271 void ipu_pre_configure(struct ipu_pre *pre, unsigned int width,
272 unsigned int height, unsigned int stride, u32 format,
273 uint64_t modifier, unsigned int bufaddr);
274 void ipu_pre_update(struct ipu_pre *pre, unsigned int bufaddr);
275
276 struct ipu_prg *ipu_prg_lookup_by_phandle(struct device *dev, const char *name,
277 int ipu_id);
278
279 extern struct platform_driver ipu_pre_drv;
280 extern struct platform_driver ipu_prg_drv;
281
282 #endif /* __IPU_PRV_H__ */
283
