1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_STREAM_H_ 27 #define DC_STREAM_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 32 /******************************************************************************* 33 * Stream Interfaces 34 ******************************************************************************/ 35 struct timing_sync_info { 36 int group_id; 37 int group_size; 38 bool master; 39 }; 40 41 struct dc_stream_status { 42 int primary_otg_inst; 43 int stream_enc_inst; 44 45 /** 46 * @plane_count: Total of planes attached to a single stream 47 */ 48 int plane_count; 49 int audio_inst; 50 struct timing_sync_info timing_sync_info; 51 struct dc_plane_state *plane_states[MAX_SURFACE_NUM]; 52 bool is_abm_supported; 53 }; 54 55 enum hubp_dmdata_mode { 56 DMDATA_SW_MODE, 57 DMDATA_HW_MODE 58 }; 59 60 struct dc_dmdata_attributes { 61 /* Specifies whether dynamic meta data will be updated by software 62 * or has to be fetched by hardware (DMA mode) 63 */ 64 enum hubp_dmdata_mode dmdata_mode; 65 /* Specifies if current dynamic meta data is to be used only for the current frame */ 66 bool dmdata_repeat; 67 /* Specifies the size of Dynamic Metadata surface in byte. Size of 0 means no Dynamic metadata is fetched */ 68 uint32_t dmdata_size; 69 /* Specifies if a new dynamic meta data should be fetched for an upcoming frame */ 70 bool dmdata_updated; 71 /* If hardware mode is used, the base address where DMDATA surface is located */ 72 PHYSICAL_ADDRESS_LOC address; 73 /* Specifies whether QOS level will be provided by TTU or it will come from DMDATA_QOS_LEVEL */ 74 bool dmdata_qos_mode; 75 /* If qos_mode = 1, this is the QOS value to be used: */ 76 uint32_t dmdata_qos_level; 77 /* Specifies the value in unit of REFCLK cycles to be added to the 78 * current time to produce the Amortized deadline for Dynamic Metadata chunk request 79 */ 80 uint32_t dmdata_dl_delta; 81 /* An unbounded array of uint32s, represents software dmdata to be loaded */ 82 uint32_t *dmdata_sw_data; 83 }; 84 85 struct dc_writeback_info { 86 bool wb_enabled; 87 int dwb_pipe_inst; 88 struct dc_dwb_params dwb_params; 89 struct mcif_buf_params mcif_buf_params; 90 struct mcif_warmup_params mcif_warmup_params; 91 /* the plane that is the input to TOP_MUX for MPCC that is the DWB source */ 92 struct dc_plane_state *writeback_source_plane; 93 /* source MPCC instance. for use by internally by dc */ 94 int mpcc_inst; 95 }; 96 97 struct dc_writeback_update { 98 unsigned int num_wb_info; 99 struct dc_writeback_info writeback_info[MAX_DWB_PIPES]; 100 }; 101 102 enum vertical_interrupt_ref_point { 103 START_V_UPDATE = 0, 104 START_V_SYNC, 105 INVALID_POINT 106 107 //For now, only v_update interrupt is used. 108 //START_V_BLANK, 109 //START_V_ACTIVE 110 }; 111 112 struct periodic_interrupt_config { 113 enum vertical_interrupt_ref_point ref_point; 114 int lines_offset; 115 }; 116 117 struct dc_mst_stream_bw_update { 118 bool is_increase; // is bandwidth reduced or increased 119 uint32_t mst_stream_bw; // new mst bandwidth in kbps 120 }; 121 122 union stream_update_flags { 123 struct { 124 uint32_t scaling:1; 125 uint32_t out_tf:1; 126 uint32_t out_csc:1; 127 uint32_t abm_level:1; 128 uint32_t dpms_off:1; 129 uint32_t gamut_remap:1; 130 uint32_t wb_update:1; 131 uint32_t dsc_changed : 1; 132 uint32_t mst_bw : 1; 133 uint32_t crtc_timing_adjust : 1; 134 uint32_t fams_changed : 1; 135 } bits; 136 137 uint32_t raw; 138 }; 139 140 struct test_pattern { 141 enum dp_test_pattern type; 142 enum dp_test_pattern_color_space color_space; 143 struct link_training_settings const *p_link_settings; 144 unsigned char const *p_custom_pattern; 145 unsigned int cust_pattern_size; 146 }; 147 148 #define SUBVP_DRR_MARGIN_US 100 // 100us for DRR margin (SubVP + DRR) 149 150 enum mall_stream_type { 151 SUBVP_NONE, // subvp not in use 152 SUBVP_MAIN, // subvp in use, this stream is main stream 153 SUBVP_PHANTOM, // subvp in use, this stream is a phantom stream 154 }; 155 156 struct mall_stream_config { 157 /* MALL stream config to indicate if the stream is phantom or not. 158 * We will use a phantom stream to indicate that the pipe is phantom. 159 */ 160 enum mall_stream_type type; 161 struct dc_stream_state *paired_stream; // master / slave stream 162 }; 163 164 /* Temp struct used to save and restore MALL config 165 * during validation. 166 * 167 * TODO: Move MALL config into dc_state instead of stream struct 168 * to avoid needing to save/restore. 169 */ 170 struct mall_temp_config { 171 struct mall_stream_config mall_stream_config[MAX_PIPES]; 172 bool is_phantom_plane[MAX_PIPES]; 173 }; 174 175 struct dc_stream_debug_options { 176 char force_odm_combine_segments; 177 }; 178 179 struct dc_stream_state { 180 // sink is deprecated, new code should not reference 181 // this pointer 182 struct dc_sink *sink; 183 184 struct dc_link *link; 185 /* For dynamic link encoder assignment, update the link encoder assigned to 186 * a stream via the volatile dc_state rather than the static dc_link. 187 */ 188 struct link_encoder *link_enc; 189 struct dc_stream_debug_options debug; 190 struct dc_panel_patch sink_patches; 191 union display_content_support content_support; 192 struct dc_crtc_timing timing; 193 struct dc_crtc_timing_adjust adjust; 194 struct dc_info_packet vrr_infopacket; 195 struct dc_info_packet vsc_infopacket; 196 struct dc_info_packet vsp_infopacket; 197 struct dc_info_packet hfvsif_infopacket; 198 struct dc_info_packet vtem_infopacket; 199 struct dc_info_packet adaptive_sync_infopacket; 200 uint8_t dsc_packed_pps[128]; 201 struct rect src; /* composition area */ 202 struct rect dst; /* stream addressable area */ 203 204 struct audio_info audio_info; 205 206 struct dc_info_packet hdr_static_metadata; 207 PHYSICAL_ADDRESS_LOC dmdata_address; 208 bool use_dynamic_meta; 209 210 struct dc_transfer_func *out_transfer_func; 211 struct colorspace_transform gamut_remap_matrix; 212 struct dc_csc_transform csc_color_matrix; 213 214 enum dc_color_space output_color_space; 215 enum dc_dither_option dither_option; 216 217 enum view_3d_format view_format; 218 219 bool use_vsc_sdp_for_colorimetry; 220 bool ignore_msa_timing_param; 221 222 /** 223 * @allow_freesync: 224 * 225 * It say if Freesync is enabled or not. 226 */ 227 bool allow_freesync; 228 229 /** 230 * @vrr_active_variable: 231 * 232 * It describes if VRR is in use. 233 */ 234 bool vrr_active_variable; 235 bool freesync_on_desktop; 236 bool vrr_active_fixed; 237 238 bool converter_disable_audio; 239 uint8_t qs_bit; 240 uint8_t qy_bit; 241 242 /* TODO: custom INFO packets */ 243 /* TODO: ABM info (DMCU) */ 244 /* TODO: CEA VIC */ 245 246 /* DMCU info */ 247 unsigned int abm_level; 248 249 struct periodic_interrupt_config periodic_interrupt; 250 251 /* from core_stream struct */ 252 struct dc_context *ctx; 253 254 /* used by DCP and FMT */ 255 struct bit_depth_reduction_params bit_depth_params; 256 struct clamping_and_pixel_encoding_params clamping; 257 258 int phy_pix_clk; 259 enum signal_type signal; 260 bool dpms_off; 261 262 void *dm_stream_context; 263 264 struct dc_cursor_attributes cursor_attributes; 265 struct dc_cursor_position cursor_position; 266 uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode 267 268 /* from stream struct */ 269 struct kref refcount; 270 271 struct crtc_trigger_info triggered_crtc_reset; 272 273 /* writeback */ 274 unsigned int num_wb_info; 275 struct dc_writeback_info writeback_info[MAX_DWB_PIPES]; 276 const struct dc_transfer_func *func_shaper; 277 const struct dc_3dlut *lut3d_func; 278 /* Computed state bits */ 279 bool mode_changed : 1; 280 281 /* Output from DC when stream state is committed or altered 282 * DC may only access these values during: 283 * dc_commit_state, dc_commit_state_no_check, dc_commit_streams 284 * values may not change outside of those calls 285 */ 286 struct { 287 // For interrupt management, some hardware instance 288 // offsets need to be exposed to DM 289 uint8_t otg_offset; 290 } out; 291 292 bool apply_edp_fast_boot_optimization; 293 bool apply_seamless_boot_optimization; 294 uint32_t apply_boot_odm_mode; 295 296 uint32_t stream_id; 297 298 struct test_pattern test_pattern; 299 union stream_update_flags update_flags; 300 301 bool has_non_synchronizable_pclk; 302 bool vblank_synchronized; 303 bool fpo_in_use; 304 struct mall_stream_config mall_stream_config; 305 bool skip_edp_power_down; 306 }; 307 308 #define ABM_LEVEL_IMMEDIATE_DISABLE 255 309 310 struct dc_stream_update { 311 struct dc_stream_state *stream; 312 313 struct rect src; 314 struct rect dst; 315 struct dc_transfer_func *out_transfer_func; 316 struct dc_info_packet *hdr_static_metadata; 317 unsigned int *abm_level; 318 319 struct periodic_interrupt_config *periodic_interrupt; 320 321 struct dc_info_packet *vrr_infopacket; 322 struct dc_info_packet *vsc_infopacket; 323 struct dc_info_packet *vsp_infopacket; 324 struct dc_info_packet *hfvsif_infopacket; 325 struct dc_info_packet *vtem_infopacket; 326 struct dc_info_packet *adaptive_sync_infopacket; 327 bool *dpms_off; 328 bool integer_scaling_update; 329 bool *allow_freesync; 330 bool *vrr_active_variable; 331 bool *vrr_active_fixed; 332 333 struct colorspace_transform *gamut_remap; 334 enum dc_color_space *output_color_space; 335 enum dc_dither_option *dither_option; 336 337 struct dc_csc_transform *output_csc_transform; 338 339 struct dc_writeback_update *wb_update; 340 struct dc_dsc_config *dsc_config; 341 struct dc_mst_stream_bw_update *mst_bw_update; 342 struct dc_transfer_func *func_shaper; 343 struct dc_3dlut *lut3d_func; 344 345 struct test_pattern *pending_test_pattern; 346 struct dc_crtc_timing_adjust *crtc_timing_adjust; 347 }; 348 349 bool dc_is_stream_unchanged( 350 struct dc_stream_state *old_stream, struct dc_stream_state *stream); 351 bool dc_is_stream_scaling_unchanged( 352 struct dc_stream_state *old_stream, struct dc_stream_state *stream); 353 354 /* 355 * Setup stream attributes if no stream updates are provided 356 * there will be no impact on the stream parameters 357 * 358 * Set up surface attributes and associate to a stream 359 * The surfaces parameter is an absolute set of all surface active for the stream. 360 * If no surfaces are provided, the stream will be blanked; no memory read. 361 * Any flip related attribute changes must be done through this interface. 362 * 363 * After this call: 364 * Surfaces attributes are programmed and configured to be composed into stream. 365 * This does not trigger a flip. No surface address is programmed. 366 * 367 */ 368 bool dc_update_planes_and_stream(struct dc *dc, 369 struct dc_surface_update *surface_updates, int surface_count, 370 struct dc_stream_state *dc_stream, 371 struct dc_stream_update *stream_update); 372 373 /* 374 * Set up surface attributes and associate to a stream 375 * The surfaces parameter is an absolute set of all surface active for the stream. 376 * If no surfaces are provided, the stream will be blanked; no memory read. 377 * Any flip related attribute changes must be done through this interface. 378 * 379 * After this call: 380 * Surfaces attributes are programmed and configured to be composed into stream. 381 * This does not trigger a flip. No surface address is programmed. 382 */ 383 void dc_commit_updates_for_stream(struct dc *dc, 384 struct dc_surface_update *srf_updates, 385 int surface_count, 386 struct dc_stream_state *stream, 387 struct dc_stream_update *stream_update, 388 struct dc_state *state); 389 /* 390 * Log the current stream state. 391 */ 392 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream); 393 394 uint8_t dc_get_current_stream_count(struct dc *dc); 395 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i); 396 397 /* 398 * Return the current frame counter. 399 */ 400 uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream); 401 402 /* 403 * Send dp sdp message. 404 */ 405 bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream, 406 const uint8_t *custom_sdp_message, 407 unsigned int sdp_message_size); 408 409 /* TODO: Return parsed values rather than direct register read 410 * This has a dependency on the caller (amdgpu_display_get_crtc_scanoutpos) 411 * being refactored properly to be dce-specific 412 */ 413 bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, 414 uint32_t *v_blank_start, 415 uint32_t *v_blank_end, 416 uint32_t *h_position, 417 uint32_t *v_position); 418 419 enum dc_status dc_add_stream_to_ctx( 420 struct dc *dc, 421 struct dc_state *new_ctx, 422 struct dc_stream_state *stream); 423 424 enum dc_status dc_remove_stream_from_ctx( 425 struct dc *dc, 426 struct dc_state *new_ctx, 427 struct dc_stream_state *stream); 428 429 430 bool dc_add_plane_to_context( 431 const struct dc *dc, 432 struct dc_stream_state *stream, 433 struct dc_plane_state *plane_state, 434 struct dc_state *context); 435 436 bool dc_remove_plane_from_context( 437 const struct dc *dc, 438 struct dc_stream_state *stream, 439 struct dc_plane_state *plane_state, 440 struct dc_state *context); 441 442 bool dc_rem_all_planes_for_stream( 443 const struct dc *dc, 444 struct dc_stream_state *stream, 445 struct dc_state *context); 446 447 bool dc_add_all_planes_for_stream( 448 const struct dc *dc, 449 struct dc_stream_state *stream, 450 struct dc_plane_state * const *plane_states, 451 int plane_count, 452 struct dc_state *context); 453 454 bool dc_stream_add_writeback(struct dc *dc, 455 struct dc_stream_state *stream, 456 struct dc_writeback_info *wb_info); 457 458 bool dc_stream_remove_writeback(struct dc *dc, 459 struct dc_stream_state *stream, 460 uint32_t dwb_pipe_inst); 461 462 enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc, 463 struct dc_state *state, 464 struct dc_stream_state *stream); 465 466 bool dc_stream_warmup_writeback(struct dc *dc, 467 int num_dwb, 468 struct dc_writeback_info *wb_info); 469 470 bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream); 471 472 bool dc_stream_set_dynamic_metadata(struct dc *dc, 473 struct dc_stream_state *stream, 474 struct dc_dmdata_attributes *dmdata_attr); 475 476 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream); 477 478 /* 479 * Set up streams and links associated to drive sinks 480 * The streams parameter is an absolute set of all active streams. 481 * 482 * After this call: 483 * Phy, Encoder, Timing Generator are programmed and enabled. 484 * New streams are enabled with blank stream; no memory read. 485 */ 486 /* 487 * Enable stereo when commit_streams is not required, 488 * for example, frame alternate. 489 */ 490 void dc_enable_stereo( 491 struct dc *dc, 492 struct dc_state *context, 493 struct dc_stream_state *streams[], 494 uint8_t stream_count); 495 496 /* Triggers multi-stream synchronization. */ 497 void dc_trigger_sync(struct dc *dc, struct dc_state *context); 498 499 enum surface_update_type dc_check_update_surfaces_for_stream( 500 struct dc *dc, 501 struct dc_surface_update *updates, 502 int surface_count, 503 struct dc_stream_update *stream_update, 504 const struct dc_stream_status *stream_status); 505 506 /** 507 * Create a new default stream for the requested sink 508 */ 509 struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink); 510 511 struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream); 512 513 void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink); 514 515 void dc_stream_retain(struct dc_stream_state *dc_stream); 516 void dc_stream_release(struct dc_stream_state *dc_stream); 517 518 struct dc_stream_status *dc_stream_get_status_from_state( 519 struct dc_state *state, 520 struct dc_stream_state *stream); 521 struct dc_stream_status *dc_stream_get_status( 522 struct dc_stream_state *dc_stream); 523 524 #ifndef TRIM_FSFT 525 bool dc_optimize_timing_for_fsft( 526 struct dc_stream_state *pStream, 527 unsigned int max_input_rate_in_khz); 528 #endif 529 530 /******************************************************************************* 531 * Cursor interfaces - To manages the cursor within a stream 532 ******************************************************************************/ 533 /* TODO: Deprecated once we switch to dc_set_cursor_position */ 534 bool dc_stream_set_cursor_attributes( 535 struct dc_stream_state *stream, 536 const struct dc_cursor_attributes *attributes); 537 538 bool dc_stream_set_cursor_position( 539 struct dc_stream_state *stream, 540 const struct dc_cursor_position *position); 541 542 543 bool dc_stream_adjust_vmin_vmax(struct dc *dc, 544 struct dc_stream_state *stream, 545 struct dc_crtc_timing_adjust *adjust); 546 547 bool dc_stream_get_last_used_drr_vtotal(struct dc *dc, 548 struct dc_stream_state *stream, 549 uint32_t *refresh_rate); 550 551 bool dc_stream_get_crtc_position(struct dc *dc, 552 struct dc_stream_state **stream, 553 int num_streams, 554 unsigned int *v_pos, 555 unsigned int *nom_v_pos); 556 557 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 558 bool dc_stream_forward_crc_window(struct dc_stream_state *stream, 559 struct rect *rect, 560 bool is_stop); 561 #endif 562 563 bool dc_stream_configure_crc(struct dc *dc, 564 struct dc_stream_state *stream, 565 struct crc_params *crc_window, 566 bool enable, 567 bool continuous); 568 569 bool dc_stream_get_crc(struct dc *dc, 570 struct dc_stream_state *stream, 571 uint32_t *r_cr, 572 uint32_t *g_y, 573 uint32_t *b_cb); 574 575 void dc_stream_set_static_screen_params(struct dc *dc, 576 struct dc_stream_state **stream, 577 int num_streams, 578 const struct dc_static_screen_params *params); 579 580 void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream, 581 enum dc_dynamic_expansion option); 582 583 void dc_stream_set_dither_option(struct dc_stream_state *stream, 584 enum dc_dither_option option); 585 586 bool dc_stream_set_gamut_remap(struct dc *dc, 587 const struct dc_stream_state *stream); 588 589 bool dc_stream_program_csc_matrix(struct dc *dc, 590 struct dc_stream_state *stream); 591 592 bool dc_stream_get_crtc_position(struct dc *dc, 593 struct dc_stream_state **stream, 594 int num_streams, 595 unsigned int *v_pos, 596 unsigned int *nom_v_pos); 597 598 struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream); 599 600 void dc_dmub_update_dirty_rect(struct dc *dc, 601 int surface_count, 602 struct dc_stream_state *stream, 603 struct dc_surface_update *srf_updates, 604 struct dc_state *context); 605 #endif /* DC_STREAM_H_ */ 606
