1 /* 2 * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __AMDGPU_DM_H__ 27 #define __AMDGPU_DM_H__ 28 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_connector.h> 31 #include <drm/drm_crtc.h> 32 #include <drm/drm_dp_mst_helper.h> 33 #include <drm/drm_plane.h> 34 35 /* 36 * This file contains the definition for amdgpu_display_manager 37 * and its API for amdgpu driver's use. 38 * This component provides all the display related functionality 39 * and this is the only component that calls DAL API. 40 * The API contained here intended for amdgpu driver use. 41 * The API that is called directly from KMS framework is located 42 * in amdgpu_dm_kms.h file 43 */ 44 45 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 46 47 #define AMDGPU_DM_MAX_CRTC 6 48 49 #define AMDGPU_DM_MAX_NUM_EDP 2 50 /* 51 #include "include/amdgpu_dal_power_if.h" 52 #include "amdgpu_dm_irq.h" 53 */ 54 55 #include "irq_types.h" 56 #include "signal_types.h" 57 #include "amdgpu_dm_crc.h" 58 struct aux_payload; 59 enum aux_return_code_type; 60 61 /* Forward declarations */ 62 struct amdgpu_device; 63 struct amdgpu_crtc; 64 struct drm_device; 65 struct dc; 66 struct amdgpu_bo; 67 struct dmub_srv; 68 struct dc_plane_state; 69 struct dmub_notification; 70 71 struct common_irq_params { 72 struct amdgpu_device *adev; 73 enum dc_irq_source irq_src; 74 atomic64_t previous_timestamp; 75 }; 76 77 /** 78 * struct dm_compressor_info - Buffer info used by frame buffer compression 79 * @cpu_addr: MMIO cpu addr 80 * @bo_ptr: Pointer to the buffer object 81 * @gpu_addr: MMIO gpu addr 82 */ 83 struct dm_compressor_info { 84 void *cpu_addr; 85 struct amdgpu_bo *bo_ptr; 86 uint64_t gpu_addr; 87 }; 88 89 /** 90 * struct vblank_control_work - Work data for vblank control 91 * @work: Kernel work data for the work event 92 * @dm: amdgpu display manager device 93 * @acrtc: amdgpu CRTC instance for which the event has occurred 94 * @stream: DC stream for which the event has occurred 95 * @enable: true if enabling vblank 96 */ 97 struct vblank_control_work { 98 struct work_struct work; 99 struct amdgpu_display_manager *dm; 100 struct amdgpu_crtc *acrtc; 101 struct dc_stream_state *stream; 102 bool enable; 103 }; 104 105 /** 106 * struct amdgpu_dm_backlight_caps - Information about backlight 107 * 108 * Describe the backlight support for ACPI or eDP AUX. 109 */ 110 struct amdgpu_dm_backlight_caps { 111 /** 112 * @ext_caps: Keep the data struct with all the information about the 113 * display support for HDR. 114 */ 115 union dpcd_sink_ext_caps *ext_caps; 116 /** 117 * @aux_min_input_signal: Min brightness value supported by the display 118 */ 119 u32 aux_min_input_signal; 120 /** 121 * @aux_max_input_signal: Max brightness value supported by the display 122 * in nits. 123 */ 124 u32 aux_max_input_signal; 125 /** 126 * @min_input_signal: minimum possible input in range 0-255. 127 */ 128 int min_input_signal; 129 /** 130 * @max_input_signal: maximum possible input in range 0-255. 131 */ 132 int max_input_signal; 133 /** 134 * @caps_valid: true if these values are from the ACPI interface. 135 */ 136 bool caps_valid; 137 /** 138 * @aux_support: Describes if the display supports AUX backlight. 139 */ 140 bool aux_support; 141 }; 142 143 /** 144 * struct dal_allocation - Tracks mapped FB memory for SMU communication 145 * @list: list of dal allocations 146 * @bo: GPU buffer object 147 * @cpu_ptr: CPU virtual address of the GPU buffer object 148 * @gpu_addr: GPU virtual address of the GPU buffer object 149 */ 150 struct dal_allocation { 151 struct list_head list; 152 struct amdgpu_bo *bo; 153 void *cpu_ptr; 154 u64 gpu_addr; 155 }; 156 157 /** 158 * struct amdgpu_display_manager - Central amdgpu display manager device 159 * 160 * @dc: Display Core control structure 161 * @adev: AMDGPU base driver structure 162 * @ddev: DRM base driver structure 163 * @display_indexes_num: Max number of display streams supported 164 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 165 * @backlight_dev: Backlight control device 166 * @backlight_link: Link on which to control backlight 167 * @backlight_caps: Capabilities of the backlight device 168 * @freesync_module: Module handling freesync calculations 169 * @hdcp_workqueue: AMDGPU content protection queue 170 * @fw_dmcu: Reference to DMCU firmware 171 * @dmcu_fw_version: Version of the DMCU firmware 172 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 173 * @cached_state: Caches device atomic state for suspend/resume 174 * @cached_dc_state: Cached state of content streams 175 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info 176 * @force_timing_sync: set via debugfs. When set, indicates that all connected 177 * displays will be forced to synchronize. 178 * @dmcub_trace_event_en: enable dmcub trace events 179 */ 180 struct amdgpu_display_manager { 181 182 struct dc *dc; 183 184 /** 185 * @dmub_srv: 186 * 187 * DMUB service, used for controlling the DMUB on hardware 188 * that supports it. The pointer to the dmub_srv will be 189 * NULL on hardware that does not support it. 190 */ 191 struct dmub_srv *dmub_srv; 192 193 struct dmub_notification *dmub_notify; 194 195 /** 196 * @dmub_fb_info: 197 * 198 * Framebuffer regions for the DMUB. 199 */ 200 struct dmub_srv_fb_info *dmub_fb_info; 201 202 /** 203 * @dmub_fw: 204 * 205 * DMUB firmware, required on hardware that has DMUB support. 206 */ 207 const struct firmware *dmub_fw; 208 209 /** 210 * @dmub_bo: 211 * 212 * Buffer object for the DMUB. 213 */ 214 struct amdgpu_bo *dmub_bo; 215 216 /** 217 * @dmub_bo_gpu_addr: 218 * 219 * GPU virtual address for the DMUB buffer object. 220 */ 221 u64 dmub_bo_gpu_addr; 222 223 /** 224 * @dmub_bo_cpu_addr: 225 * 226 * CPU address for the DMUB buffer object. 227 */ 228 void *dmub_bo_cpu_addr; 229 230 /** 231 * @dmcub_fw_version: 232 * 233 * DMCUB firmware version. 234 */ 235 uint32_t dmcub_fw_version; 236 237 /** 238 * @cgs_device: 239 * 240 * The Common Graphics Services device. It provides an interface for 241 * accessing registers. 242 */ 243 struct cgs_device *cgs_device; 244 245 struct amdgpu_device *adev; 246 struct drm_device *ddev; 247 u16 display_indexes_num; 248 249 /** 250 * @atomic_obj: 251 * 252 * In combination with &dm_atomic_state it helps manage 253 * global atomic state that doesn't map cleanly into existing 254 * drm resources, like &dc_context. 255 */ 256 struct drm_private_obj atomic_obj; 257 258 /** 259 * @dc_lock: 260 * 261 * Guards access to DC functions that can issue register write 262 * sequences. 263 */ 264 struct mutex dc_lock; 265 266 /** 267 * @audio_lock: 268 * 269 * Guards access to audio instance changes. 270 */ 271 struct mutex audio_lock; 272 273 #if defined(CONFIG_DRM_AMD_DC_DCN) 274 /** 275 * @vblank_lock: 276 * 277 * Guards access to deferred vblank work state. 278 */ 279 spinlock_t vblank_lock; 280 #endif 281 282 /** 283 * @audio_component: 284 * 285 * Used to notify ELD changes to sound driver. 286 */ 287 struct drm_audio_component *audio_component; 288 289 /** 290 * @audio_registered: 291 * 292 * True if the audio component has been registered 293 * successfully, false otherwise. 294 */ 295 bool audio_registered; 296 297 /** 298 * @irq_handler_list_low_tab: 299 * 300 * Low priority IRQ handler table. 301 * 302 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 303 * source. Low priority IRQ handlers are deferred to a workqueue to be 304 * processed. Hence, they can sleep. 305 * 306 * Note that handlers are called in the same order as they were 307 * registered (FIFO). 308 */ 309 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 310 311 /** 312 * @irq_handler_list_high_tab: 313 * 314 * High priority IRQ handler table. 315 * 316 * It is a n*m table, same as &irq_handler_list_low_tab. However, 317 * handlers in this table are not deferred and are called immediately. 318 */ 319 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 320 321 /** 322 * @pflip_params: 323 * 324 * Page flip IRQ parameters, passed to registered handlers when 325 * triggered. 326 */ 327 struct common_irq_params 328 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 329 330 /** 331 * @vblank_params: 332 * 333 * Vertical blanking IRQ parameters, passed to registered handlers when 334 * triggered. 335 */ 336 struct common_irq_params 337 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 338 339 /** 340 * @vline0_params: 341 * 342 * OTG vertical interrupt0 IRQ parameters, passed to registered 343 * handlers when triggered. 344 */ 345 struct common_irq_params 346 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; 347 348 /** 349 * @vupdate_params: 350 * 351 * Vertical update IRQ parameters, passed to registered handlers when 352 * triggered. 353 */ 354 struct common_irq_params 355 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 356 357 /** 358 * @dmub_trace_params: 359 * 360 * DMUB trace event IRQ parameters, passed to registered handlers when 361 * triggered. 362 */ 363 struct common_irq_params 364 dmub_trace_params[1]; 365 366 struct common_irq_params 367 dmub_outbox_params[1]; 368 369 spinlock_t irq_handler_list_table_lock; 370 371 struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; 372 373 const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; 374 375 uint8_t num_of_edps; 376 377 struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; 378 379 struct mod_freesync *freesync_module; 380 #ifdef CONFIG_DRM_AMD_DC_HDCP 381 struct hdcp_workqueue *hdcp_workqueue; 382 #endif 383 384 #if defined(CONFIG_DRM_AMD_DC_DCN) 385 /** 386 * @vblank_control_workqueue: 387 * 388 * Deferred work for vblank control events. 389 */ 390 struct workqueue_struct *vblank_control_workqueue; 391 #endif 392 393 struct drm_atomic_state *cached_state; 394 struct dc_state *cached_dc_state; 395 396 struct dm_compressor_info compressor; 397 398 const struct firmware *fw_dmcu; 399 uint32_t dmcu_fw_version; 400 /** 401 * @soc_bounding_box: 402 * 403 * gpu_info FW provided soc bounding box struct or 0 if not 404 * available in FW 405 */ 406 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 407 408 #if defined(CONFIG_DRM_AMD_DC_DCN) 409 /** 410 * @active_vblank_irq_count: 411 * 412 * number of currently active vblank irqs 413 */ 414 uint32_t active_vblank_irq_count; 415 #endif 416 417 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 418 /** 419 * @crc_rd_wrk: 420 * 421 * Work to be executed in a separate thread to communicate with PSP. 422 */ 423 struct crc_rd_work *crc_rd_wrk; 424 #endif 425 426 /** 427 * @mst_encoders: 428 * 429 * fake encoders used for DP MST. 430 */ 431 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; 432 bool force_timing_sync; 433 bool disable_hpd_irq; 434 bool dmcub_trace_event_en; 435 /** 436 * @da_list: 437 * 438 * DAL fb memory allocation list, for communication with SMU. 439 */ 440 struct list_head da_list; 441 struct completion dmub_aux_transfer_done; 442 443 /** 444 * @brightness: 445 * 446 * cached backlight values. 447 */ 448 u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; 449 }; 450 451 enum dsc_clock_force_state { 452 DSC_CLK_FORCE_DEFAULT = 0, 453 DSC_CLK_FORCE_ENABLE, 454 DSC_CLK_FORCE_DISABLE, 455 }; 456 457 struct dsc_preferred_settings { 458 enum dsc_clock_force_state dsc_force_enable; 459 uint32_t dsc_num_slices_v; 460 uint32_t dsc_num_slices_h; 461 uint32_t dsc_bits_per_pixel; 462 bool dsc_force_disable_passthrough; 463 }; 464 465 struct amdgpu_dm_connector { 466 467 struct drm_connector base; 468 uint32_t connector_id; 469 470 /* we need to mind the EDID between detect 471 and get modes due to analog/digital/tvencoder */ 472 struct edid *edid; 473 474 /* shared with amdgpu */ 475 struct amdgpu_hpd hpd; 476 477 /* number of modes generated from EDID at 'dc_sink' */ 478 int num_modes; 479 480 /* The 'old' sink - before an HPD. 481 * The 'current' sink is in dc_link->sink. */ 482 struct dc_sink *dc_sink; 483 struct dc_link *dc_link; 484 struct dc_sink *dc_em_sink; 485 486 /* DM only */ 487 struct drm_dp_mst_topology_mgr mst_mgr; 488 struct amdgpu_dm_dp_aux dm_dp_aux; 489 struct drm_dp_mst_port *port; 490 struct amdgpu_dm_connector *mst_port; 491 struct drm_dp_aux *dsc_aux; 492 493 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 494 struct amdgpu_i2c_adapter *i2c; 495 496 /* Monitor range limits */ 497 int min_vfreq ; 498 int max_vfreq ; 499 int pixel_clock_mhz; 500 501 /* Audio instance - protected by audio_lock. */ 502 int audio_inst; 503 504 struct mutex hpd_lock; 505 506 bool fake_enable; 507 #ifdef CONFIG_DEBUG_FS 508 uint32_t debugfs_dpcd_address; 509 uint32_t debugfs_dpcd_size; 510 #endif 511 bool force_yuv420_output; 512 struct dsc_preferred_settings dsc_settings; 513 /* Cached display modes */ 514 struct drm_display_mode freesync_vid_base; 515 516 int psr_skip_count; 517 }; 518 519 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 520 521 extern const struct amdgpu_ip_block_version dm_ip_block; 522 523 struct dm_plane_state { 524 struct drm_plane_state base; 525 struct dc_plane_state *dc_state; 526 }; 527 528 struct dm_crtc_state { 529 struct drm_crtc_state base; 530 struct dc_stream_state *stream; 531 532 bool cm_has_degamma; 533 bool cm_is_degamma_srgb; 534 535 int update_type; 536 int active_planes; 537 538 int crc_skip_count; 539 540 bool freesync_timing_changed; 541 bool freesync_vrr_info_changed; 542 543 bool dsc_force_changed; 544 bool vrr_supported; 545 struct mod_freesync_config freesync_config; 546 struct dc_info_packet vrr_infopacket; 547 548 int abm_level; 549 }; 550 551 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 552 553 struct dm_atomic_state { 554 struct drm_private_state base; 555 556 struct dc_state *context; 557 }; 558 559 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 560 561 struct dm_connector_state { 562 struct drm_connector_state base; 563 564 enum amdgpu_rmx_type scaling; 565 uint8_t underscan_vborder; 566 uint8_t underscan_hborder; 567 bool underscan_enable; 568 bool freesync_capable; 569 #ifdef CONFIG_DRM_AMD_DC_HDCP 570 bool update_hdcp; 571 #endif 572 uint8_t abm_level; 573 int vcpi_slots; 574 uint64_t pbn; 575 }; 576 577 struct amdgpu_hdmi_vsdb_info { 578 unsigned int amd_vsdb_version; /* VSDB version, should be used to determine which VSIF to send */ 579 bool freesync_supported; /* FreeSync Supported */ 580 unsigned int min_refresh_rate_hz; /* FreeSync Minimum Refresh Rate in Hz */ 581 unsigned int max_refresh_rate_hz; /* FreeSync Maximum Refresh Rate in Hz */ 582 }; 583 584 585 #define to_dm_connector_state(x)\ 586 container_of((x), struct dm_connector_state, base) 587 588 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 589 struct drm_connector_state * 590 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 591 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 592 struct drm_connector_state *state, 593 struct drm_property *property, 594 uint64_t val); 595 596 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 597 const struct drm_connector_state *state, 598 struct drm_property *property, 599 uint64_t *val); 600 601 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 602 603 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 604 struct amdgpu_dm_connector *aconnector, 605 int connector_type, 606 struct dc_link *link, 607 int link_index); 608 609 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 610 struct drm_display_mode *mode); 611 612 void dm_restore_drm_connector_state(struct drm_device *dev, 613 struct drm_connector *connector); 614 615 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 616 struct edid *edid); 617 618 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); 619 620 #define MAX_COLOR_LUT_ENTRIES 4096 621 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 622 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 623 624 void amdgpu_dm_init_color_mod(void); 625 int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); 626 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 627 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 628 struct dc_plane_state *dc_plane_state); 629 630 void amdgpu_dm_update_connector_after_detect( 631 struct amdgpu_dm_connector *aconnector); 632 633 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 634 635 int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int linkIndex, 636 struct aux_payload *payload, enum aux_return_code_type *operation_result); 637 #endif /* __AMDGPU_DM_H__ */ 638
