1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <drm/drm_atomic.h>
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_dp_mst_helper.h>
29 #include <drm/drm_dp_helper.h>
30 #include "dm_services.h"
31 #include "amdgpu.h"
32 #include "amdgpu_dm.h"
33 #include "amdgpu_dm_mst_types.h"
34
35 #include "dc.h"
36 #include "dm_helpers.h"
37
38 #include "dc_link_ddc.h"
39
40 #include "i2caux_interface.h"
41 #include "dmub_cmd.h"
42 #if defined(CONFIG_DEBUG_FS)
43 #include "amdgpu_dm_debugfs.h"
44 #endif
45
46 #if defined(CONFIG_DRM_AMD_DC_DCN)
47 #include "dc/dcn20/dcn20_resource.h"
48 #endif
49
dm_dp_aux_transfer(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)50 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
51 struct drm_dp_aux_msg *msg)
52 {
53 ssize_t result = 0;
54 struct aux_payload payload;
55 enum aux_return_code_type operation_result;
56
57 if (WARN_ON(msg->size > 16))
58 return -E2BIG;
59
60 payload.address = msg->address;
61 payload.data = msg->buffer;
62 payload.length = msg->size;
63 payload.reply = &msg->reply;
64 payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0;
65 payload.write = (msg->request & DP_AUX_I2C_READ) == 0;
66 payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0;
67 payload.defer_delay = 0;
68
69 result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,
70 &operation_result);
71
72 if (payload.write && result >= 0)
73 result = msg->size;
74
75 if (result < 0)
76 switch (operation_result) {
77 case AUX_RET_SUCCESS:
78 break;
79 case AUX_RET_ERROR_HPD_DISCON:
80 case AUX_RET_ERROR_UNKNOWN:
81 case AUX_RET_ERROR_INVALID_OPERATION:
82 case AUX_RET_ERROR_PROTOCOL_ERROR:
83 result = -EIO;
84 break;
85 case AUX_RET_ERROR_INVALID_REPLY:
86 case AUX_RET_ERROR_ENGINE_ACQUIRE:
87 result = -EBUSY;
88 break;
89 case AUX_RET_ERROR_TIMEOUT:
90 result = -ETIMEDOUT;
91 break;
92 }
93
94 return result;
95 }
96
97 static void
dm_dp_mst_connector_destroy(struct drm_connector * connector)98 dm_dp_mst_connector_destroy(struct drm_connector *connector)
99 {
100 struct amdgpu_dm_connector *aconnector =
101 to_amdgpu_dm_connector(connector);
102
103 if (aconnector->dc_sink) {
104 dc_link_remove_remote_sink(aconnector->dc_link,
105 aconnector->dc_sink);
106 dc_sink_release(aconnector->dc_sink);
107 }
108
109 kfree(aconnector->edid);
110
111 drm_connector_cleanup(connector);
112 drm_dp_mst_put_port_malloc(aconnector->port);
113 kfree(aconnector);
114 }
115
116 static int
amdgpu_dm_mst_connector_late_register(struct drm_connector * connector)117 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
118 {
119 struct amdgpu_dm_connector *amdgpu_dm_connector =
120 to_amdgpu_dm_connector(connector);
121 int r;
122
123 r = drm_dp_mst_connector_late_register(connector,
124 amdgpu_dm_connector->port);
125 if (r < 0)
126 return r;
127
128 #if defined(CONFIG_DEBUG_FS)
129 connector_debugfs_init(amdgpu_dm_connector);
130 #endif
131
132 return 0;
133 }
134
135 static void
amdgpu_dm_mst_connector_early_unregister(struct drm_connector * connector)136 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
137 {
138 struct amdgpu_dm_connector *amdgpu_dm_connector =
139 to_amdgpu_dm_connector(connector);
140 struct drm_dp_mst_port *port = amdgpu_dm_connector->port;
141
142 drm_dp_mst_connector_early_unregister(connector, port);
143 }
144
145 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
146 .fill_modes = drm_helper_probe_single_connector_modes,
147 .destroy = dm_dp_mst_connector_destroy,
148 .reset = amdgpu_dm_connector_funcs_reset,
149 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
150 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
151 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
152 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
153 .late_register = amdgpu_dm_mst_connector_late_register,
154 .early_unregister = amdgpu_dm_mst_connector_early_unregister,
155 };
156
157 #if defined(CONFIG_DRM_AMD_DC_DCN)
validate_dsc_caps_on_connector(struct amdgpu_dm_connector * aconnector)158 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
159 {
160 struct dc_sink *dc_sink = aconnector->dc_sink;
161 struct drm_dp_mst_port *port = aconnector->port;
162 u8 dsc_caps[16] = { 0 };
163 u8 dsc_branch_dec_caps_raw[3] = { 0 }; // DSC branch decoder caps 0xA0 ~ 0xA2
164 u8 *dsc_branch_dec_caps = NULL;
165
166 aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
167 #if defined(CONFIG_HP_HOOK_WORKAROUND)
168 /*
169 * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs
170 * because it only check the dsc/fec caps of the "port variable" and not the dock
171 *
172 * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display
173 *
174 * Workaround: explicitly check the use case above and use the mst dock's aux as dsc_aux
175 *
176 */
177
178 if (!aconnector->dsc_aux && !port->parent->port_parent)
179 aconnector->dsc_aux = &aconnector->mst_port->dm_dp_aux.aux;
180 #endif
181 if (!aconnector->dsc_aux)
182 return false;
183
184 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0)
185 return false;
186
187 if (drm_dp_dpcd_read(aconnector->dsc_aux,
188 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, dsc_branch_dec_caps_raw, 3) == 3)
189 dsc_branch_dec_caps = dsc_branch_dec_caps_raw;
190
191 if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
192 dsc_caps, dsc_branch_dec_caps,
193 &dc_sink->dsc_caps.dsc_dec_caps))
194 return false;
195
196 return true;
197 }
198 #endif
199
dm_dp_mst_get_modes(struct drm_connector * connector)200 static int dm_dp_mst_get_modes(struct drm_connector *connector)
201 {
202 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
203 int ret = 0;
204
205 if (!aconnector)
206 return drm_add_edid_modes(connector, NULL);
207
208 if (!aconnector->edid) {
209 struct edid *edid;
210 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
211
212 if (!edid) {
213 drm_connector_update_edid_property(
214 &aconnector->base,
215 NULL);
216
217 DRM_DEBUG_KMS("Can't get EDID of %s. Add default remote sink.", connector->name);
218 if (!aconnector->dc_sink) {
219 struct dc_sink *dc_sink;
220 struct dc_sink_init_data init_params = {
221 .link = aconnector->dc_link,
222 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
223
224 dc_sink = dc_link_add_remote_sink(
225 aconnector->dc_link,
226 NULL,
227 0,
228 &init_params);
229
230 if (!dc_sink) {
231 DRM_ERROR("Unable to add a remote sink\n");
232 return 0;
233 }
234
235 dc_sink->priv = aconnector;
236 aconnector->dc_sink = dc_sink;
237 }
238
239 return ret;
240 }
241
242 aconnector->edid = edid;
243 }
244
245 if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) {
246 dc_sink_release(aconnector->dc_sink);
247 aconnector->dc_sink = NULL;
248 }
249
250 if (!aconnector->dc_sink) {
251 struct dc_sink *dc_sink;
252 struct dc_sink_init_data init_params = {
253 .link = aconnector->dc_link,
254 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
255 dc_sink = dc_link_add_remote_sink(
256 aconnector->dc_link,
257 (uint8_t *)aconnector->edid,
258 (aconnector->edid->extensions + 1) * EDID_LENGTH,
259 &init_params);
260
261 if (!dc_sink) {
262 DRM_ERROR("Unable to add a remote sink\n");
263 return 0;
264 }
265
266 dc_sink->priv = aconnector;
267 /* dc_link_add_remote_sink returns a new reference */
268 aconnector->dc_sink = dc_sink;
269
270 if (aconnector->dc_sink) {
271 amdgpu_dm_update_freesync_caps(
272 connector, aconnector->edid);
273
274 #if defined(CONFIG_DRM_AMD_DC_DCN)
275 if (!validate_dsc_caps_on_connector(aconnector))
276 memset(&aconnector->dc_sink->dsc_caps,
277 0, sizeof(aconnector->dc_sink->dsc_caps));
278 #endif
279 }
280 }
281
282 drm_connector_update_edid_property(
283 &aconnector->base, aconnector->edid);
284
285 ret = drm_add_edid_modes(connector, aconnector->edid);
286
287 return ret;
288 }
289
290 static struct drm_encoder *
dm_mst_atomic_best_encoder(struct drm_connector * connector,struct drm_atomic_state * state)291 dm_mst_atomic_best_encoder(struct drm_connector *connector,
292 struct drm_atomic_state *state)
293 {
294 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
295 connector);
296 struct drm_device *dev = connector->dev;
297 struct amdgpu_device *adev = drm_to_adev(dev);
298 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc);
299
300 return &adev->dm.mst_encoders[acrtc->crtc_id].base;
301 }
302
303 static int
dm_dp_mst_detect(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)304 dm_dp_mst_detect(struct drm_connector *connector,
305 struct drm_modeset_acquire_ctx *ctx, bool force)
306 {
307 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
308 struct amdgpu_dm_connector *master = aconnector->mst_port;
309
310 if (drm_connector_is_unregistered(connector))
311 return connector_status_disconnected;
312
313 return drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
314 aconnector->port);
315 }
316
dm_dp_mst_atomic_check(struct drm_connector * connector,struct drm_atomic_state * state)317 static int dm_dp_mst_atomic_check(struct drm_connector *connector,
318 struct drm_atomic_state *state)
319 {
320 struct drm_connector_state *new_conn_state =
321 drm_atomic_get_new_connector_state(state, connector);
322 struct drm_connector_state *old_conn_state =
323 drm_atomic_get_old_connector_state(state, connector);
324 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
325 struct drm_crtc_state *new_crtc_state;
326 struct drm_dp_mst_topology_mgr *mst_mgr;
327 struct drm_dp_mst_port *mst_port;
328
329 mst_port = aconnector->port;
330 mst_mgr = &aconnector->mst_port->mst_mgr;
331
332 if (!old_conn_state->crtc)
333 return 0;
334
335 if (new_conn_state->crtc) {
336 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
337 if (!new_crtc_state ||
338 !drm_atomic_crtc_needs_modeset(new_crtc_state) ||
339 new_crtc_state->enable)
340 return 0;
341 }
342
343 return drm_dp_atomic_release_vcpi_slots(state,
344 mst_mgr,
345 mst_port);
346 }
347
348 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
349 .get_modes = dm_dp_mst_get_modes,
350 .mode_valid = amdgpu_dm_connector_mode_valid,
351 .atomic_best_encoder = dm_mst_atomic_best_encoder,
352 .detect_ctx = dm_dp_mst_detect,
353 .atomic_check = dm_dp_mst_atomic_check,
354 };
355
amdgpu_dm_encoder_destroy(struct drm_encoder * encoder)356 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
357 {
358 drm_encoder_cleanup(encoder);
359 kfree(encoder);
360 }
361
362 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
363 .destroy = amdgpu_dm_encoder_destroy,
364 };
365
366 void
dm_dp_create_fake_mst_encoders(struct amdgpu_device * adev)367 dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev)
368 {
369 struct drm_device *dev = adev_to_drm(adev);
370 int i;
371
372 for (i = 0; i < adev->dm.display_indexes_num; i++) {
373 struct amdgpu_encoder *amdgpu_encoder = &adev->dm.mst_encoders[i];
374 struct drm_encoder *encoder = &amdgpu_encoder->base;
375
376 encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
377
378 drm_encoder_init(
379 dev,
380 &amdgpu_encoder->base,
381 &amdgpu_dm_encoder_funcs,
382 DRM_MODE_ENCODER_DPMST,
383 NULL);
384
385 drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
386 }
387 }
388
389 static struct drm_connector *
dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr * mgr,struct drm_dp_mst_port * port,const char * pathprop)390 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
391 struct drm_dp_mst_port *port,
392 const char *pathprop)
393 {
394 struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
395 struct drm_device *dev = master->base.dev;
396 struct amdgpu_device *adev = drm_to_adev(dev);
397 struct amdgpu_dm_connector *aconnector;
398 struct drm_connector *connector;
399 int i;
400
401 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
402 if (!aconnector)
403 return NULL;
404
405 connector = &aconnector->base;
406 aconnector->port = port;
407 aconnector->mst_port = master;
408
409 if (drm_connector_init(
410 dev,
411 connector,
412 &dm_dp_mst_connector_funcs,
413 DRM_MODE_CONNECTOR_DisplayPort)) {
414 kfree(aconnector);
415 return NULL;
416 }
417 drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
418
419 amdgpu_dm_connector_init_helper(
420 &adev->dm,
421 aconnector,
422 DRM_MODE_CONNECTOR_DisplayPort,
423 master->dc_link,
424 master->connector_id);
425
426 for (i = 0; i < adev->dm.display_indexes_num; i++) {
427 drm_connector_attach_encoder(&aconnector->base,
428 &adev->dm.mst_encoders[i].base);
429 }
430
431 connector->max_bpc_property = master->base.max_bpc_property;
432 if (connector->max_bpc_property)
433 drm_connector_attach_max_bpc_property(connector, 8, 16);
434
435 connector->vrr_capable_property = master->base.vrr_capable_property;
436 if (connector->vrr_capable_property)
437 drm_connector_attach_vrr_capable_property(connector);
438
439 drm_object_attach_property(
440 &connector->base,
441 dev->mode_config.path_property,
442 0);
443 drm_object_attach_property(
444 &connector->base,
445 dev->mode_config.tile_property,
446 0);
447
448 drm_connector_set_path_property(connector, pathprop);
449
450 /*
451 * Initialize connector state before adding the connectror to drm and
452 * framebuffer lists
453 */
454 amdgpu_dm_connector_funcs_reset(connector);
455
456 drm_dp_mst_get_port_malloc(port);
457
458 return connector;
459 }
460
461 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
462 .add_connector = dm_dp_add_mst_connector,
463 };
464
amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager * dm,struct amdgpu_dm_connector * aconnector,int link_index)465 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
466 struct amdgpu_dm_connector *aconnector,
467 int link_index)
468 {
469 struct dc_link_settings max_link_enc_cap = {0};
470
471 aconnector->dm_dp_aux.aux.name =
472 kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d",
473 link_index);
474 aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
475 aconnector->dm_dp_aux.aux.drm_dev = dm->ddev;
476 aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
477
478 drm_dp_aux_init(&aconnector->dm_dp_aux.aux);
479 drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux,
480 &aconnector->base);
481
482 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
483 return;
484
485 dc_link_dp_get_max_link_enc_cap(aconnector->dc_link, &max_link_enc_cap);
486 aconnector->mst_mgr.cbs = &dm_mst_cbs;
487 drm_dp_mst_topology_mgr_init(
488 &aconnector->mst_mgr,
489 adev_to_drm(dm->adev),
490 &aconnector->dm_dp_aux.aux,
491 16,
492 4,
493 max_link_enc_cap.lane_count,
494 drm_dp_bw_code_to_link_rate(max_link_enc_cap.link_rate),
495 aconnector->connector_id);
496
497 drm_connector_attach_dp_subconnector_property(&aconnector->base);
498 }
499
dm_mst_get_pbn_divider(struct dc_link * link)500 int dm_mst_get_pbn_divider(struct dc_link *link)
501 {
502 if (!link)
503 return 0;
504
505 return dc_link_bandwidth_kbps(link,
506 dc_link_get_link_cap(link)) / (8 * 1000 * 54);
507 }
508
509 #if defined(CONFIG_DRM_AMD_DC_DCN)
510
511 struct dsc_mst_fairness_params {
512 struct dc_crtc_timing *timing;
513 struct dc_sink *sink;
514 struct dc_dsc_bw_range bw_range;
515 bool compression_possible;
516 struct drm_dp_mst_port *port;
517 enum dsc_clock_force_state clock_force_enable;
518 uint32_t num_slices_h;
519 uint32_t num_slices_v;
520 uint32_t bpp_overwrite;
521 struct amdgpu_dm_connector *aconnector;
522 };
523
kbps_to_peak_pbn(int kbps)524 static int kbps_to_peak_pbn(int kbps)
525 {
526 u64 peak_kbps = kbps;
527
528 peak_kbps *= 1006;
529 peak_kbps = div_u64(peak_kbps, 1000);
530 return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
531 }
532
set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params * params,struct dsc_mst_fairness_vars * vars,int count)533 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,
534 struct dsc_mst_fairness_vars *vars,
535 int count)
536 {
537 int i;
538
539 for (i = 0; i < count; i++) {
540 memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
541 if (vars[i].dsc_enabled && dc_dsc_compute_config(
542 params[i].sink->ctx->dc->res_pool->dscs[0],
543 ¶ms[i].sink->dsc_caps.dsc_dec_caps,
544 params[i].sink->ctx->dc->debug.dsc_min_slice_height_override,
545 0,
546 0,
547 params[i].timing,
548 ¶ms[i].timing->dsc_cfg)) {
549 params[i].timing->flags.DSC = 1;
550
551 if (params[i].bpp_overwrite)
552 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite;
553 else
554 params[i].timing->dsc_cfg.bits_per_pixel = vars[i].bpp_x16;
555
556 if (params[i].num_slices_h)
557 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h;
558
559 if (params[i].num_slices_v)
560 params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v;
561 } else {
562 params[i].timing->flags.DSC = 0;
563 }
564 }
565 }
566
bpp_x16_from_pbn(struct dsc_mst_fairness_params param,int pbn)567 static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
568 {
569 struct dc_dsc_config dsc_config;
570 u64 kbps;
571
572 kbps = div_u64((u64)pbn * 994 * 8 * 54, 64);
573 dc_dsc_compute_config(
574 param.sink->ctx->dc->res_pool->dscs[0],
575 ¶m.sink->dsc_caps.dsc_dec_caps,
576 param.sink->ctx->dc->debug.dsc_min_slice_height_override,
577 0,
578 (int) kbps, param.timing, &dsc_config);
579
580 return dsc_config.bits_per_pixel;
581 }
582
increase_dsc_bpp(struct drm_atomic_state * state,struct dc_link * dc_link,struct dsc_mst_fairness_params * params,struct dsc_mst_fairness_vars * vars,int count)583 static void increase_dsc_bpp(struct drm_atomic_state *state,
584 struct dc_link *dc_link,
585 struct dsc_mst_fairness_params *params,
586 struct dsc_mst_fairness_vars *vars,
587 int count)
588 {
589 int i;
590 bool bpp_increased[MAX_PIPES];
591 int initial_slack[MAX_PIPES];
592 int min_initial_slack;
593 int next_index;
594 int remaining_to_increase = 0;
595 int pbn_per_timeslot;
596 int link_timeslots_used;
597 int fair_pbn_alloc;
598
599 pbn_per_timeslot = dm_mst_get_pbn_divider(dc_link);
600
601 for (i = 0; i < count; i++) {
602 if (vars[i].dsc_enabled) {
603 initial_slack[i] = kbps_to_peak_pbn(params[i].bw_range.max_kbps) - vars[i].pbn;
604 bpp_increased[i] = false;
605 remaining_to_increase += 1;
606 } else {
607 initial_slack[i] = 0;
608 bpp_increased[i] = true;
609 }
610 }
611
612 while (remaining_to_increase) {
613 next_index = -1;
614 min_initial_slack = -1;
615 for (i = 0; i < count; i++) {
616 if (!bpp_increased[i]) {
617 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) {
618 min_initial_slack = initial_slack[i];
619 next_index = i;
620 }
621 }
622 }
623
624 if (next_index == -1)
625 break;
626
627 link_timeslots_used = 0;
628
629 for (i = 0; i < count; i++)
630 link_timeslots_used += DIV_ROUND_UP(vars[i].pbn, pbn_per_timeslot);
631
632 fair_pbn_alloc = (63 - link_timeslots_used) / remaining_to_increase * pbn_per_timeslot;
633
634 if (initial_slack[next_index] > fair_pbn_alloc) {
635 vars[next_index].pbn += fair_pbn_alloc;
636 if (drm_dp_atomic_find_vcpi_slots(state,
637 params[next_index].port->mgr,
638 params[next_index].port,
639 vars[next_index].pbn,
640 pbn_per_timeslot) < 0)
641 return;
642 if (!drm_dp_mst_atomic_check(state)) {
643 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
644 } else {
645 vars[next_index].pbn -= fair_pbn_alloc;
646 if (drm_dp_atomic_find_vcpi_slots(state,
647 params[next_index].port->mgr,
648 params[next_index].port,
649 vars[next_index].pbn,
650 pbn_per_timeslot) < 0)
651 return;
652 }
653 } else {
654 vars[next_index].pbn += initial_slack[next_index];
655 if (drm_dp_atomic_find_vcpi_slots(state,
656 params[next_index].port->mgr,
657 params[next_index].port,
658 vars[next_index].pbn,
659 pbn_per_timeslot) < 0)
660 return;
661 if (!drm_dp_mst_atomic_check(state)) {
662 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
663 } else {
664 vars[next_index].pbn -= initial_slack[next_index];
665 if (drm_dp_atomic_find_vcpi_slots(state,
666 params[next_index].port->mgr,
667 params[next_index].port,
668 vars[next_index].pbn,
669 pbn_per_timeslot) < 0)
670 return;
671 }
672 }
673
674 bpp_increased[next_index] = true;
675 remaining_to_increase--;
676 }
677 }
678
try_disable_dsc(struct drm_atomic_state * state,struct dc_link * dc_link,struct dsc_mst_fairness_params * params,struct dsc_mst_fairness_vars * vars,int count)679 static void try_disable_dsc(struct drm_atomic_state *state,
680 struct dc_link *dc_link,
681 struct dsc_mst_fairness_params *params,
682 struct dsc_mst_fairness_vars *vars,
683 int count)
684 {
685 int i;
686 bool tried[MAX_PIPES];
687 int kbps_increase[MAX_PIPES];
688 int max_kbps_increase;
689 int next_index;
690 int remaining_to_try = 0;
691
692 for (i = 0; i < count; i++) {
693 if (vars[i].dsc_enabled
694 && vars[i].bpp_x16 == params[i].bw_range.max_target_bpp_x16
695 && params[i].clock_force_enable == DSC_CLK_FORCE_DEFAULT) {
696 kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps;
697 tried[i] = false;
698 remaining_to_try += 1;
699 } else {
700 kbps_increase[i] = 0;
701 tried[i] = true;
702 }
703 }
704
705 while (remaining_to_try) {
706 next_index = -1;
707 max_kbps_increase = -1;
708 for (i = 0; i < count; i++) {
709 if (!tried[i]) {
710 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) {
711 max_kbps_increase = kbps_increase[i];
712 next_index = i;
713 }
714 }
715 }
716
717 if (next_index == -1)
718 break;
719
720 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps);
721 if (drm_dp_atomic_find_vcpi_slots(state,
722 params[next_index].port->mgr,
723 params[next_index].port,
724 vars[next_index].pbn,
725 dm_mst_get_pbn_divider(dc_link)) < 0)
726 return;
727
728 if (!drm_dp_mst_atomic_check(state)) {
729 vars[next_index].dsc_enabled = false;
730 vars[next_index].bpp_x16 = 0;
731 } else {
732 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps);
733 if (drm_dp_atomic_find_vcpi_slots(state,
734 params[next_index].port->mgr,
735 params[next_index].port,
736 vars[next_index].pbn,
737 dm_mst_get_pbn_divider(dc_link)) < 0)
738 return;
739 }
740
741 tried[next_index] = true;
742 remaining_to_try--;
743 }
744 }
745
compute_mst_dsc_configs_for_link(struct drm_atomic_state * state,struct dc_state * dc_state,struct dc_link * dc_link,struct dsc_mst_fairness_vars * vars)746 static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
747 struct dc_state *dc_state,
748 struct dc_link *dc_link,
749 struct dsc_mst_fairness_vars *vars)
750 {
751 int i;
752 struct dc_stream_state *stream;
753 struct dsc_mst_fairness_params params[MAX_PIPES];
754 struct amdgpu_dm_connector *aconnector;
755 int count = 0;
756 bool debugfs_overwrite = false;
757
758 memset(params, 0, sizeof(params));
759
760 /* Set up params */
761 for (i = 0; i < dc_state->stream_count; i++) {
762 struct dc_dsc_policy dsc_policy = {0};
763
764 stream = dc_state->streams[i];
765
766 if (stream->link != dc_link)
767 continue;
768
769 stream->timing.flags.DSC = 0;
770
771 params[count].timing = &stream->timing;
772 params[count].sink = stream->sink;
773 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
774 params[count].aconnector = aconnector;
775 params[count].port = aconnector->port;
776 params[count].clock_force_enable = aconnector->dsc_settings.dsc_force_enable;
777 if (params[count].clock_force_enable == DSC_CLK_FORCE_ENABLE)
778 debugfs_overwrite = true;
779 params[count].num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
780 params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
781 params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel;
782 params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
783 dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy);
784 if (!dc_dsc_compute_bandwidth_range(
785 stream->sink->ctx->dc->res_pool->dscs[0],
786 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
787 dsc_policy.min_target_bpp * 16,
788 dsc_policy.max_target_bpp * 16,
789 &stream->sink->dsc_caps.dsc_dec_caps,
790 &stream->timing, ¶ms[count].bw_range))
791 params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
792
793 count++;
794 }
795 /* Try no compression */
796 for (i = 0; i < count; i++) {
797 vars[i].aconnector = params[i].aconnector;
798 vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
799 vars[i].dsc_enabled = false;
800 vars[i].bpp_x16 = 0;
801 if (drm_dp_atomic_find_vcpi_slots(state,
802 params[i].port->mgr,
803 params[i].port,
804 vars[i].pbn,
805 dm_mst_get_pbn_divider(dc_link)) < 0)
806 return false;
807 }
808 if (!drm_dp_mst_atomic_check(state) && !debugfs_overwrite) {
809 set_dsc_configs_from_fairness_vars(params, vars, count);
810 return true;
811 }
812
813 /* Try max compression */
814 for (i = 0; i < count; i++) {
815 if (params[i].compression_possible && params[i].clock_force_enable != DSC_CLK_FORCE_DISABLE) {
816 vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps);
817 vars[i].dsc_enabled = true;
818 vars[i].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
819 if (drm_dp_atomic_find_vcpi_slots(state,
820 params[i].port->mgr,
821 params[i].port,
822 vars[i].pbn,
823 dm_mst_get_pbn_divider(dc_link)) < 0)
824 return false;
825 } else {
826 vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
827 vars[i].dsc_enabled = false;
828 vars[i].bpp_x16 = 0;
829 if (drm_dp_atomic_find_vcpi_slots(state,
830 params[i].port->mgr,
831 params[i].port,
832 vars[i].pbn,
833 dm_mst_get_pbn_divider(dc_link)) < 0)
834 return false;
835 }
836 }
837 if (drm_dp_mst_atomic_check(state))
838 return false;
839
840 /* Optimize degree of compression */
841 increase_dsc_bpp(state, dc_link, params, vars, count);
842
843 try_disable_dsc(state, dc_link, params, vars, count);
844
845 set_dsc_configs_from_fairness_vars(params, vars, count);
846
847 return true;
848 }
849
compute_mst_dsc_configs_for_state(struct drm_atomic_state * state,struct dc_state * dc_state,struct dsc_mst_fairness_vars * vars)850 bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
851 struct dc_state *dc_state,
852 struct dsc_mst_fairness_vars *vars)
853 {
854 int i, j;
855 struct dc_stream_state *stream;
856 bool computed_streams[MAX_PIPES];
857 struct amdgpu_dm_connector *aconnector;
858
859 for (i = 0; i < dc_state->stream_count; i++)
860 computed_streams[i] = false;
861
862 for (i = 0; i < dc_state->stream_count; i++) {
863 stream = dc_state->streams[i];
864
865 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
866 continue;
867
868 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
869
870 if (!aconnector || !aconnector->dc_sink)
871 continue;
872
873 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
874 continue;
875
876 if (computed_streams[i])
877 continue;
878
879 if (dcn20_remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK)
880 return false;
881
882 mutex_lock(&aconnector->mst_mgr.lock);
883 if (!compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars)) {
884 mutex_unlock(&aconnector->mst_mgr.lock);
885 return false;
886 }
887 mutex_unlock(&aconnector->mst_mgr.lock);
888
889 for (j = 0; j < dc_state->stream_count; j++) {
890 if (dc_state->streams[j]->link == stream->link)
891 computed_streams[j] = true;
892 }
893 }
894
895 for (i = 0; i < dc_state->stream_count; i++) {
896 stream = dc_state->streams[i];
897
898 if (stream->timing.flags.DSC == 1)
899 if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK)
900 return false;
901 }
902
903 return true;
904 }
905
906 #endif
907
