1 /*
2 * TI DaVinci DM355 chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12 #include <linux/clk-provider.h>
13 #include <linux/clk/davinci.h>
14 #include <linux/clkdev.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/dmaengine.h>
17 #include <linux/init.h>
18 #include <linux/platform_data/edma.h>
19 #include <linux/platform_data/gpio-davinci.h>
20 #include <linux/platform_data/spi-davinci.h>
21 #include <linux/platform_device.h>
22 #include <linux/serial_8250.h>
23 #include <linux/spi/spi.h>
24
25 #include <asm/mach/map.h>
26
27 #include <mach/common.h>
28 #include <mach/cputype.h>
29 #include <mach/irqs.h>
30 #include <mach/mux.h>
31 #include <mach/serial.h>
32 #include <mach/time.h>
33
34 #include "asp.h"
35 #include "davinci.h"
36 #include "mux.h"
37
38 #define DM355_UART2_BASE (IO_PHYS + 0x206000)
39 #define DM355_OSD_BASE (IO_PHYS + 0x70200)
40 #define DM355_VENC_BASE (IO_PHYS + 0x70400)
41
42 /*
43 * Device specific clocks
44 */
45 #define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */
46
47 static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
48
49 static struct resource dm355_spi0_resources[] = {
50 {
51 .start = 0x01c66000,
52 .end = 0x01c667ff,
53 .flags = IORESOURCE_MEM,
54 },
55 {
56 .start = IRQ_DM355_SPINT0_0,
57 .flags = IORESOURCE_IRQ,
58 },
59 };
60
61 static struct davinci_spi_platform_data dm355_spi0_pdata = {
62 .version = SPI_VERSION_1,
63 .num_chipselect = 2,
64 .cshold_bug = true,
65 .dma_event_q = EVENTQ_1,
66 .prescaler_limit = 1,
67 };
68 static struct platform_device dm355_spi0_device = {
69 .name = "spi_davinci",
70 .id = 0,
71 .dev = {
72 .dma_mask = &dm355_spi0_dma_mask,
73 .coherent_dma_mask = DMA_BIT_MASK(32),
74 .platform_data = &dm355_spi0_pdata,
75 },
76 .num_resources = ARRAY_SIZE(dm355_spi0_resources),
77 .resource = dm355_spi0_resources,
78 };
79
dm355_init_spi0(unsigned chipselect_mask,const struct spi_board_info * info,unsigned len)80 void __init dm355_init_spi0(unsigned chipselect_mask,
81 const struct spi_board_info *info, unsigned len)
82 {
83 /* for now, assume we need MISO */
84 davinci_cfg_reg(DM355_SPI0_SDI);
85
86 /* not all slaves will be wired up */
87 if (chipselect_mask & BIT(0))
88 davinci_cfg_reg(DM355_SPI0_SDENA0);
89 if (chipselect_mask & BIT(1))
90 davinci_cfg_reg(DM355_SPI0_SDENA1);
91
92 spi_register_board_info(info, len);
93
94 platform_device_register(&dm355_spi0_device);
95 }
96
97 /*----------------------------------------------------------------------*/
98
99 #define INTMUX 0x18
100 #define EVTMUX 0x1c
101
102 /*
103 * Device specific mux setup
104 *
105 * soc description mux mode mode mux dbg
106 * reg offset mask mode
107 */
108 static const struct mux_config dm355_pins[] = {
109 #ifdef CONFIG_DAVINCI_MUX
110 MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false)
111
112 MUX_CFG(DM355, SD1_CLK, 3, 6, 1, 1, false)
113 MUX_CFG(DM355, SD1_CMD, 3, 7, 1, 1, false)
114 MUX_CFG(DM355, SD1_DATA3, 3, 8, 3, 1, false)
115 MUX_CFG(DM355, SD1_DATA2, 3, 10, 3, 1, false)
116 MUX_CFG(DM355, SD1_DATA1, 3, 12, 3, 1, false)
117 MUX_CFG(DM355, SD1_DATA0, 3, 14, 3, 1, false)
118
119 MUX_CFG(DM355, I2C_SDA, 3, 19, 1, 1, false)
120 MUX_CFG(DM355, I2C_SCL, 3, 20, 1, 1, false)
121
122 MUX_CFG(DM355, MCBSP0_BDX, 3, 0, 1, 1, false)
123 MUX_CFG(DM355, MCBSP0_X, 3, 1, 1, 1, false)
124 MUX_CFG(DM355, MCBSP0_BFSX, 3, 2, 1, 1, false)
125 MUX_CFG(DM355, MCBSP0_BDR, 3, 3, 1, 1, false)
126 MUX_CFG(DM355, MCBSP0_R, 3, 4, 1, 1, false)
127 MUX_CFG(DM355, MCBSP0_BFSR, 3, 5, 1, 1, false)
128
129 MUX_CFG(DM355, SPI0_SDI, 4, 1, 1, 0, false)
130 MUX_CFG(DM355, SPI0_SDENA0, 4, 0, 1, 0, false)
131 MUX_CFG(DM355, SPI0_SDENA1, 3, 28, 1, 1, false)
132
133 INT_CFG(DM355, INT_EDMA_CC, 2, 1, 1, false)
134 INT_CFG(DM355, INT_EDMA_TC0_ERR, 3, 1, 1, false)
135 INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false)
136
137 EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false)
138 EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false)
139 EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false)
140
141 MUX_CFG(DM355, VOUT_FIELD, 1, 18, 3, 1, false)
142 MUX_CFG(DM355, VOUT_FIELD_G70, 1, 18, 3, 0, false)
143 MUX_CFG(DM355, VOUT_HVSYNC, 1, 16, 1, 0, false)
144 MUX_CFG(DM355, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
145 MUX_CFG(DM355, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
146
147 MUX_CFG(DM355, VIN_PCLK, 0, 14, 1, 1, false)
148 MUX_CFG(DM355, VIN_CAM_WEN, 0, 13, 1, 1, false)
149 MUX_CFG(DM355, VIN_CAM_VD, 0, 12, 1, 1, false)
150 MUX_CFG(DM355, VIN_CAM_HD, 0, 11, 1, 1, false)
151 MUX_CFG(DM355, VIN_YIN_EN, 0, 10, 1, 1, false)
152 MUX_CFG(DM355, VIN_CINL_EN, 0, 0, 0xff, 0x55, false)
153 MUX_CFG(DM355, VIN_CINH_EN, 0, 8, 3, 3, false)
154 #endif
155 };
156
157 static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
158 [IRQ_DM355_CCDC_VDINT0] = 2,
159 [IRQ_DM355_CCDC_VDINT1] = 6,
160 [IRQ_DM355_CCDC_VDINT2] = 6,
161 [IRQ_DM355_IPIPE_HST] = 6,
162 [IRQ_DM355_H3AINT] = 6,
163 [IRQ_DM355_IPIPE_SDR] = 6,
164 [IRQ_DM355_IPIPEIFINT] = 6,
165 [IRQ_DM355_OSDINT] = 7,
166 [IRQ_DM355_VENCINT] = 6,
167 [IRQ_ASQINT] = 6,
168 [IRQ_IMXINT] = 6,
169 [IRQ_USBINT] = 4,
170 [IRQ_DM355_RTOINT] = 4,
171 [IRQ_DM355_UARTINT2] = 7,
172 [IRQ_DM355_TINT6] = 7,
173 [IRQ_CCINT0] = 5, /* dma */
174 [IRQ_CCERRINT] = 5, /* dma */
175 [IRQ_TCERRINT0] = 5, /* dma */
176 [IRQ_TCERRINT] = 5, /* dma */
177 [IRQ_DM355_SPINT2_1] = 7,
178 [IRQ_DM355_TINT7] = 4,
179 [IRQ_DM355_SDIOINT0] = 7,
180 [IRQ_MBXINT] = 7,
181 [IRQ_MBRINT] = 7,
182 [IRQ_MMCINT] = 7,
183 [IRQ_DM355_MMCINT1] = 7,
184 [IRQ_DM355_PWMINT3] = 7,
185 [IRQ_DDRINT] = 7,
186 [IRQ_AEMIFINT] = 7,
187 [IRQ_DM355_SDIOINT1] = 4,
188 [IRQ_TINT0_TINT12] = 2, /* clockevent */
189 [IRQ_TINT0_TINT34] = 2, /* clocksource */
190 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
191 [IRQ_TINT1_TINT34] = 7, /* system tick */
192 [IRQ_PWMINT0] = 7,
193 [IRQ_PWMINT1] = 7,
194 [IRQ_PWMINT2] = 7,
195 [IRQ_I2C] = 3,
196 [IRQ_UARTINT0] = 3,
197 [IRQ_UARTINT1] = 3,
198 [IRQ_DM355_SPINT0_0] = 3,
199 [IRQ_DM355_SPINT0_1] = 3,
200 [IRQ_DM355_GPIO0] = 3,
201 [IRQ_DM355_GPIO1] = 7,
202 [IRQ_DM355_GPIO2] = 4,
203 [IRQ_DM355_GPIO3] = 4,
204 [IRQ_DM355_GPIO4] = 7,
205 [IRQ_DM355_GPIO5] = 7,
206 [IRQ_DM355_GPIO6] = 7,
207 [IRQ_DM355_GPIO7] = 7,
208 [IRQ_DM355_GPIO8] = 7,
209 [IRQ_DM355_GPIO9] = 7,
210 [IRQ_DM355_GPIOBNK0] = 7,
211 [IRQ_DM355_GPIOBNK1] = 7,
212 [IRQ_DM355_GPIOBNK2] = 7,
213 [IRQ_DM355_GPIOBNK3] = 7,
214 [IRQ_DM355_GPIOBNK4] = 7,
215 [IRQ_DM355_GPIOBNK5] = 7,
216 [IRQ_DM355_GPIOBNK6] = 7,
217 [IRQ_COMMTX] = 7,
218 [IRQ_COMMRX] = 7,
219 [IRQ_EMUINT] = 7,
220 };
221
222 /*----------------------------------------------------------------------*/
223
224 static s8 queue_priority_mapping[][2] = {
225 /* {event queue no, Priority} */
226 {0, 3},
227 {1, 7},
228 {-1, -1},
229 };
230
231 static const struct dma_slave_map dm355_edma_map[] = {
232 { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 2) },
233 { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 3) },
234 { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 8) },
235 { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 9) },
236 { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
237 { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
238 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
239 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
240 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
241 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
242 { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
243 { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
244 { "dm6441-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
245 { "dm6441-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
246 };
247
248 static struct edma_soc_info dm355_edma_pdata = {
249 .queue_priority_mapping = queue_priority_mapping,
250 .default_queue = EVENTQ_1,
251 .slave_map = dm355_edma_map,
252 .slavecnt = ARRAY_SIZE(dm355_edma_map),
253 };
254
255 static struct resource edma_resources[] = {
256 {
257 .name = "edma3_cc",
258 .start = 0x01c00000,
259 .end = 0x01c00000 + SZ_64K - 1,
260 .flags = IORESOURCE_MEM,
261 },
262 {
263 .name = "edma3_tc0",
264 .start = 0x01c10000,
265 .end = 0x01c10000 + SZ_1K - 1,
266 .flags = IORESOURCE_MEM,
267 },
268 {
269 .name = "edma3_tc1",
270 .start = 0x01c10400,
271 .end = 0x01c10400 + SZ_1K - 1,
272 .flags = IORESOURCE_MEM,
273 },
274 {
275 .name = "edma3_ccint",
276 .start = IRQ_CCINT0,
277 .flags = IORESOURCE_IRQ,
278 },
279 {
280 .name = "edma3_ccerrint",
281 .start = IRQ_CCERRINT,
282 .flags = IORESOURCE_IRQ,
283 },
284 /* not using (or muxing) TC*_ERR */
285 };
286
287 static const struct platform_device_info dm355_edma_device __initconst = {
288 .name = "edma",
289 .id = 0,
290 .dma_mask = DMA_BIT_MASK(32),
291 .res = edma_resources,
292 .num_res = ARRAY_SIZE(edma_resources),
293 .data = &dm355_edma_pdata,
294 .size_data = sizeof(dm355_edma_pdata),
295 };
296
297 static struct resource dm355_asp1_resources[] = {
298 {
299 .name = "mpu",
300 .start = DAVINCI_ASP1_BASE,
301 .end = DAVINCI_ASP1_BASE + SZ_8K - 1,
302 .flags = IORESOURCE_MEM,
303 },
304 {
305 .start = DAVINCI_DMA_ASP1_TX,
306 .end = DAVINCI_DMA_ASP1_TX,
307 .flags = IORESOURCE_DMA,
308 },
309 {
310 .start = DAVINCI_DMA_ASP1_RX,
311 .end = DAVINCI_DMA_ASP1_RX,
312 .flags = IORESOURCE_DMA,
313 },
314 };
315
316 static struct platform_device dm355_asp1_device = {
317 .name = "davinci-mcbsp",
318 .id = 1,
319 .num_resources = ARRAY_SIZE(dm355_asp1_resources),
320 .resource = dm355_asp1_resources,
321 };
322
dm355_ccdc_setup_pinmux(void)323 static void dm355_ccdc_setup_pinmux(void)
324 {
325 davinci_cfg_reg(DM355_VIN_PCLK);
326 davinci_cfg_reg(DM355_VIN_CAM_WEN);
327 davinci_cfg_reg(DM355_VIN_CAM_VD);
328 davinci_cfg_reg(DM355_VIN_CAM_HD);
329 davinci_cfg_reg(DM355_VIN_YIN_EN);
330 davinci_cfg_reg(DM355_VIN_CINL_EN);
331 davinci_cfg_reg(DM355_VIN_CINH_EN);
332 }
333
334 static struct resource dm355_vpss_resources[] = {
335 {
336 /* VPSS BL Base address */
337 .name = "vpss",
338 .start = 0x01c70800,
339 .end = 0x01c70800 + 0xff,
340 .flags = IORESOURCE_MEM,
341 },
342 {
343 /* VPSS CLK Base address */
344 .name = "vpss",
345 .start = 0x01c70000,
346 .end = 0x01c70000 + 0xf,
347 .flags = IORESOURCE_MEM,
348 },
349 };
350
351 static struct platform_device dm355_vpss_device = {
352 .name = "vpss",
353 .id = -1,
354 .dev.platform_data = "dm355_vpss",
355 .num_resources = ARRAY_SIZE(dm355_vpss_resources),
356 .resource = dm355_vpss_resources,
357 };
358
359 static struct resource vpfe_resources[] = {
360 {
361 .start = IRQ_VDINT0,
362 .end = IRQ_VDINT0,
363 .flags = IORESOURCE_IRQ,
364 },
365 {
366 .start = IRQ_VDINT1,
367 .end = IRQ_VDINT1,
368 .flags = IORESOURCE_IRQ,
369 },
370 };
371
372 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
373 static struct resource dm355_ccdc_resource[] = {
374 /* CCDC Base address */
375 {
376 .flags = IORESOURCE_MEM,
377 .start = 0x01c70600,
378 .end = 0x01c70600 + 0x1ff,
379 },
380 };
381 static struct platform_device dm355_ccdc_dev = {
382 .name = "dm355_ccdc",
383 .id = -1,
384 .num_resources = ARRAY_SIZE(dm355_ccdc_resource),
385 .resource = dm355_ccdc_resource,
386 .dev = {
387 .dma_mask = &vpfe_capture_dma_mask,
388 .coherent_dma_mask = DMA_BIT_MASK(32),
389 .platform_data = dm355_ccdc_setup_pinmux,
390 },
391 };
392
393 static struct platform_device vpfe_capture_dev = {
394 .name = CAPTURE_DRV_NAME,
395 .id = -1,
396 .num_resources = ARRAY_SIZE(vpfe_resources),
397 .resource = vpfe_resources,
398 .dev = {
399 .dma_mask = &vpfe_capture_dma_mask,
400 .coherent_dma_mask = DMA_BIT_MASK(32),
401 },
402 };
403
404 static struct resource dm355_osd_resources[] = {
405 {
406 .start = DM355_OSD_BASE,
407 .end = DM355_OSD_BASE + 0x17f,
408 .flags = IORESOURCE_MEM,
409 },
410 };
411
412 static struct platform_device dm355_osd_dev = {
413 .name = DM355_VPBE_OSD_SUBDEV_NAME,
414 .id = -1,
415 .num_resources = ARRAY_SIZE(dm355_osd_resources),
416 .resource = dm355_osd_resources,
417 .dev = {
418 .dma_mask = &vpfe_capture_dma_mask,
419 .coherent_dma_mask = DMA_BIT_MASK(32),
420 },
421 };
422
423 static struct resource dm355_venc_resources[] = {
424 {
425 .start = IRQ_VENCINT,
426 .end = IRQ_VENCINT,
427 .flags = IORESOURCE_IRQ,
428 },
429 /* venc registers io space */
430 {
431 .start = DM355_VENC_BASE,
432 .end = DM355_VENC_BASE + 0x17f,
433 .flags = IORESOURCE_MEM,
434 },
435 /* VDAC config register io space */
436 {
437 .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
438 .end = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
439 .flags = IORESOURCE_MEM,
440 },
441 };
442
443 static struct resource dm355_v4l2_disp_resources[] = {
444 {
445 .start = IRQ_VENCINT,
446 .end = IRQ_VENCINT,
447 .flags = IORESOURCE_IRQ,
448 },
449 /* venc registers io space */
450 {
451 .start = DM355_VENC_BASE,
452 .end = DM355_VENC_BASE + 0x17f,
453 .flags = IORESOURCE_MEM,
454 },
455 };
456
dm355_vpbe_setup_pinmux(u32 if_type,int field)457 static int dm355_vpbe_setup_pinmux(u32 if_type, int field)
458 {
459 switch (if_type) {
460 case MEDIA_BUS_FMT_SGRBG8_1X8:
461 davinci_cfg_reg(DM355_VOUT_FIELD_G70);
462 break;
463 case MEDIA_BUS_FMT_YUYV10_1X20:
464 if (field)
465 davinci_cfg_reg(DM355_VOUT_FIELD);
466 else
467 davinci_cfg_reg(DM355_VOUT_FIELD_G70);
468 break;
469 default:
470 return -EINVAL;
471 }
472
473 davinci_cfg_reg(DM355_VOUT_COUTL_EN);
474 davinci_cfg_reg(DM355_VOUT_COUTH_EN);
475
476 return 0;
477 }
478
dm355_venc_setup_clock(enum vpbe_enc_timings_type type,unsigned int pclock)479 static int dm355_venc_setup_clock(enum vpbe_enc_timings_type type,
480 unsigned int pclock)
481 {
482 void __iomem *vpss_clk_ctrl_reg;
483
484 vpss_clk_ctrl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
485
486 switch (type) {
487 case VPBE_ENC_STD:
488 writel(VPSS_DACCLKEN_ENABLE | VPSS_VENCCLKEN_ENABLE,
489 vpss_clk_ctrl_reg);
490 break;
491 case VPBE_ENC_DV_TIMINGS:
492 if (pclock > 27000000)
493 /*
494 * For HD, use external clock source since we cannot
495 * support HD mode with internal clocks.
496 */
497 writel(VPSS_MUXSEL_EXTCLK_ENABLE, vpss_clk_ctrl_reg);
498 break;
499 default:
500 return -EINVAL;
501 }
502
503 return 0;
504 }
505
506 static struct platform_device dm355_vpbe_display = {
507 .name = "vpbe-v4l2",
508 .id = -1,
509 .num_resources = ARRAY_SIZE(dm355_v4l2_disp_resources),
510 .resource = dm355_v4l2_disp_resources,
511 .dev = {
512 .dma_mask = &vpfe_capture_dma_mask,
513 .coherent_dma_mask = DMA_BIT_MASK(32),
514 },
515 };
516
517 static struct venc_platform_data dm355_venc_pdata = {
518 .setup_pinmux = dm355_vpbe_setup_pinmux,
519 .setup_clock = dm355_venc_setup_clock,
520 };
521
522 static struct platform_device dm355_venc_dev = {
523 .name = DM355_VPBE_VENC_SUBDEV_NAME,
524 .id = -1,
525 .num_resources = ARRAY_SIZE(dm355_venc_resources),
526 .resource = dm355_venc_resources,
527 .dev = {
528 .dma_mask = &vpfe_capture_dma_mask,
529 .coherent_dma_mask = DMA_BIT_MASK(32),
530 .platform_data = (void *)&dm355_venc_pdata,
531 },
532 };
533
534 static struct platform_device dm355_vpbe_dev = {
535 .name = "vpbe_controller",
536 .id = -1,
537 .dev = {
538 .dma_mask = &vpfe_capture_dma_mask,
539 .coherent_dma_mask = DMA_BIT_MASK(32),
540 },
541 };
542
543 static struct resource dm355_gpio_resources[] = {
544 { /* registers */
545 .start = DAVINCI_GPIO_BASE,
546 .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
547 .flags = IORESOURCE_MEM,
548 },
549 { /* interrupt */
550 .start = IRQ_DM355_GPIOBNK0,
551 .end = IRQ_DM355_GPIOBNK6,
552 .flags = IORESOURCE_IRQ,
553 },
554 };
555
556 static struct davinci_gpio_platform_data dm355_gpio_platform_data = {
557 .ngpio = 104,
558 };
559
dm355_gpio_register(void)560 int __init dm355_gpio_register(void)
561 {
562 return davinci_gpio_register(dm355_gpio_resources,
563 ARRAY_SIZE(dm355_gpio_resources),
564 &dm355_gpio_platform_data);
565 }
566 /*----------------------------------------------------------------------*/
567
568 static struct map_desc dm355_io_desc[] = {
569 {
570 .virtual = IO_VIRT,
571 .pfn = __phys_to_pfn(IO_PHYS),
572 .length = IO_SIZE,
573 .type = MT_DEVICE
574 },
575 };
576
577 /* Contents of JTAG ID register used to identify exact cpu type */
578 static struct davinci_id dm355_ids[] = {
579 {
580 .variant = 0x0,
581 .part_no = 0xb73b,
582 .manufacturer = 0x00f,
583 .cpu_id = DAVINCI_CPU_ID_DM355,
584 .name = "dm355",
585 },
586 };
587
588 /*
589 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
590 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
591 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
592 * T1_TOP: Timer 1, top : <unused>
593 */
594 static struct davinci_timer_info dm355_timer_info = {
595 .timers = davinci_timer_instance,
596 .clockevent_id = T0_BOT,
597 .clocksource_id = T0_TOP,
598 };
599
600 static struct plat_serial8250_port dm355_serial0_platform_data[] = {
601 {
602 .mapbase = DAVINCI_UART0_BASE,
603 .irq = IRQ_UARTINT0,
604 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
605 UPF_IOREMAP,
606 .iotype = UPIO_MEM,
607 .regshift = 2,
608 },
609 {
610 .flags = 0,
611 }
612 };
613 static struct plat_serial8250_port dm355_serial1_platform_data[] = {
614 {
615 .mapbase = DAVINCI_UART1_BASE,
616 .irq = IRQ_UARTINT1,
617 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
618 UPF_IOREMAP,
619 .iotype = UPIO_MEM,
620 .regshift = 2,
621 },
622 {
623 .flags = 0,
624 }
625 };
626 static struct plat_serial8250_port dm355_serial2_platform_data[] = {
627 {
628 .mapbase = DM355_UART2_BASE,
629 .irq = IRQ_DM355_UARTINT2,
630 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
631 UPF_IOREMAP,
632 .iotype = UPIO_MEM,
633 .regshift = 2,
634 },
635 {
636 .flags = 0,
637 }
638 };
639
640 struct platform_device dm355_serial_device[] = {
641 {
642 .name = "serial8250",
643 .id = PLAT8250_DEV_PLATFORM,
644 .dev = {
645 .platform_data = dm355_serial0_platform_data,
646 }
647 },
648 {
649 .name = "serial8250",
650 .id = PLAT8250_DEV_PLATFORM1,
651 .dev = {
652 .platform_data = dm355_serial1_platform_data,
653 }
654 },
655 {
656 .name = "serial8250",
657 .id = PLAT8250_DEV_PLATFORM2,
658 .dev = {
659 .platform_data = dm355_serial2_platform_data,
660 }
661 },
662 {
663 }
664 };
665
666 static const struct davinci_soc_info davinci_soc_info_dm355 = {
667 .io_desc = dm355_io_desc,
668 .io_desc_num = ARRAY_SIZE(dm355_io_desc),
669 .jtag_id_reg = 0x01c40028,
670 .ids = dm355_ids,
671 .ids_num = ARRAY_SIZE(dm355_ids),
672 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
673 .pinmux_pins = dm355_pins,
674 .pinmux_pins_num = ARRAY_SIZE(dm355_pins),
675 .intc_base = DAVINCI_ARM_INTC_BASE,
676 .intc_type = DAVINCI_INTC_TYPE_AINTC,
677 .intc_irq_prios = dm355_default_priorities,
678 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
679 .timer_info = &dm355_timer_info,
680 .sram_dma = 0x00010000,
681 .sram_len = SZ_32K,
682 };
683
dm355_init_asp1(u32 evt_enable)684 void __init dm355_init_asp1(u32 evt_enable)
685 {
686 /* we don't use ASP1 IRQs, or we'd need to mux them ... */
687 if (evt_enable & ASP1_TX_EVT_EN)
688 davinci_cfg_reg(DM355_EVT8_ASP1_TX);
689
690 if (evt_enable & ASP1_RX_EVT_EN)
691 davinci_cfg_reg(DM355_EVT9_ASP1_RX);
692
693 platform_device_register(&dm355_asp1_device);
694 }
695
dm355_init(void)696 void __init dm355_init(void)
697 {
698 davinci_common_init(&davinci_soc_info_dm355);
699 davinci_map_sysmod();
700 }
701
dm355_init_time(void)702 void __init dm355_init_time(void)
703 {
704 void __iomem *pll1, *psc;
705 struct clk *clk;
706
707 clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM355_REF_FREQ);
708
709 pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
710 dm355_pll1_init(NULL, pll1, NULL);
711
712 psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
713 dm355_psc_init(NULL, psc);
714
715 clk = clk_get(NULL, "timer0");
716
717 davinci_timer_init(clk);
718 }
719
720 static struct resource dm355_pll2_resources[] = {
721 {
722 .start = DAVINCI_PLL2_BASE,
723 .end = DAVINCI_PLL2_BASE + SZ_1K - 1,
724 .flags = IORESOURCE_MEM,
725 },
726 };
727
728 static struct platform_device dm355_pll2_device = {
729 .name = "dm355-pll2",
730 .id = -1,
731 .resource = dm355_pll2_resources,
732 .num_resources = ARRAY_SIZE(dm355_pll2_resources),
733 };
734
dm355_register_clocks(void)735 void __init dm355_register_clocks(void)
736 {
737 /* PLL1 and PSC are registered in dm355_init_time() */
738 platform_device_register(&dm355_pll2_device);
739 }
740
dm355_init_video(struct vpfe_config * vpfe_cfg,struct vpbe_config * vpbe_cfg)741 int __init dm355_init_video(struct vpfe_config *vpfe_cfg,
742 struct vpbe_config *vpbe_cfg)
743 {
744 if (vpfe_cfg || vpbe_cfg)
745 platform_device_register(&dm355_vpss_device);
746
747 if (vpfe_cfg) {
748 vpfe_capture_dev.dev.platform_data = vpfe_cfg;
749 platform_device_register(&dm355_ccdc_dev);
750 platform_device_register(&vpfe_capture_dev);
751 }
752
753 if (vpbe_cfg) {
754 dm355_vpbe_dev.dev.platform_data = vpbe_cfg;
755 platform_device_register(&dm355_osd_dev);
756 platform_device_register(&dm355_venc_dev);
757 platform_device_register(&dm355_vpbe_dev);
758 platform_device_register(&dm355_vpbe_display);
759 }
760
761 return 0;
762 }
763
dm355_init_devices(void)764 static int __init dm355_init_devices(void)
765 {
766 struct platform_device *edma_pdev;
767 int ret = 0;
768
769 if (!cpu_is_davinci_dm355())
770 return 0;
771
772 davinci_cfg_reg(DM355_INT_EDMA_CC);
773 edma_pdev = platform_device_register_full(&dm355_edma_device);
774 if (IS_ERR(edma_pdev)) {
775 pr_warn("%s: Failed to register eDMA\n", __func__);
776 return PTR_ERR(edma_pdev);
777 }
778
779 ret = davinci_init_wdt();
780 if (ret)
781 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
782
783 return ret;
784 }
785 postcore_initcall(dm355_init_devices);
786
