1 /*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #define DSS_SUBSYS_NAME "DISPC"
24
25 #include <linux/kernel.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/vmalloc.h>
28 #include <linux/export.h>
29 #include <linux/clk.h>
30 #include <linux/io.h>
31 #include <linux/jiffies.h>
32 #include <linux/seq_file.h>
33 #include <linux/delay.h>
34 #include <linux/workqueue.h>
35 #include <linux/hardirq.h>
36 #include <linux/platform_device.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/sizes.h>
39 #include <linux/mfd/syscon.h>
40 #include <linux/regmap.h>
41 #include <linux/of.h>
42 #include <linux/component.h>
43
44 #include <video/omapfb_dss.h>
45
46 #include "dss.h"
47 #include "dss_features.h"
48 #include "dispc.h"
49
50 /* DISPC */
51 #define DISPC_SZ_REGS SZ_4K
52
53 enum omap_burst_size {
54 BURST_SIZE_X2 = 0,
55 BURST_SIZE_X4 = 1,
56 BURST_SIZE_X8 = 2,
57 };
58
59 #define REG_GET(idx, start, end) \
60 FLD_GET(dispc_read_reg(idx), start, end)
61
62 #define REG_FLD_MOD(idx, val, start, end) \
63 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
64
65 struct dispc_features {
66 u8 sw_start;
67 u8 fp_start;
68 u8 bp_start;
69 u16 sw_max;
70 u16 vp_max;
71 u16 hp_max;
72 u8 mgr_width_start;
73 u8 mgr_height_start;
74 u16 mgr_width_max;
75 u16 mgr_height_max;
76 unsigned long max_lcd_pclk;
77 unsigned long max_tv_pclk;
78 int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
79 const struct omap_video_timings *mgr_timings,
80 u16 width, u16 height, u16 out_width, u16 out_height,
81 enum omap_color_mode color_mode, bool *five_taps,
82 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
83 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
84 unsigned long (*calc_core_clk) (unsigned long pclk,
85 u16 width, u16 height, u16 out_width, u16 out_height,
86 bool mem_to_mem);
87 u8 num_fifos;
88
89 /* swap GFX & WB fifos */
90 bool gfx_fifo_workaround:1;
91
92 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
93 bool no_framedone_tv:1;
94
95 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
96 bool mstandby_workaround:1;
97
98 bool set_max_preload:1;
99
100 /* PIXEL_INC is not added to the last pixel of a line */
101 bool last_pixel_inc_missing:1;
102
103 /* POL_FREQ has ALIGN bit */
104 bool supports_sync_align:1;
105
106 bool has_writeback:1;
107 };
108
109 #define DISPC_MAX_NR_FIFOS 5
110
111 static struct {
112 struct platform_device *pdev;
113 void __iomem *base;
114
115 int irq;
116 irq_handler_t user_handler;
117 void *user_data;
118
119 unsigned long core_clk_rate;
120 unsigned long tv_pclk_rate;
121
122 u32 fifo_size[DISPC_MAX_NR_FIFOS];
123 /* maps which plane is using a fifo. fifo-id -> plane-id */
124 int fifo_assignment[DISPC_MAX_NR_FIFOS];
125
126 bool ctx_valid;
127 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
128
129 const struct dispc_features *feat;
130
131 bool is_enabled;
132
133 struct regmap *syscon_pol;
134 u32 syscon_pol_offset;
135
136 /* DISPC_CONTROL & DISPC_CONFIG lock*/
137 spinlock_t control_lock;
138 } dispc;
139
140 enum omap_color_component {
141 /* used for all color formats for OMAP3 and earlier
142 * and for RGB and Y color component on OMAP4
143 */
144 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
145 /* used for UV component for
146 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
147 * color formats on OMAP4
148 */
149 DISPC_COLOR_COMPONENT_UV = 1 << 1,
150 };
151
152 enum mgr_reg_fields {
153 DISPC_MGR_FLD_ENABLE,
154 DISPC_MGR_FLD_STNTFT,
155 DISPC_MGR_FLD_GO,
156 DISPC_MGR_FLD_TFTDATALINES,
157 DISPC_MGR_FLD_STALLMODE,
158 DISPC_MGR_FLD_TCKENABLE,
159 DISPC_MGR_FLD_TCKSELECTION,
160 DISPC_MGR_FLD_CPR,
161 DISPC_MGR_FLD_FIFOHANDCHECK,
162 /* used to maintain a count of the above fields */
163 DISPC_MGR_FLD_NUM,
164 };
165
166 struct dispc_reg_field {
167 u16 reg;
168 u8 high;
169 u8 low;
170 };
171
172 static const struct {
173 const char *name;
174 u32 vsync_irq;
175 u32 framedone_irq;
176 u32 sync_lost_irq;
177 struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
178 } mgr_desc[] = {
179 [OMAP_DSS_CHANNEL_LCD] = {
180 .name = "LCD",
181 .vsync_irq = DISPC_IRQ_VSYNC,
182 .framedone_irq = DISPC_IRQ_FRAMEDONE,
183 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
184 .reg_desc = {
185 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
186 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
187 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
188 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
189 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
190 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
191 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
192 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
193 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
194 },
195 },
196 [OMAP_DSS_CHANNEL_DIGIT] = {
197 .name = "DIGIT",
198 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
199 .framedone_irq = DISPC_IRQ_FRAMEDONETV,
200 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
201 .reg_desc = {
202 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
203 [DISPC_MGR_FLD_STNTFT] = { },
204 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
205 [DISPC_MGR_FLD_TFTDATALINES] = { },
206 [DISPC_MGR_FLD_STALLMODE] = { },
207 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
208 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
209 [DISPC_MGR_FLD_CPR] = { },
210 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
211 },
212 },
213 [OMAP_DSS_CHANNEL_LCD2] = {
214 .name = "LCD2",
215 .vsync_irq = DISPC_IRQ_VSYNC2,
216 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
217 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
218 .reg_desc = {
219 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
220 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
221 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
222 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
223 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
224 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
225 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
226 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
227 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
228 },
229 },
230 [OMAP_DSS_CHANNEL_LCD3] = {
231 .name = "LCD3",
232 .vsync_irq = DISPC_IRQ_VSYNC3,
233 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
234 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
235 .reg_desc = {
236 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
237 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
238 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
239 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
240 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
241 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
242 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
243 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
244 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
245 },
246 },
247 };
248
249 struct color_conv_coef {
250 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
251 int full_range;
252 };
253
254 static unsigned long dispc_fclk_rate(void);
255 static unsigned long dispc_core_clk_rate(void);
256 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
257 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
258
259 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
260 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
261
dispc_write_reg(const u16 idx,u32 val)262 static inline void dispc_write_reg(const u16 idx, u32 val)
263 {
264 __raw_writel(val, dispc.base + idx);
265 }
266
dispc_read_reg(const u16 idx)267 static inline u32 dispc_read_reg(const u16 idx)
268 {
269 return __raw_readl(dispc.base + idx);
270 }
271
mgr_fld_read(enum omap_channel channel,enum mgr_reg_fields regfld)272 static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
273 {
274 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
275 return REG_GET(rfld.reg, rfld.high, rfld.low);
276 }
277
mgr_fld_write(enum omap_channel channel,enum mgr_reg_fields regfld,int val)278 static void mgr_fld_write(enum omap_channel channel,
279 enum mgr_reg_fields regfld, int val) {
280 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
281 const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
282 unsigned long flags;
283
284 if (need_lock)
285 spin_lock_irqsave(&dispc.control_lock, flags);
286
287 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
288
289 if (need_lock)
290 spin_unlock_irqrestore(&dispc.control_lock, flags);
291 }
292
293 #define SR(reg) \
294 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
295 #define RR(reg) \
296 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
297
dispc_save_context(void)298 static void dispc_save_context(void)
299 {
300 int i, j;
301
302 DSSDBG("dispc_save_context\n");
303
304 SR(IRQENABLE);
305 SR(CONTROL);
306 SR(CONFIG);
307 SR(LINE_NUMBER);
308 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
309 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
310 SR(GLOBAL_ALPHA);
311 if (dss_has_feature(FEAT_MGR_LCD2)) {
312 SR(CONTROL2);
313 SR(CONFIG2);
314 }
315 if (dss_has_feature(FEAT_MGR_LCD3)) {
316 SR(CONTROL3);
317 SR(CONFIG3);
318 }
319
320 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
321 SR(DEFAULT_COLOR(i));
322 SR(TRANS_COLOR(i));
323 SR(SIZE_MGR(i));
324 if (i == OMAP_DSS_CHANNEL_DIGIT)
325 continue;
326 SR(TIMING_H(i));
327 SR(TIMING_V(i));
328 SR(POL_FREQ(i));
329 SR(DIVISORo(i));
330
331 SR(DATA_CYCLE1(i));
332 SR(DATA_CYCLE2(i));
333 SR(DATA_CYCLE3(i));
334
335 if (dss_has_feature(FEAT_CPR)) {
336 SR(CPR_COEF_R(i));
337 SR(CPR_COEF_G(i));
338 SR(CPR_COEF_B(i));
339 }
340 }
341
342 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
343 SR(OVL_BA0(i));
344 SR(OVL_BA1(i));
345 SR(OVL_POSITION(i));
346 SR(OVL_SIZE(i));
347 SR(OVL_ATTRIBUTES(i));
348 SR(OVL_FIFO_THRESHOLD(i));
349 SR(OVL_ROW_INC(i));
350 SR(OVL_PIXEL_INC(i));
351 if (dss_has_feature(FEAT_PRELOAD))
352 SR(OVL_PRELOAD(i));
353 if (i == OMAP_DSS_GFX) {
354 SR(OVL_WINDOW_SKIP(i));
355 SR(OVL_TABLE_BA(i));
356 continue;
357 }
358 SR(OVL_FIR(i));
359 SR(OVL_PICTURE_SIZE(i));
360 SR(OVL_ACCU0(i));
361 SR(OVL_ACCU1(i));
362
363 for (j = 0; j < 8; j++)
364 SR(OVL_FIR_COEF_H(i, j));
365
366 for (j = 0; j < 8; j++)
367 SR(OVL_FIR_COEF_HV(i, j));
368
369 for (j = 0; j < 5; j++)
370 SR(OVL_CONV_COEF(i, j));
371
372 if (dss_has_feature(FEAT_FIR_COEF_V)) {
373 for (j = 0; j < 8; j++)
374 SR(OVL_FIR_COEF_V(i, j));
375 }
376
377 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
378 SR(OVL_BA0_UV(i));
379 SR(OVL_BA1_UV(i));
380 SR(OVL_FIR2(i));
381 SR(OVL_ACCU2_0(i));
382 SR(OVL_ACCU2_1(i));
383
384 for (j = 0; j < 8; j++)
385 SR(OVL_FIR_COEF_H2(i, j));
386
387 for (j = 0; j < 8; j++)
388 SR(OVL_FIR_COEF_HV2(i, j));
389
390 for (j = 0; j < 8; j++)
391 SR(OVL_FIR_COEF_V2(i, j));
392 }
393 if (dss_has_feature(FEAT_ATTR2))
394 SR(OVL_ATTRIBUTES2(i));
395 }
396
397 if (dss_has_feature(FEAT_CORE_CLK_DIV))
398 SR(DIVISOR);
399
400 dispc.ctx_valid = true;
401
402 DSSDBG("context saved\n");
403 }
404
dispc_restore_context(void)405 static void dispc_restore_context(void)
406 {
407 int i, j;
408
409 DSSDBG("dispc_restore_context\n");
410
411 if (!dispc.ctx_valid)
412 return;
413
414 /*RR(IRQENABLE);*/
415 /*RR(CONTROL);*/
416 RR(CONFIG);
417 RR(LINE_NUMBER);
418 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
419 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
420 RR(GLOBAL_ALPHA);
421 if (dss_has_feature(FEAT_MGR_LCD2))
422 RR(CONFIG2);
423 if (dss_has_feature(FEAT_MGR_LCD3))
424 RR(CONFIG3);
425
426 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
427 RR(DEFAULT_COLOR(i));
428 RR(TRANS_COLOR(i));
429 RR(SIZE_MGR(i));
430 if (i == OMAP_DSS_CHANNEL_DIGIT)
431 continue;
432 RR(TIMING_H(i));
433 RR(TIMING_V(i));
434 RR(POL_FREQ(i));
435 RR(DIVISORo(i));
436
437 RR(DATA_CYCLE1(i));
438 RR(DATA_CYCLE2(i));
439 RR(DATA_CYCLE3(i));
440
441 if (dss_has_feature(FEAT_CPR)) {
442 RR(CPR_COEF_R(i));
443 RR(CPR_COEF_G(i));
444 RR(CPR_COEF_B(i));
445 }
446 }
447
448 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
449 RR(OVL_BA0(i));
450 RR(OVL_BA1(i));
451 RR(OVL_POSITION(i));
452 RR(OVL_SIZE(i));
453 RR(OVL_ATTRIBUTES(i));
454 RR(OVL_FIFO_THRESHOLD(i));
455 RR(OVL_ROW_INC(i));
456 RR(OVL_PIXEL_INC(i));
457 if (dss_has_feature(FEAT_PRELOAD))
458 RR(OVL_PRELOAD(i));
459 if (i == OMAP_DSS_GFX) {
460 RR(OVL_WINDOW_SKIP(i));
461 RR(OVL_TABLE_BA(i));
462 continue;
463 }
464 RR(OVL_FIR(i));
465 RR(OVL_PICTURE_SIZE(i));
466 RR(OVL_ACCU0(i));
467 RR(OVL_ACCU1(i));
468
469 for (j = 0; j < 8; j++)
470 RR(OVL_FIR_COEF_H(i, j));
471
472 for (j = 0; j < 8; j++)
473 RR(OVL_FIR_COEF_HV(i, j));
474
475 for (j = 0; j < 5; j++)
476 RR(OVL_CONV_COEF(i, j));
477
478 if (dss_has_feature(FEAT_FIR_COEF_V)) {
479 for (j = 0; j < 8; j++)
480 RR(OVL_FIR_COEF_V(i, j));
481 }
482
483 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
484 RR(OVL_BA0_UV(i));
485 RR(OVL_BA1_UV(i));
486 RR(OVL_FIR2(i));
487 RR(OVL_ACCU2_0(i));
488 RR(OVL_ACCU2_1(i));
489
490 for (j = 0; j < 8; j++)
491 RR(OVL_FIR_COEF_H2(i, j));
492
493 for (j = 0; j < 8; j++)
494 RR(OVL_FIR_COEF_HV2(i, j));
495
496 for (j = 0; j < 8; j++)
497 RR(OVL_FIR_COEF_V2(i, j));
498 }
499 if (dss_has_feature(FEAT_ATTR2))
500 RR(OVL_ATTRIBUTES2(i));
501 }
502
503 if (dss_has_feature(FEAT_CORE_CLK_DIV))
504 RR(DIVISOR);
505
506 /* enable last, because LCD & DIGIT enable are here */
507 RR(CONTROL);
508 if (dss_has_feature(FEAT_MGR_LCD2))
509 RR(CONTROL2);
510 if (dss_has_feature(FEAT_MGR_LCD3))
511 RR(CONTROL3);
512 /* clear spurious SYNC_LOST_DIGIT interrupts */
513 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
514
515 /*
516 * enable last so IRQs won't trigger before
517 * the context is fully restored
518 */
519 RR(IRQENABLE);
520
521 DSSDBG("context restored\n");
522 }
523
524 #undef SR
525 #undef RR
526
dispc_runtime_get(void)527 int dispc_runtime_get(void)
528 {
529 int r;
530
531 DSSDBG("dispc_runtime_get\n");
532
533 r = pm_runtime_get_sync(&dispc.pdev->dev);
534 WARN_ON(r < 0);
535 return r < 0 ? r : 0;
536 }
537 EXPORT_SYMBOL(dispc_runtime_get);
538
dispc_runtime_put(void)539 void dispc_runtime_put(void)
540 {
541 int r;
542
543 DSSDBG("dispc_runtime_put\n");
544
545 r = pm_runtime_put_sync(&dispc.pdev->dev);
546 WARN_ON(r < 0 && r != -ENOSYS);
547 }
548 EXPORT_SYMBOL(dispc_runtime_put);
549
dispc_mgr_get_vsync_irq(enum omap_channel channel)550 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
551 {
552 return mgr_desc[channel].vsync_irq;
553 }
554 EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
555
dispc_mgr_get_framedone_irq(enum omap_channel channel)556 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
557 {
558 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
559 return 0;
560
561 return mgr_desc[channel].framedone_irq;
562 }
563 EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
564
dispc_mgr_get_sync_lost_irq(enum omap_channel channel)565 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
566 {
567 return mgr_desc[channel].sync_lost_irq;
568 }
569 EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
570
dispc_wb_get_framedone_irq(void)571 u32 dispc_wb_get_framedone_irq(void)
572 {
573 return DISPC_IRQ_FRAMEDONEWB;
574 }
575
dispc_mgr_go_busy(enum omap_channel channel)576 bool dispc_mgr_go_busy(enum omap_channel channel)
577 {
578 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
579 }
580 EXPORT_SYMBOL(dispc_mgr_go_busy);
581
dispc_mgr_go(enum omap_channel channel)582 void dispc_mgr_go(enum omap_channel channel)
583 {
584 WARN_ON(!dispc_mgr_is_enabled(channel));
585 WARN_ON(dispc_mgr_go_busy(channel));
586
587 DSSDBG("GO %s\n", mgr_desc[channel].name);
588
589 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
590 }
591 EXPORT_SYMBOL(dispc_mgr_go);
592
dispc_wb_go_busy(void)593 bool dispc_wb_go_busy(void)
594 {
595 return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
596 }
597
dispc_wb_go(void)598 void dispc_wb_go(void)
599 {
600 enum omap_plane plane = OMAP_DSS_WB;
601 bool enable, go;
602
603 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
604
605 if (!enable)
606 return;
607
608 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
609 if (go) {
610 DSSERR("GO bit not down for WB\n");
611 return;
612 }
613
614 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
615 }
616
dispc_ovl_write_firh_reg(enum omap_plane plane,int reg,u32 value)617 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
618 {
619 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
620 }
621
dispc_ovl_write_firhv_reg(enum omap_plane plane,int reg,u32 value)622 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
623 {
624 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
625 }
626
dispc_ovl_write_firv_reg(enum omap_plane plane,int reg,u32 value)627 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
628 {
629 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
630 }
631
dispc_ovl_write_firh2_reg(enum omap_plane plane,int reg,u32 value)632 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
633 {
634 BUG_ON(plane == OMAP_DSS_GFX);
635
636 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
637 }
638
dispc_ovl_write_firhv2_reg(enum omap_plane plane,int reg,u32 value)639 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
640 u32 value)
641 {
642 BUG_ON(plane == OMAP_DSS_GFX);
643
644 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
645 }
646
dispc_ovl_write_firv2_reg(enum omap_plane plane,int reg,u32 value)647 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
648 {
649 BUG_ON(plane == OMAP_DSS_GFX);
650
651 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
652 }
653
dispc_ovl_set_scale_coef(enum omap_plane plane,int fir_hinc,int fir_vinc,int five_taps,enum omap_color_component color_comp)654 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
655 int fir_vinc, int five_taps,
656 enum omap_color_component color_comp)
657 {
658 const struct dispc_coef *h_coef, *v_coef;
659 int i;
660
661 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
662 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
663
664 for (i = 0; i < 8; i++) {
665 u32 h, hv;
666
667 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
668 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
669 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
670 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
671 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
672 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
673 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
674 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
675
676 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
677 dispc_ovl_write_firh_reg(plane, i, h);
678 dispc_ovl_write_firhv_reg(plane, i, hv);
679 } else {
680 dispc_ovl_write_firh2_reg(plane, i, h);
681 dispc_ovl_write_firhv2_reg(plane, i, hv);
682 }
683
684 }
685
686 if (five_taps) {
687 for (i = 0; i < 8; i++) {
688 u32 v;
689 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
690 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
691 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
692 dispc_ovl_write_firv_reg(plane, i, v);
693 else
694 dispc_ovl_write_firv2_reg(plane, i, v);
695 }
696 }
697 }
698
699
dispc_ovl_write_color_conv_coef(enum omap_plane plane,const struct color_conv_coef * ct)700 static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
701 const struct color_conv_coef *ct)
702 {
703 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
704
705 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
706 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
707 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
708 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
709 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
710
711 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
712
713 #undef CVAL
714 }
715
dispc_setup_color_conv_coef(void)716 static void dispc_setup_color_conv_coef(void)
717 {
718 int i;
719 int num_ovl = dss_feat_get_num_ovls();
720 const struct color_conv_coef ctbl_bt601_5_ovl = {
721 /* YUV -> RGB */
722 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
723 };
724 const struct color_conv_coef ctbl_bt601_5_wb = {
725 /* RGB -> YUV */
726 66, 129, 25, 112, -94, -18, -38, -74, 112, 0,
727 };
728
729 for (i = 1; i < num_ovl; i++)
730 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
731
732 if (dispc.feat->has_writeback)
733 dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb);
734 }
735
dispc_ovl_set_ba0(enum omap_plane plane,u32 paddr)736 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
737 {
738 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
739 }
740
dispc_ovl_set_ba1(enum omap_plane plane,u32 paddr)741 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
742 {
743 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
744 }
745
dispc_ovl_set_ba0_uv(enum omap_plane plane,u32 paddr)746 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
747 {
748 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
749 }
750
dispc_ovl_set_ba1_uv(enum omap_plane plane,u32 paddr)751 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
752 {
753 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
754 }
755
dispc_ovl_set_pos(enum omap_plane plane,enum omap_overlay_caps caps,int x,int y)756 static void dispc_ovl_set_pos(enum omap_plane plane,
757 enum omap_overlay_caps caps, int x, int y)
758 {
759 u32 val;
760
761 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
762 return;
763
764 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
765
766 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
767 }
768
dispc_ovl_set_input_size(enum omap_plane plane,int width,int height)769 static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
770 int height)
771 {
772 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
773
774 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
775 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
776 else
777 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
778 }
779
dispc_ovl_set_output_size(enum omap_plane plane,int width,int height)780 static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
781 int height)
782 {
783 u32 val;
784
785 BUG_ON(plane == OMAP_DSS_GFX);
786
787 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
788
789 if (plane == OMAP_DSS_WB)
790 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
791 else
792 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
793 }
794
dispc_ovl_set_zorder(enum omap_plane plane,enum omap_overlay_caps caps,u8 zorder)795 static void dispc_ovl_set_zorder(enum omap_plane plane,
796 enum omap_overlay_caps caps, u8 zorder)
797 {
798 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
799 return;
800
801 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
802 }
803
dispc_ovl_enable_zorder_planes(void)804 static void dispc_ovl_enable_zorder_planes(void)
805 {
806 int i;
807
808 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
809 return;
810
811 for (i = 0; i < dss_feat_get_num_ovls(); i++)
812 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
813 }
814
dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,enum omap_overlay_caps caps,bool enable)815 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
816 enum omap_overlay_caps caps, bool enable)
817 {
818 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
819 return;
820
821 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
822 }
823
dispc_ovl_setup_global_alpha(enum omap_plane plane,enum omap_overlay_caps caps,u8 global_alpha)824 static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
825 enum omap_overlay_caps caps, u8 global_alpha)
826 {
827 static const unsigned shifts[] = { 0, 8, 16, 24, };
828 int shift;
829
830 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
831 return;
832
833 shift = shifts[plane];
834 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
835 }
836
dispc_ovl_set_pix_inc(enum omap_plane plane,s32 inc)837 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
838 {
839 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
840 }
841
dispc_ovl_set_row_inc(enum omap_plane plane,s32 inc)842 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
843 {
844 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
845 }
846
dispc_ovl_set_color_mode(enum omap_plane plane,enum omap_color_mode color_mode)847 static void dispc_ovl_set_color_mode(enum omap_plane plane,
848 enum omap_color_mode color_mode)
849 {
850 u32 m = 0;
851 if (plane != OMAP_DSS_GFX) {
852 switch (color_mode) {
853 case OMAP_DSS_COLOR_NV12:
854 m = 0x0; break;
855 case OMAP_DSS_COLOR_RGBX16:
856 m = 0x1; break;
857 case OMAP_DSS_COLOR_RGBA16:
858 m = 0x2; break;
859 case OMAP_DSS_COLOR_RGB12U:
860 m = 0x4; break;
861 case OMAP_DSS_COLOR_ARGB16:
862 m = 0x5; break;
863 case OMAP_DSS_COLOR_RGB16:
864 m = 0x6; break;
865 case OMAP_DSS_COLOR_ARGB16_1555:
866 m = 0x7; break;
867 case OMAP_DSS_COLOR_RGB24U:
868 m = 0x8; break;
869 case OMAP_DSS_COLOR_RGB24P:
870 m = 0x9; break;
871 case OMAP_DSS_COLOR_YUV2:
872 m = 0xa; break;
873 case OMAP_DSS_COLOR_UYVY:
874 m = 0xb; break;
875 case OMAP_DSS_COLOR_ARGB32:
876 m = 0xc; break;
877 case OMAP_DSS_COLOR_RGBA32:
878 m = 0xd; break;
879 case OMAP_DSS_COLOR_RGBX32:
880 m = 0xe; break;
881 case OMAP_DSS_COLOR_XRGB16_1555:
882 m = 0xf; break;
883 default:
884 BUG(); return;
885 }
886 } else {
887 switch (color_mode) {
888 case OMAP_DSS_COLOR_CLUT1:
889 m = 0x0; break;
890 case OMAP_DSS_COLOR_CLUT2:
891 m = 0x1; break;
892 case OMAP_DSS_COLOR_CLUT4:
893 m = 0x2; break;
894 case OMAP_DSS_COLOR_CLUT8:
895 m = 0x3; break;
896 case OMAP_DSS_COLOR_RGB12U:
897 m = 0x4; break;
898 case OMAP_DSS_COLOR_ARGB16:
899 m = 0x5; break;
900 case OMAP_DSS_COLOR_RGB16:
901 m = 0x6; break;
902 case OMAP_DSS_COLOR_ARGB16_1555:
903 m = 0x7; break;
904 case OMAP_DSS_COLOR_RGB24U:
905 m = 0x8; break;
906 case OMAP_DSS_COLOR_RGB24P:
907 m = 0x9; break;
908 case OMAP_DSS_COLOR_RGBX16:
909 m = 0xa; break;
910 case OMAP_DSS_COLOR_RGBA16:
911 m = 0xb; break;
912 case OMAP_DSS_COLOR_ARGB32:
913 m = 0xc; break;
914 case OMAP_DSS_COLOR_RGBA32:
915 m = 0xd; break;
916 case OMAP_DSS_COLOR_RGBX32:
917 m = 0xe; break;
918 case OMAP_DSS_COLOR_XRGB16_1555:
919 m = 0xf; break;
920 default:
921 BUG(); return;
922 }
923 }
924
925 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
926 }
927
dispc_ovl_configure_burst_type(enum omap_plane plane,enum omap_dss_rotation_type rotation_type)928 static void dispc_ovl_configure_burst_type(enum omap_plane plane,
929 enum omap_dss_rotation_type rotation_type)
930 {
931 if (dss_has_feature(FEAT_BURST_2D) == 0)
932 return;
933
934 if (rotation_type == OMAP_DSS_ROT_TILER)
935 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
936 else
937 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
938 }
939
dispc_ovl_set_channel_out(enum omap_plane plane,enum omap_channel channel)940 void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
941 {
942 int shift;
943 u32 val;
944 int chan = 0, chan2 = 0;
945
946 switch (plane) {
947 case OMAP_DSS_GFX:
948 shift = 8;
949 break;
950 case OMAP_DSS_VIDEO1:
951 case OMAP_DSS_VIDEO2:
952 case OMAP_DSS_VIDEO3:
953 shift = 16;
954 break;
955 default:
956 BUG();
957 return;
958 }
959
960 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
961 if (dss_has_feature(FEAT_MGR_LCD2)) {
962 switch (channel) {
963 case OMAP_DSS_CHANNEL_LCD:
964 chan = 0;
965 chan2 = 0;
966 break;
967 case OMAP_DSS_CHANNEL_DIGIT:
968 chan = 1;
969 chan2 = 0;
970 break;
971 case OMAP_DSS_CHANNEL_LCD2:
972 chan = 0;
973 chan2 = 1;
974 break;
975 case OMAP_DSS_CHANNEL_LCD3:
976 if (dss_has_feature(FEAT_MGR_LCD3)) {
977 chan = 0;
978 chan2 = 2;
979 } else {
980 BUG();
981 return;
982 }
983 break;
984 case OMAP_DSS_CHANNEL_WB:
985 chan = 0;
986 chan2 = 3;
987 break;
988 default:
989 BUG();
990 return;
991 }
992
993 val = FLD_MOD(val, chan, shift, shift);
994 val = FLD_MOD(val, chan2, 31, 30);
995 } else {
996 val = FLD_MOD(val, channel, shift, shift);
997 }
998 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
999 }
1000 EXPORT_SYMBOL(dispc_ovl_set_channel_out);
1001
dispc_ovl_get_channel_out(enum omap_plane plane)1002 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
1003 {
1004 int shift;
1005 u32 val;
1006
1007 switch (plane) {
1008 case OMAP_DSS_GFX:
1009 shift = 8;
1010 break;
1011 case OMAP_DSS_VIDEO1:
1012 case OMAP_DSS_VIDEO2:
1013 case OMAP_DSS_VIDEO3:
1014 shift = 16;
1015 break;
1016 default:
1017 BUG();
1018 return 0;
1019 }
1020
1021 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1022
1023 if (FLD_GET(val, shift, shift) == 1)
1024 return OMAP_DSS_CHANNEL_DIGIT;
1025
1026 if (!dss_has_feature(FEAT_MGR_LCD2))
1027 return OMAP_DSS_CHANNEL_LCD;
1028
1029 switch (FLD_GET(val, 31, 30)) {
1030 case 0:
1031 default:
1032 return OMAP_DSS_CHANNEL_LCD;
1033 case 1:
1034 return OMAP_DSS_CHANNEL_LCD2;
1035 case 2:
1036 return OMAP_DSS_CHANNEL_LCD3;
1037 case 3:
1038 return OMAP_DSS_CHANNEL_WB;
1039 }
1040 }
1041
dispc_wb_set_channel_in(enum dss_writeback_channel channel)1042 void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1043 {
1044 enum omap_plane plane = OMAP_DSS_WB;
1045
1046 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1047 }
1048
dispc_ovl_set_burst_size(enum omap_plane plane,enum omap_burst_size burst_size)1049 static void dispc_ovl_set_burst_size(enum omap_plane plane,
1050 enum omap_burst_size burst_size)
1051 {
1052 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
1053 int shift;
1054
1055 shift = shifts[plane];
1056 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1057 }
1058
dispc_configure_burst_sizes(void)1059 static void dispc_configure_burst_sizes(void)
1060 {
1061 int i;
1062 const int burst_size = BURST_SIZE_X8;
1063
1064 /* Configure burst size always to maximum size */
1065 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1066 dispc_ovl_set_burst_size(i, burst_size);
1067 if (dispc.feat->has_writeback)
1068 dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size);
1069 }
1070
dispc_ovl_get_burst_size(enum omap_plane plane)1071 static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
1072 {
1073 unsigned unit = dss_feat_get_burst_size_unit();
1074 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1075 return unit * 8;
1076 }
1077
dispc_enable_gamma_table(bool enable)1078 void dispc_enable_gamma_table(bool enable)
1079 {
1080 /*
1081 * This is partially implemented to support only disabling of
1082 * the gamma table.
1083 */
1084 if (enable) {
1085 DSSWARN("Gamma table enabling for TV not yet supported");
1086 return;
1087 }
1088
1089 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1090 }
1091
dispc_mgr_enable_cpr(enum omap_channel channel,bool enable)1092 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1093 {
1094 if (channel == OMAP_DSS_CHANNEL_DIGIT)
1095 return;
1096
1097 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
1098 }
1099
dispc_mgr_set_cpr_coef(enum omap_channel channel,const struct omap_dss_cpr_coefs * coefs)1100 static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1101 const struct omap_dss_cpr_coefs *coefs)
1102 {
1103 u32 coef_r, coef_g, coef_b;
1104
1105 if (!dss_mgr_is_lcd(channel))
1106 return;
1107
1108 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1109 FLD_VAL(coefs->rb, 9, 0);
1110 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1111 FLD_VAL(coefs->gb, 9, 0);
1112 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1113 FLD_VAL(coefs->bb, 9, 0);
1114
1115 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1116 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1117 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1118 }
1119
dispc_ovl_set_vid_color_conv(enum omap_plane plane,bool enable)1120 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1121 {
1122 u32 val;
1123
1124 BUG_ON(plane == OMAP_DSS_GFX);
1125
1126 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1127 val = FLD_MOD(val, enable, 9, 9);
1128 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1129 }
1130
dispc_ovl_enable_replication(enum omap_plane plane,enum omap_overlay_caps caps,bool enable)1131 static void dispc_ovl_enable_replication(enum omap_plane plane,
1132 enum omap_overlay_caps caps, bool enable)
1133 {
1134 static const unsigned shifts[] = { 5, 10, 10, 10 };
1135 int shift;
1136
1137 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1138 return;
1139
1140 shift = shifts[plane];
1141 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1142 }
1143
dispc_mgr_set_size(enum omap_channel channel,u16 width,u16 height)1144 static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
1145 u16 height)
1146 {
1147 u32 val;
1148
1149 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1150 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1151
1152 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1153 }
1154
dispc_init_fifos(void)1155 static void dispc_init_fifos(void)
1156 {
1157 u32 size;
1158 int fifo;
1159 u8 start, end;
1160 u32 unit;
1161 int i;
1162
1163 unit = dss_feat_get_buffer_size_unit();
1164
1165 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1166
1167 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1168 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
1169 size *= unit;
1170 dispc.fifo_size[fifo] = size;
1171
1172 /*
1173 * By default fifos are mapped directly to overlays, fifo 0 to
1174 * ovl 0, fifo 1 to ovl 1, etc.
1175 */
1176 dispc.fifo_assignment[fifo] = fifo;
1177 }
1178
1179 /*
1180 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1181 * causes problems with certain use cases, like using the tiler in 2D
1182 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1183 * giving GFX plane a larger fifo. WB but should work fine with a
1184 * smaller fifo.
1185 */
1186 if (dispc.feat->gfx_fifo_workaround) {
1187 u32 v;
1188
1189 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1190
1191 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1192 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1193 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1194 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1195
1196 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1197
1198 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1199 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1200 }
1201
1202 /*
1203 * Setup default fifo thresholds.
1204 */
1205 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1206 u32 low, high;
1207 const bool use_fifomerge = false;
1208 const bool manual_update = false;
1209
1210 dispc_ovl_compute_fifo_thresholds(i, &low, &high,
1211 use_fifomerge, manual_update);
1212
1213 dispc_ovl_set_fifo_threshold(i, low, high);
1214 }
1215
1216 if (dispc.feat->has_writeback) {
1217 u32 low, high;
1218 const bool use_fifomerge = false;
1219 const bool manual_update = false;
1220
1221 dispc_ovl_compute_fifo_thresholds(OMAP_DSS_WB, &low, &high,
1222 use_fifomerge, manual_update);
1223
1224 dispc_ovl_set_fifo_threshold(OMAP_DSS_WB, low, high);
1225 }
1226 }
1227
dispc_ovl_get_fifo_size(enum omap_plane plane)1228 static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1229 {
1230 int fifo;
1231 u32 size = 0;
1232
1233 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1234 if (dispc.fifo_assignment[fifo] == plane)
1235 size += dispc.fifo_size[fifo];
1236 }
1237
1238 return size;
1239 }
1240
dispc_ovl_set_fifo_threshold(enum omap_plane plane,u32 low,u32 high)1241 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1242 {
1243 u8 hi_start, hi_end, lo_start, lo_end;
1244 u32 unit;
1245
1246 unit = dss_feat_get_buffer_size_unit();
1247
1248 WARN_ON(low % unit != 0);
1249 WARN_ON(high % unit != 0);
1250
1251 low /= unit;
1252 high /= unit;
1253
1254 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1255 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1256
1257 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1258 plane,
1259 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1260 lo_start, lo_end) * unit,
1261 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1262 hi_start, hi_end) * unit,
1263 low * unit, high * unit);
1264
1265 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1266 FLD_VAL(high, hi_start, hi_end) |
1267 FLD_VAL(low, lo_start, lo_end));
1268
1269 /*
1270 * configure the preload to the pipeline's high threhold, if HT it's too
1271 * large for the preload field, set the threshold to the maximum value
1272 * that can be held by the preload register
1273 */
1274 if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1275 plane != OMAP_DSS_WB)
1276 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
1277 }
1278
dispc_enable_fifomerge(bool enable)1279 void dispc_enable_fifomerge(bool enable)
1280 {
1281 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1282 WARN_ON(enable);
1283 return;
1284 }
1285
1286 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1287 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1288 }
1289
dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,u32 * fifo_low,u32 * fifo_high,bool use_fifomerge,bool manual_update)1290 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1291 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1292 bool manual_update)
1293 {
1294 /*
1295 * All sizes are in bytes. Both the buffer and burst are made of
1296 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1297 */
1298
1299 unsigned buf_unit = dss_feat_get_buffer_size_unit();
1300 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1301 int i;
1302
1303 burst_size = dispc_ovl_get_burst_size(plane);
1304 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
1305
1306 if (use_fifomerge) {
1307 total_fifo_size = 0;
1308 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1309 total_fifo_size += dispc_ovl_get_fifo_size(i);
1310 } else {
1311 total_fifo_size = ovl_fifo_size;
1312 }
1313
1314 /*
1315 * We use the same low threshold for both fifomerge and non-fifomerge
1316 * cases, but for fifomerge we calculate the high threshold using the
1317 * combined fifo size
1318 */
1319
1320 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1321 *fifo_low = ovl_fifo_size - burst_size * 2;
1322 *fifo_high = total_fifo_size - burst_size;
1323 } else if (plane == OMAP_DSS_WB) {
1324 /*
1325 * Most optimal configuration for writeback is to push out data
1326 * to the interconnect the moment writeback pushes enough pixels
1327 * in the FIFO to form a burst
1328 */
1329 *fifo_low = 0;
1330 *fifo_high = burst_size;
1331 } else {
1332 *fifo_low = ovl_fifo_size - burst_size;
1333 *fifo_high = total_fifo_size - buf_unit;
1334 }
1335 }
1336
dispc_ovl_set_mflag(enum omap_plane plane,bool enable)1337 static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable)
1338 {
1339 int bit;
1340
1341 if (plane == OMAP_DSS_GFX)
1342 bit = 14;
1343 else
1344 bit = 23;
1345
1346 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1347 }
1348
dispc_ovl_set_mflag_threshold(enum omap_plane plane,int low,int high)1349 static void dispc_ovl_set_mflag_threshold(enum omap_plane plane,
1350 int low, int high)
1351 {
1352 dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),
1353 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
1354 }
1355
dispc_init_mflag(void)1356 static void dispc_init_mflag(void)
1357 {
1358 int i;
1359
1360 /*
1361 * HACK: NV12 color format and MFLAG seem to have problems working
1362 * together: using two displays, and having an NV12 overlay on one of
1363 * the displays will cause underflows/synclosts when MFLAG_CTRL=2.
1364 * Changing MFLAG thresholds and PRELOAD to certain values seem to
1365 * remove the errors, but there doesn't seem to be a clear logic on
1366 * which values work and which not.
1367 *
1368 * As a work-around, set force MFLAG to always on.
1369 */
1370 dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE,
1371 (1 << 0) | /* MFLAG_CTRL = force always on */
1372 (0 << 2)); /* MFLAG_START = disable */
1373
1374 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1375 u32 size = dispc_ovl_get_fifo_size(i);
1376 u32 unit = dss_feat_get_buffer_size_unit();
1377 u32 low, high;
1378
1379 dispc_ovl_set_mflag(i, true);
1380
1381 /*
1382 * Simulation team suggests below thesholds:
1383 * HT = fifosize * 5 / 8;
1384 * LT = fifosize * 4 / 8;
1385 */
1386
1387 low = size * 4 / 8 / unit;
1388 high = size * 5 / 8 / unit;
1389
1390 dispc_ovl_set_mflag_threshold(i, low, high);
1391 }
1392
1393 if (dispc.feat->has_writeback) {
1394 u32 size = dispc_ovl_get_fifo_size(OMAP_DSS_WB);
1395 u32 unit = dss_feat_get_buffer_size_unit();
1396 u32 low, high;
1397
1398 dispc_ovl_set_mflag(OMAP_DSS_WB, true);
1399
1400 /*
1401 * Simulation team suggests below thesholds:
1402 * HT = fifosize * 5 / 8;
1403 * LT = fifosize * 4 / 8;
1404 */
1405
1406 low = size * 4 / 8 / unit;
1407 high = size * 5 / 8 / unit;
1408
1409 dispc_ovl_set_mflag_threshold(OMAP_DSS_WB, low, high);
1410 }
1411 }
1412
dispc_ovl_set_fir(enum omap_plane plane,int hinc,int vinc,enum omap_color_component color_comp)1413 static void dispc_ovl_set_fir(enum omap_plane plane,
1414 int hinc, int vinc,
1415 enum omap_color_component color_comp)
1416 {
1417 u32 val;
1418
1419 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1420 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1421
1422 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1423 &hinc_start, &hinc_end);
1424 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1425 &vinc_start, &vinc_end);
1426 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1427 FLD_VAL(hinc, hinc_start, hinc_end);
1428
1429 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1430 } else {
1431 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1432 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1433 }
1434 }
1435
dispc_ovl_set_vid_accu0(enum omap_plane plane,int haccu,int vaccu)1436 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1437 {
1438 u32 val;
1439 u8 hor_start, hor_end, vert_start, vert_end;
1440
1441 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1442 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1443
1444 val = FLD_VAL(vaccu, vert_start, vert_end) |
1445 FLD_VAL(haccu, hor_start, hor_end);
1446
1447 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1448 }
1449
dispc_ovl_set_vid_accu1(enum omap_plane plane,int haccu,int vaccu)1450 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1451 {
1452 u32 val;
1453 u8 hor_start, hor_end, vert_start, vert_end;
1454
1455 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1456 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1457
1458 val = FLD_VAL(vaccu, vert_start, vert_end) |
1459 FLD_VAL(haccu, hor_start, hor_end);
1460
1461 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1462 }
1463
dispc_ovl_set_vid_accu2_0(enum omap_plane plane,int haccu,int vaccu)1464 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1465 int vaccu)
1466 {
1467 u32 val;
1468
1469 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1470 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1471 }
1472
dispc_ovl_set_vid_accu2_1(enum omap_plane plane,int haccu,int vaccu)1473 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1474 int vaccu)
1475 {
1476 u32 val;
1477
1478 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1479 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1480 }
1481
dispc_ovl_set_scale_param(enum omap_plane plane,u16 orig_width,u16 orig_height,u16 out_width,u16 out_height,bool five_taps,u8 rotation,enum omap_color_component color_comp)1482 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1483 u16 orig_width, u16 orig_height,
1484 u16 out_width, u16 out_height,
1485 bool five_taps, u8 rotation,
1486 enum omap_color_component color_comp)
1487 {
1488 int fir_hinc, fir_vinc;
1489
1490 fir_hinc = 1024 * orig_width / out_width;
1491 fir_vinc = 1024 * orig_height / out_height;
1492
1493 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1494 color_comp);
1495 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1496 }
1497
dispc_ovl_set_accu_uv(enum omap_plane plane,u16 orig_width,u16 orig_height,u16 out_width,u16 out_height,bool ilace,enum omap_color_mode color_mode,u8 rotation)1498 static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1499 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1500 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1501 {
1502 int h_accu2_0, h_accu2_1;
1503 int v_accu2_0, v_accu2_1;
1504 int chroma_hinc, chroma_vinc;
1505 int idx;
1506
1507 struct accu {
1508 s8 h0_m, h0_n;
1509 s8 h1_m, h1_n;
1510 s8 v0_m, v0_n;
1511 s8 v1_m, v1_n;
1512 };
1513
1514 const struct accu *accu_table;
1515 const struct accu *accu_val;
1516
1517 static const struct accu accu_nv12[4] = {
1518 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1519 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1520 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1521 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1522 };
1523
1524 static const struct accu accu_nv12_ilace[4] = {
1525 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1526 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1527 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1528 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1529 };
1530
1531 static const struct accu accu_yuv[4] = {
1532 { 0, 1, 0, 1, 0, 1, 0, 1 },
1533 { 0, 1, 0, 1, 0, 1, 0, 1 },
1534 { -1, 1, 0, 1, 0, 1, 0, 1 },
1535 { 0, 1, 0, 1, -1, 1, 0, 1 },
1536 };
1537
1538 switch (rotation) {
1539 case OMAP_DSS_ROT_0:
1540 idx = 0;
1541 break;
1542 case OMAP_DSS_ROT_90:
1543 idx = 1;
1544 break;
1545 case OMAP_DSS_ROT_180:
1546 idx = 2;
1547 break;
1548 case OMAP_DSS_ROT_270:
1549 idx = 3;
1550 break;
1551 default:
1552 BUG();
1553 return;
1554 }
1555
1556 switch (color_mode) {
1557 case OMAP_DSS_COLOR_NV12:
1558 if (ilace)
1559 accu_table = accu_nv12_ilace;
1560 else
1561 accu_table = accu_nv12;
1562 break;
1563 case OMAP_DSS_COLOR_YUV2:
1564 case OMAP_DSS_COLOR_UYVY:
1565 accu_table = accu_yuv;
1566 break;
1567 default:
1568 BUG();
1569 return;
1570 }
1571
1572 accu_val = &accu_table[idx];
1573
1574 chroma_hinc = 1024 * orig_width / out_width;
1575 chroma_vinc = 1024 * orig_height / out_height;
1576
1577 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1578 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1579 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1580 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1581
1582 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1583 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1584 }
1585
dispc_ovl_set_scaling_common(enum omap_plane plane,u16 orig_width,u16 orig_height,u16 out_width,u16 out_height,bool ilace,bool five_taps,bool fieldmode,enum omap_color_mode color_mode,u8 rotation)1586 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1587 u16 orig_width, u16 orig_height,
1588 u16 out_width, u16 out_height,
1589 bool ilace, bool five_taps,
1590 bool fieldmode, enum omap_color_mode color_mode,
1591 u8 rotation)
1592 {
1593 int accu0 = 0;
1594 int accu1 = 0;
1595 u32 l;
1596
1597 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1598 out_width, out_height, five_taps,
1599 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1600 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1601
1602 /* RESIZEENABLE and VERTICALTAPS */
1603 l &= ~((0x3 << 5) | (0x1 << 21));
1604 l |= (orig_width != out_width) ? (1 << 5) : 0;
1605 l |= (orig_height != out_height) ? (1 << 6) : 0;
1606 l |= five_taps ? (1 << 21) : 0;
1607
1608 /* VRESIZECONF and HRESIZECONF */
1609 if (dss_has_feature(FEAT_RESIZECONF)) {
1610 l &= ~(0x3 << 7);
1611 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1612 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1613 }
1614
1615 /* LINEBUFFERSPLIT */
1616 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1617 l &= ~(0x1 << 22);
1618 l |= five_taps ? (1 << 22) : 0;
1619 }
1620
1621 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1622
1623 /*
1624 * field 0 = even field = bottom field
1625 * field 1 = odd field = top field
1626 */
1627 if (ilace && !fieldmode) {
1628 accu1 = 0;
1629 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1630 if (accu0 >= 1024/2) {
1631 accu1 = 1024/2;
1632 accu0 -= accu1;
1633 }
1634 }
1635
1636 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1637 dispc_ovl_set_vid_accu1(plane, 0, accu1);
1638 }
1639
dispc_ovl_set_scaling_uv(enum omap_plane plane,u16 orig_width,u16 orig_height,u16 out_width,u16 out_height,bool ilace,bool five_taps,bool fieldmode,enum omap_color_mode color_mode,u8 rotation)1640 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1641 u16 orig_width, u16 orig_height,
1642 u16 out_width, u16 out_height,
1643 bool ilace, bool five_taps,
1644 bool fieldmode, enum omap_color_mode color_mode,
1645 u8 rotation)
1646 {
1647 int scale_x = out_width != orig_width;
1648 int scale_y = out_height != orig_height;
1649 bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
1650
1651 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1652 return;
1653 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1654 color_mode != OMAP_DSS_COLOR_UYVY &&
1655 color_mode != OMAP_DSS_COLOR_NV12)) {
1656 /* reset chroma resampling for RGB formats */
1657 if (plane != OMAP_DSS_WB)
1658 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1659 return;
1660 }
1661
1662 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1663 out_height, ilace, color_mode, rotation);
1664
1665 switch (color_mode) {
1666 case OMAP_DSS_COLOR_NV12:
1667 if (chroma_upscale) {
1668 /* UV is subsampled by 2 horizontally and vertically */
1669 orig_height >>= 1;
1670 orig_width >>= 1;
1671 } else {
1672 /* UV is downsampled by 2 horizontally and vertically */
1673 orig_height <<= 1;
1674 orig_width <<= 1;
1675 }
1676
1677 break;
1678 case OMAP_DSS_COLOR_YUV2:
1679 case OMAP_DSS_COLOR_UYVY:
1680 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
1681 if (rotation == OMAP_DSS_ROT_0 ||
1682 rotation == OMAP_DSS_ROT_180) {
1683 if (chroma_upscale)
1684 /* UV is subsampled by 2 horizontally */
1685 orig_width >>= 1;
1686 else
1687 /* UV is downsampled by 2 horizontally */
1688 orig_width <<= 1;
1689 }
1690
1691 /* must use FIR for YUV422 if rotated */
1692 if (rotation != OMAP_DSS_ROT_0)
1693 scale_x = scale_y = true;
1694
1695 break;
1696 default:
1697 BUG();
1698 return;
1699 }
1700
1701 if (out_width != orig_width)
1702 scale_x = true;
1703 if (out_height != orig_height)
1704 scale_y = true;
1705
1706 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1707 out_width, out_height, five_taps,
1708 rotation, DISPC_COLOR_COMPONENT_UV);
1709
1710 if (plane != OMAP_DSS_WB)
1711 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1712 (scale_x || scale_y) ? 1 : 0, 8, 8);
1713
1714 /* set H scaling */
1715 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1716 /* set V scaling */
1717 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1718 }
1719
dispc_ovl_set_scaling(enum omap_plane plane,u16 orig_width,u16 orig_height,u16 out_width,u16 out_height,bool ilace,bool five_taps,bool fieldmode,enum omap_color_mode color_mode,u8 rotation)1720 static void dispc_ovl_set_scaling(enum omap_plane plane,
1721 u16 orig_width, u16 orig_height,
1722 u16 out_width, u16 out_height,
1723 bool ilace, bool five_taps,
1724 bool fieldmode, enum omap_color_mode color_mode,
1725 u8 rotation)
1726 {
1727 BUG_ON(plane == OMAP_DSS_GFX);
1728
1729 dispc_ovl_set_scaling_common(plane,
1730 orig_width, orig_height,
1731 out_width, out_height,
1732 ilace, five_taps,
1733 fieldmode, color_mode,
1734 rotation);
1735
1736 dispc_ovl_set_scaling_uv(plane,
1737 orig_width, orig_height,
1738 out_width, out_height,
1739 ilace, five_taps,
1740 fieldmode, color_mode,
1741 rotation);
1742 }
1743
dispc_ovl_set_rotation_attrs(enum omap_plane plane,u8 rotation,enum omap_dss_rotation_type rotation_type,bool mirroring,enum omap_color_mode color_mode)1744 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1745 enum omap_dss_rotation_type rotation_type,
1746 bool mirroring, enum omap_color_mode color_mode)
1747 {
1748 bool row_repeat = false;
1749 int vidrot = 0;
1750
1751 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1752 color_mode == OMAP_DSS_COLOR_UYVY) {
1753
1754 if (mirroring) {
1755 switch (rotation) {
1756 case OMAP_DSS_ROT_0:
1757 vidrot = 2;
1758 break;
1759 case OMAP_DSS_ROT_90:
1760 vidrot = 1;
1761 break;
1762 case OMAP_DSS_ROT_180:
1763 vidrot = 0;
1764 break;
1765 case OMAP_DSS_ROT_270:
1766 vidrot = 3;
1767 break;
1768 }
1769 } else {
1770 switch (rotation) {
1771 case OMAP_DSS_ROT_0:
1772 vidrot = 0;
1773 break;
1774 case OMAP_DSS_ROT_90:
1775 vidrot = 1;
1776 break;
1777 case OMAP_DSS_ROT_180:
1778 vidrot = 2;
1779 break;
1780 case OMAP_DSS_ROT_270:
1781 vidrot = 3;
1782 break;
1783 }
1784 }
1785
1786 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1787 row_repeat = true;
1788 else
1789 row_repeat = false;
1790 }
1791
1792 /*
1793 * OMAP4/5 Errata i631:
1794 * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra
1795 * rows beyond the framebuffer, which may cause OCP error.
1796 */
1797 if (color_mode == OMAP_DSS_COLOR_NV12 &&
1798 rotation_type != OMAP_DSS_ROT_TILER)
1799 vidrot = 1;
1800
1801 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1802 if (dss_has_feature(FEAT_ROWREPEATENABLE))
1803 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1804 row_repeat ? 1 : 0, 18, 18);
1805
1806 if (color_mode == OMAP_DSS_COLOR_NV12) {
1807 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
1808 (rotation == OMAP_DSS_ROT_0 ||
1809 rotation == OMAP_DSS_ROT_180);
1810 /* DOUBLESTRIDE */
1811 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1812 }
1813
1814 }
1815
color_mode_to_bpp(enum omap_color_mode color_mode)1816 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1817 {
1818 switch (color_mode) {
1819 case OMAP_DSS_COLOR_CLUT1:
1820 return 1;
1821 case OMAP_DSS_COLOR_CLUT2:
1822 return 2;
1823 case OMAP_DSS_COLOR_CLUT4:
1824 return 4;
1825 case OMAP_DSS_COLOR_CLUT8:
1826 case OMAP_DSS_COLOR_NV12:
1827 return 8;
1828 case OMAP_DSS_COLOR_RGB12U:
1829 case OMAP_DSS_COLOR_RGB16:
1830 case OMAP_DSS_COLOR_ARGB16:
1831 case OMAP_DSS_COLOR_YUV2:
1832 case OMAP_DSS_COLOR_UYVY:
1833 case OMAP_DSS_COLOR_RGBA16:
1834 case OMAP_DSS_COLOR_RGBX16:
1835 case OMAP_DSS_COLOR_ARGB16_1555:
1836 case OMAP_DSS_COLOR_XRGB16_1555:
1837 return 16;
1838 case OMAP_DSS_COLOR_RGB24P:
1839 return 24;
1840 case OMAP_DSS_COLOR_RGB24U:
1841 case OMAP_DSS_COLOR_ARGB32:
1842 case OMAP_DSS_COLOR_RGBA32:
1843 case OMAP_DSS_COLOR_RGBX32:
1844 return 32;
1845 default:
1846 BUG();
1847 return 0;
1848 }
1849 }
1850
pixinc(int pixels,u8 ps)1851 static s32 pixinc(int pixels, u8 ps)
1852 {
1853 if (pixels == 1)
1854 return 1;
1855 else if (pixels > 1)
1856 return 1 + (pixels - 1) * ps;
1857 else if (pixels < 0)
1858 return 1 - (-pixels + 1) * ps;
1859 else
1860 BUG();
1861 return 0;
1862 }
1863
calc_vrfb_rotation_offset(u8 rotation,bool mirror,u16 screen_width,u16 width,u16 height,enum omap_color_mode color_mode,bool fieldmode,unsigned int field_offset,unsigned * offset0,unsigned * offset1,s32 * row_inc,s32 * pix_inc,int x_predecim,int y_predecim)1864 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1865 u16 screen_width,
1866 u16 width, u16 height,
1867 enum omap_color_mode color_mode, bool fieldmode,
1868 unsigned int field_offset,
1869 unsigned *offset0, unsigned *offset1,
1870 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1871 {
1872 u8 ps;
1873
1874 /* FIXME CLUT formats */
1875 switch (color_mode) {
1876 case OMAP_DSS_COLOR_CLUT1:
1877 case OMAP_DSS_COLOR_CLUT2:
1878 case OMAP_DSS_COLOR_CLUT4:
1879 case OMAP_DSS_COLOR_CLUT8:
1880 BUG();
1881 return;
1882 case OMAP_DSS_COLOR_YUV2:
1883 case OMAP_DSS_COLOR_UYVY:
1884 ps = 4;
1885 break;
1886 default:
1887 ps = color_mode_to_bpp(color_mode) / 8;
1888 break;
1889 }
1890
1891 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1892 width, height);
1893
1894 /*
1895 * field 0 = even field = bottom field
1896 * field 1 = odd field = top field
1897 */
1898 switch (rotation + mirror * 4) {
1899 case OMAP_DSS_ROT_0:
1900 case OMAP_DSS_ROT_180:
1901 /*
1902 * If the pixel format is YUV or UYVY divide the width
1903 * of the image by 2 for 0 and 180 degree rotation.
1904 */
1905 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1906 color_mode == OMAP_DSS_COLOR_UYVY)
1907 width = width >> 1;
1908 /* fall through */
1909 case OMAP_DSS_ROT_90:
1910 case OMAP_DSS_ROT_270:
1911 *offset1 = 0;
1912 if (field_offset)
1913 *offset0 = field_offset * screen_width * ps;
1914 else
1915 *offset0 = 0;
1916
1917 *row_inc = pixinc(1 +
1918 (y_predecim * screen_width - x_predecim * width) +
1919 (fieldmode ? screen_width : 0), ps);
1920 *pix_inc = pixinc(x_predecim, ps);
1921 break;
1922
1923 case OMAP_DSS_ROT_0 + 4:
1924 case OMAP_DSS_ROT_180 + 4:
1925 /* If the pixel format is YUV or UYVY divide the width
1926 * of the image by 2 for 0 degree and 180 degree
1927 */
1928 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1929 color_mode == OMAP_DSS_COLOR_UYVY)
1930 width = width >> 1;
1931 /* fall through */
1932 case OMAP_DSS_ROT_90 + 4:
1933 case OMAP_DSS_ROT_270 + 4:
1934 *offset1 = 0;
1935 if (field_offset)
1936 *offset0 = field_offset * screen_width * ps;
1937 else
1938 *offset0 = 0;
1939 *row_inc = pixinc(1 -
1940 (y_predecim * screen_width + x_predecim * width) -
1941 (fieldmode ? screen_width : 0), ps);
1942 *pix_inc = pixinc(x_predecim, ps);
1943 break;
1944
1945 default:
1946 BUG();
1947 return;
1948 }
1949 }
1950
calc_dma_rotation_offset(u8 rotation,bool mirror,u16 screen_width,u16 width,u16 height,enum omap_color_mode color_mode,bool fieldmode,unsigned int field_offset,unsigned * offset0,unsigned * offset1,s32 * row_inc,s32 * pix_inc,int x_predecim,int y_predecim)1951 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1952 u16 screen_width,
1953 u16 width, u16 height,
1954 enum omap_color_mode color_mode, bool fieldmode,
1955 unsigned int field_offset,
1956 unsigned *offset0, unsigned *offset1,
1957 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1958 {
1959 u8 ps;
1960 u16 fbw, fbh;
1961
1962 /* FIXME CLUT formats */
1963 switch (color_mode) {
1964 case OMAP_DSS_COLOR_CLUT1:
1965 case OMAP_DSS_COLOR_CLUT2:
1966 case OMAP_DSS_COLOR_CLUT4:
1967 case OMAP_DSS_COLOR_CLUT8:
1968 BUG();
1969 return;
1970 default:
1971 ps = color_mode_to_bpp(color_mode) / 8;
1972 break;
1973 }
1974
1975 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1976 width, height);
1977
1978 /* width & height are overlay sizes, convert to fb sizes */
1979
1980 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1981 fbw = width;
1982 fbh = height;
1983 } else {
1984 fbw = height;
1985 fbh = width;
1986 }
1987
1988 /*
1989 * field 0 = even field = bottom field
1990 * field 1 = odd field = top field
1991 */
1992 switch (rotation + mirror * 4) {
1993 case OMAP_DSS_ROT_0:
1994 *offset1 = 0;
1995 if (field_offset)
1996 *offset0 = *offset1 + field_offset * screen_width * ps;
1997 else
1998 *offset0 = *offset1;
1999 *row_inc = pixinc(1 +
2000 (y_predecim * screen_width - fbw * x_predecim) +
2001 (fieldmode ? screen_width : 0), ps);
2002 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2003 color_mode == OMAP_DSS_COLOR_UYVY)
2004 *pix_inc = pixinc(x_predecim, 2 * ps);
2005 else
2006 *pix_inc = pixinc(x_predecim, ps);
2007 break;
2008 case OMAP_DSS_ROT_90:
2009 *offset1 = screen_width * (fbh - 1) * ps;
2010 if (field_offset)
2011 *offset0 = *offset1 + field_offset * ps;
2012 else
2013 *offset0 = *offset1;
2014 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
2015 y_predecim + (fieldmode ? 1 : 0), ps);
2016 *pix_inc = pixinc(-x_predecim * screen_width, ps);
2017 break;
2018 case OMAP_DSS_ROT_180:
2019 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2020 if (field_offset)
2021 *offset0 = *offset1 - field_offset * screen_width * ps;
2022 else
2023 *offset0 = *offset1;
2024 *row_inc = pixinc(-1 -
2025 (y_predecim * screen_width - fbw * x_predecim) -
2026 (fieldmode ? screen_width : 0), ps);
2027 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2028 color_mode == OMAP_DSS_COLOR_UYVY)
2029 *pix_inc = pixinc(-x_predecim, 2 * ps);
2030 else
2031 *pix_inc = pixinc(-x_predecim, ps);
2032 break;
2033 case OMAP_DSS_ROT_270:
2034 *offset1 = (fbw - 1) * ps;
2035 if (field_offset)
2036 *offset0 = *offset1 - field_offset * ps;
2037 else
2038 *offset0 = *offset1;
2039 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
2040 y_predecim - (fieldmode ? 1 : 0), ps);
2041 *pix_inc = pixinc(x_predecim * screen_width, ps);
2042 break;
2043
2044 /* mirroring */
2045 case OMAP_DSS_ROT_0 + 4:
2046 *offset1 = (fbw - 1) * ps;
2047 if (field_offset)
2048 *offset0 = *offset1 + field_offset * screen_width * ps;
2049 else
2050 *offset0 = *offset1;
2051 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
2052 (fieldmode ? screen_width : 0),
2053 ps);
2054 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2055 color_mode == OMAP_DSS_COLOR_UYVY)
2056 *pix_inc = pixinc(-x_predecim, 2 * ps);
2057 else
2058 *pix_inc = pixinc(-x_predecim, ps);
2059 break;
2060
2061 case OMAP_DSS_ROT_90 + 4:
2062 *offset1 = 0;
2063 if (field_offset)
2064 *offset0 = *offset1 + field_offset * ps;
2065 else
2066 *offset0 = *offset1;
2067 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
2068 y_predecim + (fieldmode ? 1 : 0),
2069 ps);
2070 *pix_inc = pixinc(x_predecim * screen_width, ps);
2071 break;
2072
2073 case OMAP_DSS_ROT_180 + 4:
2074 *offset1 = screen_width * (fbh - 1) * ps;
2075 if (field_offset)
2076 *offset0 = *offset1 - field_offset * screen_width * ps;
2077 else
2078 *offset0 = *offset1;
2079 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
2080 (fieldmode ? screen_width : 0),
2081 ps);
2082 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2083 color_mode == OMAP_DSS_COLOR_UYVY)
2084 *pix_inc = pixinc(x_predecim, 2 * ps);
2085 else
2086 *pix_inc = pixinc(x_predecim, ps);
2087 break;
2088
2089 case OMAP_DSS_ROT_270 + 4:
2090 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2091 if (field_offset)
2092 *offset0 = *offset1 - field_offset * ps;
2093 else
2094 *offset0 = *offset1;
2095 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
2096 y_predecim - (fieldmode ? 1 : 0),
2097 ps);
2098 *pix_inc = pixinc(-x_predecim * screen_width, ps);
2099 break;
2100
2101 default:
2102 BUG();
2103 return;
2104 }
2105 }
2106
calc_tiler_rotation_offset(u16 screen_width,u16 width,enum omap_color_mode color_mode,bool fieldmode,unsigned int field_offset,unsigned * offset0,unsigned * offset1,s32 * row_inc,s32 * pix_inc,int x_predecim,int y_predecim)2107 static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
2108 enum omap_color_mode color_mode, bool fieldmode,
2109 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
2110 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
2111 {
2112 u8 ps;
2113
2114 switch (color_mode) {
2115 case OMAP_DSS_COLOR_CLUT1:
2116 case OMAP_DSS_COLOR_CLUT2:
2117 case OMAP_DSS_COLOR_CLUT4:
2118 case OMAP_DSS_COLOR_CLUT8:
2119 BUG();
2120 return;
2121 default:
2122 ps = color_mode_to_bpp(color_mode) / 8;
2123 break;
2124 }
2125
2126 DSSDBG("scrw %d, width %d\n", screen_width, width);
2127
2128 /*
2129 * field 0 = even field = bottom field
2130 * field 1 = odd field = top field
2131 */
2132 *offset1 = 0;
2133 if (field_offset)
2134 *offset0 = *offset1 + field_offset * screen_width * ps;
2135 else
2136 *offset0 = *offset1;
2137 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
2138 (fieldmode ? screen_width : 0), ps);
2139 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2140 color_mode == OMAP_DSS_COLOR_UYVY)
2141 *pix_inc = pixinc(x_predecim, 2 * ps);
2142 else
2143 *pix_inc = pixinc(x_predecim, ps);
2144 }
2145
2146 /*
2147 * This function is used to avoid synclosts in OMAP3, because of some
2148 * undocumented horizontal position and timing related limitations.
2149 */
check_horiz_timing_omap3(unsigned long pclk,unsigned long lclk,const struct omap_video_timings * t,u16 pos_x,u16 width,u16 height,u16 out_width,u16 out_height,bool five_taps)2150 static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
2151 const struct omap_video_timings *t, u16 pos_x,
2152 u16 width, u16 height, u16 out_width, u16 out_height,
2153 bool five_taps)
2154 {
2155 const int ds = DIV_ROUND_UP(height, out_height);
2156 unsigned long nonactive;
2157 static const u8 limits[3] = { 8, 10, 20 };
2158 u64 val, blank;
2159 int i;
2160
2161 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
2162
2163 i = 0;
2164 if (out_height < height)
2165 i++;
2166 if (out_width < width)
2167 i++;
2168 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
2169 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2170 if (blank <= limits[i])
2171 return -EINVAL;
2172
2173 /* FIXME add checks for 3-tap filter once the limitations are known */
2174 if (!five_taps)
2175 return 0;
2176
2177 /*
2178 * Pixel data should be prepared before visible display point starts.
2179 * So, atleast DS-2 lines must have already been fetched by DISPC
2180 * during nonactive - pos_x period.
2181 */
2182 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2183 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
2184 val, max(0, ds - 2) * width);
2185 if (val < max(0, ds - 2) * width)
2186 return -EINVAL;
2187
2188 /*
2189 * All lines need to be refilled during the nonactive period of which
2190 * only one line can be loaded during the active period. So, atleast
2191 * DS - 1 lines should be loaded during nonactive period.
2192 */
2193 val = div_u64((u64)nonactive * lclk, pclk);
2194 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
2195 val, max(0, ds - 1) * width);
2196 if (val < max(0, ds - 1) * width)
2197 return -EINVAL;
2198
2199 return 0;
2200 }
2201
calc_core_clk_five_taps(unsigned long pclk,const struct omap_video_timings * mgr_timings,u16 width,u16 height,u16 out_width,u16 out_height,enum omap_color_mode color_mode)2202 static unsigned long calc_core_clk_five_taps(unsigned long pclk,
2203 const struct omap_video_timings *mgr_timings, u16 width,
2204 u16 height, u16 out_width, u16 out_height,
2205 enum omap_color_mode color_mode)
2206 {
2207 u32 core_clk = 0;
2208 u64 tmp;
2209
2210 if (height <= out_height && width <= out_width)
2211 return (unsigned long) pclk;
2212
2213 if (height > out_height) {
2214 unsigned int ppl = mgr_timings->x_res;
2215
2216 tmp = (u64)pclk * height * out_width;
2217 do_div(tmp, 2 * out_height * ppl);
2218 core_clk = tmp;
2219
2220 if (height > 2 * out_height) {
2221 if (ppl == out_width)
2222 return 0;
2223
2224 tmp = (u64)pclk * (height - 2 * out_height) * out_width;
2225 do_div(tmp, 2 * out_height * (ppl - out_width));
2226 core_clk = max_t(u32, core_clk, tmp);
2227 }
2228 }
2229
2230 if (width > out_width) {
2231 tmp = (u64)pclk * width;
2232 do_div(tmp, out_width);
2233 core_clk = max_t(u32, core_clk, tmp);
2234
2235 if (color_mode == OMAP_DSS_COLOR_RGB24U)
2236 core_clk <<= 1;
2237 }
2238
2239 return core_clk;
2240 }
2241
calc_core_clk_24xx(unsigned long pclk,u16 width,u16 height,u16 out_width,u16 out_height,bool mem_to_mem)2242 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
2243 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2244 {
2245 if (height > out_height && width > out_width)
2246 return pclk * 4;
2247 else
2248 return pclk * 2;
2249 }
2250
calc_core_clk_34xx(unsigned long pclk,u16 width,u16 height,u16 out_width,u16 out_height,bool mem_to_mem)2251 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
2252 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2253 {
2254 unsigned int hf, vf;
2255
2256 /*
2257 * FIXME how to determine the 'A' factor
2258 * for the no downscaling case ?
2259 */
2260
2261 if (width > 3 * out_width)
2262 hf = 4;
2263 else if (width > 2 * out_width)
2264 hf = 3;
2265 else if (width > out_width)
2266 hf = 2;
2267 else
2268 hf = 1;
2269 if (height > out_height)
2270 vf = 2;
2271 else
2272 vf = 1;
2273
2274 return pclk * vf * hf;
2275 }
2276
calc_core_clk_44xx(unsigned long pclk,u16 width,u16 height,u16 out_width,u16 out_height,bool mem_to_mem)2277 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
2278 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2279 {
2280 /*
2281 * If the overlay/writeback is in mem to mem mode, there are no
2282 * downscaling limitations with respect to pixel clock, return 1 as
2283 * required core clock to represent that we have sufficient enough
2284 * core clock to do maximum downscaling
2285 */
2286 if (mem_to_mem)
2287 return 1;
2288
2289 if (width > out_width)
2290 return DIV_ROUND_UP(pclk, out_width) * width;
2291 else
2292 return pclk;
2293 }
2294
dispc_ovl_calc_scaling_24xx(unsigned long pclk,unsigned long lclk,const struct omap_video_timings * mgr_timings,u16 width,u16 height,u16 out_width,u16 out_height,enum omap_color_mode color_mode,bool * five_taps,int * x_predecim,int * y_predecim,int * decim_x,int * decim_y,u16 pos_x,unsigned long * core_clk,bool mem_to_mem)2295 static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
2296 const struct omap_video_timings *mgr_timings,
2297 u16 width, u16 height, u16 out_width, u16 out_height,
2298 enum omap_color_mode color_mode, bool *five_taps,
2299 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2300 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2301 {
2302 int error;
2303 u16 in_width, in_height;
2304 int min_factor = min(*decim_x, *decim_y);
2305 const int maxsinglelinewidth =
2306 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2307
2308 *five_taps = false;
2309
2310 do {
2311 in_height = height / *decim_y;
2312 in_width = width / *decim_x;
2313 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2314 in_height, out_width, out_height, mem_to_mem);
2315 error = (in_width > maxsinglelinewidth || !*core_clk ||
2316 *core_clk > dispc_core_clk_rate());
2317 if (error) {
2318 if (*decim_x == *decim_y) {
2319 *decim_x = min_factor;
2320 ++*decim_y;
2321 } else {
2322 swap(*decim_x, *decim_y);
2323 if (*decim_x < *decim_y)
2324 ++*decim_x;
2325 }
2326 }
2327 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2328
2329 if (error) {
2330 DSSERR("failed to find scaling settings\n");
2331 return -EINVAL;
2332 }
2333
2334 if (in_width > maxsinglelinewidth) {
2335 DSSERR("Cannot scale max input width exceeded");
2336 return -EINVAL;
2337 }
2338 return 0;
2339 }
2340
dispc_ovl_calc_scaling_34xx(unsigned long pclk,unsigned long lclk,const struct omap_video_timings * mgr_timings,u16 width,u16 height,u16 out_width,u16 out_height,enum omap_color_mode color_mode,bool * five_taps,int * x_predecim,int * y_predecim,int * decim_x,int * decim_y,u16 pos_x,unsigned long * core_clk,bool mem_to_mem)2341 static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
2342 const struct omap_video_timings *mgr_timings,
2343 u16 width, u16 height, u16 out_width, u16 out_height,
2344 enum omap_color_mode color_mode, bool *five_taps,
2345 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2346 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2347 {
2348 int error;
2349 u16 in_width, in_height;
2350 const int maxsinglelinewidth =
2351 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2352
2353 do {
2354 in_height = height / *decim_y;
2355 in_width = width / *decim_x;
2356 *five_taps = in_height > out_height;
2357
2358 if (in_width > maxsinglelinewidth)
2359 if (in_height > out_height &&
2360 in_height < out_height * 2)
2361 *five_taps = false;
2362 again:
2363 if (*five_taps)
2364 *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2365 in_width, in_height, out_width,
2366 out_height, color_mode);
2367 else
2368 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2369 in_height, out_width, out_height,
2370 mem_to_mem);
2371
2372 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2373 pos_x, in_width, in_height, out_width,
2374 out_height, *five_taps);
2375 if (error && *five_taps) {
2376 *five_taps = false;
2377 goto again;
2378 }
2379
2380 error = (error || in_width > maxsinglelinewidth * 2 ||
2381 (in_width > maxsinglelinewidth && *five_taps) ||
2382 !*core_clk || *core_clk > dispc_core_clk_rate());
2383
2384 if (!error) {
2385 /* verify that we're inside the limits of scaler */
2386 if (in_width / 4 > out_width)
2387 error = 1;
2388
2389 if (*five_taps) {
2390 if (in_height / 4 > out_height)
2391 error = 1;
2392 } else {
2393 if (in_height / 2 > out_height)
2394 error = 1;
2395 }
2396 }
2397
2398 if (error)
2399 ++*decim_y;
2400 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2401
2402 if (error) {
2403 DSSERR("failed to find scaling settings\n");
2404 return -EINVAL;
2405 }
2406
2407 if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, in_width,
2408 in_height, out_width, out_height, *five_taps)) {
2409 DSSERR("horizontal timing too tight\n");
2410 return -EINVAL;
2411 }
2412
2413 if (in_width > (maxsinglelinewidth * 2)) {
2414 DSSERR("Cannot setup scaling");
2415 DSSERR("width exceeds maximum width possible");
2416 return -EINVAL;
2417 }
2418
2419 if (in_width > maxsinglelinewidth && *five_taps) {
2420 DSSERR("cannot setup scaling with five taps");
2421 return -EINVAL;
2422 }
2423 return 0;
2424 }
2425
dispc_ovl_calc_scaling_44xx(unsigned long pclk,unsigned long lclk,const struct omap_video_timings * mgr_timings,u16 width,u16 height,u16 out_width,u16 out_height,enum omap_color_mode color_mode,bool * five_taps,int * x_predecim,int * y_predecim,int * decim_x,int * decim_y,u16 pos_x,unsigned long * core_clk,bool mem_to_mem)2426 static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
2427 const struct omap_video_timings *mgr_timings,
2428 u16 width, u16 height, u16 out_width, u16 out_height,
2429 enum omap_color_mode color_mode, bool *five_taps,
2430 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2431 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2432 {
2433 u16 in_width, in_width_max;
2434 int decim_x_min = *decim_x;
2435 u16 in_height = height / *decim_y;
2436 const int maxsinglelinewidth =
2437 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2438 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2439
2440 if (mem_to_mem) {
2441 in_width_max = out_width * maxdownscale;
2442 } else {
2443 in_width_max = dispc_core_clk_rate() /
2444 DIV_ROUND_UP(pclk, out_width);
2445 }
2446
2447 *decim_x = DIV_ROUND_UP(width, in_width_max);
2448
2449 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2450 if (*decim_x > *x_predecim)
2451 return -EINVAL;
2452
2453 do {
2454 in_width = width / *decim_x;
2455 } while (*decim_x <= *x_predecim &&
2456 in_width > maxsinglelinewidth && ++*decim_x);
2457
2458 if (in_width > maxsinglelinewidth) {
2459 DSSERR("Cannot scale width exceeds max line width");
2460 return -EINVAL;
2461 }
2462
2463 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
2464 out_width, out_height, mem_to_mem);
2465 return 0;
2466 }
2467
2468 #define DIV_FRAC(dividend, divisor) \
2469 ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
2470
dispc_ovl_calc_scaling(unsigned long pclk,unsigned long lclk,enum omap_overlay_caps caps,const struct omap_video_timings * mgr_timings,u16 width,u16 height,u16 out_width,u16 out_height,enum omap_color_mode color_mode,bool * five_taps,int * x_predecim,int * y_predecim,u16 pos_x,enum omap_dss_rotation_type rotation_type,bool mem_to_mem)2471 static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2472 enum omap_overlay_caps caps,
2473 const struct omap_video_timings *mgr_timings,
2474 u16 width, u16 height, u16 out_width, u16 out_height,
2475 enum omap_color_mode color_mode, bool *five_taps,
2476 int *x_predecim, int *y_predecim, u16 pos_x,
2477 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
2478 {
2479 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2480 const int max_decim_limit = 16;
2481 unsigned long core_clk = 0;
2482 int decim_x, decim_y, ret;
2483
2484 if (width == out_width && height == out_height)
2485 return 0;
2486
2487 if (!mem_to_mem && (pclk == 0 || mgr_timings->pixelclock == 0)) {
2488 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2489 return -EINVAL;
2490 }
2491
2492 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2493 return -EINVAL;
2494
2495 if (mem_to_mem) {
2496 *x_predecim = *y_predecim = 1;
2497 } else {
2498 *x_predecim = max_decim_limit;
2499 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2500 dss_has_feature(FEAT_BURST_2D)) ?
2501 2 : max_decim_limit;
2502 }
2503
2504 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2505 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2506 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2507 color_mode == OMAP_DSS_COLOR_CLUT8) {
2508 *x_predecim = 1;
2509 *y_predecim = 1;
2510 *five_taps = false;
2511 return 0;
2512 }
2513
2514 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2515 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2516
2517 if (decim_x > *x_predecim || out_width > width * 8)
2518 return -EINVAL;
2519
2520 if (decim_y > *y_predecim || out_height > height * 8)
2521 return -EINVAL;
2522
2523 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
2524 out_width, out_height, color_mode, five_taps,
2525 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2526 mem_to_mem);
2527 if (ret)
2528 return ret;
2529
2530 DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n",
2531 width, height,
2532 out_width, out_height,
2533 out_width / width, DIV_FRAC(out_width, width),
2534 out_height / height, DIV_FRAC(out_height, height),
2535
2536 decim_x, decim_y,
2537 width / decim_x, height / decim_y,
2538 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x),
2539 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y),
2540
2541 *five_taps ? 5 : 3,
2542 core_clk, dispc_core_clk_rate());
2543
2544 if (!core_clk || core_clk > dispc_core_clk_rate()) {
2545 DSSERR("failed to set up scaling, "
2546 "required core clk rate = %lu Hz, "
2547 "current core clk rate = %lu Hz\n",
2548 core_clk, dispc_core_clk_rate());
2549 return -EINVAL;
2550 }
2551
2552 *x_predecim = decim_x;
2553 *y_predecim = decim_y;
2554 return 0;
2555 }
2556
dispc_ovl_check(enum omap_plane plane,enum omap_channel channel,const struct omap_overlay_info * oi,const struct omap_video_timings * timings,int * x_predecim,int * y_predecim)2557 int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
2558 const struct omap_overlay_info *oi,
2559 const struct omap_video_timings *timings,
2560 int *x_predecim, int *y_predecim)
2561 {
2562 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2563 bool five_taps = true;
2564 bool fieldmode = false;
2565 u16 in_height = oi->height;
2566 u16 in_width = oi->width;
2567 bool ilace = timings->interlace;
2568 u16 out_width, out_height;
2569 int pos_x = oi->pos_x;
2570 unsigned long pclk = dispc_mgr_pclk_rate(channel);
2571 unsigned long lclk = dispc_mgr_lclk_rate(channel);
2572
2573 out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2574 out_height = oi->out_height == 0 ? oi->height : oi->out_height;
2575
2576 if (ilace && oi->height == out_height)
2577 fieldmode = true;
2578
2579 if (ilace) {
2580 if (fieldmode)
2581 in_height /= 2;
2582 out_height /= 2;
2583
2584 DSSDBG("adjusting for ilace: height %d, out_height %d\n",
2585 in_height, out_height);
2586 }
2587
2588 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
2589 return -EINVAL;
2590
2591 return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width,
2592 in_height, out_width, out_height, oi->color_mode,
2593 &five_taps, x_predecim, y_predecim, pos_x,
2594 oi->rotation_type, false);
2595 }
2596 EXPORT_SYMBOL(dispc_ovl_check);
2597
dispc_ovl_setup_common(enum omap_plane plane,enum omap_overlay_caps caps,u32 paddr,u32 p_uv_addr,u16 screen_width,int pos_x,int pos_y,u16 width,u16 height,u16 out_width,u16 out_height,enum omap_color_mode color_mode,u8 rotation,bool mirror,u8 zorder,u8 pre_mult_alpha,u8 global_alpha,enum omap_dss_rotation_type rotation_type,bool replication,const struct omap_video_timings * mgr_timings,bool mem_to_mem)2598 static int dispc_ovl_setup_common(enum omap_plane plane,
2599 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2600 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2601 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2602 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2603 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
2604 bool replication, const struct omap_video_timings *mgr_timings,
2605 bool mem_to_mem)
2606 {
2607 bool five_taps = true;
2608 bool fieldmode = false;
2609 int r, cconv = 0;
2610 unsigned offset0, offset1;
2611 s32 row_inc;
2612 s32 pix_inc;
2613 u16 frame_width, frame_height;
2614 unsigned int field_offset = 0;
2615 u16 in_height = height;
2616 u16 in_width = width;
2617 int x_predecim = 1, y_predecim = 1;
2618 bool ilace = mgr_timings->interlace;
2619 unsigned long pclk = dispc_plane_pclk_rate(plane);
2620 unsigned long lclk = dispc_plane_lclk_rate(plane);
2621
2622 if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
2623 return -EINVAL;
2624
2625 switch (color_mode) {
2626 case OMAP_DSS_COLOR_YUV2:
2627 case OMAP_DSS_COLOR_UYVY:
2628 case OMAP_DSS_COLOR_NV12:
2629 if (in_width & 1) {
2630 DSSERR("input width %d is not even for YUV format\n",
2631 in_width);
2632 return -EINVAL;
2633 }
2634 break;
2635
2636 default:
2637 break;
2638 }
2639
2640 out_width = out_width == 0 ? width : out_width;
2641 out_height = out_height == 0 ? height : out_height;
2642
2643 if (ilace && height == out_height)
2644 fieldmode = true;
2645
2646 if (ilace) {
2647 if (fieldmode)
2648 in_height /= 2;
2649 pos_y /= 2;
2650 out_height /= 2;
2651
2652 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2653 "out_height %d\n", in_height, pos_y,
2654 out_height);
2655 }
2656
2657 if (!dss_feat_color_mode_supported(plane, color_mode))
2658 return -EINVAL;
2659
2660 r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
2661 in_height, out_width, out_height, color_mode,
2662 &five_taps, &x_predecim, &y_predecim, pos_x,
2663 rotation_type, mem_to_mem);
2664 if (r)
2665 return r;
2666
2667 in_width = in_width / x_predecim;
2668 in_height = in_height / y_predecim;
2669
2670 if (x_predecim > 1 || y_predecim > 1)
2671 DSSDBG("predecimation %d x %x, new input size %d x %d\n",
2672 x_predecim, y_predecim, in_width, in_height);
2673
2674 switch (color_mode) {
2675 case OMAP_DSS_COLOR_YUV2:
2676 case OMAP_DSS_COLOR_UYVY:
2677 case OMAP_DSS_COLOR_NV12:
2678 if (in_width & 1) {
2679 DSSDBG("predecimated input width is not even for YUV format\n");
2680 DSSDBG("adjusting input width %d -> %d\n",
2681 in_width, in_width & ~1);
2682
2683 in_width &= ~1;
2684 }
2685 break;
2686
2687 default:
2688 break;
2689 }
2690
2691 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2692 color_mode == OMAP_DSS_COLOR_UYVY ||
2693 color_mode == OMAP_DSS_COLOR_NV12)
2694 cconv = 1;
2695
2696 if (ilace && !fieldmode) {
2697 /*
2698 * when downscaling the bottom field may have to start several
2699 * source lines below the top field. Unfortunately ACCUI
2700 * registers will only hold the fractional part of the offset
2701 * so the integer part must be added to the base address of the
2702 * bottom field.
2703 */
2704 if (!in_height || in_height == out_height)
2705 field_offset = 0;
2706 else
2707 field_offset = in_height / out_height / 2;
2708 }
2709
2710 /* Fields are independent but interleaved in memory. */
2711 if (fieldmode)
2712 field_offset = 1;
2713
2714 offset0 = 0;
2715 offset1 = 0;
2716 row_inc = 0;
2717 pix_inc = 0;
2718
2719 if (plane == OMAP_DSS_WB) {
2720 frame_width = out_width;
2721 frame_height = out_height;
2722 } else {
2723 frame_width = in_width;
2724 frame_height = height;
2725 }
2726
2727 if (rotation_type == OMAP_DSS_ROT_TILER)
2728 calc_tiler_rotation_offset(screen_width, frame_width,
2729 color_mode, fieldmode, field_offset,
2730 &offset0, &offset1, &row_inc, &pix_inc,
2731 x_predecim, y_predecim);
2732 else if (rotation_type == OMAP_DSS_ROT_DMA)
2733 calc_dma_rotation_offset(rotation, mirror, screen_width,
2734 frame_width, frame_height,
2735 color_mode, fieldmode, field_offset,
2736 &offset0, &offset1, &row_inc, &pix_inc,
2737 x_predecim, y_predecim);
2738 else
2739 calc_vrfb_rotation_offset(rotation, mirror,
2740 screen_width, frame_width, frame_height,
2741 color_mode, fieldmode, field_offset,
2742 &offset0, &offset1, &row_inc, &pix_inc,
2743 x_predecim, y_predecim);
2744
2745 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2746 offset0, offset1, row_inc, pix_inc);
2747
2748 dispc_ovl_set_color_mode(plane, color_mode);
2749
2750 dispc_ovl_configure_burst_type(plane, rotation_type);
2751
2752 dispc_ovl_set_ba0(plane, paddr + offset0);
2753 dispc_ovl_set_ba1(plane, paddr + offset1);
2754
2755 if (OMAP_DSS_COLOR_NV12 == color_mode) {
2756 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2757 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
2758 }
2759
2760 if (dispc.feat->last_pixel_inc_missing)
2761 row_inc += pix_inc - 1;
2762
2763 dispc_ovl_set_row_inc(plane, row_inc);
2764 dispc_ovl_set_pix_inc(plane, pix_inc);
2765
2766 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
2767 in_height, out_width, out_height);
2768
2769 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
2770
2771 dispc_ovl_set_input_size(plane, in_width, in_height);
2772
2773 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
2774 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2775 out_height, ilace, five_taps, fieldmode,
2776 color_mode, rotation);
2777 dispc_ovl_set_output_size(plane, out_width, out_height);
2778 dispc_ovl_set_vid_color_conv(plane, cconv);
2779 }
2780
2781 dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
2782 color_mode);
2783
2784 dispc_ovl_set_zorder(plane, caps, zorder);
2785 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2786 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
2787
2788 dispc_ovl_enable_replication(plane, caps, replication);
2789
2790 return 0;
2791 }
2792
dispc_ovl_setup(enum omap_plane plane,const struct omap_overlay_info * oi,bool replication,const struct omap_video_timings * mgr_timings,bool mem_to_mem)2793 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
2794 bool replication, const struct omap_video_timings *mgr_timings,
2795 bool mem_to_mem)
2796 {
2797 int r;
2798 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2799 enum omap_channel channel;
2800
2801 channel = dispc_ovl_get_channel_out(plane);
2802
2803 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
2804 " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2805 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
2806 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2807 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2808
2809 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
2810 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2811 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2812 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
2813 oi->rotation_type, replication, mgr_timings, mem_to_mem);
2814
2815 return r;
2816 }
2817 EXPORT_SYMBOL(dispc_ovl_setup);
2818
dispc_wb_setup(const struct omap_dss_writeback_info * wi,bool mem_to_mem,const struct omap_video_timings * mgr_timings)2819 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2820 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
2821 {
2822 int r;
2823 u32 l;
2824 enum omap_plane plane = OMAP_DSS_WB;
2825 const int pos_x = 0, pos_y = 0;
2826 const u8 zorder = 0, global_alpha = 0;
2827 const bool replication = false;
2828 bool truncation;
2829 int in_width = mgr_timings->x_res;
2830 int in_height = mgr_timings->y_res;
2831 enum omap_overlay_caps caps =
2832 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2833
2834 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2835 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2836 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2837 wi->mirror);
2838
2839 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2840 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2841 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2842 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
2843 replication, mgr_timings, mem_to_mem);
2844
2845 switch (wi->color_mode) {
2846 case OMAP_DSS_COLOR_RGB16:
2847 case OMAP_DSS_COLOR_RGB24P:
2848 case OMAP_DSS_COLOR_ARGB16:
2849 case OMAP_DSS_COLOR_RGBA16:
2850 case OMAP_DSS_COLOR_RGB12U:
2851 case OMAP_DSS_COLOR_ARGB16_1555:
2852 case OMAP_DSS_COLOR_XRGB16_1555:
2853 case OMAP_DSS_COLOR_RGBX16:
2854 truncation = true;
2855 break;
2856 default:
2857 truncation = false;
2858 break;
2859 }
2860
2861 /* setup extra DISPC_WB_ATTRIBUTES */
2862 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2863 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */
2864 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */
2865 if (mem_to_mem)
2866 l = FLD_MOD(l, 1, 26, 24); /* CAPTUREMODE */
2867 else
2868 l = FLD_MOD(l, 0, 26, 24); /* CAPTUREMODE */
2869 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
2870
2871 if (mem_to_mem) {
2872 /* WBDELAYCOUNT */
2873 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0);
2874 } else {
2875 int wbdelay;
2876
2877 wbdelay = min(mgr_timings->vfp + mgr_timings->vsw +
2878 mgr_timings->vbp, 255);
2879
2880 /* WBDELAYCOUNT */
2881 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0);
2882 }
2883
2884 return r;
2885 }
2886
dispc_ovl_enable(enum omap_plane plane,bool enable)2887 int dispc_ovl_enable(enum omap_plane plane, bool enable)
2888 {
2889 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2890
2891 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2892
2893 return 0;
2894 }
2895 EXPORT_SYMBOL(dispc_ovl_enable);
2896
dispc_ovl_enabled(enum omap_plane plane)2897 bool dispc_ovl_enabled(enum omap_plane plane)
2898 {
2899 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2900 }
2901 EXPORT_SYMBOL(dispc_ovl_enabled);
2902
dispc_mgr_enable(enum omap_channel channel,bool enable)2903 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2904 {
2905 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2906 /* flush posted write */
2907 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2908 }
2909 EXPORT_SYMBOL(dispc_mgr_enable);
2910
dispc_mgr_is_enabled(enum omap_channel channel)2911 bool dispc_mgr_is_enabled(enum omap_channel channel)
2912 {
2913 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2914 }
2915 EXPORT_SYMBOL(dispc_mgr_is_enabled);
2916
dispc_wb_enable(bool enable)2917 void dispc_wb_enable(bool enable)
2918 {
2919 dispc_ovl_enable(OMAP_DSS_WB, enable);
2920 }
2921
dispc_wb_is_enabled(void)2922 bool dispc_wb_is_enabled(void)
2923 {
2924 return dispc_ovl_enabled(OMAP_DSS_WB);
2925 }
2926
dispc_lcd_enable_signal_polarity(bool act_high)2927 static void dispc_lcd_enable_signal_polarity(bool act_high)
2928 {
2929 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2930 return;
2931
2932 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2933 }
2934
dispc_lcd_enable_signal(bool enable)2935 void dispc_lcd_enable_signal(bool enable)
2936 {
2937 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2938 return;
2939
2940 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2941 }
2942
dispc_pck_free_enable(bool enable)2943 void dispc_pck_free_enable(bool enable)
2944 {
2945 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2946 return;
2947
2948 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2949 }
2950
dispc_mgr_enable_fifohandcheck(enum omap_channel channel,bool enable)2951 static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2952 {
2953 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2954 }
2955
2956
dispc_mgr_set_lcd_type_tft(enum omap_channel channel)2957 static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
2958 {
2959 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
2960 }
2961
dispc_set_loadmode(enum omap_dss_load_mode mode)2962 static void dispc_set_loadmode(enum omap_dss_load_mode mode)
2963 {
2964 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2965 }
2966
2967
dispc_mgr_set_default_color(enum omap_channel channel,u32 color)2968 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2969 {
2970 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2971 }
2972
dispc_mgr_set_trans_key(enum omap_channel ch,enum omap_dss_trans_key_type type,u32 trans_key)2973 static void dispc_mgr_set_trans_key(enum omap_channel ch,
2974 enum omap_dss_trans_key_type type,
2975 u32 trans_key)
2976 {
2977 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
2978
2979 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2980 }
2981
dispc_mgr_enable_trans_key(enum omap_channel ch,bool enable)2982 static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2983 {
2984 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
2985 }
2986
dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,bool enable)2987 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2988 bool enable)
2989 {
2990 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2991 return;
2992
2993 if (ch == OMAP_DSS_CHANNEL_LCD)
2994 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2995 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2996 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2997 }
2998
dispc_mgr_setup(enum omap_channel channel,const struct omap_overlay_manager_info * info)2999 void dispc_mgr_setup(enum omap_channel channel,
3000 const struct omap_overlay_manager_info *info)
3001 {
3002 dispc_mgr_set_default_color(channel, info->default_color);
3003 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
3004 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
3005 dispc_mgr_enable_alpha_fixed_zorder(channel,
3006 info->partial_alpha_enabled);
3007 if (dss_has_feature(FEAT_CPR)) {
3008 dispc_mgr_enable_cpr(channel, info->cpr_enable);
3009 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
3010 }
3011 }
3012 EXPORT_SYMBOL(dispc_mgr_setup);
3013
dispc_mgr_set_tft_data_lines(enum omap_channel channel,u8 data_lines)3014 static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
3015 {
3016 int code;
3017
3018 switch (data_lines) {
3019 case 12:
3020 code = 0;
3021 break;
3022 case 16:
3023 code = 1;
3024 break;
3025 case 18:
3026 code = 2;
3027 break;
3028 case 24:
3029 code = 3;
3030 break;
3031 default:
3032 BUG();
3033 return;
3034 }
3035
3036 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
3037 }
3038
dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)3039 static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
3040 {
3041 u32 l;
3042 int gpout0, gpout1;
3043
3044 switch (mode) {
3045 case DSS_IO_PAD_MODE_RESET:
3046 gpout0 = 0;
3047 gpout1 = 0;
3048 break;
3049 case DSS_IO_PAD_MODE_RFBI:
3050 gpout0 = 1;
3051 gpout1 = 0;
3052 break;
3053 case DSS_IO_PAD_MODE_BYPASS:
3054 gpout0 = 1;
3055 gpout1 = 1;
3056 break;
3057 default:
3058 BUG();
3059 return;
3060 }
3061
3062 l = dispc_read_reg(DISPC_CONTROL);
3063 l = FLD_MOD(l, gpout0, 15, 15);
3064 l = FLD_MOD(l, gpout1, 16, 16);
3065 dispc_write_reg(DISPC_CONTROL, l);
3066 }
3067
dispc_mgr_enable_stallmode(enum omap_channel channel,bool enable)3068 static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
3069 {
3070 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
3071 }
3072
dispc_mgr_set_lcd_config(enum omap_channel channel,const struct dss_lcd_mgr_config * config)3073 void dispc_mgr_set_lcd_config(enum omap_channel channel,
3074 const struct dss_lcd_mgr_config *config)
3075 {
3076 dispc_mgr_set_io_pad_mode(config->io_pad_mode);
3077
3078 dispc_mgr_enable_stallmode(channel, config->stallmode);
3079 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
3080
3081 dispc_mgr_set_clock_div(channel, &config->clock_info);
3082
3083 dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
3084
3085 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
3086
3087 dispc_mgr_set_lcd_type_tft(channel);
3088 }
3089 EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
3090
_dispc_mgr_size_ok(u16 width,u16 height)3091 static bool _dispc_mgr_size_ok(u16 width, u16 height)
3092 {
3093 return width <= dispc.feat->mgr_width_max &&
3094 height <= dispc.feat->mgr_height_max;
3095 }
3096
_dispc_lcd_timings_ok(int hsw,int hfp,int hbp,int vsw,int vfp,int vbp)3097 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
3098 int vsw, int vfp, int vbp)
3099 {
3100 if (hsw < 1 || hsw > dispc.feat->sw_max ||
3101 hfp < 1 || hfp > dispc.feat->hp_max ||
3102 hbp < 1 || hbp > dispc.feat->hp_max ||
3103 vsw < 1 || vsw > dispc.feat->sw_max ||
3104 vfp < 0 || vfp > dispc.feat->vp_max ||
3105 vbp < 0 || vbp > dispc.feat->vp_max)
3106 return false;
3107 return true;
3108 }
3109
_dispc_mgr_pclk_ok(enum omap_channel channel,unsigned long pclk)3110 static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
3111 unsigned long pclk)
3112 {
3113 if (dss_mgr_is_lcd(channel))
3114 return pclk <= dispc.feat->max_lcd_pclk ? true : false;
3115 else
3116 return pclk <= dispc.feat->max_tv_pclk ? true : false;
3117 }
3118
dispc_mgr_timings_ok(enum omap_channel channel,const struct omap_video_timings * timings)3119 bool dispc_mgr_timings_ok(enum omap_channel channel,
3120 const struct omap_video_timings *timings)
3121 {
3122 if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res))
3123 return false;
3124
3125 if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock))
3126 return false;
3127
3128 if (dss_mgr_is_lcd(channel)) {
3129 /* TODO: OMAP4+ supports interlace for LCD outputs */
3130 if (timings->interlace)
3131 return false;
3132
3133 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
3134 timings->hbp, timings->vsw, timings->vfp,
3135 timings->vbp))
3136 return false;
3137 }
3138
3139 return true;
3140 }
3141
_dispc_mgr_set_lcd_timings(enum omap_channel channel,int hsw,int hfp,int hbp,int vsw,int vfp,int vbp,enum omap_dss_signal_level vsync_level,enum omap_dss_signal_level hsync_level,enum omap_dss_signal_edge data_pclk_edge,enum omap_dss_signal_level de_level,enum omap_dss_signal_edge sync_pclk_edge)3142 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
3143 int hfp, int hbp, int vsw, int vfp, int vbp,
3144 enum omap_dss_signal_level vsync_level,
3145 enum omap_dss_signal_level hsync_level,
3146 enum omap_dss_signal_edge data_pclk_edge,
3147 enum omap_dss_signal_level de_level,
3148 enum omap_dss_signal_edge sync_pclk_edge)
3149
3150 {
3151 u32 timing_h, timing_v, l;
3152 bool onoff, rf, ipc, vs, hs, de;
3153
3154 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
3155 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
3156 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
3157 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
3158 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
3159 FLD_VAL(vbp, dispc.feat->bp_start, 20);
3160
3161 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
3162 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
3163
3164 switch (vsync_level) {
3165 case OMAPDSS_SIG_ACTIVE_LOW:
3166 vs = true;
3167 break;
3168 case OMAPDSS_SIG_ACTIVE_HIGH:
3169 vs = false;
3170 break;
3171 default:
3172 BUG();
3173 }
3174
3175 switch (hsync_level) {
3176 case OMAPDSS_SIG_ACTIVE_LOW:
3177 hs = true;
3178 break;
3179 case OMAPDSS_SIG_ACTIVE_HIGH:
3180 hs = false;
3181 break;
3182 default:
3183 BUG();
3184 }
3185
3186 switch (de_level) {
3187 case OMAPDSS_SIG_ACTIVE_LOW:
3188 de = true;
3189 break;
3190 case OMAPDSS_SIG_ACTIVE_HIGH:
3191 de = false;
3192 break;
3193 default:
3194 BUG();
3195 }
3196
3197 switch (data_pclk_edge) {
3198 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3199 ipc = false;
3200 break;
3201 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3202 ipc = true;
3203 break;
3204 default:
3205 BUG();
3206 }
3207
3208 /* always use the 'rf' setting */
3209 onoff = true;
3210
3211 switch (sync_pclk_edge) {
3212 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3213 rf = false;
3214 break;
3215 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3216 rf = true;
3217 break;
3218 default:
3219 BUG();
3220 }
3221
3222 l = FLD_VAL(onoff, 17, 17) |
3223 FLD_VAL(rf, 16, 16) |
3224 FLD_VAL(de, 15, 15) |
3225 FLD_VAL(ipc, 14, 14) |
3226 FLD_VAL(hs, 13, 13) |
3227 FLD_VAL(vs, 12, 12);
3228
3229 /* always set ALIGN bit when available */
3230 if (dispc.feat->supports_sync_align)
3231 l |= (1 << 18);
3232
3233 dispc_write_reg(DISPC_POL_FREQ(channel), l);
3234
3235 if (dispc.syscon_pol) {
3236 const int shifts[] = {
3237 [OMAP_DSS_CHANNEL_LCD] = 0,
3238 [OMAP_DSS_CHANNEL_LCD2] = 1,
3239 [OMAP_DSS_CHANNEL_LCD3] = 2,
3240 };
3241
3242 u32 mask, val;
3243
3244 mask = (1 << 0) | (1 << 3) | (1 << 6);
3245 val = (rf << 0) | (ipc << 3) | (onoff << 6);
3246
3247 mask <<= 16 + shifts[channel];
3248 val <<= 16 + shifts[channel];
3249
3250 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset,
3251 mask, val);
3252 }
3253 }
3254
3255 /* change name to mode? */
dispc_mgr_set_timings(enum omap_channel channel,const struct omap_video_timings * timings)3256 void dispc_mgr_set_timings(enum omap_channel channel,
3257 const struct omap_video_timings *timings)
3258 {
3259 unsigned xtot, ytot;
3260 unsigned long ht, vt;
3261 struct omap_video_timings t = *timings;
3262
3263 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
3264
3265 if (!dispc_mgr_timings_ok(channel, &t)) {
3266 BUG();
3267 return;
3268 }
3269
3270 if (dss_mgr_is_lcd(channel)) {
3271 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
3272 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
3273 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
3274
3275 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
3276 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
3277
3278 ht = timings->pixelclock / xtot;
3279 vt = timings->pixelclock / xtot / ytot;
3280
3281 DSSDBG("pck %u\n", timings->pixelclock);
3282 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
3283 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
3284 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3285 t.vsync_level, t.hsync_level, t.data_pclk_edge,
3286 t.de_level, t.sync_pclk_edge);
3287
3288 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
3289 } else {
3290 if (t.interlace)
3291 t.y_res /= 2;
3292 }
3293
3294 dispc_mgr_set_size(channel, t.x_res, t.y_res);
3295 }
3296 EXPORT_SYMBOL(dispc_mgr_set_timings);
3297
dispc_mgr_set_lcd_divisor(enum omap_channel channel,u16 lck_div,u16 pck_div)3298 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
3299 u16 pck_div)
3300 {
3301 BUG_ON(lck_div < 1);
3302 BUG_ON(pck_div < 1);
3303
3304 dispc_write_reg(DISPC_DIVISORo(channel),
3305 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
3306
3307 if (!dss_has_feature(FEAT_CORE_CLK_DIV) &&
3308 channel == OMAP_DSS_CHANNEL_LCD)
3309 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
3310 }
3311
dispc_mgr_get_lcd_divisor(enum omap_channel channel,int * lck_div,int * pck_div)3312 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
3313 int *pck_div)
3314 {
3315 u32 l;
3316 l = dispc_read_reg(DISPC_DIVISORo(channel));
3317 *lck_div = FLD_GET(l, 23, 16);
3318 *pck_div = FLD_GET(l, 7, 0);
3319 }
3320
dispc_fclk_rate(void)3321 static unsigned long dispc_fclk_rate(void)
3322 {
3323 struct dss_pll *pll;
3324 unsigned long r = 0;
3325
3326 switch (dss_get_dispc_clk_source()) {
3327 case OMAP_DSS_CLK_SRC_FCK:
3328 r = dss_get_dispc_clk_rate();
3329 break;
3330 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3331 pll = dss_pll_find("dsi0");
3332 if (!pll)
3333 pll = dss_pll_find("video0");
3334
3335 r = pll->cinfo.clkout[0];
3336 break;
3337 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3338 pll = dss_pll_find("dsi1");
3339 if (!pll)
3340 pll = dss_pll_find("video1");
3341
3342 r = pll->cinfo.clkout[0];
3343 break;
3344 default:
3345 BUG();
3346 return 0;
3347 }
3348
3349 return r;
3350 }
3351
dispc_mgr_lclk_rate(enum omap_channel channel)3352 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
3353 {
3354 struct dss_pll *pll;
3355 int lcd;
3356 unsigned long r;
3357 u32 l;
3358
3359 if (dss_mgr_is_lcd(channel)) {
3360 l = dispc_read_reg(DISPC_DIVISORo(channel));
3361
3362 lcd = FLD_GET(l, 23, 16);
3363
3364 switch (dss_get_lcd_clk_source(channel)) {
3365 case OMAP_DSS_CLK_SRC_FCK:
3366 r = dss_get_dispc_clk_rate();
3367 break;
3368 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3369 pll = dss_pll_find("dsi0");
3370 if (!pll)
3371 pll = dss_pll_find("video0");
3372
3373 r = pll->cinfo.clkout[0];
3374 break;
3375 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3376 pll = dss_pll_find("dsi1");
3377 if (!pll)
3378 pll = dss_pll_find("video1");
3379
3380 r = pll->cinfo.clkout[0];
3381 break;
3382 default:
3383 BUG();
3384 return 0;
3385 }
3386
3387 return r / lcd;
3388 } else {
3389 return dispc_fclk_rate();
3390 }
3391 }
3392
dispc_mgr_pclk_rate(enum omap_channel channel)3393 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
3394 {
3395 unsigned long r;
3396
3397 if (dss_mgr_is_lcd(channel)) {
3398 int pcd;
3399 u32 l;
3400
3401 l = dispc_read_reg(DISPC_DIVISORo(channel));
3402
3403 pcd = FLD_GET(l, 7, 0);
3404
3405 r = dispc_mgr_lclk_rate(channel);
3406
3407 return r / pcd;
3408 } else {
3409 return dispc.tv_pclk_rate;
3410 }
3411 }
3412
dispc_set_tv_pclk(unsigned long pclk)3413 void dispc_set_tv_pclk(unsigned long pclk)
3414 {
3415 dispc.tv_pclk_rate = pclk;
3416 }
3417
dispc_core_clk_rate(void)3418 static unsigned long dispc_core_clk_rate(void)
3419 {
3420 return dispc.core_clk_rate;
3421 }
3422
dispc_plane_pclk_rate(enum omap_plane plane)3423 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3424 {
3425 enum omap_channel channel;
3426
3427 if (plane == OMAP_DSS_WB)
3428 return 0;
3429
3430 channel = dispc_ovl_get_channel_out(plane);
3431
3432 return dispc_mgr_pclk_rate(channel);
3433 }
3434
dispc_plane_lclk_rate(enum omap_plane plane)3435 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3436 {
3437 enum omap_channel channel;
3438
3439 if (plane == OMAP_DSS_WB)
3440 return 0;
3441
3442 channel = dispc_ovl_get_channel_out(plane);
3443
3444 return dispc_mgr_lclk_rate(channel);
3445 }
3446
dispc_dump_clocks_channel(struct seq_file * s,enum omap_channel channel)3447 static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
3448 {
3449 int lcd, pcd;
3450 enum omap_dss_clk_source lcd_clk_src;
3451
3452 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3453
3454 lcd_clk_src = dss_get_lcd_clk_source(channel);
3455
3456 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3457 dss_get_generic_clk_source_name(lcd_clk_src),
3458 dss_feat_get_clk_source_name(lcd_clk_src));
3459
3460 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3461
3462 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3463 dispc_mgr_lclk_rate(channel), lcd);
3464 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3465 dispc_mgr_pclk_rate(channel), pcd);
3466 }
3467
dispc_dump_clocks(struct seq_file * s)3468 void dispc_dump_clocks(struct seq_file *s)
3469 {
3470 int lcd;
3471 u32 l;
3472 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
3473
3474 if (dispc_runtime_get())
3475 return;
3476
3477 seq_printf(s, "- DISPC -\n");
3478
3479 seq_printf(s, "dispc fclk source = %s (%s)\n",
3480 dss_get_generic_clk_source_name(dispc_clk_src),
3481 dss_feat_get_clk_source_name(dispc_clk_src));
3482
3483 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
3484
3485 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3486 seq_printf(s, "- DISPC-CORE-CLK -\n");
3487 l = dispc_read_reg(DISPC_DIVISOR);
3488 lcd = FLD_GET(l, 23, 16);
3489
3490 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3491 (dispc_fclk_rate()/lcd), lcd);
3492 }
3493
3494 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
3495
3496 if (dss_has_feature(FEAT_MGR_LCD2))
3497 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3498 if (dss_has_feature(FEAT_MGR_LCD3))
3499 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
3500
3501 dispc_runtime_put();
3502 }
3503
dispc_dump_regs(struct seq_file * s)3504 static void dispc_dump_regs(struct seq_file *s)
3505 {
3506 int i, j;
3507 const char *mgr_names[] = {
3508 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3509 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3510 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
3511 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
3512 };
3513 const char *ovl_names[] = {
3514 [OMAP_DSS_GFX] = "GFX",
3515 [OMAP_DSS_VIDEO1] = "VID1",
3516 [OMAP_DSS_VIDEO2] = "VID2",
3517 [OMAP_DSS_VIDEO3] = "VID3",
3518 [OMAP_DSS_WB] = "WB",
3519 };
3520 const char **p_names;
3521
3522 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
3523
3524 if (dispc_runtime_get())
3525 return;
3526
3527 /* DISPC common registers */
3528 DUMPREG(DISPC_REVISION);
3529 DUMPREG(DISPC_SYSCONFIG);
3530 DUMPREG(DISPC_SYSSTATUS);
3531 DUMPREG(DISPC_IRQSTATUS);
3532 DUMPREG(DISPC_IRQENABLE);
3533 DUMPREG(DISPC_CONTROL);
3534 DUMPREG(DISPC_CONFIG);
3535 DUMPREG(DISPC_CAPABLE);
3536 DUMPREG(DISPC_LINE_STATUS);
3537 DUMPREG(DISPC_LINE_NUMBER);
3538 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3539 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
3540 DUMPREG(DISPC_GLOBAL_ALPHA);
3541 if (dss_has_feature(FEAT_MGR_LCD2)) {
3542 DUMPREG(DISPC_CONTROL2);
3543 DUMPREG(DISPC_CONFIG2);
3544 }
3545 if (dss_has_feature(FEAT_MGR_LCD3)) {
3546 DUMPREG(DISPC_CONTROL3);
3547 DUMPREG(DISPC_CONFIG3);
3548 }
3549 if (dss_has_feature(FEAT_MFLAG))
3550 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
3551
3552 #undef DUMPREG
3553
3554 #define DISPC_REG(i, name) name(i)
3555 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3556 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
3557 dispc_read_reg(DISPC_REG(i, r)))
3558
3559 p_names = mgr_names;
3560
3561 /* DISPC channel specific registers */
3562 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3563 DUMPREG(i, DISPC_DEFAULT_COLOR);
3564 DUMPREG(i, DISPC_TRANS_COLOR);
3565 DUMPREG(i, DISPC_SIZE_MGR);
3566
3567 if (i == OMAP_DSS_CHANNEL_DIGIT)
3568 continue;
3569
3570 DUMPREG(i, DISPC_TIMING_H);
3571 DUMPREG(i, DISPC_TIMING_V);
3572 DUMPREG(i, DISPC_POL_FREQ);
3573 DUMPREG(i, DISPC_DIVISORo);
3574
3575 DUMPREG(i, DISPC_DATA_CYCLE1);
3576 DUMPREG(i, DISPC_DATA_CYCLE2);
3577 DUMPREG(i, DISPC_DATA_CYCLE3);
3578
3579 if (dss_has_feature(FEAT_CPR)) {
3580 DUMPREG(i, DISPC_CPR_COEF_R);
3581 DUMPREG(i, DISPC_CPR_COEF_G);
3582 DUMPREG(i, DISPC_CPR_COEF_B);
3583 }
3584 }
3585
3586 p_names = ovl_names;
3587
3588 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3589 DUMPREG(i, DISPC_OVL_BA0);
3590 DUMPREG(i, DISPC_OVL_BA1);
3591 DUMPREG(i, DISPC_OVL_POSITION);
3592 DUMPREG(i, DISPC_OVL_SIZE);
3593 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3594 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3595 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3596 DUMPREG(i, DISPC_OVL_ROW_INC);
3597 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3598
3599 if (dss_has_feature(FEAT_PRELOAD))
3600 DUMPREG(i, DISPC_OVL_PRELOAD);
3601 if (dss_has_feature(FEAT_MFLAG))
3602 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3603
3604 if (i == OMAP_DSS_GFX) {
3605 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3606 DUMPREG(i, DISPC_OVL_TABLE_BA);
3607 continue;
3608 }
3609
3610 DUMPREG(i, DISPC_OVL_FIR);
3611 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3612 DUMPREG(i, DISPC_OVL_ACCU0);
3613 DUMPREG(i, DISPC_OVL_ACCU1);
3614 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3615 DUMPREG(i, DISPC_OVL_BA0_UV);
3616 DUMPREG(i, DISPC_OVL_BA1_UV);
3617 DUMPREG(i, DISPC_OVL_FIR2);
3618 DUMPREG(i, DISPC_OVL_ACCU2_0);
3619 DUMPREG(i, DISPC_OVL_ACCU2_1);
3620 }
3621 if (dss_has_feature(FEAT_ATTR2))
3622 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3623 }
3624
3625 if (dispc.feat->has_writeback) {
3626 i = OMAP_DSS_WB;
3627 DUMPREG(i, DISPC_OVL_BA0);
3628 DUMPREG(i, DISPC_OVL_BA1);
3629 DUMPREG(i, DISPC_OVL_SIZE);
3630 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3631 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3632 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3633 DUMPREG(i, DISPC_OVL_ROW_INC);
3634 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3635
3636 if (dss_has_feature(FEAT_MFLAG))
3637 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3638
3639 DUMPREG(i, DISPC_OVL_FIR);
3640 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3641 DUMPREG(i, DISPC_OVL_ACCU0);
3642 DUMPREG(i, DISPC_OVL_ACCU1);
3643 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3644 DUMPREG(i, DISPC_OVL_BA0_UV);
3645 DUMPREG(i, DISPC_OVL_BA1_UV);
3646 DUMPREG(i, DISPC_OVL_FIR2);
3647 DUMPREG(i, DISPC_OVL_ACCU2_0);
3648 DUMPREG(i, DISPC_OVL_ACCU2_1);
3649 }
3650 if (dss_has_feature(FEAT_ATTR2))
3651 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3652 }
3653
3654 #undef DISPC_REG
3655 #undef DUMPREG
3656
3657 #define DISPC_REG(plane, name, i) name(plane, i)
3658 #define DUMPREG(plane, name, i) \
3659 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3660 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
3661 dispc_read_reg(DISPC_REG(plane, name, i)))
3662
3663 /* Video pipeline coefficient registers */
3664
3665 /* start from OMAP_DSS_VIDEO1 */
3666 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3667 for (j = 0; j < 8; j++)
3668 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
3669
3670 for (j = 0; j < 8; j++)
3671 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
3672
3673 for (j = 0; j < 5; j++)
3674 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
3675
3676 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3677 for (j = 0; j < 8; j++)
3678 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3679 }
3680
3681 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3682 for (j = 0; j < 8; j++)
3683 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3684
3685 for (j = 0; j < 8; j++)
3686 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3687
3688 for (j = 0; j < 8; j++)
3689 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3690 }
3691 }
3692
3693 dispc_runtime_put();
3694
3695 #undef DISPC_REG
3696 #undef DUMPREG
3697 }
3698
3699 /* calculate clock rates using dividers in cinfo */
dispc_calc_clock_rates(unsigned long dispc_fclk_rate,struct dispc_clock_info * cinfo)3700 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3701 struct dispc_clock_info *cinfo)
3702 {
3703 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3704 return -EINVAL;
3705 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
3706 return -EINVAL;
3707
3708 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3709 cinfo->pck = cinfo->lck / cinfo->pck_div;
3710
3711 return 0;
3712 }
3713
dispc_div_calc(unsigned long dispc,unsigned long pck_min,unsigned long pck_max,dispc_div_calc_func func,void * data)3714 bool dispc_div_calc(unsigned long dispc,
3715 unsigned long pck_min, unsigned long pck_max,
3716 dispc_div_calc_func func, void *data)
3717 {
3718 int lckd, lckd_start, lckd_stop;
3719 int pckd, pckd_start, pckd_stop;
3720 unsigned long pck, lck;
3721 unsigned long lck_max;
3722 unsigned long pckd_hw_min, pckd_hw_max;
3723 unsigned min_fck_per_pck;
3724 unsigned long fck;
3725
3726 #ifdef CONFIG_FB_OMAP2_DSS_MIN_FCK_PER_PCK
3727 min_fck_per_pck = CONFIG_FB_OMAP2_DSS_MIN_FCK_PER_PCK;
3728 #else
3729 min_fck_per_pck = 0;
3730 #endif
3731
3732 pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3733 pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3734
3735 lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
3736
3737 pck_min = pck_min ? pck_min : 1;
3738 pck_max = pck_max ? pck_max : ULONG_MAX;
3739
3740 lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3741 lckd_stop = min(dispc / pck_min, 255ul);
3742
3743 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3744 lck = dispc / lckd;
3745
3746 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3747 pckd_stop = min(lck / pck_min, pckd_hw_max);
3748
3749 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3750 pck = lck / pckd;
3751
3752 /*
3753 * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3754 * clock, which means we're configuring DISPC fclk here
3755 * also. Thus we need to use the calculated lck. For
3756 * OMAP4+ the DISPC fclk is a separate clock.
3757 */
3758 if (dss_has_feature(FEAT_CORE_CLK_DIV))
3759 fck = dispc_core_clk_rate();
3760 else
3761 fck = lck;
3762
3763 if (fck < pck * min_fck_per_pck)
3764 continue;
3765
3766 if (func(lckd, pckd, lck, pck, data))
3767 return true;
3768 }
3769 }
3770
3771 return false;
3772 }
3773
dispc_mgr_set_clock_div(enum omap_channel channel,const struct dispc_clock_info * cinfo)3774 void dispc_mgr_set_clock_div(enum omap_channel channel,
3775 const struct dispc_clock_info *cinfo)
3776 {
3777 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3778 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3779
3780 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
3781 }
3782
dispc_mgr_get_clock_div(enum omap_channel channel,struct dispc_clock_info * cinfo)3783 int dispc_mgr_get_clock_div(enum omap_channel channel,
3784 struct dispc_clock_info *cinfo)
3785 {
3786 unsigned long fck;
3787
3788 fck = dispc_fclk_rate();
3789
3790 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3791 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
3792
3793 cinfo->lck = fck / cinfo->lck_div;
3794 cinfo->pck = cinfo->lck / cinfo->pck_div;
3795
3796 return 0;
3797 }
3798
dispc_read_irqstatus(void)3799 u32 dispc_read_irqstatus(void)
3800 {
3801 return dispc_read_reg(DISPC_IRQSTATUS);
3802 }
3803 EXPORT_SYMBOL(dispc_read_irqstatus);
3804
dispc_clear_irqstatus(u32 mask)3805 void dispc_clear_irqstatus(u32 mask)
3806 {
3807 dispc_write_reg(DISPC_IRQSTATUS, mask);
3808 }
3809 EXPORT_SYMBOL(dispc_clear_irqstatus);
3810
dispc_read_irqenable(void)3811 u32 dispc_read_irqenable(void)
3812 {
3813 return dispc_read_reg(DISPC_IRQENABLE);
3814 }
3815 EXPORT_SYMBOL(dispc_read_irqenable);
3816
dispc_write_irqenable(u32 mask)3817 void dispc_write_irqenable(u32 mask)
3818 {
3819 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3820
3821 /* clear the irqstatus for newly enabled irqs */
3822 dispc_clear_irqstatus((mask ^ old_mask) & mask);
3823
3824 dispc_write_reg(DISPC_IRQENABLE, mask);
3825 }
3826 EXPORT_SYMBOL(dispc_write_irqenable);
3827
dispc_enable_sidle(void)3828 void dispc_enable_sidle(void)
3829 {
3830 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3831 }
3832
dispc_disable_sidle(void)3833 void dispc_disable_sidle(void)
3834 {
3835 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3836 }
3837
_omap_dispc_initial_config(void)3838 static void _omap_dispc_initial_config(void)
3839 {
3840 u32 l;
3841
3842 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3843 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3844 l = dispc_read_reg(DISPC_DIVISOR);
3845 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3846 l = FLD_MOD(l, 1, 0, 0);
3847 l = FLD_MOD(l, 1, 23, 16);
3848 dispc_write_reg(DISPC_DIVISOR, l);
3849
3850 dispc.core_clk_rate = dispc_fclk_rate();
3851 }
3852
3853 /* FUNCGATED */
3854 if (dss_has_feature(FEAT_FUNCGATED))
3855 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3856
3857 dispc_setup_color_conv_coef();
3858
3859 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3860
3861 dispc_init_fifos();
3862
3863 dispc_configure_burst_sizes();
3864
3865 dispc_ovl_enable_zorder_planes();
3866
3867 if (dispc.feat->mstandby_workaround)
3868 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
3869
3870 if (dss_has_feature(FEAT_MFLAG))
3871 dispc_init_mflag();
3872 }
3873
3874 static const struct dispc_features omap24xx_dispc_feats = {
3875 .sw_start = 5,
3876 .fp_start = 15,
3877 .bp_start = 27,
3878 .sw_max = 64,
3879 .vp_max = 255,
3880 .hp_max = 256,
3881 .mgr_width_start = 10,
3882 .mgr_height_start = 26,
3883 .mgr_width_max = 2048,
3884 .mgr_height_max = 2048,
3885 .max_lcd_pclk = 66500000,
3886 .calc_scaling = dispc_ovl_calc_scaling_24xx,
3887 .calc_core_clk = calc_core_clk_24xx,
3888 .num_fifos = 3,
3889 .no_framedone_tv = true,
3890 .set_max_preload = false,
3891 .last_pixel_inc_missing = true,
3892 };
3893
3894 static const struct dispc_features omap34xx_rev1_0_dispc_feats = {
3895 .sw_start = 5,
3896 .fp_start = 15,
3897 .bp_start = 27,
3898 .sw_max = 64,
3899 .vp_max = 255,
3900 .hp_max = 256,
3901 .mgr_width_start = 10,
3902 .mgr_height_start = 26,
3903 .mgr_width_max = 2048,
3904 .mgr_height_max = 2048,
3905 .max_lcd_pclk = 173000000,
3906 .max_tv_pclk = 59000000,
3907 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3908 .calc_core_clk = calc_core_clk_34xx,
3909 .num_fifos = 3,
3910 .no_framedone_tv = true,
3911 .set_max_preload = false,
3912 .last_pixel_inc_missing = true,
3913 };
3914
3915 static const struct dispc_features omap34xx_rev3_0_dispc_feats = {
3916 .sw_start = 7,
3917 .fp_start = 19,
3918 .bp_start = 31,
3919 .sw_max = 256,
3920 .vp_max = 4095,
3921 .hp_max = 4096,
3922 .mgr_width_start = 10,
3923 .mgr_height_start = 26,
3924 .mgr_width_max = 2048,
3925 .mgr_height_max = 2048,
3926 .max_lcd_pclk = 173000000,
3927 .max_tv_pclk = 59000000,
3928 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3929 .calc_core_clk = calc_core_clk_34xx,
3930 .num_fifos = 3,
3931 .no_framedone_tv = true,
3932 .set_max_preload = false,
3933 .last_pixel_inc_missing = true,
3934 };
3935
3936 static const struct dispc_features omap44xx_dispc_feats = {
3937 .sw_start = 7,
3938 .fp_start = 19,
3939 .bp_start = 31,
3940 .sw_max = 256,
3941 .vp_max = 4095,
3942 .hp_max = 4096,
3943 .mgr_width_start = 10,
3944 .mgr_height_start = 26,
3945 .mgr_width_max = 2048,
3946 .mgr_height_max = 2048,
3947 .max_lcd_pclk = 170000000,
3948 .max_tv_pclk = 185625000,
3949 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3950 .calc_core_clk = calc_core_clk_44xx,
3951 .num_fifos = 5,
3952 .gfx_fifo_workaround = true,
3953 .set_max_preload = true,
3954 .supports_sync_align = true,
3955 .has_writeback = true,
3956 };
3957
3958 static const struct dispc_features omap54xx_dispc_feats = {
3959 .sw_start = 7,
3960 .fp_start = 19,
3961 .bp_start = 31,
3962 .sw_max = 256,
3963 .vp_max = 4095,
3964 .hp_max = 4096,
3965 .mgr_width_start = 11,
3966 .mgr_height_start = 27,
3967 .mgr_width_max = 4096,
3968 .mgr_height_max = 4096,
3969 .max_lcd_pclk = 170000000,
3970 .max_tv_pclk = 186000000,
3971 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3972 .calc_core_clk = calc_core_clk_44xx,
3973 .num_fifos = 5,
3974 .gfx_fifo_workaround = true,
3975 .mstandby_workaround = true,
3976 .set_max_preload = true,
3977 .supports_sync_align = true,
3978 .has_writeback = true,
3979 };
3980
dispc_get_features(void)3981 static const struct dispc_features *dispc_get_features(void)
3982 {
3983 switch (omapdss_get_version()) {
3984 case OMAPDSS_VER_OMAP24xx:
3985 return &omap24xx_dispc_feats;
3986
3987 case OMAPDSS_VER_OMAP34xx_ES1:
3988 return &omap34xx_rev1_0_dispc_feats;
3989
3990 case OMAPDSS_VER_OMAP34xx_ES3:
3991 case OMAPDSS_VER_OMAP3630:
3992 case OMAPDSS_VER_AM35xx:
3993 case OMAPDSS_VER_AM43xx:
3994 return &omap34xx_rev3_0_dispc_feats;
3995
3996 case OMAPDSS_VER_OMAP4430_ES1:
3997 case OMAPDSS_VER_OMAP4430_ES2:
3998 case OMAPDSS_VER_OMAP4:
3999 return &omap44xx_dispc_feats;
4000
4001 case OMAPDSS_VER_OMAP5:
4002 case OMAPDSS_VER_DRA7xx:
4003 return &omap54xx_dispc_feats;
4004
4005 default:
4006 return NULL;
4007 }
4008 }
4009
dispc_irq_handler(int irq,void * arg)4010 static irqreturn_t dispc_irq_handler(int irq, void *arg)
4011 {
4012 if (!dispc.is_enabled)
4013 return IRQ_NONE;
4014
4015 return dispc.user_handler(irq, dispc.user_data);
4016 }
4017
dispc_request_irq(irq_handler_t handler,void * dev_id)4018 int dispc_request_irq(irq_handler_t handler, void *dev_id)
4019 {
4020 int r;
4021
4022 if (dispc.user_handler != NULL)
4023 return -EBUSY;
4024
4025 dispc.user_handler = handler;
4026 dispc.user_data = dev_id;
4027
4028 /* ensure the dispc_irq_handler sees the values above */
4029 smp_wmb();
4030
4031 r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler,
4032 IRQF_SHARED, "OMAP DISPC", &dispc);
4033 if (r) {
4034 dispc.user_handler = NULL;
4035 dispc.user_data = NULL;
4036 }
4037
4038 return r;
4039 }
4040 EXPORT_SYMBOL(dispc_request_irq);
4041
dispc_free_irq(void * dev_id)4042 void dispc_free_irq(void *dev_id)
4043 {
4044 devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);
4045
4046 dispc.user_handler = NULL;
4047 dispc.user_data = NULL;
4048 }
4049 EXPORT_SYMBOL(dispc_free_irq);
4050
4051 /* DISPC HW IP initialisation */
dispc_bind(struct device * dev,struct device * master,void * data)4052 static int dispc_bind(struct device *dev, struct device *master, void *data)
4053 {
4054 struct platform_device *pdev = to_platform_device(dev);
4055 u32 rev;
4056 int r = 0;
4057 struct resource *dispc_mem;
4058 struct device_node *np = pdev->dev.of_node;
4059
4060 dispc.pdev = pdev;
4061
4062 spin_lock_init(&dispc.control_lock);
4063
4064 dispc.feat = dispc_get_features();
4065 if (!dispc.feat)
4066 return -ENODEV;
4067
4068 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
4069 if (!dispc_mem) {
4070 DSSERR("can't get IORESOURCE_MEM DISPC\n");
4071 return -EINVAL;
4072 }
4073
4074 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
4075 resource_size(dispc_mem));
4076 if (!dispc.base) {
4077 DSSERR("can't ioremap DISPC\n");
4078 return -ENOMEM;
4079 }
4080
4081 dispc.irq = platform_get_irq(dispc.pdev, 0);
4082 if (dispc.irq < 0) {
4083 DSSERR("platform_get_irq failed\n");
4084 return -ENODEV;
4085 }
4086
4087 if (np && of_property_read_bool(np, "syscon-pol")) {
4088 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");
4089 if (IS_ERR(dispc.syscon_pol)) {
4090 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n");
4091 return PTR_ERR(dispc.syscon_pol);
4092 }
4093
4094 if (of_property_read_u32_index(np, "syscon-pol", 1,
4095 &dispc.syscon_pol_offset)) {
4096 dev_err(&pdev->dev, "failed to get syscon-pol offset\n");
4097 return -EINVAL;
4098 }
4099 }
4100
4101 pm_runtime_enable(&pdev->dev);
4102
4103 r = dispc_runtime_get();
4104 if (r)
4105 goto err_runtime_get;
4106
4107 _omap_dispc_initial_config();
4108
4109 rev = dispc_read_reg(DISPC_REVISION);
4110 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
4111 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4112
4113 dispc_runtime_put();
4114
4115 dss_init_overlay_managers();
4116
4117 dss_debugfs_create_file("dispc", dispc_dump_regs);
4118
4119 return 0;
4120
4121 err_runtime_get:
4122 pm_runtime_disable(&pdev->dev);
4123 return r;
4124 }
4125
dispc_unbind(struct device * dev,struct device * master,void * data)4126 static void dispc_unbind(struct device *dev, struct device *master,
4127 void *data)
4128 {
4129 pm_runtime_disable(dev);
4130
4131 dss_uninit_overlay_managers();
4132 }
4133
4134 static const struct component_ops dispc_component_ops = {
4135 .bind = dispc_bind,
4136 .unbind = dispc_unbind,
4137 };
4138
dispc_probe(struct platform_device * pdev)4139 static int dispc_probe(struct platform_device *pdev)
4140 {
4141 return component_add(&pdev->dev, &dispc_component_ops);
4142 }
4143
dispc_remove(struct platform_device * pdev)4144 static int dispc_remove(struct platform_device *pdev)
4145 {
4146 component_del(&pdev->dev, &dispc_component_ops);
4147 return 0;
4148 }
4149
dispc_runtime_suspend(struct device * dev)4150 static int dispc_runtime_suspend(struct device *dev)
4151 {
4152 dispc.is_enabled = false;
4153 /* ensure the dispc_irq_handler sees the is_enabled value */
4154 smp_wmb();
4155 /* wait for current handler to finish before turning the DISPC off */
4156 synchronize_irq(dispc.irq);
4157
4158 dispc_save_context();
4159
4160 return 0;
4161 }
4162
dispc_runtime_resume(struct device * dev)4163 static int dispc_runtime_resume(struct device *dev)
4164 {
4165 /*
4166 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
4167 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
4168 * _omap_dispc_initial_config(). We can thus use it to detect if
4169 * we have lost register context.
4170 */
4171 if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
4172 _omap_dispc_initial_config();
4173
4174 dispc_restore_context();
4175 }
4176
4177 dispc.is_enabled = true;
4178 /* ensure the dispc_irq_handler sees the is_enabled value */
4179 smp_wmb();
4180
4181 return 0;
4182 }
4183
4184 static const struct dev_pm_ops dispc_pm_ops = {
4185 .runtime_suspend = dispc_runtime_suspend,
4186 .runtime_resume = dispc_runtime_resume,
4187 };
4188
4189 static const struct of_device_id dispc_of_match[] = {
4190 { .compatible = "ti,omap2-dispc", },
4191 { .compatible = "ti,omap3-dispc", },
4192 { .compatible = "ti,omap4-dispc", },
4193 { .compatible = "ti,omap5-dispc", },
4194 { .compatible = "ti,dra7-dispc", },
4195 {},
4196 };
4197
4198 static struct platform_driver omap_dispchw_driver = {
4199 .probe = dispc_probe,
4200 .remove = dispc_remove,
4201 .driver = {
4202 .name = "omapdss_dispc",
4203 .pm = &dispc_pm_ops,
4204 .of_match_table = dispc_of_match,
4205 .suppress_bind_attrs = true,
4206 },
4207 };
4208
dispc_init_platform_driver(void)4209 int __init dispc_init_platform_driver(void)
4210 {
4211 return platform_driver_register(&omap_dispchw_driver);
4212 }
4213
dispc_uninit_platform_driver(void)4214 void dispc_uninit_platform_driver(void)
4215 {
4216 platform_driver_unregister(&omap_dispchw_driver);
4217 }
4218