1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
2 /* Copyright(c) 2014 - 2020 Intel Corporation */
3 #ifndef ADF_ACCEL_DEVICES_H_
4 #define ADF_ACCEL_DEVICES_H_
5 #include <linux/interrupt.h>
6 #include <linux/module.h>
7 #include <linux/list.h>
8 #include <linux/io.h>
9 #include <linux/ratelimit.h>
10 #include "adf_cfg_common.h"
11
12 #define ADF_DH895XCC_DEVICE_NAME "dh895xcc"
13 #define ADF_DH895XCCVF_DEVICE_NAME "dh895xccvf"
14 #define ADF_C62X_DEVICE_NAME "c6xx"
15 #define ADF_C62XVF_DEVICE_NAME "c6xxvf"
16 #define ADF_C3XXX_DEVICE_NAME "c3xxx"
17 #define ADF_C3XXXVF_DEVICE_NAME "c3xxxvf"
18 #define ADF_ERRSOU3 (0x3A000 + 0x0C)
19 #define ADF_ERRSOU5 (0x3A000 + 0xD8)
20 #define ADF_DEVICE_FUSECTL_OFFSET 0x40
21 #define ADF_DEVICE_LEGFUSE_OFFSET 0x4C
22 #define ADF_DEVICE_FUSECTL_MASK 0x80000000
23 #define ADF_PCI_MAX_BARS 3
24 #define ADF_DEVICE_NAME_LENGTH 32
25 #define ADF_ETR_MAX_RINGS_PER_BANK 16
26 #define ADF_MAX_MSIX_VECTOR_NAME 16
27 #define ADF_DEVICE_NAME_PREFIX "qat_"
28
29 enum adf_accel_capabilities {
30 ADF_ACCEL_CAPABILITIES_NULL = 0,
31 ADF_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = 1,
32 ADF_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC = 2,
33 ADF_ACCEL_CAPABILITIES_CIPHER = 4,
34 ADF_ACCEL_CAPABILITIES_AUTHENTICATION = 8,
35 ADF_ACCEL_CAPABILITIES_COMPRESSION = 32,
36 ADF_ACCEL_CAPABILITIES_LZS_COMPRESSION = 64,
37 ADF_ACCEL_CAPABILITIES_RANDOM_NUMBER = 128
38 };
39
40 struct adf_bar {
41 resource_size_t base_addr;
42 void __iomem *virt_addr;
43 resource_size_t size;
44 } __packed;
45
46 struct adf_accel_msix {
47 struct msix_entry *entries;
48 char **names;
49 u32 num_entries;
50 } __packed;
51
52 struct adf_accel_pci {
53 struct pci_dev *pci_dev;
54 struct adf_accel_msix msix_entries;
55 struct adf_bar pci_bars[ADF_PCI_MAX_BARS];
56 u8 revid;
57 u8 sku;
58 } __packed;
59
60 enum dev_state {
61 DEV_DOWN = 0,
62 DEV_UP
63 };
64
65 enum dev_sku_info {
66 DEV_SKU_1 = 0,
67 DEV_SKU_2,
68 DEV_SKU_3,
69 DEV_SKU_4,
70 DEV_SKU_VF,
71 DEV_SKU_UNKNOWN,
72 };
73
get_sku_info(enum dev_sku_info info)74 static inline const char *get_sku_info(enum dev_sku_info info)
75 {
76 switch (info) {
77 case DEV_SKU_1:
78 return "SKU1";
79 case DEV_SKU_2:
80 return "SKU2";
81 case DEV_SKU_3:
82 return "SKU3";
83 case DEV_SKU_4:
84 return "SKU4";
85 case DEV_SKU_VF:
86 return "SKUVF";
87 case DEV_SKU_UNKNOWN:
88 default:
89 break;
90 }
91 return "Unknown SKU";
92 }
93
94 struct adf_hw_device_class {
95 const char *name;
96 const enum adf_device_type type;
97 u32 instances;
98 } __packed;
99
100 struct adf_cfg_device_data;
101 struct adf_accel_dev;
102 struct adf_etr_data;
103 struct adf_etr_ring_data;
104
105 struct adf_hw_device_data {
106 struct adf_hw_device_class *dev_class;
107 u32 (*get_accel_mask)(u32 fuse);
108 u32 (*get_ae_mask)(u32 fuse);
109 u32 (*get_sram_bar_id)(struct adf_hw_device_data *self);
110 u32 (*get_misc_bar_id)(struct adf_hw_device_data *self);
111 u32 (*get_etr_bar_id)(struct adf_hw_device_data *self);
112 u32 (*get_num_aes)(struct adf_hw_device_data *self);
113 u32 (*get_num_accels)(struct adf_hw_device_data *self);
114 u32 (*get_pf2vf_offset)(u32 i);
115 u32 (*get_vintmsk_offset)(u32 i);
116 enum dev_sku_info (*get_sku)(struct adf_hw_device_data *self);
117 int (*alloc_irq)(struct adf_accel_dev *accel_dev);
118 void (*free_irq)(struct adf_accel_dev *accel_dev);
119 void (*enable_error_correction)(struct adf_accel_dev *accel_dev);
120 int (*init_admin_comms)(struct adf_accel_dev *accel_dev);
121 void (*exit_admin_comms)(struct adf_accel_dev *accel_dev);
122 int (*send_admin_init)(struct adf_accel_dev *accel_dev);
123 int (*init_arb)(struct adf_accel_dev *accel_dev);
124 void (*exit_arb)(struct adf_accel_dev *accel_dev);
125 void (*get_arb_mapping)(struct adf_accel_dev *accel_dev,
126 const u32 **cfg);
127 void (*disable_iov)(struct adf_accel_dev *accel_dev);
128 void (*enable_ints)(struct adf_accel_dev *accel_dev);
129 int (*enable_vf2pf_comms)(struct adf_accel_dev *accel_dev);
130 void (*reset_device)(struct adf_accel_dev *accel_dev);
131 const char *fw_name;
132 const char *fw_mmp_name;
133 u32 fuses;
134 u32 accel_capabilities_mask;
135 u32 instance_id;
136 u16 accel_mask;
137 u16 ae_mask;
138 u16 tx_rings_mask;
139 u8 tx_rx_gap;
140 u8 num_banks;
141 u8 num_accel;
142 u8 num_logical_accel;
143 u8 num_engines;
144 u8 min_iov_compat_ver;
145 } __packed;
146
147 /* CSR write macro */
148 #define ADF_CSR_WR(csr_base, csr_offset, val) \
149 __raw_writel(val, csr_base + csr_offset)
150
151 /* CSR read macro */
152 #define ADF_CSR_RD(csr_base, csr_offset) __raw_readl(csr_base + csr_offset)
153
154 #define GET_DEV(accel_dev) ((accel_dev)->accel_pci_dev.pci_dev->dev)
155 #define GET_BARS(accel_dev) ((accel_dev)->accel_pci_dev.pci_bars)
156 #define GET_HW_DATA(accel_dev) (accel_dev->hw_device)
157 #define GET_MAX_BANKS(accel_dev) (GET_HW_DATA(accel_dev)->num_banks)
158 #define GET_MAX_ACCELENGINES(accel_dev) (GET_HW_DATA(accel_dev)->num_engines)
159 #define accel_to_pci_dev(accel_ptr) accel_ptr->accel_pci_dev.pci_dev
160
161 struct adf_admin_comms;
162 struct icp_qat_fw_loader_handle;
163 struct adf_fw_loader_data {
164 struct icp_qat_fw_loader_handle *fw_loader;
165 const struct firmware *uof_fw;
166 const struct firmware *mmp_fw;
167 };
168
169 struct adf_accel_vf_info {
170 struct adf_accel_dev *accel_dev;
171 struct tasklet_struct vf2pf_bh_tasklet;
172 struct mutex pf2vf_lock; /* protect CSR access for PF2VF messages */
173 struct ratelimit_state vf2pf_ratelimit;
174 u32 vf_nr;
175 bool init;
176 };
177
178 struct adf_accel_dev {
179 struct adf_etr_data *transport;
180 struct adf_hw_device_data *hw_device;
181 struct adf_cfg_device_data *cfg;
182 struct adf_fw_loader_data *fw_loader;
183 struct adf_admin_comms *admin;
184 struct list_head crypto_list;
185 unsigned long status;
186 atomic_t ref_count;
187 struct dentry *debugfs_dir;
188 struct list_head list;
189 struct module *owner;
190 struct adf_accel_pci accel_pci_dev;
191 union {
192 struct {
193 /* vf_info is non-zero when SR-IOV is init'ed */
194 struct adf_accel_vf_info *vf_info;
195 } pf;
196 struct {
197 char *irq_name;
198 struct tasklet_struct pf2vf_bh_tasklet;
199 struct mutex vf2pf_lock; /* protect CSR access */
200 struct completion iov_msg_completion;
201 u8 compatible;
202 u8 pf_version;
203 } vf;
204 };
205 bool is_vf;
206 u32 accel_id;
207 } __packed;
208 #endif
209
