1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * dim2.c - MediaLB DIM2 Hardware Dependent Module
4 *
5 * Copyright (C) 2015-2016, Microchip Technology Germany II GmbH & Co. KG
6 */
7
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10 #include <linux/module.h>
11 #include <linux/of_platform.h>
12 #include <linux/printk.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/interrupt.h>
17 #include <linux/slab.h>
18 #include <linux/io.h>
19 #include <linux/clk.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/sched.h>
22 #include <linux/kthread.h>
23
24 #include "most/core.h"
25 #include "hal.h"
26 #include "errors.h"
27 #include "sysfs.h"
28
29 #define DMA_CHANNELS (32 - 1) /* channel 0 is a system channel */
30
31 #define MAX_BUFFERS_PACKET 32
32 #define MAX_BUFFERS_STREAMING 32
33 #define MAX_BUF_SIZE_PACKET 2048
34 #define MAX_BUF_SIZE_STREAMING (8 * 1024)
35
36 /*
37 * The parameter representing the number of frames per sub-buffer for
38 * synchronous channels. Valid values: [0 .. 6].
39 *
40 * The values 0, 1, 2, 3, 4, 5, 6 represent corresponding number of frames per
41 * sub-buffer 1, 2, 4, 8, 16, 32, 64.
42 */
43 static u8 fcnt = 4; /* (1 << fcnt) frames per subbuffer */
44 module_param(fcnt, byte, 0000);
45 MODULE_PARM_DESC(fcnt, "Num of frames per sub-buffer for sync channels as a power of 2");
46
47 static DEFINE_SPINLOCK(dim_lock);
48
49 static void dim2_tasklet_fn(unsigned long data);
50 static DECLARE_TASKLET(dim2_tasklet, dim2_tasklet_fn, 0);
51
52 /**
53 * struct hdm_channel - private structure to keep channel specific data
54 * @is_initialized: identifier to know whether the channel is initialized
55 * @ch: HAL specific channel data
56 * @pending_list: list to keep MBO's before starting transfer
57 * @started_list: list to keep MBO's after starting transfer
58 * @direction: channel direction (TX or RX)
59 * @data_type: channel data type
60 */
61 struct hdm_channel {
62 char name[sizeof "caNNN"];
63 bool is_initialized;
64 struct dim_channel ch;
65 u16 *reset_dbr_size;
66 struct list_head pending_list; /* before dim_enqueue_buffer() */
67 struct list_head started_list; /* after dim_enqueue_buffer() */
68 enum most_channel_direction direction;
69 enum most_channel_data_type data_type;
70 };
71
72 /**
73 * struct dim2_hdm - private structure to keep interface specific data
74 * @hch: an array of channel specific data
75 * @most_iface: most interface structure
76 * @capabilities: an array of channel capability data
77 * @io_base: I/O register base address
78 * @netinfo_task: thread to deliver network status
79 * @netinfo_waitq: waitq for the thread to sleep
80 * @deliver_netinfo: to identify whether network status received
81 * @mac_addrs: INIC mac address
82 * @link_state: network link state
83 * @atx_idx: index of async tx channel
84 */
85 struct dim2_hdm {
86 struct device dev;
87 struct hdm_channel hch[DMA_CHANNELS];
88 struct most_channel_capability capabilities[DMA_CHANNELS];
89 struct most_interface most_iface;
90 char name[16 + sizeof "dim2-"];
91 void __iomem *io_base;
92 u8 clk_speed;
93 struct clk *clk;
94 struct clk *clk_pll;
95 struct task_struct *netinfo_task;
96 wait_queue_head_t netinfo_waitq;
97 int deliver_netinfo;
98 unsigned char mac_addrs[6];
99 unsigned char link_state;
100 int atx_idx;
101 struct medialb_bus bus;
102 void (*on_netinfo)(struct most_interface *most_iface,
103 unsigned char link_state, unsigned char *addrs);
104 void (*disable_platform)(struct platform_device *);
105 };
106
107 struct dim2_platform_data {
108 int (*enable)(struct platform_device *);
109 void (*disable)(struct platform_device *);
110 };
111
112 #define iface_to_hdm(iface) container_of(iface, struct dim2_hdm, most_iface)
113
114 /* Macro to identify a network status message */
115 #define PACKET_IS_NET_INFO(p) \
116 (((p)[1] == 0x18) && ((p)[2] == 0x05) && ((p)[3] == 0x0C) && \
117 ((p)[13] == 0x3C) && ((p)[14] == 0x00) && ((p)[15] == 0x0A))
118
dim2_sysfs_get_state_cb(void)119 bool dim2_sysfs_get_state_cb(void)
120 {
121 bool state;
122 unsigned long flags;
123
124 spin_lock_irqsave(&dim_lock, flags);
125 state = dim_get_lock_state();
126 spin_unlock_irqrestore(&dim_lock, flags);
127
128 return state;
129 }
130
131 /**
132 * dimcb_on_error - callback from HAL to report miscommunication between
133 * HDM and HAL
134 * @error_id: Error ID
135 * @error_message: Error message. Some text in a free format
136 */
dimcb_on_error(u8 error_id,const char * error_message)137 void dimcb_on_error(u8 error_id, const char *error_message)
138 {
139 pr_err("%s: error_id - %d, error_message - %s\n", __func__, error_id,
140 error_message);
141 }
142
143 /**
144 * try_start_dim_transfer - try to transfer a buffer on a channel
145 * @hdm_ch: channel specific data
146 *
147 * Transfer a buffer from pending_list if the channel is ready
148 */
try_start_dim_transfer(struct hdm_channel * hdm_ch)149 static int try_start_dim_transfer(struct hdm_channel *hdm_ch)
150 {
151 u16 buf_size;
152 struct list_head *head = &hdm_ch->pending_list;
153 struct mbo *mbo;
154 unsigned long flags;
155 struct dim_ch_state_t st;
156
157 BUG_ON(!hdm_ch);
158 BUG_ON(!hdm_ch->is_initialized);
159
160 spin_lock_irqsave(&dim_lock, flags);
161 if (list_empty(head)) {
162 spin_unlock_irqrestore(&dim_lock, flags);
163 return -EAGAIN;
164 }
165
166 if (!dim_get_channel_state(&hdm_ch->ch, &st)->ready) {
167 spin_unlock_irqrestore(&dim_lock, flags);
168 return -EAGAIN;
169 }
170
171 mbo = list_first_entry(head, struct mbo, list);
172 buf_size = mbo->buffer_length;
173
174 if (dim_dbr_space(&hdm_ch->ch) < buf_size) {
175 spin_unlock_irqrestore(&dim_lock, flags);
176 return -EAGAIN;
177 }
178
179 BUG_ON(mbo->bus_address == 0);
180 if (!dim_enqueue_buffer(&hdm_ch->ch, mbo->bus_address, buf_size)) {
181 list_del(head->next);
182 spin_unlock_irqrestore(&dim_lock, flags);
183 mbo->processed_length = 0;
184 mbo->status = MBO_E_INVAL;
185 mbo->complete(mbo);
186 return -EFAULT;
187 }
188
189 list_move_tail(head->next, &hdm_ch->started_list);
190 spin_unlock_irqrestore(&dim_lock, flags);
191
192 return 0;
193 }
194
195 /**
196 * deliver_netinfo_thread - thread to deliver network status to mostcore
197 * @data: private data
198 *
199 * Wait for network status and deliver it to mostcore once it is received
200 */
deliver_netinfo_thread(void * data)201 static int deliver_netinfo_thread(void *data)
202 {
203 struct dim2_hdm *dev = data;
204
205 while (!kthread_should_stop()) {
206 wait_event_interruptible(dev->netinfo_waitq,
207 dev->deliver_netinfo ||
208 kthread_should_stop());
209
210 if (dev->deliver_netinfo) {
211 dev->deliver_netinfo--;
212 if (dev->on_netinfo) {
213 dev->on_netinfo(&dev->most_iface,
214 dev->link_state,
215 dev->mac_addrs);
216 }
217 }
218 }
219
220 return 0;
221 }
222
223 /**
224 * retrieve_netinfo - retrieve network status from received buffer
225 * @dev: private data
226 * @mbo: received MBO
227 *
228 * Parse the message in buffer and get node address, link state, MAC address.
229 * Wake up a thread to deliver this status to mostcore
230 */
retrieve_netinfo(struct dim2_hdm * dev,struct mbo * mbo)231 static void retrieve_netinfo(struct dim2_hdm *dev, struct mbo *mbo)
232 {
233 u8 *data = mbo->virt_address;
234
235 pr_info("Node Address: 0x%03x\n", (u16)data[16] << 8 | data[17]);
236 dev->link_state = data[18];
237 pr_info("NIState: %d\n", dev->link_state);
238 memcpy(dev->mac_addrs, data + 19, 6);
239 dev->deliver_netinfo++;
240 wake_up_interruptible(&dev->netinfo_waitq);
241 }
242
243 /**
244 * service_done_flag - handle completed buffers
245 * @dev: private data
246 * @ch_idx: channel index
247 *
248 * Return back the completed buffers to mostcore, using completion callback
249 */
service_done_flag(struct dim2_hdm * dev,int ch_idx)250 static void service_done_flag(struct dim2_hdm *dev, int ch_idx)
251 {
252 struct hdm_channel *hdm_ch = dev->hch + ch_idx;
253 struct dim_ch_state_t st;
254 struct list_head *head;
255 struct mbo *mbo;
256 int done_buffers;
257 unsigned long flags;
258 u8 *data;
259
260 BUG_ON(!hdm_ch);
261 BUG_ON(!hdm_ch->is_initialized);
262
263 spin_lock_irqsave(&dim_lock, flags);
264
265 done_buffers = dim_get_channel_state(&hdm_ch->ch, &st)->done_buffers;
266 if (!done_buffers) {
267 spin_unlock_irqrestore(&dim_lock, flags);
268 return;
269 }
270
271 if (!dim_detach_buffers(&hdm_ch->ch, done_buffers)) {
272 spin_unlock_irqrestore(&dim_lock, flags);
273 return;
274 }
275 spin_unlock_irqrestore(&dim_lock, flags);
276
277 head = &hdm_ch->started_list;
278
279 while (done_buffers) {
280 spin_lock_irqsave(&dim_lock, flags);
281 if (list_empty(head)) {
282 spin_unlock_irqrestore(&dim_lock, flags);
283 pr_crit("hard error: started_mbo list is empty whereas DIM2 has sent buffers\n");
284 break;
285 }
286
287 mbo = list_first_entry(head, struct mbo, list);
288 list_del(head->next);
289 spin_unlock_irqrestore(&dim_lock, flags);
290
291 data = mbo->virt_address;
292
293 if (hdm_ch->data_type == MOST_CH_ASYNC &&
294 hdm_ch->direction == MOST_CH_RX &&
295 PACKET_IS_NET_INFO(data)) {
296 retrieve_netinfo(dev, mbo);
297
298 spin_lock_irqsave(&dim_lock, flags);
299 list_add_tail(&mbo->list, &hdm_ch->pending_list);
300 spin_unlock_irqrestore(&dim_lock, flags);
301 } else {
302 if (hdm_ch->data_type == MOST_CH_CONTROL ||
303 hdm_ch->data_type == MOST_CH_ASYNC) {
304 u32 const data_size =
305 (u32)data[0] * 256 + data[1] + 2;
306
307 mbo->processed_length =
308 min_t(u32, data_size,
309 mbo->buffer_length);
310 } else {
311 mbo->processed_length = mbo->buffer_length;
312 }
313 mbo->status = MBO_SUCCESS;
314 mbo->complete(mbo);
315 }
316
317 done_buffers--;
318 }
319 }
320
get_active_channels(struct dim2_hdm * dev,struct dim_channel ** buffer)321 static struct dim_channel **get_active_channels(struct dim2_hdm *dev,
322 struct dim_channel **buffer)
323 {
324 int idx = 0;
325 int ch_idx;
326
327 for (ch_idx = 0; ch_idx < DMA_CHANNELS; ch_idx++) {
328 if (dev->hch[ch_idx].is_initialized)
329 buffer[idx++] = &dev->hch[ch_idx].ch;
330 }
331 buffer[idx++] = NULL;
332
333 return buffer;
334 }
335
dim2_mlb_isr(int irq,void * _dev)336 static irqreturn_t dim2_mlb_isr(int irq, void *_dev)
337 {
338 struct dim2_hdm *dev = _dev;
339 unsigned long flags;
340
341 spin_lock_irqsave(&dim_lock, flags);
342 dim_service_mlb_int_irq();
343 spin_unlock_irqrestore(&dim_lock, flags);
344
345 if (dev->atx_idx >= 0 && dev->hch[dev->atx_idx].is_initialized)
346 while (!try_start_dim_transfer(dev->hch + dev->atx_idx))
347 continue;
348
349 return IRQ_HANDLED;
350 }
351
352 /**
353 * dim2_tasklet_fn - tasklet function
354 * @data: private data
355 *
356 * Service each initialized channel, if needed
357 */
dim2_tasklet_fn(unsigned long data)358 static void dim2_tasklet_fn(unsigned long data)
359 {
360 struct dim2_hdm *dev = (struct dim2_hdm *)data;
361 unsigned long flags;
362 int ch_idx;
363
364 for (ch_idx = 0; ch_idx < DMA_CHANNELS; ch_idx++) {
365 if (!dev->hch[ch_idx].is_initialized)
366 continue;
367
368 spin_lock_irqsave(&dim_lock, flags);
369 dim_service_channel(&dev->hch[ch_idx].ch);
370 spin_unlock_irqrestore(&dim_lock, flags);
371
372 service_done_flag(dev, ch_idx);
373 while (!try_start_dim_transfer(dev->hch + ch_idx))
374 continue;
375 }
376 }
377
378 /**
379 * dim2_ahb_isr - interrupt service routine
380 * @irq: irq number
381 * @_dev: private data
382 *
383 * Acknowledge the interrupt and schedule a tasklet to service channels.
384 * Return IRQ_HANDLED.
385 */
dim2_ahb_isr(int irq,void * _dev)386 static irqreturn_t dim2_ahb_isr(int irq, void *_dev)
387 {
388 struct dim2_hdm *dev = _dev;
389 struct dim_channel *buffer[DMA_CHANNELS + 1];
390 unsigned long flags;
391
392 spin_lock_irqsave(&dim_lock, flags);
393 dim_service_ahb_int_irq(get_active_channels(dev, buffer));
394 spin_unlock_irqrestore(&dim_lock, flags);
395
396 dim2_tasklet.data = (unsigned long)dev;
397 tasklet_schedule(&dim2_tasklet);
398 return IRQ_HANDLED;
399 }
400
401 /**
402 * complete_all_mbos - complete MBO's in a list
403 * @head: list head
404 *
405 * Delete all the entries in list and return back MBO's to mostcore using
406 * completion call back.
407 */
complete_all_mbos(struct list_head * head)408 static void complete_all_mbos(struct list_head *head)
409 {
410 unsigned long flags;
411 struct mbo *mbo;
412
413 for (;;) {
414 spin_lock_irqsave(&dim_lock, flags);
415 if (list_empty(head)) {
416 spin_unlock_irqrestore(&dim_lock, flags);
417 break;
418 }
419
420 mbo = list_first_entry(head, struct mbo, list);
421 list_del(head->next);
422 spin_unlock_irqrestore(&dim_lock, flags);
423
424 mbo->processed_length = 0;
425 mbo->status = MBO_E_CLOSE;
426 mbo->complete(mbo);
427 }
428 }
429
430 /**
431 * configure_channel - initialize a channel
432 * @iface: interface the channel belongs to
433 * @channel: channel to be configured
434 * @channel_config: structure that holds the configuration information
435 *
436 * Receives configuration information from mostcore and initialize
437 * the corresponding channel. Return 0 on success, negative on failure.
438 */
configure_channel(struct most_interface * most_iface,int ch_idx,struct most_channel_config * ccfg)439 static int configure_channel(struct most_interface *most_iface, int ch_idx,
440 struct most_channel_config *ccfg)
441 {
442 struct dim2_hdm *dev = iface_to_hdm(most_iface);
443 bool const is_tx = ccfg->direction == MOST_CH_TX;
444 u16 const sub_size = ccfg->subbuffer_size;
445 u16 const buf_size = ccfg->buffer_size;
446 u16 new_size;
447 unsigned long flags;
448 u8 hal_ret;
449 int const ch_addr = ch_idx * 2 + 2;
450 struct hdm_channel *const hdm_ch = dev->hch + ch_idx;
451
452 BUG_ON(ch_idx < 0 || ch_idx >= DMA_CHANNELS);
453
454 if (hdm_ch->is_initialized)
455 return -EPERM;
456
457 /* do not reset if the property was set by user, see poison_channel */
458 hdm_ch->reset_dbr_size = ccfg->dbr_size ? NULL : &ccfg->dbr_size;
459
460 /* zero value is default dbr_size, see dim2 hal */
461 hdm_ch->ch.dbr_size = ccfg->dbr_size;
462
463 switch (ccfg->data_type) {
464 case MOST_CH_CONTROL:
465 new_size = dim_norm_ctrl_async_buffer_size(buf_size);
466 if (new_size == 0) {
467 pr_err("%s: too small buffer size\n", hdm_ch->name);
468 return -EINVAL;
469 }
470 ccfg->buffer_size = new_size;
471 if (new_size != buf_size)
472 pr_warn("%s: fixed buffer size (%d -> %d)\n",
473 hdm_ch->name, buf_size, new_size);
474 spin_lock_irqsave(&dim_lock, flags);
475 hal_ret = dim_init_control(&hdm_ch->ch, is_tx, ch_addr,
476 is_tx ? new_size * 2 : new_size);
477 break;
478 case MOST_CH_ASYNC:
479 new_size = dim_norm_ctrl_async_buffer_size(buf_size);
480 if (new_size == 0) {
481 pr_err("%s: too small buffer size\n", hdm_ch->name);
482 return -EINVAL;
483 }
484 ccfg->buffer_size = new_size;
485 if (new_size != buf_size)
486 pr_warn("%s: fixed buffer size (%d -> %d)\n",
487 hdm_ch->name, buf_size, new_size);
488 spin_lock_irqsave(&dim_lock, flags);
489 hal_ret = dim_init_async(&hdm_ch->ch, is_tx, ch_addr,
490 is_tx ? new_size * 2 : new_size);
491 break;
492 case MOST_CH_ISOC:
493 new_size = dim_norm_isoc_buffer_size(buf_size, sub_size);
494 if (new_size == 0) {
495 pr_err("%s: invalid sub-buffer size or too small buffer size\n",
496 hdm_ch->name);
497 return -EINVAL;
498 }
499 ccfg->buffer_size = new_size;
500 if (new_size != buf_size)
501 pr_warn("%s: fixed buffer size (%d -> %d)\n",
502 hdm_ch->name, buf_size, new_size);
503 spin_lock_irqsave(&dim_lock, flags);
504 hal_ret = dim_init_isoc(&hdm_ch->ch, is_tx, ch_addr, sub_size);
505 break;
506 case MOST_CH_SYNC:
507 new_size = dim_norm_sync_buffer_size(buf_size, sub_size);
508 if (new_size == 0) {
509 pr_err("%s: invalid sub-buffer size or too small buffer size\n",
510 hdm_ch->name);
511 return -EINVAL;
512 }
513 ccfg->buffer_size = new_size;
514 if (new_size != buf_size)
515 pr_warn("%s: fixed buffer size (%d -> %d)\n",
516 hdm_ch->name, buf_size, new_size);
517 spin_lock_irqsave(&dim_lock, flags);
518 hal_ret = dim_init_sync(&hdm_ch->ch, is_tx, ch_addr, sub_size);
519 break;
520 default:
521 pr_err("%s: configure failed, bad channel type: %d\n",
522 hdm_ch->name, ccfg->data_type);
523 return -EINVAL;
524 }
525
526 if (hal_ret != DIM_NO_ERROR) {
527 spin_unlock_irqrestore(&dim_lock, flags);
528 pr_err("%s: configure failed (%d), type: %d, is_tx: %d\n",
529 hdm_ch->name, hal_ret, ccfg->data_type, (int)is_tx);
530 return -ENODEV;
531 }
532
533 hdm_ch->data_type = ccfg->data_type;
534 hdm_ch->direction = ccfg->direction;
535 hdm_ch->is_initialized = true;
536
537 if (hdm_ch->data_type == MOST_CH_ASYNC &&
538 hdm_ch->direction == MOST_CH_TX &&
539 dev->atx_idx < 0)
540 dev->atx_idx = ch_idx;
541
542 spin_unlock_irqrestore(&dim_lock, flags);
543 ccfg->dbr_size = hdm_ch->ch.dbr_size;
544
545 return 0;
546 }
547
548 /**
549 * enqueue - enqueue a buffer for data transfer
550 * @iface: intended interface
551 * @channel: ID of the channel the buffer is intended for
552 * @mbo: pointer to the buffer object
553 *
554 * Push the buffer into pending_list and try to transfer one buffer from
555 * pending_list. Return 0 on success, negative on failure.
556 */
enqueue(struct most_interface * most_iface,int ch_idx,struct mbo * mbo)557 static int enqueue(struct most_interface *most_iface, int ch_idx,
558 struct mbo *mbo)
559 {
560 struct dim2_hdm *dev = iface_to_hdm(most_iface);
561 struct hdm_channel *hdm_ch = dev->hch + ch_idx;
562 unsigned long flags;
563
564 BUG_ON(ch_idx < 0 || ch_idx >= DMA_CHANNELS);
565
566 if (!hdm_ch->is_initialized)
567 return -EPERM;
568
569 if (mbo->bus_address == 0)
570 return -EFAULT;
571
572 spin_lock_irqsave(&dim_lock, flags);
573 list_add_tail(&mbo->list, &hdm_ch->pending_list);
574 spin_unlock_irqrestore(&dim_lock, flags);
575
576 (void)try_start_dim_transfer(hdm_ch);
577
578 return 0;
579 }
580
581 /**
582 * request_netinfo - triggers retrieving of network info
583 * @iface: pointer to the interface
584 * @channel_id: corresponding channel ID
585 *
586 * Send a command to INIC which triggers retrieving of network info by means of
587 * "Message exchange over MDP/MEP". Return 0 on success, negative on failure.
588 */
request_netinfo(struct most_interface * most_iface,int ch_idx,void (* on_netinfo)(struct most_interface *,unsigned char,unsigned char *))589 static void request_netinfo(struct most_interface *most_iface, int ch_idx,
590 void (*on_netinfo)(struct most_interface *,
591 unsigned char, unsigned char *))
592 {
593 struct dim2_hdm *dev = iface_to_hdm(most_iface);
594 struct mbo *mbo;
595 u8 *data;
596
597 dev->on_netinfo = on_netinfo;
598 if (!on_netinfo)
599 return;
600
601 if (dev->atx_idx < 0) {
602 pr_err("Async Tx Not initialized\n");
603 return;
604 }
605
606 mbo = most_get_mbo(&dev->most_iface, dev->atx_idx, NULL);
607 if (!mbo)
608 return;
609
610 mbo->buffer_length = 5;
611
612 data = mbo->virt_address;
613
614 data[0] = 0x00; /* PML High byte */
615 data[1] = 0x03; /* PML Low byte */
616 data[2] = 0x02; /* PMHL */
617 data[3] = 0x08; /* FPH */
618 data[4] = 0x40; /* FMF (FIFO cmd msg - Triggers NAOverMDP) */
619
620 most_submit_mbo(mbo);
621 }
622
623 /**
624 * poison_channel - poison buffers of a channel
625 * @iface: pointer to the interface the channel to be poisoned belongs to
626 * @channel_id: corresponding channel ID
627 *
628 * Destroy a channel and complete all the buffers in both started_list &
629 * pending_list. Return 0 on success, negative on failure.
630 */
poison_channel(struct most_interface * most_iface,int ch_idx)631 static int poison_channel(struct most_interface *most_iface, int ch_idx)
632 {
633 struct dim2_hdm *dev = iface_to_hdm(most_iface);
634 struct hdm_channel *hdm_ch = dev->hch + ch_idx;
635 unsigned long flags;
636 u8 hal_ret;
637 int ret = 0;
638
639 BUG_ON(ch_idx < 0 || ch_idx >= DMA_CHANNELS);
640
641 if (!hdm_ch->is_initialized)
642 return -EPERM;
643
644 tasklet_disable(&dim2_tasklet);
645 spin_lock_irqsave(&dim_lock, flags);
646 hal_ret = dim_destroy_channel(&hdm_ch->ch);
647 hdm_ch->is_initialized = false;
648 if (ch_idx == dev->atx_idx)
649 dev->atx_idx = -1;
650 spin_unlock_irqrestore(&dim_lock, flags);
651 tasklet_enable(&dim2_tasklet);
652 if (hal_ret != DIM_NO_ERROR) {
653 pr_err("HAL Failed to close channel %s\n", hdm_ch->name);
654 ret = -EFAULT;
655 }
656
657 complete_all_mbos(&hdm_ch->started_list);
658 complete_all_mbos(&hdm_ch->pending_list);
659 if (hdm_ch->reset_dbr_size)
660 *hdm_ch->reset_dbr_size = 0;
661
662 return ret;
663 }
664
dma_alloc(struct mbo * mbo,u32 size)665 static void *dma_alloc(struct mbo *mbo, u32 size)
666 {
667 struct device *dev = mbo->ifp->driver_dev;
668
669 return dma_alloc_coherent(dev, size, &mbo->bus_address, GFP_KERNEL);
670 }
671
dma_free(struct mbo * mbo,u32 size)672 static void dma_free(struct mbo *mbo, u32 size)
673 {
674 struct device *dev = mbo->ifp->driver_dev;
675
676 dma_free_coherent(dev, size, mbo->virt_address, mbo->bus_address);
677 }
678
679 static const struct of_device_id dim2_of_match[];
680
681 static struct {
682 const char *clock_speed;
683 u8 clk_speed;
684 } clk_mt[] = {
685 { "256fs", CLK_256FS },
686 { "512fs", CLK_512FS },
687 { "1024fs", CLK_1024FS },
688 { "2048fs", CLK_2048FS },
689 { "3072fs", CLK_3072FS },
690 { "4096fs", CLK_4096FS },
691 { "6144fs", CLK_6144FS },
692 { "8192fs", CLK_8192FS },
693 };
694
695 /**
696 * get_dim2_clk_speed - converts string to DIM2 clock speed value
697 *
698 * @clock_speed: string in the format "{NUMBER}fs"
699 * @val: pointer to get one of the CLK_{NUMBER}FS values
700 *
701 * By success stores one of the CLK_{NUMBER}FS in the *val and returns 0,
702 * otherwise returns -EINVAL.
703 */
get_dim2_clk_speed(const char * clock_speed,u8 * val)704 static int get_dim2_clk_speed(const char *clock_speed, u8 *val)
705 {
706 int i;
707
708 for (i = 0; i < ARRAY_SIZE(clk_mt); i++) {
709 if (!strcmp(clock_speed, clk_mt[i].clock_speed)) {
710 *val = clk_mt[i].clk_speed;
711 return 0;
712 }
713 }
714 return -EINVAL;
715 }
716
717 /*
718 * dim2_probe - dim2 probe handler
719 * @pdev: platform device structure
720 *
721 * Register the dim2 interface with mostcore and initialize it.
722 * Return 0 on success, negative on failure.
723 */
dim2_probe(struct platform_device * pdev)724 static int dim2_probe(struct platform_device *pdev)
725 {
726 const struct dim2_platform_data *pdata;
727 const struct of_device_id *of_id;
728 const char *clock_speed;
729 struct dim2_hdm *dev;
730 struct resource *res;
731 int ret, i;
732 u8 hal_ret;
733 int irq;
734
735 enum { MLB_INT_IDX, AHB0_INT_IDX };
736
737 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
738 if (!dev)
739 return -ENOMEM;
740
741 dev->atx_idx = -1;
742
743 platform_set_drvdata(pdev, dev);
744
745 ret = of_property_read_string(pdev->dev.of_node,
746 "microchip,clock-speed", &clock_speed);
747 if (ret) {
748 dev_err(&pdev->dev, "missing dt property clock-speed\n");
749 return ret;
750 }
751
752 ret = get_dim2_clk_speed(clock_speed, &dev->clk_speed);
753 if (ret) {
754 dev_err(&pdev->dev, "bad dt property clock-speed\n");
755 return ret;
756 }
757
758 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
759 dev->io_base = devm_ioremap_resource(&pdev->dev, res);
760 if (IS_ERR(dev->io_base))
761 return PTR_ERR(dev->io_base);
762
763 of_id = of_match_node(dim2_of_match, pdev->dev.of_node);
764 pdata = of_id->data;
765 ret = pdata && pdata->enable ? pdata->enable(pdev) : 0;
766 if (ret)
767 return ret;
768
769 dev->disable_platform = pdata ? pdata->disable : NULL;
770
771 dev_info(&pdev->dev, "sync: num of frames per sub-buffer: %u\n", fcnt);
772 hal_ret = dim_startup(dev->io_base, dev->clk_speed, fcnt);
773 if (hal_ret != DIM_NO_ERROR) {
774 dev_err(&pdev->dev, "dim_startup failed: %d\n", hal_ret);
775 ret = -ENODEV;
776 goto err_disable_platform;
777 }
778
779 irq = platform_get_irq(pdev, AHB0_INT_IDX);
780 if (irq < 0) {
781 ret = irq;
782 goto err_shutdown_dim;
783 }
784
785 ret = devm_request_irq(&pdev->dev, irq, dim2_ahb_isr, 0,
786 "dim2_ahb0_int", dev);
787 if (ret) {
788 dev_err(&pdev->dev, "failed to request ahb0_int irq %d\n", irq);
789 goto err_shutdown_dim;
790 }
791
792 irq = platform_get_irq(pdev, MLB_INT_IDX);
793 if (irq < 0) {
794 ret = irq;
795 goto err_shutdown_dim;
796 }
797
798 ret = devm_request_irq(&pdev->dev, irq, dim2_mlb_isr, 0,
799 "dim2_mlb_int", dev);
800 if (ret) {
801 dev_err(&pdev->dev, "failed to request mlb_int irq %d\n", irq);
802 goto err_shutdown_dim;
803 }
804
805 init_waitqueue_head(&dev->netinfo_waitq);
806 dev->deliver_netinfo = 0;
807 dev->netinfo_task = kthread_run(&deliver_netinfo_thread, dev,
808 "dim2_netinfo");
809 if (IS_ERR(dev->netinfo_task)) {
810 ret = PTR_ERR(dev->netinfo_task);
811 goto err_shutdown_dim;
812 }
813
814 for (i = 0; i < DMA_CHANNELS; i++) {
815 struct most_channel_capability *cap = dev->capabilities + i;
816 struct hdm_channel *hdm_ch = dev->hch + i;
817
818 INIT_LIST_HEAD(&hdm_ch->pending_list);
819 INIT_LIST_HEAD(&hdm_ch->started_list);
820 hdm_ch->is_initialized = false;
821 snprintf(hdm_ch->name, sizeof(hdm_ch->name), "ca%d", i * 2 + 2);
822
823 cap->name_suffix = hdm_ch->name;
824 cap->direction = MOST_CH_RX | MOST_CH_TX;
825 cap->data_type = MOST_CH_CONTROL | MOST_CH_ASYNC |
826 MOST_CH_ISOC | MOST_CH_SYNC;
827 cap->num_buffers_packet = MAX_BUFFERS_PACKET;
828 cap->buffer_size_packet = MAX_BUF_SIZE_PACKET;
829 cap->num_buffers_streaming = MAX_BUFFERS_STREAMING;
830 cap->buffer_size_streaming = MAX_BUF_SIZE_STREAMING;
831 }
832
833 {
834 const char *fmt;
835
836 if (sizeof(res->start) == sizeof(long long))
837 fmt = "dim2-%016llx";
838 else if (sizeof(res->start) == sizeof(long))
839 fmt = "dim2-%016lx";
840 else
841 fmt = "dim2-%016x";
842
843 snprintf(dev->name, sizeof(dev->name), fmt, res->start);
844 }
845
846 dev->most_iface.interface = ITYPE_MEDIALB_DIM2;
847 dev->most_iface.description = dev->name;
848 dev->most_iface.num_channels = DMA_CHANNELS;
849 dev->most_iface.channel_vector = dev->capabilities;
850 dev->most_iface.configure = configure_channel;
851 dev->most_iface.enqueue = enqueue;
852 dev->most_iface.dma_alloc = dma_alloc;
853 dev->most_iface.dma_free = dma_free;
854 dev->most_iface.poison_channel = poison_channel;
855 dev->most_iface.request_netinfo = request_netinfo;
856 dev->most_iface.driver_dev = &pdev->dev;
857 dev->dev.init_name = "dim2_state";
858 dev->dev.parent = &dev->most_iface.dev;
859
860 ret = most_register_interface(&dev->most_iface);
861 if (ret) {
862 dev_err(&pdev->dev, "failed to register MOST interface\n");
863 goto err_stop_thread;
864 }
865
866 ret = dim2_sysfs_probe(&dev->dev);
867 if (ret) {
868 dev_err(&pdev->dev, "failed to create sysfs attribute\n");
869 goto err_unreg_iface;
870 }
871
872 return 0;
873
874 err_unreg_iface:
875 most_deregister_interface(&dev->most_iface);
876 err_stop_thread:
877 kthread_stop(dev->netinfo_task);
878 err_shutdown_dim:
879 dim_shutdown();
880 err_disable_platform:
881 if (dev->disable_platform)
882 dev->disable_platform(pdev);
883
884 return ret;
885 }
886
887 /**
888 * dim2_remove - dim2 remove handler
889 * @pdev: platform device structure
890 *
891 * Unregister the interface from mostcore
892 */
dim2_remove(struct platform_device * pdev)893 static int dim2_remove(struct platform_device *pdev)
894 {
895 struct dim2_hdm *dev = platform_get_drvdata(pdev);
896 unsigned long flags;
897
898 dim2_sysfs_destroy(&dev->dev);
899 most_deregister_interface(&dev->most_iface);
900 kthread_stop(dev->netinfo_task);
901
902 spin_lock_irqsave(&dim_lock, flags);
903 dim_shutdown();
904 spin_unlock_irqrestore(&dim_lock, flags);
905
906 if (dev->disable_platform)
907 dev->disable_platform(pdev);
908
909 return 0;
910 }
911
912 /* platform specific functions [[ */
913
fsl_mx6_enable(struct platform_device * pdev)914 static int fsl_mx6_enable(struct platform_device *pdev)
915 {
916 struct dim2_hdm *dev = platform_get_drvdata(pdev);
917 int ret;
918
919 dev->clk = devm_clk_get(&pdev->dev, "mlb");
920 if (IS_ERR_OR_NULL(dev->clk)) {
921 dev_err(&pdev->dev, "unable to get mlb clock\n");
922 return -EFAULT;
923 }
924
925 ret = clk_prepare_enable(dev->clk);
926 if (ret) {
927 dev_err(&pdev->dev, "%s\n", "clk_prepare_enable failed");
928 return ret;
929 }
930
931 if (dev->clk_speed >= CLK_2048FS) {
932 /* enable pll */
933 dev->clk_pll = devm_clk_get(&pdev->dev, "pll8_mlb");
934 if (IS_ERR_OR_NULL(dev->clk_pll)) {
935 dev_err(&pdev->dev, "unable to get mlb pll clock\n");
936 clk_disable_unprepare(dev->clk);
937 return -EFAULT;
938 }
939
940 writel(0x888, dev->io_base + 0x38);
941 clk_prepare_enable(dev->clk_pll);
942 }
943
944 return 0;
945 }
946
fsl_mx6_disable(struct platform_device * pdev)947 static void fsl_mx6_disable(struct platform_device *pdev)
948 {
949 struct dim2_hdm *dev = platform_get_drvdata(pdev);
950
951 if (dev->clk_speed >= CLK_2048FS)
952 clk_disable_unprepare(dev->clk_pll);
953
954 clk_disable_unprepare(dev->clk);
955 }
956
rcar_h2_enable(struct platform_device * pdev)957 static int rcar_h2_enable(struct platform_device *pdev)
958 {
959 struct dim2_hdm *dev = platform_get_drvdata(pdev);
960 int ret;
961
962 dev->clk = devm_clk_get(&pdev->dev, NULL);
963 if (IS_ERR(dev->clk)) {
964 dev_err(&pdev->dev, "cannot get clock\n");
965 return PTR_ERR(dev->clk);
966 }
967
968 ret = clk_prepare_enable(dev->clk);
969 if (ret) {
970 dev_err(&pdev->dev, "%s\n", "clk_prepare_enable failed");
971 return ret;
972 }
973
974 if (dev->clk_speed >= CLK_2048FS) {
975 /* enable MLP pll and LVDS drivers */
976 writel(0x03, dev->io_base + 0x600);
977 /* set bias */
978 writel(0x888, dev->io_base + 0x38);
979 } else {
980 /* PLL */
981 writel(0x04, dev->io_base + 0x600);
982 }
983
984
985 /* BBCR = 0b11 */
986 writel(0x03, dev->io_base + 0x500);
987 writel(0x0002FF02, dev->io_base + 0x508);
988
989 return 0;
990 }
991
rcar_h2_disable(struct platform_device * pdev)992 static void rcar_h2_disable(struct platform_device *pdev)
993 {
994 struct dim2_hdm *dev = platform_get_drvdata(pdev);
995
996 clk_disable_unprepare(dev->clk);
997
998 /* disable PLLs and LVDS drivers */
999 writel(0x0, dev->io_base + 0x600);
1000 }
1001
rcar_m3_enable(struct platform_device * pdev)1002 static int rcar_m3_enable(struct platform_device *pdev)
1003 {
1004 struct dim2_hdm *dev = platform_get_drvdata(pdev);
1005 u32 enable_512fs = dev->clk_speed == CLK_512FS;
1006 int ret;
1007
1008 dev->clk = devm_clk_get(&pdev->dev, NULL);
1009 if (IS_ERR(dev->clk)) {
1010 dev_err(&pdev->dev, "cannot get clock\n");
1011 return PTR_ERR(dev->clk);
1012 }
1013
1014 ret = clk_prepare_enable(dev->clk);
1015 if (ret) {
1016 dev_err(&pdev->dev, "%s\n", "clk_prepare_enable failed");
1017 return ret;
1018 }
1019
1020 /* PLL */
1021 writel(0x04, dev->io_base + 0x600);
1022
1023 writel(enable_512fs, dev->io_base + 0x604);
1024
1025 /* BBCR = 0b11 */
1026 writel(0x03, dev->io_base + 0x500);
1027 writel(0x0002FF02, dev->io_base + 0x508);
1028
1029 return 0;
1030 }
1031
rcar_m3_disable(struct platform_device * pdev)1032 static void rcar_m3_disable(struct platform_device *pdev)
1033 {
1034 struct dim2_hdm *dev = platform_get_drvdata(pdev);
1035
1036 clk_disable_unprepare(dev->clk);
1037
1038 /* disable PLLs and LVDS drivers */
1039 writel(0x0, dev->io_base + 0x600);
1040 }
1041
1042 /* ]] platform specific functions */
1043
1044 enum dim2_platforms { FSL_MX6, RCAR_H2, RCAR_M3 };
1045
1046 static struct dim2_platform_data plat_data[] = {
1047 [FSL_MX6] = { .enable = fsl_mx6_enable, .disable = fsl_mx6_disable },
1048 [RCAR_H2] = { .enable = rcar_h2_enable, .disable = rcar_h2_disable },
1049 [RCAR_M3] = { .enable = rcar_m3_enable, .disable = rcar_m3_disable },
1050 };
1051
1052 static const struct of_device_id dim2_of_match[] = {
1053 {
1054 .compatible = "fsl,imx6q-mlb150",
1055 .data = plat_data + FSL_MX6
1056 },
1057 {
1058 .compatible = "renesas,mlp",
1059 .data = plat_data + RCAR_H2
1060 },
1061 {
1062 .compatible = "rcar,medialb-dim2",
1063 .data = plat_data + RCAR_M3
1064 },
1065 {
1066 .compatible = "xlnx,axi4-os62420_3pin-1.00.a",
1067 },
1068 {
1069 .compatible = "xlnx,axi4-os62420_6pin-1.00.a",
1070 },
1071 {},
1072 };
1073
1074 MODULE_DEVICE_TABLE(of, dim2_of_match);
1075
1076 static struct platform_driver dim2_driver = {
1077 .probe = dim2_probe,
1078 .remove = dim2_remove,
1079 .driver = {
1080 .name = "hdm_dim2",
1081 .of_match_table = dim2_of_match,
1082 },
1083 };
1084
1085 module_platform_driver(dim2_driver);
1086
1087 MODULE_AUTHOR("Andrey Shvetsov <andrey.shvetsov@k2l.de>");
1088 MODULE_DESCRIPTION("MediaLB DIM2 Hardware Dependent Module");
1089 MODULE_LICENSE("GPL");
1090
