1 // SPDX-License-Identifier: GPL-2.0
2 /*++
3 Copyright-c Realtek Semiconductor Corp. All rights reserved.
4
5 Module Name:
6 r8192U_dm.c
7
8 Abstract:
9 HW dynamic mechanism.
10
11 Major Change History:
12 When Who What
13 ---------- --------------- -------------------------------
14 2008-05-14 amy create version 0 porting from windows code.
15
16 --*/
17 #include "r8192U.h"
18 #include "r8192U_dm.h"
19 #include "r8192U_hw.h"
20 #include "r819xU_phy.h"
21 #include "r819xU_phyreg.h"
22 #include "r8190_rtl8256.h"
23 #include "r819xU_cmdpkt.h"
24 /*---------------------------Define Local Constant---------------------------*/
25 /* Indicate different AP vendor for IOT issue. */
26 static u32 edca_setting_DL[HT_IOT_PEER_MAX] = {
27 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0x00a44f, 0x5ea44f
28 };
29 static u32 edca_setting_UL[HT_IOT_PEER_MAX] = {
30 0x5e4322, 0x00a44f, 0x5e4322, 0x604322, 0x5ea44f, 0x5ea44f
31 };
32
33 #define RTK_UL_EDCA 0xa44f
34 #define RTK_DL_EDCA 0x5e4322
35 /*---------------------------Define Local Constant---------------------------*/
36
37
38 /*------------------------Define global variable-----------------------------*/
39 /* Debug variable ? */
40 struct dig dm_digtable;
41 /* Store current software write register content for MAC PHY. */
42 u8 dm_shadow[16][256] = { {0} };
43 /* For Dynamic Rx Path Selection by Signal Strength */
44 static struct dynamic_rx_path_sel DM_RxPathSelTable;
45
46 extern void dm_check_fsync(struct net_device *dev);
47
48 /* DM --> Rate Adaptive */
49 static void dm_check_rate_adaptive(struct net_device *dev);
50
51 /* DM --> Bandwidth switch */
52 static void dm_init_bandwidth_autoswitch(struct net_device *dev);
53 static void dm_bandwidth_autoswitch(struct net_device *dev);
54
55 /* DM --> TX power control */
56 /*static void dm_initialize_txpower_tracking(struct net_device *dev);*/
57
58 static void dm_check_txpower_tracking(struct net_device *dev);
59
60 /*static void dm_txpower_reset_recovery(struct net_device *dev);*/
61
62 /* DM --> Dynamic Init Gain by RSSI */
63 static void dm_dig_init(struct net_device *dev);
64 static void dm_ctrl_initgain_byrssi(struct net_device *dev);
65 static void dm_ctrl_initgain_byrssi_highpwr(struct net_device *dev);
66 static void dm_ctrl_initgain_byrssi_by_driverrssi(struct net_device *dev);
67 static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(struct net_device *dev);
68 static void dm_initial_gain(struct net_device *dev);
69 static void dm_pd_th(struct net_device *dev);
70 static void dm_cs_ratio(struct net_device *dev);
71
72 static void dm_init_ctstoself(struct net_device *dev);
73 /* DM --> EDCA turbo mode control */
74 static void dm_check_edca_turbo(struct net_device *dev);
75
76 /*static void dm_gpio_change_rf(struct net_device *dev);*/
77 /* DM --> Check PBC */
78 static void dm_check_pbc_gpio(struct net_device *dev);
79
80 /* DM --> Check current RX RF path state */
81 static void dm_check_rx_path_selection(struct net_device *dev);
82 static void dm_init_rxpath_selection(struct net_device *dev);
83 static void dm_rxpath_sel_byrssi(struct net_device *dev);
84
85 /* DM --> Fsync for broadcom ap */
86 static void dm_init_fsync(struct net_device *dev);
87 static void dm_deInit_fsync(struct net_device *dev);
88
89 /* Added by vivi, 20080522 */
90 static void dm_check_txrateandretrycount(struct net_device *dev);
91
92 /*---------------------Define local function prototype-----------------------*/
93
94 /*---------------------Define of Tx Power Control For Near/Far Range --------*/ /*Add by Jacken 2008/02/18 */
95 static void dm_init_dynamic_txpower(struct net_device *dev);
96 static void dm_dynamic_txpower(struct net_device *dev);
97
98 /* DM --> For rate adaptive and DIG, we must send RSSI to firmware */
99 static void dm_send_rssi_tofw(struct net_device *dev);
100 static void dm_ctstoself(struct net_device *dev);
101 /*---------------------------Define function prototype------------------------*/
102 /* ================================================================================
103 * HW Dynamic mechanism interface.
104 * ================================================================================
105 *
106 *
107 * Description:
108 * Prepare SW resource for HW dynamic mechanism.
109 *
110 * Assumption:
111 * This function is only invoked at driver initialization once.
112 */
init_hal_dm(struct net_device * dev)113 void init_hal_dm(struct net_device *dev)
114 {
115 struct r8192_priv *priv = ieee80211_priv(dev);
116
117 /* Undecorated Smoothed Signal Strength, it can utilized to dynamic mechanism. */
118 priv->undecorated_smoothed_pwdb = -1;
119
120 /* Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code. */
121 dm_init_dynamic_txpower(dev);
122 init_rate_adaptive(dev);
123 /*dm_initialize_txpower_tracking(dev);*/
124 dm_dig_init(dev);
125 dm_init_edca_turbo(dev);
126 dm_init_bandwidth_autoswitch(dev);
127 dm_init_fsync(dev);
128 dm_init_rxpath_selection(dev);
129 dm_init_ctstoself(dev);
130
131 } /* InitHalDm */
132
deinit_hal_dm(struct net_device * dev)133 void deinit_hal_dm(struct net_device *dev)
134 {
135 dm_deInit_fsync(dev);
136 }
137
138 #ifdef USB_RX_AGGREGATION_SUPPORT
dm_CheckRxAggregation(struct net_device * dev)139 void dm_CheckRxAggregation(struct net_device *dev)
140 {
141 struct r8192_priv *priv = ieee80211_priv(dev);
142 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
143 static unsigned long lastTxOkCnt;
144 static unsigned long lastRxOkCnt;
145 unsigned long curTxOkCnt = 0;
146 unsigned long curRxOkCnt = 0;
147
148 /*
149 if (pHalData->bForcedUsbRxAggr) {
150 if (pHalData->ForcedUsbRxAggrInfo == 0) {
151 if (pHalData->bCurrentRxAggrEnable) {
152 Adapter->HalFunc.HalUsbRxAggrHandler(Adapter, FALSE);
153 }
154 } else {
155 if (!pHalData->bCurrentRxAggrEnable || (pHalData->ForcedUsbRxAggrInfo != pHalData->LastUsbRxAggrInfoSetting)) {
156 Adapter->HalFunc.HalUsbRxAggrHandler(Adapter, TRUE);
157 }
158 }
159 return;
160 }
161
162 */
163 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
164 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
165
166 if ((curTxOkCnt + curRxOkCnt) < 15000000)
167 return;
168
169 if (curTxOkCnt > 4*curRxOkCnt) {
170 if (priv->bCurrentRxAggrEnable) {
171 write_nic_dword(dev, 0x1a8, 0);
172 priv->bCurrentRxAggrEnable = false;
173 }
174 } else {
175 if (!priv->bCurrentRxAggrEnable && !pHTInfo->bCurrentRT2RTAggregation) {
176 u32 ulValue;
177
178 ulValue = (pHTInfo->UsbRxFwAggrEn<<24) | (pHTInfo->UsbRxFwAggrPageNum<<16) |
179 (pHTInfo->UsbRxFwAggrPacketNum<<8) | (pHTInfo->UsbRxFwAggrTimeout);
180 /* If usb rx firmware aggregation is enabled,
181 * when anyone of three threshold conditions above is reached,
182 * firmware will send aggregated packet to driver.
183 */
184 write_nic_dword(dev, 0x1a8, ulValue);
185 priv->bCurrentRxAggrEnable = true;
186 }
187 }
188
189 lastTxOkCnt = priv->stats.txbytesunicast;
190 lastRxOkCnt = priv->stats.rxbytesunicast;
191 } /* dm_CheckEdcaTurbo */
192 #endif
193
hal_dm_watchdog(struct net_device * dev)194 void hal_dm_watchdog(struct net_device *dev)
195 {
196 /*struct r8192_priv *priv = ieee80211_priv(dev);*/
197
198 /*static u8 previous_bssid[6] ={0};*/
199
200 /*Add by amy 2008/05/15 ,porting from windows code.*/
201 dm_check_rate_adaptive(dev);
202 dm_dynamic_txpower(dev);
203 dm_check_txrateandretrycount(dev);
204 dm_check_txpower_tracking(dev);
205 dm_ctrl_initgain_byrssi(dev);
206 dm_check_edca_turbo(dev);
207 dm_bandwidth_autoswitch(dev);
208 dm_check_rx_path_selection(dev);
209 dm_check_fsync(dev);
210
211 /* Add by amy 2008-05-15 porting from windows code. */
212 dm_check_pbc_gpio(dev);
213 dm_send_rssi_tofw(dev);
214 dm_ctstoself(dev);
215 #ifdef USB_RX_AGGREGATION_SUPPORT
216 dm_CheckRxAggregation(dev);
217 #endif
218 } /* HalDmWatchDog */
219
220 /* Decide Rate Adaptive Set according to distance (signal strength)
221 * 01/11/2008 MHC Modify input arguments and RATR table level.
222 * 01/16/2008 MHC RF_Type is assigned in ReadAdapterInfo(). We must call
223 * the function after making sure RF_Type.
224 */
init_rate_adaptive(struct net_device * dev)225 void init_rate_adaptive(struct net_device *dev)
226 {
227 struct r8192_priv *priv = ieee80211_priv(dev);
228 prate_adaptive pra = (prate_adaptive)&priv->rate_adaptive;
229
230 pra->ratr_state = DM_RATR_STA_MAX;
231 pra->high2low_rssi_thresh_for_ra = RATE_ADAPTIVE_TH_HIGH;
232 pra->low2high_rssi_thresh_for_ra20M = RATE_ADAPTIVE_TH_LOW_20M + 5;
233 pra->low2high_rssi_thresh_for_ra40M = RATE_ADAPTIVE_TH_LOW_40M + 5;
234
235 pra->high_rssi_thresh_for_ra = RATE_ADAPTIVE_TH_HIGH + 5;
236 pra->low_rssi_thresh_for_ra20M = RATE_ADAPTIVE_TH_LOW_20M;
237 pra->low_rssi_thresh_for_ra40M = RATE_ADAPTIVE_TH_LOW_40M;
238
239 if (priv->CustomerID == RT_CID_819x_Netcore)
240 pra->ping_rssi_enable = 1;
241 else
242 pra->ping_rssi_enable = 0;
243 pra->ping_rssi_thresh_for_ra = 15;
244
245 if (priv->rf_type == RF_2T4R) {
246 /* 07/10/08 MH Modify for RA smooth scheme.
247 * 2008/01/11 MH Modify 2T RATR table for different RSSI. 080515 porting by amy from windows code.
248 */
249 pra->upper_rssi_threshold_ratr = 0x8f0f0000;
250 pra->middle_rssi_threshold_ratr = 0x8f0ff000;
251 pra->low_rssi_threshold_ratr = 0x8f0ff001;
252 pra->low_rssi_threshold_ratr_40M = 0x8f0ff005;
253 pra->low_rssi_threshold_ratr_20M = 0x8f0ff001;
254 pra->ping_rssi_ratr = 0x0000000d;/* cosa add for test */
255 } else if (priv->rf_type == RF_1T2R) {
256 pra->upper_rssi_threshold_ratr = 0x000f0000;
257 pra->middle_rssi_threshold_ratr = 0x000ff000;
258 pra->low_rssi_threshold_ratr = 0x000ff001;
259 pra->low_rssi_threshold_ratr_40M = 0x000ff005;
260 pra->low_rssi_threshold_ratr_20M = 0x000ff001;
261 pra->ping_rssi_ratr = 0x0000000d;/* cosa add for test */
262 }
263
264 } /* InitRateAdaptive */
265
266 /*-----------------------------------------------------------------------------
267 * Function: dm_check_rate_adaptive()
268 *
269 * Overview:
270 *
271 * Input: NONE
272 *
273 * Output: NONE
274 *
275 * Return: NONE
276 *
277 * Revised History:
278 * When Who Remark
279 * 05/26/08 amy Create version 0 porting from windows code.
280 *
281 *---------------------------------------------------------------------------*/
dm_check_rate_adaptive(struct net_device * dev)282 static void dm_check_rate_adaptive(struct net_device *dev)
283 {
284 struct r8192_priv *priv = ieee80211_priv(dev);
285 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
286 prate_adaptive pra = (prate_adaptive)&priv->rate_adaptive;
287 u32 currentRATR, targetRATR = 0;
288 u32 LowRSSIThreshForRA = 0, HighRSSIThreshForRA = 0;
289 bool bshort_gi_enabled = false;
290 static u8 ping_rssi_state;
291
292 if (!priv->up) {
293 RT_TRACE(COMP_RATE, "<---- dm_check_rate_adaptive(): driver is going to unload\n");
294 return;
295 }
296
297 if (pra->rate_adaptive_disabled) /* this variable is set by ioctl. */
298 return;
299
300 /* TODO: Only 11n mode is implemented currently, */
301 if (!(priv->ieee80211->mode == WIRELESS_MODE_N_24G ||
302 priv->ieee80211->mode == WIRELESS_MODE_N_5G))
303 return;
304
305 if (priv->ieee80211->state == IEEE80211_LINKED) {
306 /*RT_TRACE(COMP_RATE, "dm_CheckRateAdaptive(): \t");*/
307
308 /* Check whether Short GI is enabled */
309 bshort_gi_enabled = (pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI40MHz) ||
310 (!pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI20MHz);
311
312 pra->upper_rssi_threshold_ratr =
313 (pra->upper_rssi_threshold_ratr & (~BIT(31))) |
314 ((bshort_gi_enabled) ? BIT(31) : 0);
315
316 pra->middle_rssi_threshold_ratr =
317 (pra->middle_rssi_threshold_ratr & (~BIT(31))) |
318 ((bshort_gi_enabled) ? BIT(31) : 0);
319
320 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
321 pra->low_rssi_threshold_ratr =
322 (pra->low_rssi_threshold_ratr_40M & (~BIT(31))) |
323 ((bshort_gi_enabled) ? BIT(31) : 0);
324 } else {
325 pra->low_rssi_threshold_ratr =
326 (pra->low_rssi_threshold_ratr_20M & (~BIT(31))) |
327 ((bshort_gi_enabled) ? BIT(31) : 0);
328 }
329 /* cosa add for test */
330 pra->ping_rssi_ratr =
331 (pra->ping_rssi_ratr & (~BIT(31))) |
332 ((bshort_gi_enabled) ? BIT(31) : 0);
333
334 /* 2007/10/08 MH We support RA smooth scheme now. When it is the first
335 * time to link with AP. We will not change upper/lower threshold. If
336 * STA stay in high or low level, we must change two different threshold
337 * to prevent jumping frequently.
338 */
339 if (pra->ratr_state == DM_RATR_STA_HIGH) {
340 HighRSSIThreshForRA = pra->high2low_rssi_thresh_for_ra;
341 LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ?
342 (pra->low_rssi_thresh_for_ra40M):(pra->low_rssi_thresh_for_ra20M);
343 } else if (pra->ratr_state == DM_RATR_STA_LOW) {
344 HighRSSIThreshForRA = pra->high_rssi_thresh_for_ra;
345 LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ?
346 (pra->low2high_rssi_thresh_for_ra40M):(pra->low2high_rssi_thresh_for_ra20M);
347 } else {
348 HighRSSIThreshForRA = pra->high_rssi_thresh_for_ra;
349 LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ?
350 (pra->low_rssi_thresh_for_ra40M):(pra->low_rssi_thresh_for_ra20M);
351 }
352
353 /*DbgPrint("[DM] THresh H/L=%d/%d\n\r", RATR.HighRSSIThreshForRA, RATR.LowRSSIThreshForRA);*/
354 if (priv->undecorated_smoothed_pwdb >= (long)HighRSSIThreshForRA) {
355 /*DbgPrint("[DM] RSSI=%d STA=HIGH\n\r", pHalData->UndecoratedSmoothedPWDB);*/
356 pra->ratr_state = DM_RATR_STA_HIGH;
357 targetRATR = pra->upper_rssi_threshold_ratr;
358 } else if (priv->undecorated_smoothed_pwdb >= (long)LowRSSIThreshForRA) {
359 /*DbgPrint("[DM] RSSI=%d STA=Middle\n\r", pHalData->UndecoratedSmoothedPWDB);*/
360 pra->ratr_state = DM_RATR_STA_MIDDLE;
361 targetRATR = pra->middle_rssi_threshold_ratr;
362 } else {
363 /*DbgPrint("[DM] RSSI=%d STA=LOW\n\r", pHalData->UndecoratedSmoothedPWDB);*/
364 pra->ratr_state = DM_RATR_STA_LOW;
365 targetRATR = pra->low_rssi_threshold_ratr;
366 }
367
368 /* cosa add for test */
369 if (pra->ping_rssi_enable) {
370 /*pHalData->UndecoratedSmoothedPWDB = 19;*/
371 if (priv->undecorated_smoothed_pwdb < (long)(pra->ping_rssi_thresh_for_ra+5)) {
372 if ((priv->undecorated_smoothed_pwdb < (long)pra->ping_rssi_thresh_for_ra) ||
373 ping_rssi_state) {
374 /*DbgPrint("TestRSSI = %d, set RATR to 0x%x\n", pHalData->UndecoratedSmoothedPWDB, pRA->TestRSSIRATR);*/
375 pra->ratr_state = DM_RATR_STA_LOW;
376 targetRATR = pra->ping_rssi_ratr;
377 ping_rssi_state = 1;
378 }
379 /*else
380 DbgPrint("TestRSSI is between the range.\n");*/
381 } else {
382 /*DbgPrint("TestRSSI Recover to 0x%x\n", targetRATR);*/
383 ping_rssi_state = 0;
384 }
385 }
386
387 /* 2008.04.01
388 * For RTL819X, if pairwisekey = wep/tkip, we support only MCS0~7.
389 */
390 if (priv->ieee80211->GetHalfNmodeSupportByAPsHandler(dev))
391 targetRATR &= 0xf00fffff;
392
393 /* Check whether updating of RATR0 is required */
394 read_nic_dword(dev, RATR0, ¤tRATR);
395 if (targetRATR != currentRATR) {
396 u32 ratr_value;
397
398 ratr_value = targetRATR;
399 RT_TRACE(COMP_RATE, "currentRATR = %x, targetRATR = %x\n", currentRATR, targetRATR);
400 if (priv->rf_type == RF_1T2R)
401 ratr_value &= ~(RATE_ALL_OFDM_2SS);
402 write_nic_dword(dev, RATR0, ratr_value);
403 write_nic_byte(dev, UFWP, 1);
404
405 pra->last_ratr = targetRATR;
406 }
407
408 } else {
409 pra->ratr_state = DM_RATR_STA_MAX;
410 }
411
412 } /* dm_CheckRateAdaptive */
413
dm_init_bandwidth_autoswitch(struct net_device * dev)414 static void dm_init_bandwidth_autoswitch(struct net_device *dev)
415 {
416 struct r8192_priv *priv = ieee80211_priv(dev);
417
418 priv->ieee80211->bandwidth_auto_switch.threshold_20Mhzto40Mhz = BW_AUTO_SWITCH_LOW_HIGH;
419 priv->ieee80211->bandwidth_auto_switch.threshold_40Mhzto20Mhz = BW_AUTO_SWITCH_HIGH_LOW;
420 priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = false;
421 priv->ieee80211->bandwidth_auto_switch.bautoswitch_enable = false;
422
423 } /* dm_init_bandwidth_autoswitch */
424
dm_bandwidth_autoswitch(struct net_device * dev)425 static void dm_bandwidth_autoswitch(struct net_device *dev)
426 {
427 struct r8192_priv *priv = ieee80211_priv(dev);
428
429 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 || !priv->ieee80211->bandwidth_auto_switch.bautoswitch_enable)
430 return;
431 if (!priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz) { /* If send packets in 40 Mhz in 20/40 */
432 if (priv->undecorated_smoothed_pwdb <= priv->ieee80211->bandwidth_auto_switch.threshold_40Mhzto20Mhz)
433 priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = true;
434 } else { /* in force send packets in 20 Mhz in 20/40 */
435 if (priv->undecorated_smoothed_pwdb >= priv->ieee80211->bandwidth_auto_switch.threshold_20Mhzto40Mhz)
436 priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = false;
437 }
438 } /* dm_BandwidthAutoSwitch */
439
440 /* OFDM default at 0db, index=6. */
441 static u32 OFDMSwingTable[OFDM_Table_Length] = {
442 0x7f8001fe, /* 0, +6db */
443 0x71c001c7, /* 1, +5db */
444 0x65400195, /* 2, +4db */
445 0x5a400169, /* 3, +3db */
446 0x50800142, /* 4, +2db */
447 0x47c0011f, /* 5, +1db */
448 0x40000100, /* 6, +0db ===> default, upper for higher temperature, lower for low temperature */
449 0x390000e4, /* 7, -1db */
450 0x32c000cb, /* 8, -2db */
451 0x2d4000b5, /* 9, -3db */
452 0x288000a2, /* 10, -4db */
453 0x24000090, /* 11, -5db */
454 0x20000080, /* 12, -6db */
455 0x1c800072, /* 13, -7db */
456 0x19800066, /* 14, -8db */
457 0x26c0005b, /* 15, -9db */
458 0x24400051, /* 16, -10db */
459 0x12000048, /* 17, -11db */
460 0x10000040 /* 18, -12db */
461 };
462
463 static u8 CCKSwingTable_Ch1_Ch13[CCK_Table_length][8] = {
464 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0db ===> CCK40M default */
465 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 1, -1db */
466 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 2, -2db */
467 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 3, -3db */
468 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 4, -4db */
469 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 5, -5db */
470 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 6, -6db ===> CCK20M default */
471 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 7, -7db */
472 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 8, -8db */
473 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 9, -9db */
474 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 10, -10db */
475 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01} /* 11, -11db */
476 };
477
478 static u8 CCKSwingTable_Ch14[CCK_Table_length][8] = {
479 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0db ===> CCK40M default */
480 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 1, -1db */
481 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 2, -2db */
482 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 3, -3db */
483 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 4, -4db */
484 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 5, -5db */
485 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 6, -6db ===> CCK20M default */
486 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 7, -7db */
487 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 8, -8db */
488 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 9, -9db */
489 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 10, -10db */
490 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00} /* 11, -11db */
491 };
492
dm_TXPowerTrackingCallback_TSSI(struct net_device * dev)493 static void dm_TXPowerTrackingCallback_TSSI(struct net_device *dev)
494 {
495 struct r8192_priv *priv = ieee80211_priv(dev);
496 bool viviflag = false;
497 struct tx_config_cmd tx_cmd;
498 u8 powerlevelOFDM24G;
499 int i = 0, j = 0, k = 0;
500 u8 RF_Type, tmp_report[5] = {0, 0, 0, 0, 0};
501 u32 Value;
502 u8 Pwr_Flag;
503 u16 Avg_TSSI_Meas, TSSI_13dBm, Avg_TSSI_Meas_from_driver = 0;
504 /*RT_STATUS rtStatus = RT_STATUS_SUCCESS;*/
505 bool rtStatus = true;
506 u32 delta = 0;
507
508 write_nic_byte(dev, 0x1ba, 0);
509
510 priv->ieee80211->bdynamic_txpower_enable = false;
511
512 powerlevelOFDM24G = (u8)(priv->Pwr_Track>>24);
513 RF_Type = priv->rf_type;
514 Value = (RF_Type<<8) | powerlevelOFDM24G;
515
516 RT_TRACE(COMP_POWER_TRACKING, "powerlevelOFDM24G = %x\n", powerlevelOFDM24G);
517
518 for (j = 0; j <= 30; j++) { /* fill tx_cmd */
519 tx_cmd.cmd_op = TXCMD_SET_TX_PWR_TRACKING;
520 tx_cmd.cmd_length = sizeof(tx_cmd.cmd_op);
521 tx_cmd.cmd_value = Value;
522 rtStatus = SendTxCommandPacket(dev, &tx_cmd, sizeof(struct tx_config_cmd));
523 if (rtStatus == RT_STATUS_FAILURE)
524 RT_TRACE(COMP_POWER_TRACKING, "Set configuration with tx cmd queue fail!\n");
525 usleep_range(1000, 2000);
526 /*DbgPrint("hi, vivi, strange\n");*/
527 for (i = 0; i <= 30; i++) {
528 read_nic_byte(dev, 0x1ba, &Pwr_Flag);
529
530 if (Pwr_Flag == 0) {
531 usleep_range(1000, 2000);
532 continue;
533 }
534 read_nic_word(dev, 0x13c, &Avg_TSSI_Meas);
535 if (Avg_TSSI_Meas == 0) {
536 write_nic_byte(dev, 0x1ba, 0);
537 break;
538 }
539
540 for (k = 0; k < 5; k++) {
541 if (k != 4)
542 read_nic_byte(dev, 0x134+k, &tmp_report[k]);
543 else
544 read_nic_byte(dev, 0x13e, &tmp_report[k]);
545 RT_TRACE(COMP_POWER_TRACKING, "TSSI_report_value = %d\n", tmp_report[k]);
546 }
547
548 /* check if the report value is right */
549 for (k = 0; k < 5; k++) {
550 if (tmp_report[k] <= 20) {
551 viviflag = true;
552 break;
553 }
554 }
555 if (viviflag) {
556 write_nic_byte(dev, 0x1ba, 0);
557 viviflag = false;
558 RT_TRACE(COMP_POWER_TRACKING, "we filtered the data\n");
559 for (k = 0; k < 5; k++)
560 tmp_report[k] = 0;
561 break;
562 }
563
564 for (k = 0; k < 5; k++)
565 Avg_TSSI_Meas_from_driver += tmp_report[k];
566
567 Avg_TSSI_Meas_from_driver = Avg_TSSI_Meas_from_driver*100/5;
568 RT_TRACE(COMP_POWER_TRACKING, "Avg_TSSI_Meas_from_driver = %d\n", Avg_TSSI_Meas_from_driver);
569 TSSI_13dBm = priv->TSSI_13dBm;
570 RT_TRACE(COMP_POWER_TRACKING, "TSSI_13dBm = %d\n", TSSI_13dBm);
571
572 /*if (abs(Avg_TSSI_Meas_from_driver - TSSI_13dBm) <= E_FOR_TX_POWER_TRACK)*/
573 /* For MacOS-compatible */
574 if (Avg_TSSI_Meas_from_driver > TSSI_13dBm)
575 delta = Avg_TSSI_Meas_from_driver - TSSI_13dBm;
576 else
577 delta = TSSI_13dBm - Avg_TSSI_Meas_from_driver;
578
579 if (delta <= E_FOR_TX_POWER_TRACK) {
580 priv->ieee80211->bdynamic_txpower_enable = true;
581 write_nic_byte(dev, 0x1ba, 0);
582 RT_TRACE(COMP_POWER_TRACKING, "tx power track is done\n");
583 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex);
584 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real);
585 RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attenuation_difference = %d\n", priv->cck_present_attenuation_difference);
586 RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attenuation = %d\n", priv->cck_present_attenuation);
587 return;
588 }
589 if (Avg_TSSI_Meas_from_driver < TSSI_13dBm - E_FOR_TX_POWER_TRACK) {
590 if (priv->rfa_txpowertrackingindex > 0) {
591 priv->rfa_txpowertrackingindex--;
592 if (priv->rfa_txpowertrackingindex_real > 4) {
593 priv->rfa_txpowertrackingindex_real--;
594 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value);
595 }
596 }
597 } else {
598 if (priv->rfa_txpowertrackingindex < 36) {
599 priv->rfa_txpowertrackingindex++;
600 priv->rfa_txpowertrackingindex_real++;
601 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value);
602
603 }
604 }
605 priv->cck_present_attenuation_difference
606 = priv->rfa_txpowertrackingindex - priv->rfa_txpowertracking_default;
607
608 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
609 priv->cck_present_attenuation
610 = priv->cck_present_attenuation_20Mdefault + priv->cck_present_attenuation_difference;
611 else
612 priv->cck_present_attenuation
613 = priv->cck_present_attenuation_40Mdefault + priv->cck_present_attenuation_difference;
614
615 if (priv->cck_present_attenuation > -1 && priv->cck_present_attenuation < 23) {
616 if (priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14) {
617 priv->bcck_in_ch14 = true;
618 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
619 } else if (priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14) {
620 priv->bcck_in_ch14 = false;
621 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
622 } else
623 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
624 }
625 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex);
626 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real);
627 RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attenuation_difference = %d\n", priv->cck_present_attenuation_difference);
628 RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attenuation = %d\n", priv->cck_present_attenuation);
629
630 if (priv->cck_present_attenuation_difference <= -12 || priv->cck_present_attenuation_difference >= 24) {
631 priv->ieee80211->bdynamic_txpower_enable = true;
632 write_nic_byte(dev, 0x1ba, 0);
633 RT_TRACE(COMP_POWER_TRACKING, "tx power track--->limited\n");
634 return;
635 }
636
637 write_nic_byte(dev, 0x1ba, 0);
638 Avg_TSSI_Meas_from_driver = 0;
639 for (k = 0; k < 5; k++)
640 tmp_report[k] = 0;
641 break;
642 }
643 }
644 priv->ieee80211->bdynamic_txpower_enable = true;
645 write_nic_byte(dev, 0x1ba, 0);
646 }
647
dm_TXPowerTrackingCallback_ThermalMeter(struct net_device * dev)648 static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device *dev)
649 {
650 #define ThermalMeterVal 9
651 struct r8192_priv *priv = ieee80211_priv(dev);
652 u32 tmpRegA, TempCCk;
653 u8 tmpOFDMindex, tmpCCKindex, tmpCCK20Mindex, tmpCCK40Mindex, tmpval;
654 int i = 0, CCKSwingNeedUpdate = 0;
655
656 if (!priv->btxpower_trackingInit) {
657 /* Query OFDM default setting */
658 tmpRegA = rtl8192_QueryBBReg(dev, rOFDM0_XATxIQImbalance, bMaskDWord);
659 for (i = 0; i < OFDM_Table_Length; i++) { /* find the index */
660 if (tmpRegA == OFDMSwingTable[i]) {
661 priv->OFDM_index = (u8)i;
662 RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x = 0x%x, OFDM_index=0x%x\n",
663 rOFDM0_XATxIQImbalance, tmpRegA, priv->OFDM_index);
664 }
665 }
666
667 /* Query CCK default setting From 0xa22 */
668 TempCCk = rtl8192_QueryBBReg(dev, rCCK0_TxFilter1, bMaskByte2);
669 for (i = 0; i < CCK_Table_length; i++) {
670 if (TempCCk == (u32)CCKSwingTable_Ch1_Ch13[i][0]) {
671 priv->CCK_index = (u8) i;
672 RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x = 0x%x, CCK_index=0x%x\n",
673 rCCK0_TxFilter1, TempCCk, priv->CCK_index);
674 break;
675 }
676 }
677 priv->btxpower_trackingInit = true;
678 /*pHalData->TXPowercount = 0;*/
679 return;
680 }
681
682 /* ==========================
683 * this is only for test, should be masked
684 * ==========================
685 */
686
687 /* read and filter out unreasonable value */
688 tmpRegA = rtl8192_phy_QueryRFReg(dev, RF90_PATH_A, 0x12, 0x078); /* 0x12: RF Reg[10:7] */
689 RT_TRACE(COMP_POWER_TRACKING, "Readback ThermalMeterA = %d\n", tmpRegA);
690 if (tmpRegA < 3 || tmpRegA > 13)
691 return;
692 if (tmpRegA >= 12) /* if over 12, TP will be bad when high temperature */
693 tmpRegA = 12;
694 RT_TRACE(COMP_POWER_TRACKING, "Valid ThermalMeterA = %d\n", tmpRegA);
695 priv->ThermalMeter[0] = ThermalMeterVal; /* We use fixed value by Bryant's suggestion */
696 priv->ThermalMeter[1] = ThermalMeterVal; /* We use fixed value by Bryant's suggestion */
697
698 /* Get current RF-A temperature index */
699 if (priv->ThermalMeter[0] >= (u8)tmpRegA) { /* lower temperature */
700 tmpOFDMindex = tmpCCK20Mindex = 6+(priv->ThermalMeter[0]-(u8)tmpRegA);
701 tmpCCK40Mindex = tmpCCK20Mindex - 6;
702 if (tmpOFDMindex >= OFDM_Table_Length)
703 tmpOFDMindex = OFDM_Table_Length-1;
704 if (tmpCCK20Mindex >= CCK_Table_length)
705 tmpCCK20Mindex = CCK_Table_length-1;
706 if (tmpCCK40Mindex >= CCK_Table_length)
707 tmpCCK40Mindex = CCK_Table_length-1;
708 } else {
709 tmpval = (u8)tmpRegA - priv->ThermalMeter[0];
710
711 if (tmpval >= 6) {
712 /* higher temperature */
713 tmpOFDMindex = 0;
714 tmpCCK20Mindex = 0;
715 } else {
716 /* max to +6dB */
717 tmpOFDMindex = 6 - tmpval;
718 tmpCCK20Mindex = 6 - tmpval;
719 }
720 tmpCCK40Mindex = 0;
721 }
722 /*DbgPrint("%ddb, tmpOFDMindex = %d, tmpCCK20Mindex = %d, tmpCCK40Mindex = %d",
723 ((u1Byte)tmpRegA - pHalData->ThermalMeter[0]),
724 tmpOFDMindex, tmpCCK20Mindex, tmpCCK40Mindex);*/
725 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) /* 40M */
726 tmpCCKindex = tmpCCK40Mindex;
727 else
728 tmpCCKindex = tmpCCK20Mindex;
729
730 if (priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14) {
731 priv->bcck_in_ch14 = true;
732 CCKSwingNeedUpdate = 1;
733 } else if (priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14) {
734 priv->bcck_in_ch14 = false;
735 CCKSwingNeedUpdate = 1;
736 }
737
738 if (priv->CCK_index != tmpCCKindex) {
739 priv->CCK_index = tmpCCKindex;
740 CCKSwingNeedUpdate = 1;
741 }
742
743 if (CCKSwingNeedUpdate) {
744 /*DbgPrint("Update CCK Swing, CCK_index = %d\n", pHalData->CCK_index);*/
745 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
746 }
747 if (priv->OFDM_index != tmpOFDMindex) {
748 priv->OFDM_index = tmpOFDMindex;
749 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable[priv->OFDM_index]);
750 RT_TRACE(COMP_POWER_TRACKING, "Update OFDMSwing[%d] = 0x%x\n",
751 priv->OFDM_index, OFDMSwingTable[priv->OFDM_index]);
752 }
753 priv->txpower_count = 0;
754 }
755
dm_txpower_trackingcallback(struct work_struct * work)756 void dm_txpower_trackingcallback(struct work_struct *work)
757 {
758 struct delayed_work *dwork = to_delayed_work(work);
759 struct r8192_priv *priv = container_of(dwork, struct r8192_priv, txpower_tracking_wq);
760 struct net_device *dev = priv->ieee80211->dev;
761
762 if (priv->bDcut)
763 dm_TXPowerTrackingCallback_TSSI(dev);
764 else
765 dm_TXPowerTrackingCallback_ThermalMeter(dev);
766 }
767
dm_InitializeTXPowerTracking_TSSI(struct net_device * dev)768 static void dm_InitializeTXPowerTracking_TSSI(struct net_device *dev)
769 {
770 struct r8192_priv *priv = ieee80211_priv(dev);
771
772 /* Initial the Tx BB index and mapping value */
773 priv->txbbgain_table[0].txbb_iq_amplifygain = 12;
774 priv->txbbgain_table[0].txbbgain_value = 0x7f8001fe;
775 priv->txbbgain_table[1].txbb_iq_amplifygain = 11;
776 priv->txbbgain_table[1].txbbgain_value = 0x788001e2;
777 priv->txbbgain_table[2].txbb_iq_amplifygain = 10;
778 priv->txbbgain_table[2].txbbgain_value = 0x71c001c7;
779 priv->txbbgain_table[3].txbb_iq_amplifygain = 9;
780 priv->txbbgain_table[3].txbbgain_value = 0x6b8001ae;
781 priv->txbbgain_table[4].txbb_iq_amplifygain = 8;
782 priv->txbbgain_table[4].txbbgain_value = 0x65400195;
783 priv->txbbgain_table[5].txbb_iq_amplifygain = 7;
784 priv->txbbgain_table[5].txbbgain_value = 0x5fc0017f;
785 priv->txbbgain_table[6].txbb_iq_amplifygain = 6;
786 priv->txbbgain_table[6].txbbgain_value = 0x5a400169;
787 priv->txbbgain_table[7].txbb_iq_amplifygain = 5;
788 priv->txbbgain_table[7].txbbgain_value = 0x55400155;
789 priv->txbbgain_table[8].txbb_iq_amplifygain = 4;
790 priv->txbbgain_table[8].txbbgain_value = 0x50800142;
791 priv->txbbgain_table[9].txbb_iq_amplifygain = 3;
792 priv->txbbgain_table[9].txbbgain_value = 0x4c000130;
793 priv->txbbgain_table[10].txbb_iq_amplifygain = 2;
794 priv->txbbgain_table[10].txbbgain_value = 0x47c0011f;
795 priv->txbbgain_table[11].txbb_iq_amplifygain = 1;
796 priv->txbbgain_table[11].txbbgain_value = 0x43c0010f;
797 priv->txbbgain_table[12].txbb_iq_amplifygain = 0;
798 priv->txbbgain_table[12].txbbgain_value = 0x40000100;
799 priv->txbbgain_table[13].txbb_iq_amplifygain = -1;
800 priv->txbbgain_table[13].txbbgain_value = 0x3c8000f2;
801 priv->txbbgain_table[14].txbb_iq_amplifygain = -2;
802 priv->txbbgain_table[14].txbbgain_value = 0x390000e4;
803 priv->txbbgain_table[15].txbb_iq_amplifygain = -3;
804 priv->txbbgain_table[15].txbbgain_value = 0x35c000d7;
805 priv->txbbgain_table[16].txbb_iq_amplifygain = -4;
806 priv->txbbgain_table[16].txbbgain_value = 0x32c000cb;
807 priv->txbbgain_table[17].txbb_iq_amplifygain = -5;
808 priv->txbbgain_table[17].txbbgain_value = 0x300000c0;
809 priv->txbbgain_table[18].txbb_iq_amplifygain = -6;
810 priv->txbbgain_table[18].txbbgain_value = 0x2d4000b5;
811 priv->txbbgain_table[19].txbb_iq_amplifygain = -7;
812 priv->txbbgain_table[19].txbbgain_value = 0x2ac000ab;
813 priv->txbbgain_table[20].txbb_iq_amplifygain = -8;
814 priv->txbbgain_table[20].txbbgain_value = 0x288000a2;
815 priv->txbbgain_table[21].txbb_iq_amplifygain = -9;
816 priv->txbbgain_table[21].txbbgain_value = 0x26000098;
817 priv->txbbgain_table[22].txbb_iq_amplifygain = -10;
818 priv->txbbgain_table[22].txbbgain_value = 0x24000090;
819 priv->txbbgain_table[23].txbb_iq_amplifygain = -11;
820 priv->txbbgain_table[23].txbbgain_value = 0x22000088;
821 priv->txbbgain_table[24].txbb_iq_amplifygain = -12;
822 priv->txbbgain_table[24].txbbgain_value = 0x20000080;
823 priv->txbbgain_table[25].txbb_iq_amplifygain = -13;
824 priv->txbbgain_table[25].txbbgain_value = 0x1a00006c;
825 priv->txbbgain_table[26].txbb_iq_amplifygain = -14;
826 priv->txbbgain_table[26].txbbgain_value = 0x1c800072;
827 priv->txbbgain_table[27].txbb_iq_amplifygain = -15;
828 priv->txbbgain_table[27].txbbgain_value = 0x18000060;
829 priv->txbbgain_table[28].txbb_iq_amplifygain = -16;
830 priv->txbbgain_table[28].txbbgain_value = 0x19800066;
831 priv->txbbgain_table[29].txbb_iq_amplifygain = -17;
832 priv->txbbgain_table[29].txbbgain_value = 0x15800056;
833 priv->txbbgain_table[30].txbb_iq_amplifygain = -18;
834 priv->txbbgain_table[30].txbbgain_value = 0x26c0005b;
835 priv->txbbgain_table[31].txbb_iq_amplifygain = -19;
836 priv->txbbgain_table[31].txbbgain_value = 0x14400051;
837 priv->txbbgain_table[32].txbb_iq_amplifygain = -20;
838 priv->txbbgain_table[32].txbbgain_value = 0x24400051;
839 priv->txbbgain_table[33].txbb_iq_amplifygain = -21;
840 priv->txbbgain_table[33].txbbgain_value = 0x1300004c;
841 priv->txbbgain_table[34].txbb_iq_amplifygain = -22;
842 priv->txbbgain_table[34].txbbgain_value = 0x12000048;
843 priv->txbbgain_table[35].txbb_iq_amplifygain = -23;
844 priv->txbbgain_table[35].txbbgain_value = 0x11000044;
845 priv->txbbgain_table[36].txbb_iq_amplifygain = -24;
846 priv->txbbgain_table[36].txbbgain_value = 0x10000040;
847
848 /* ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29
849 * This Table is for CH1~CH13
850 */
851 priv->cck_txbbgain_table[0].ccktxbb_valuearray[0] = 0x36;
852 priv->cck_txbbgain_table[0].ccktxbb_valuearray[1] = 0x35;
853 priv->cck_txbbgain_table[0].ccktxbb_valuearray[2] = 0x2e;
854 priv->cck_txbbgain_table[0].ccktxbb_valuearray[3] = 0x25;
855 priv->cck_txbbgain_table[0].ccktxbb_valuearray[4] = 0x1c;
856 priv->cck_txbbgain_table[0].ccktxbb_valuearray[5] = 0x12;
857 priv->cck_txbbgain_table[0].ccktxbb_valuearray[6] = 0x09;
858 priv->cck_txbbgain_table[0].ccktxbb_valuearray[7] = 0x04;
859
860 priv->cck_txbbgain_table[1].ccktxbb_valuearray[0] = 0x33;
861 priv->cck_txbbgain_table[1].ccktxbb_valuearray[1] = 0x32;
862 priv->cck_txbbgain_table[1].ccktxbb_valuearray[2] = 0x2b;
863 priv->cck_txbbgain_table[1].ccktxbb_valuearray[3] = 0x23;
864 priv->cck_txbbgain_table[1].ccktxbb_valuearray[4] = 0x1a;
865 priv->cck_txbbgain_table[1].ccktxbb_valuearray[5] = 0x11;
866 priv->cck_txbbgain_table[1].ccktxbb_valuearray[6] = 0x08;
867 priv->cck_txbbgain_table[1].ccktxbb_valuearray[7] = 0x04;
868
869 priv->cck_txbbgain_table[2].ccktxbb_valuearray[0] = 0x30;
870 priv->cck_txbbgain_table[2].ccktxbb_valuearray[1] = 0x2f;
871 priv->cck_txbbgain_table[2].ccktxbb_valuearray[2] = 0x29;
872 priv->cck_txbbgain_table[2].ccktxbb_valuearray[3] = 0x21;
873 priv->cck_txbbgain_table[2].ccktxbb_valuearray[4] = 0x19;
874 priv->cck_txbbgain_table[2].ccktxbb_valuearray[5] = 0x10;
875 priv->cck_txbbgain_table[2].ccktxbb_valuearray[6] = 0x08;
876 priv->cck_txbbgain_table[2].ccktxbb_valuearray[7] = 0x03;
877
878 priv->cck_txbbgain_table[3].ccktxbb_valuearray[0] = 0x2d;
879 priv->cck_txbbgain_table[3].ccktxbb_valuearray[1] = 0x2d;
880 priv->cck_txbbgain_table[3].ccktxbb_valuearray[2] = 0x27;
881 priv->cck_txbbgain_table[3].ccktxbb_valuearray[3] = 0x1f;
882 priv->cck_txbbgain_table[3].ccktxbb_valuearray[4] = 0x18;
883 priv->cck_txbbgain_table[3].ccktxbb_valuearray[5] = 0x0f;
884 priv->cck_txbbgain_table[3].ccktxbb_valuearray[6] = 0x08;
885 priv->cck_txbbgain_table[3].ccktxbb_valuearray[7] = 0x03;
886
887 priv->cck_txbbgain_table[4].ccktxbb_valuearray[0] = 0x2b;
888 priv->cck_txbbgain_table[4].ccktxbb_valuearray[1] = 0x2a;
889 priv->cck_txbbgain_table[4].ccktxbb_valuearray[2] = 0x25;
890 priv->cck_txbbgain_table[4].ccktxbb_valuearray[3] = 0x1e;
891 priv->cck_txbbgain_table[4].ccktxbb_valuearray[4] = 0x16;
892 priv->cck_txbbgain_table[4].ccktxbb_valuearray[5] = 0x0e;
893 priv->cck_txbbgain_table[4].ccktxbb_valuearray[6] = 0x07;
894 priv->cck_txbbgain_table[4].ccktxbb_valuearray[7] = 0x03;
895
896 priv->cck_txbbgain_table[5].ccktxbb_valuearray[0] = 0x28;
897 priv->cck_txbbgain_table[5].ccktxbb_valuearray[1] = 0x28;
898 priv->cck_txbbgain_table[5].ccktxbb_valuearray[2] = 0x22;
899 priv->cck_txbbgain_table[5].ccktxbb_valuearray[3] = 0x1c;
900 priv->cck_txbbgain_table[5].ccktxbb_valuearray[4] = 0x15;
901 priv->cck_txbbgain_table[5].ccktxbb_valuearray[5] = 0x0d;
902 priv->cck_txbbgain_table[5].ccktxbb_valuearray[6] = 0x07;
903 priv->cck_txbbgain_table[5].ccktxbb_valuearray[7] = 0x03;
904
905 priv->cck_txbbgain_table[6].ccktxbb_valuearray[0] = 0x26;
906 priv->cck_txbbgain_table[6].ccktxbb_valuearray[1] = 0x25;
907 priv->cck_txbbgain_table[6].ccktxbb_valuearray[2] = 0x21;
908 priv->cck_txbbgain_table[6].ccktxbb_valuearray[3] = 0x1b;
909 priv->cck_txbbgain_table[6].ccktxbb_valuearray[4] = 0x14;
910 priv->cck_txbbgain_table[6].ccktxbb_valuearray[5] = 0x0d;
911 priv->cck_txbbgain_table[6].ccktxbb_valuearray[6] = 0x06;
912 priv->cck_txbbgain_table[6].ccktxbb_valuearray[7] = 0x03;
913
914 priv->cck_txbbgain_table[7].ccktxbb_valuearray[0] = 0x24;
915 priv->cck_txbbgain_table[7].ccktxbb_valuearray[1] = 0x23;
916 priv->cck_txbbgain_table[7].ccktxbb_valuearray[2] = 0x1f;
917 priv->cck_txbbgain_table[7].ccktxbb_valuearray[3] = 0x19;
918 priv->cck_txbbgain_table[7].ccktxbb_valuearray[4] = 0x13;
919 priv->cck_txbbgain_table[7].ccktxbb_valuearray[5] = 0x0c;
920 priv->cck_txbbgain_table[7].ccktxbb_valuearray[6] = 0x06;
921 priv->cck_txbbgain_table[7].ccktxbb_valuearray[7] = 0x03;
922
923 priv->cck_txbbgain_table[8].ccktxbb_valuearray[0] = 0x22;
924 priv->cck_txbbgain_table[8].ccktxbb_valuearray[1] = 0x21;
925 priv->cck_txbbgain_table[8].ccktxbb_valuearray[2] = 0x1d;
926 priv->cck_txbbgain_table[8].ccktxbb_valuearray[3] = 0x18;
927 priv->cck_txbbgain_table[8].ccktxbb_valuearray[4] = 0x11;
928 priv->cck_txbbgain_table[8].ccktxbb_valuearray[5] = 0x0b;
929 priv->cck_txbbgain_table[8].ccktxbb_valuearray[6] = 0x06;
930 priv->cck_txbbgain_table[8].ccktxbb_valuearray[7] = 0x02;
931
932 priv->cck_txbbgain_table[9].ccktxbb_valuearray[0] = 0x20;
933 priv->cck_txbbgain_table[9].ccktxbb_valuearray[1] = 0x20;
934 priv->cck_txbbgain_table[9].ccktxbb_valuearray[2] = 0x1b;
935 priv->cck_txbbgain_table[9].ccktxbb_valuearray[3] = 0x16;
936 priv->cck_txbbgain_table[9].ccktxbb_valuearray[4] = 0x11;
937 priv->cck_txbbgain_table[9].ccktxbb_valuearray[5] = 0x08;
938 priv->cck_txbbgain_table[9].ccktxbb_valuearray[6] = 0x05;
939 priv->cck_txbbgain_table[9].ccktxbb_valuearray[7] = 0x02;
940
941 priv->cck_txbbgain_table[10].ccktxbb_valuearray[0] = 0x1f;
942 priv->cck_txbbgain_table[10].ccktxbb_valuearray[1] = 0x1e;
943 priv->cck_txbbgain_table[10].ccktxbb_valuearray[2] = 0x1a;
944 priv->cck_txbbgain_table[10].ccktxbb_valuearray[3] = 0x15;
945 priv->cck_txbbgain_table[10].ccktxbb_valuearray[4] = 0x10;
946 priv->cck_txbbgain_table[10].ccktxbb_valuearray[5] = 0x0a;
947 priv->cck_txbbgain_table[10].ccktxbb_valuearray[6] = 0x05;
948 priv->cck_txbbgain_table[10].ccktxbb_valuearray[7] = 0x02;
949
950 priv->cck_txbbgain_table[11].ccktxbb_valuearray[0] = 0x1d;
951 priv->cck_txbbgain_table[11].ccktxbb_valuearray[1] = 0x1c;
952 priv->cck_txbbgain_table[11].ccktxbb_valuearray[2] = 0x18;
953 priv->cck_txbbgain_table[11].ccktxbb_valuearray[3] = 0x14;
954 priv->cck_txbbgain_table[11].ccktxbb_valuearray[4] = 0x0f;
955 priv->cck_txbbgain_table[11].ccktxbb_valuearray[5] = 0x0a;
956 priv->cck_txbbgain_table[11].ccktxbb_valuearray[6] = 0x05;
957 priv->cck_txbbgain_table[11].ccktxbb_valuearray[7] = 0x02;
958
959 priv->cck_txbbgain_table[12].ccktxbb_valuearray[0] = 0x1b;
960 priv->cck_txbbgain_table[12].ccktxbb_valuearray[1] = 0x1a;
961 priv->cck_txbbgain_table[12].ccktxbb_valuearray[2] = 0x17;
962 priv->cck_txbbgain_table[12].ccktxbb_valuearray[3] = 0x13;
963 priv->cck_txbbgain_table[12].ccktxbb_valuearray[4] = 0x0e;
964 priv->cck_txbbgain_table[12].ccktxbb_valuearray[5] = 0x09;
965 priv->cck_txbbgain_table[12].ccktxbb_valuearray[6] = 0x04;
966 priv->cck_txbbgain_table[12].ccktxbb_valuearray[7] = 0x02;
967
968 priv->cck_txbbgain_table[13].ccktxbb_valuearray[0] = 0x1a;
969 priv->cck_txbbgain_table[13].ccktxbb_valuearray[1] = 0x19;
970 priv->cck_txbbgain_table[13].ccktxbb_valuearray[2] = 0x16;
971 priv->cck_txbbgain_table[13].ccktxbb_valuearray[3] = 0x12;
972 priv->cck_txbbgain_table[13].ccktxbb_valuearray[4] = 0x0d;
973 priv->cck_txbbgain_table[13].ccktxbb_valuearray[5] = 0x09;
974 priv->cck_txbbgain_table[13].ccktxbb_valuearray[6] = 0x04;
975 priv->cck_txbbgain_table[13].ccktxbb_valuearray[7] = 0x02;
976
977 priv->cck_txbbgain_table[14].ccktxbb_valuearray[0] = 0x18;
978 priv->cck_txbbgain_table[14].ccktxbb_valuearray[1] = 0x17;
979 priv->cck_txbbgain_table[14].ccktxbb_valuearray[2] = 0x15;
980 priv->cck_txbbgain_table[14].ccktxbb_valuearray[3] = 0x11;
981 priv->cck_txbbgain_table[14].ccktxbb_valuearray[4] = 0x0c;
982 priv->cck_txbbgain_table[14].ccktxbb_valuearray[5] = 0x08;
983 priv->cck_txbbgain_table[14].ccktxbb_valuearray[6] = 0x04;
984 priv->cck_txbbgain_table[14].ccktxbb_valuearray[7] = 0x02;
985
986 priv->cck_txbbgain_table[15].ccktxbb_valuearray[0] = 0x17;
987 priv->cck_txbbgain_table[15].ccktxbb_valuearray[1] = 0x16;
988 priv->cck_txbbgain_table[15].ccktxbb_valuearray[2] = 0x13;
989 priv->cck_txbbgain_table[15].ccktxbb_valuearray[3] = 0x10;
990 priv->cck_txbbgain_table[15].ccktxbb_valuearray[4] = 0x0c;
991 priv->cck_txbbgain_table[15].ccktxbb_valuearray[5] = 0x08;
992 priv->cck_txbbgain_table[15].ccktxbb_valuearray[6] = 0x04;
993 priv->cck_txbbgain_table[15].ccktxbb_valuearray[7] = 0x02;
994
995 priv->cck_txbbgain_table[16].ccktxbb_valuearray[0] = 0x16;
996 priv->cck_txbbgain_table[16].ccktxbb_valuearray[1] = 0x15;
997 priv->cck_txbbgain_table[16].ccktxbb_valuearray[2] = 0x12;
998 priv->cck_txbbgain_table[16].ccktxbb_valuearray[3] = 0x0f;
999 priv->cck_txbbgain_table[16].ccktxbb_valuearray[4] = 0x0b;
1000 priv->cck_txbbgain_table[16].ccktxbb_valuearray[5] = 0x07;
1001 priv->cck_txbbgain_table[16].ccktxbb_valuearray[6] = 0x04;
1002 priv->cck_txbbgain_table[16].ccktxbb_valuearray[7] = 0x01;
1003
1004 priv->cck_txbbgain_table[17].ccktxbb_valuearray[0] = 0x14;
1005 priv->cck_txbbgain_table[17].ccktxbb_valuearray[1] = 0x14;
1006 priv->cck_txbbgain_table[17].ccktxbb_valuearray[2] = 0x11;
1007 priv->cck_txbbgain_table[17].ccktxbb_valuearray[3] = 0x0e;
1008 priv->cck_txbbgain_table[17].ccktxbb_valuearray[4] = 0x0b;
1009 priv->cck_txbbgain_table[17].ccktxbb_valuearray[5] = 0x07;
1010 priv->cck_txbbgain_table[17].ccktxbb_valuearray[6] = 0x03;
1011 priv->cck_txbbgain_table[17].ccktxbb_valuearray[7] = 0x02;
1012
1013 priv->cck_txbbgain_table[18].ccktxbb_valuearray[0] = 0x13;
1014 priv->cck_txbbgain_table[18].ccktxbb_valuearray[1] = 0x13;
1015 priv->cck_txbbgain_table[18].ccktxbb_valuearray[2] = 0x10;
1016 priv->cck_txbbgain_table[18].ccktxbb_valuearray[3] = 0x0d;
1017 priv->cck_txbbgain_table[18].ccktxbb_valuearray[4] = 0x0a;
1018 priv->cck_txbbgain_table[18].ccktxbb_valuearray[5] = 0x06;
1019 priv->cck_txbbgain_table[18].ccktxbb_valuearray[6] = 0x03;
1020 priv->cck_txbbgain_table[18].ccktxbb_valuearray[7] = 0x01;
1021
1022 priv->cck_txbbgain_table[19].ccktxbb_valuearray[0] = 0x12;
1023 priv->cck_txbbgain_table[19].ccktxbb_valuearray[1] = 0x12;
1024 priv->cck_txbbgain_table[19].ccktxbb_valuearray[2] = 0x0f;
1025 priv->cck_txbbgain_table[19].ccktxbb_valuearray[3] = 0x0c;
1026 priv->cck_txbbgain_table[19].ccktxbb_valuearray[4] = 0x09;
1027 priv->cck_txbbgain_table[19].ccktxbb_valuearray[5] = 0x06;
1028 priv->cck_txbbgain_table[19].ccktxbb_valuearray[6] = 0x03;
1029 priv->cck_txbbgain_table[19].ccktxbb_valuearray[7] = 0x01;
1030
1031 priv->cck_txbbgain_table[20].ccktxbb_valuearray[0] = 0x11;
1032 priv->cck_txbbgain_table[20].ccktxbb_valuearray[1] = 0x11;
1033 priv->cck_txbbgain_table[20].ccktxbb_valuearray[2] = 0x0f;
1034 priv->cck_txbbgain_table[20].ccktxbb_valuearray[3] = 0x0c;
1035 priv->cck_txbbgain_table[20].ccktxbb_valuearray[4] = 0x09;
1036 priv->cck_txbbgain_table[20].ccktxbb_valuearray[5] = 0x06;
1037 priv->cck_txbbgain_table[20].ccktxbb_valuearray[6] = 0x03;
1038 priv->cck_txbbgain_table[20].ccktxbb_valuearray[7] = 0x01;
1039
1040 priv->cck_txbbgain_table[21].ccktxbb_valuearray[0] = 0x10;
1041 priv->cck_txbbgain_table[21].ccktxbb_valuearray[1] = 0x10;
1042 priv->cck_txbbgain_table[21].ccktxbb_valuearray[2] = 0x0e;
1043 priv->cck_txbbgain_table[21].ccktxbb_valuearray[3] = 0x0b;
1044 priv->cck_txbbgain_table[21].ccktxbb_valuearray[4] = 0x08;
1045 priv->cck_txbbgain_table[21].ccktxbb_valuearray[5] = 0x05;
1046 priv->cck_txbbgain_table[21].ccktxbb_valuearray[6] = 0x03;
1047 priv->cck_txbbgain_table[21].ccktxbb_valuearray[7] = 0x01;
1048
1049 priv->cck_txbbgain_table[22].ccktxbb_valuearray[0] = 0x0f;
1050 priv->cck_txbbgain_table[22].ccktxbb_valuearray[1] = 0x0f;
1051 priv->cck_txbbgain_table[22].ccktxbb_valuearray[2] = 0x0d;
1052 priv->cck_txbbgain_table[22].ccktxbb_valuearray[3] = 0x0b;
1053 priv->cck_txbbgain_table[22].ccktxbb_valuearray[4] = 0x08;
1054 priv->cck_txbbgain_table[22].ccktxbb_valuearray[5] = 0x05;
1055 priv->cck_txbbgain_table[22].ccktxbb_valuearray[6] = 0x03;
1056 priv->cck_txbbgain_table[22].ccktxbb_valuearray[7] = 0x01;
1057
1058 /* ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29
1059 * This Table is for CH14
1060 */
1061 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[0] = 0x36;
1062 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[1] = 0x35;
1063 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[2] = 0x2e;
1064 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[3] = 0x1b;
1065 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[4] = 0x00;
1066 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[5] = 0x00;
1067 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[6] = 0x00;
1068 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[7] = 0x00;
1069
1070 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[0] = 0x33;
1071 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[1] = 0x32;
1072 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[2] = 0x2b;
1073 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[3] = 0x19;
1074 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[4] = 0x00;
1075 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[5] = 0x00;
1076 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[6] = 0x00;
1077 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[7] = 0x00;
1078
1079 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[0] = 0x30;
1080 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[1] = 0x2f;
1081 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[2] = 0x29;
1082 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[3] = 0x18;
1083 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[4] = 0x00;
1084 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[5] = 0x00;
1085 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[6] = 0x00;
1086 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[7] = 0x00;
1087
1088 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[0] = 0x2d;
1089 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[1] = 0x2d;
1090 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[2] = 0x27;
1091 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[3] = 0x17;
1092 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[4] = 0x00;
1093 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[5] = 0x00;
1094 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[6] = 0x00;
1095 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[7] = 0x00;
1096
1097 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[0] = 0x2b;
1098 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[1] = 0x2a;
1099 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[2] = 0x25;
1100 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[3] = 0x15;
1101 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[4] = 0x00;
1102 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[5] = 0x00;
1103 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[6] = 0x00;
1104 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[7] = 0x00;
1105
1106 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[0] = 0x28;
1107 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[1] = 0x28;
1108 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[2] = 0x22;
1109 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[3] = 0x14;
1110 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[4] = 0x00;
1111 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[5] = 0x00;
1112 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[6] = 0x00;
1113 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[7] = 0x00;
1114
1115 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[0] = 0x26;
1116 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[1] = 0x25;
1117 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[2] = 0x21;
1118 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[3] = 0x13;
1119 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[4] = 0x00;
1120 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[5] = 0x00;
1121 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[6] = 0x00;
1122 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[7] = 0x00;
1123
1124 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[0] = 0x24;
1125 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[1] = 0x23;
1126 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[2] = 0x1f;
1127 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[3] = 0x12;
1128 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[4] = 0x00;
1129 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[5] = 0x00;
1130 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[6] = 0x00;
1131 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[7] = 0x00;
1132
1133 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[0] = 0x22;
1134 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[1] = 0x21;
1135 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[2] = 0x1d;
1136 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[3] = 0x11;
1137 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[4] = 0x00;
1138 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[5] = 0x00;
1139 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[6] = 0x00;
1140 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[7] = 0x00;
1141
1142 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[0] = 0x20;
1143 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[1] = 0x20;
1144 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[2] = 0x1b;
1145 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[3] = 0x10;
1146 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[4] = 0x00;
1147 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[5] = 0x00;
1148 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[6] = 0x00;
1149 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[7] = 0x00;
1150
1151 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[0] = 0x1f;
1152 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[1] = 0x1e;
1153 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[2] = 0x1a;
1154 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[3] = 0x0f;
1155 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[4] = 0x00;
1156 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[5] = 0x00;
1157 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[6] = 0x00;
1158 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[7] = 0x00;
1159
1160 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[0] = 0x1d;
1161 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[1] = 0x1c;
1162 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[2] = 0x18;
1163 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[3] = 0x0e;
1164 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[4] = 0x00;
1165 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[5] = 0x00;
1166 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[6] = 0x00;
1167 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[7] = 0x00;
1168
1169 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[0] = 0x1b;
1170 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[1] = 0x1a;
1171 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[2] = 0x17;
1172 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[3] = 0x0e;
1173 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[4] = 0x00;
1174 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[5] = 0x00;
1175 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[6] = 0x00;
1176 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[7] = 0x00;
1177
1178 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[0] = 0x1a;
1179 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[1] = 0x19;
1180 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[2] = 0x16;
1181 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[3] = 0x0d;
1182 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[4] = 0x00;
1183 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[5] = 0x00;
1184 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[6] = 0x00;
1185 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[7] = 0x00;
1186
1187 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[0] = 0x18;
1188 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[1] = 0x17;
1189 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[2] = 0x15;
1190 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[3] = 0x0c;
1191 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[4] = 0x00;
1192 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[5] = 0x00;
1193 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[6] = 0x00;
1194 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[7] = 0x00;
1195
1196 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[0] = 0x17;
1197 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[1] = 0x16;
1198 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[2] = 0x13;
1199 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[3] = 0x0b;
1200 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[4] = 0x00;
1201 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[5] = 0x00;
1202 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[6] = 0x00;
1203 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[7] = 0x00;
1204
1205 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[0] = 0x16;
1206 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[1] = 0x15;
1207 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[2] = 0x12;
1208 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[3] = 0x0b;
1209 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[4] = 0x00;
1210 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[5] = 0x00;
1211 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[6] = 0x00;
1212 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[7] = 0x00;
1213
1214 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[0] = 0x14;
1215 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[1] = 0x14;
1216 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[2] = 0x11;
1217 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[3] = 0x0a;
1218 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[4] = 0x00;
1219 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[5] = 0x00;
1220 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[6] = 0x00;
1221 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[7] = 0x00;
1222
1223 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[0] = 0x13;
1224 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[1] = 0x13;
1225 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[2] = 0x10;
1226 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[3] = 0x0a;
1227 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[4] = 0x00;
1228 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[5] = 0x00;
1229 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[6] = 0x00;
1230 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[7] = 0x00;
1231
1232 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[0] = 0x12;
1233 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[1] = 0x12;
1234 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[2] = 0x0f;
1235 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[3] = 0x09;
1236 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[4] = 0x00;
1237 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[5] = 0x00;
1238 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[6] = 0x00;
1239 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[7] = 0x00;
1240
1241 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[0] = 0x11;
1242 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[1] = 0x11;
1243 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[2] = 0x0f;
1244 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[3] = 0x09;
1245 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[4] = 0x00;
1246 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[5] = 0x00;
1247 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[6] = 0x00;
1248 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[7] = 0x00;
1249
1250 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[0] = 0x10;
1251 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[1] = 0x10;
1252 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[2] = 0x0e;
1253 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[3] = 0x08;
1254 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[4] = 0x00;
1255 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[5] = 0x00;
1256 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[6] = 0x00;
1257 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[7] = 0x00;
1258
1259 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[0] = 0x0f;
1260 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[1] = 0x0f;
1261 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[2] = 0x0d;
1262 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[3] = 0x08;
1263 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[4] = 0x00;
1264 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[5] = 0x00;
1265 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[6] = 0x00;
1266 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[7] = 0x00;
1267
1268 priv->btxpower_tracking = true;
1269 priv->txpower_count = 0;
1270 priv->btxpower_trackingInit = false;
1271
1272 }
1273
dm_InitializeTXPowerTracking_ThermalMeter(struct net_device * dev)1274 static void dm_InitializeTXPowerTracking_ThermalMeter(struct net_device *dev)
1275 {
1276 struct r8192_priv *priv = ieee80211_priv(dev);
1277
1278 /* Tx Power tracking by Thermal Meter requires Firmware R/W 3-wire. This mechanism
1279 * can be enabled only when Firmware R/W 3-wire is enabled. Otherwise, frequent r/w
1280 * 3-wire by driver causes RF to go into a wrong state.
1281 */
1282 if (priv->ieee80211->FwRWRF)
1283 priv->btxpower_tracking = true;
1284 else
1285 priv->btxpower_tracking = false;
1286 priv->txpower_count = 0;
1287 priv->btxpower_trackingInit = false;
1288 }
1289
dm_initialize_txpower_tracking(struct net_device * dev)1290 void dm_initialize_txpower_tracking(struct net_device *dev)
1291 {
1292 struct r8192_priv *priv = ieee80211_priv(dev);
1293
1294 if (priv->bDcut)
1295 dm_InitializeTXPowerTracking_TSSI(dev);
1296 else
1297 dm_InitializeTXPowerTracking_ThermalMeter(dev);
1298 } /* dm_InitializeTXPowerTracking */
1299
dm_CheckTXPowerTracking_TSSI(struct net_device * dev)1300 static void dm_CheckTXPowerTracking_TSSI(struct net_device *dev)
1301 {
1302 struct r8192_priv *priv = ieee80211_priv(dev);
1303 static u32 tx_power_track_counter;
1304
1305 if (!priv->btxpower_tracking)
1306 return;
1307 if ((tx_power_track_counter % 30 == 0) && (tx_power_track_counter != 0))
1308 queue_delayed_work(priv->priv_wq, &priv->txpower_tracking_wq, 0);
1309 tx_power_track_counter++;
1310 }
1311
dm_CheckTXPowerTracking_ThermalMeter(struct net_device * dev)1312 static void dm_CheckTXPowerTracking_ThermalMeter(struct net_device *dev)
1313 {
1314 struct r8192_priv *priv = ieee80211_priv(dev);
1315 static u8 TM_Trigger;
1316 /*DbgPrint("dm_CheckTXPowerTracking()\n");*/
1317 if (!priv->btxpower_tracking)
1318 return;
1319 if (priv->txpower_count <= 2) {
1320 priv->txpower_count++;
1321 return;
1322 }
1323
1324 if (!TM_Trigger) {
1325 /* Attention!! You have to write all 12bits of data to RF, or it may cause RF to crash
1326 * actually write reg0x02 bit1=0, then bit1=1.
1327 * DbgPrint("Trigger ThermalMeter, write RF reg0x2 = 0x4d to 0x4f\n");
1328 */
1329 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
1330 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
1331 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
1332 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
1333 TM_Trigger = 1;
1334 return;
1335 }
1336 /*DbgPrint("Schedule TxPowerTrackingWorkItem\n");*/
1337 queue_delayed_work(priv->priv_wq, &priv->txpower_tracking_wq, 0);
1338 TM_Trigger = 0;
1339 }
1340
dm_check_txpower_tracking(struct net_device * dev)1341 static void dm_check_txpower_tracking(struct net_device *dev)
1342 {
1343 struct r8192_priv *priv = ieee80211_priv(dev);
1344 /*static u32 tx_power_track_counter = 0;*/
1345
1346 #ifdef RTL8190P
1347 dm_CheckTXPowerTracking_TSSI(dev);
1348 #else
1349 if (priv->bDcut)
1350 dm_CheckTXPowerTracking_TSSI(dev);
1351 else
1352 dm_CheckTXPowerTracking_ThermalMeter(dev);
1353 #endif
1354
1355 } /* dm_CheckTXPowerTracking */
1356
dm_CCKTxPowerAdjust_TSSI(struct net_device * dev,bool bInCH14)1357 static void dm_CCKTxPowerAdjust_TSSI(struct net_device *dev, bool bInCH14)
1358 {
1359 u32 TempVal;
1360 struct r8192_priv *priv = ieee80211_priv(dev);
1361
1362 /* Write 0xa22 0xa23 */
1363 TempVal = 0;
1364 if (!bInCH14) {
1365 /* Write 0xa22 0xa23 */
1366 TempVal = priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[0] +
1367 (priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[1]<<8);
1368
1369 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1370 /* Write 0xa24 ~ 0xa27 */
1371 TempVal = priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[2] +
1372 (priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[3]<<8) +
1373 (priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[4]<<16)+
1374 (priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[5]<<24);
1375 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1376 /* Write 0xa28 0xa29 */
1377 TempVal = priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[6] +
1378 (priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[7]<<8);
1379
1380 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1381 } else {
1382 TempVal = priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[0] +
1383 (priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[1]<<8);
1384
1385 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1386 /* Write 0xa24 ~ 0xa27 */
1387 TempVal = priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[2] +
1388 (priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[3]<<8) +
1389 (priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[4]<<16)+
1390 (priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[5]<<24);
1391 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1392 /* Write 0xa28 0xa29 */
1393 TempVal = priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[6] +
1394 (priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[7]<<8);
1395
1396 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1397 }
1398 }
1399
dm_CCKTxPowerAdjust_ThermalMeter(struct net_device * dev,bool bInCH14)1400 static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device *dev, bool bInCH14)
1401 {
1402 u32 TempVal;
1403 struct r8192_priv *priv = ieee80211_priv(dev);
1404
1405 TempVal = 0;
1406 if (!bInCH14) {
1407 /* Write 0xa22 0xa23 */
1408 TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][0] +
1409 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][1]<<8);
1410 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1411 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1412 rCCK0_TxFilter1, TempVal);
1413 /* Write 0xa24 ~ 0xa27 */
1414 TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][2] +
1415 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][3]<<8) +
1416 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][4]<<16)+
1417 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][5]<<24);
1418 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1419 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1420 rCCK0_TxFilter2, TempVal);
1421 /* Write 0xa28 0xa29 */
1422 TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][6] +
1423 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][7]<<8);
1424
1425 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1426 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1427 rCCK0_DebugPort, TempVal);
1428 } else {
1429 /*priv->CCKTxPowerAdjustCntNotCh14++; cosa add for debug.*/
1430 /* Write 0xa22 0xa23 */
1431 TempVal = CCKSwingTable_Ch14[priv->CCK_index][0] +
1432 (CCKSwingTable_Ch14[priv->CCK_index][1]<<8);
1433
1434 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1435 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1436 rCCK0_TxFilter1, TempVal);
1437 /* Write 0xa24 ~ 0xa27 */
1438 TempVal = CCKSwingTable_Ch14[priv->CCK_index][2] +
1439 (CCKSwingTable_Ch14[priv->CCK_index][3]<<8) +
1440 (CCKSwingTable_Ch14[priv->CCK_index][4]<<16)+
1441 (CCKSwingTable_Ch14[priv->CCK_index][5]<<24);
1442 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1443 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1444 rCCK0_TxFilter2, TempVal);
1445 /* Write 0xa28 0xa29 */
1446 TempVal = CCKSwingTable_Ch14[priv->CCK_index][6] +
1447 (CCKSwingTable_Ch14[priv->CCK_index][7]<<8);
1448
1449 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1450 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1451 rCCK0_DebugPort, TempVal);
1452 }
1453 }
1454
dm_cck_txpower_adjust(struct net_device * dev,bool binch14)1455 void dm_cck_txpower_adjust(struct net_device *dev, bool binch14)
1456 { /* dm_CCKTxPowerAdjust */
1457 struct r8192_priv *priv = ieee80211_priv(dev);
1458
1459 if (priv->bDcut)
1460 dm_CCKTxPowerAdjust_TSSI(dev, binch14);
1461 else
1462 dm_CCKTxPowerAdjust_ThermalMeter(dev, binch14);
1463 }
1464
1465 #ifndef RTL8192U
dm_txpower_reset_recovery(struct net_device * dev)1466 static void dm_txpower_reset_recovery(
1467 struct net_device *dev
1468 )
1469 {
1470 struct r8192_priv *priv = ieee80211_priv(dev);
1471
1472 RT_TRACE(COMP_POWER_TRACKING, "Start Reset Recovery ==>\n");
1473 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value);
1474 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc80 is %08x\n", priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value);
1475 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFA_txPowerTrackingIndex is %x\n", priv->rfa_txpowertrackingindex);
1476 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF A I/Q Amplify Gain is %ld\n", priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbb_iq_amplifygain);
1477 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: CCK Attenuation is %d dB\n", priv->cck_present_attenuation);
1478 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1479
1480 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value);
1481 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc90 is %08x\n", priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value);
1482 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFC_txPowerTrackingIndex is %x\n", priv->rfc_txpowertrackingindex);
1483 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF C I/Q Amplify Gain is %ld\n", priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbb_iq_amplifygain);
1484
1485 } /* dm_TXPowerResetRecovery */
1486
dm_restore_dynamic_mechanism_state(struct net_device * dev)1487 void dm_restore_dynamic_mechanism_state(struct net_device *dev)
1488 {
1489 struct r8192_priv *priv = ieee80211_priv(dev);
1490 u32 reg_ratr = priv->rate_adaptive.last_ratr;
1491
1492 if (!priv->up) {
1493 RT_TRACE(COMP_RATE, "<---- dm_restore_dynamic_mechanism_state(): driver is going to unload\n");
1494 return;
1495 }
1496
1497 /* Restore previous state for rate adaptive */
1498 if (priv->rate_adaptive.rate_adaptive_disabled)
1499 return;
1500 /* TODO: Only 11n mode is implemented currently, */
1501 if (!(priv->ieee80211->mode == WIRELESS_MODE_N_24G ||
1502 priv->ieee80211->mode == WIRELESS_MODE_N_5G))
1503 return;
1504
1505 {
1506 /* 2007/11/15 MH Copy from 8190PCI. */
1507 u32 ratr_value;
1508
1509 ratr_value = reg_ratr;
1510 if (priv->rf_type == RF_1T2R) { /* 1T2R, Spatial Stream 2 should be disabled */
1511 ratr_value &= ~(RATE_ALL_OFDM_2SS);
1512 /*DbgPrint("HW_VAR_TATR_0 from 0x%x ==> 0x%x\n", ((pu4Byte)(val))[0], ratr_value);*/
1513 }
1514 /*DbgPrint("set HW_VAR_TATR_0 = 0x%x\n", ratr_value);*/
1515 /*cosa PlatformEFIOWrite4Byte(Adapter, RATR0, ((pu4Byte)(val))[0]);*/
1516 write_nic_dword(dev, RATR0, ratr_value);
1517 write_nic_byte(dev, UFWP, 1);
1518 }
1519 /* Restore TX Power Tracking Index */
1520 if (priv->btxpower_trackingInit && priv->btxpower_tracking)
1521 dm_txpower_reset_recovery(dev);
1522
1523 /* Restore BB Initial Gain */
1524 dm_bb_initialgain_restore(dev);
1525
1526 } /* DM_RestoreDynamicMechanismState */
1527
dm_bb_initialgain_restore(struct net_device * dev)1528 static void dm_bb_initialgain_restore(struct net_device *dev)
1529 {
1530 struct r8192_priv *priv = ieee80211_priv(dev);
1531 u32 bit_mask = 0x7f; /* Bit0~ Bit6 */
1532
1533 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1534 return;
1535
1536 /* Disable Initial Gain */
1537 /*PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);*/
1538 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); /* Only clear byte 1 and rewrite. */
1539 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bit_mask, (u32)priv->initgain_backup.xaagccore1);
1540 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bit_mask, (u32)priv->initgain_backup.xbagccore1);
1541 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bit_mask, (u32)priv->initgain_backup.xcagccore1);
1542 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bit_mask, (u32)priv->initgain_backup.xdagccore1);
1543 bit_mask = bMaskByte2;
1544 rtl8192_setBBreg(dev, rCCK0_CCA, bit_mask, (u32)priv->initgain_backup.cca);
1545
1546 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc50 is %x\n", priv->initgain_backup.xaagccore1);
1547 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc58 is %x\n", priv->initgain_backup.xbagccore1);
1548 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc60 is %x\n", priv->initgain_backup.xcagccore1);
1549 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc68 is %x\n", priv->initgain_backup.xdagccore1);
1550 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xa0a is %x\n", priv->initgain_backup.cca);
1551 /* Enable Initial Gain */
1552 /*PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x100);*/
1553 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); /* Only clear byte 1 and rewrite. */
1554
1555 } /* dm_BBInitialGainRestore */
1556
dm_bb_initialgain_backup(struct net_device * dev)1557 static void dm_bb_initialgain_backup(struct net_device *dev)
1558 {
1559 struct r8192_priv *priv = ieee80211_priv(dev);
1560 u32 bit_mask = bMaskByte0; /* Bit0~ Bit6 */
1561
1562 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1563 return;
1564
1565 /*PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);*/
1566 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); /* Only clear byte 1 and rewrite. */
1567 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bit_mask);
1568 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bit_mask);
1569 priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bit_mask);
1570 priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bit_mask);
1571 bit_mask = bMaskByte2;
1572 priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bit_mask);
1573
1574 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc50 is %x\n", priv->initgain_backup.xaagccore1);
1575 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc58 is %x\n", priv->initgain_backup.xbagccore1);
1576 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc60 is %x\n", priv->initgain_backup.xcagccore1);
1577 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc68 is %x\n", priv->initgain_backup.xdagccore1);
1578 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xa0a is %x\n", priv->initgain_backup.cca);
1579
1580 } /* dm_BBInitialGainBakcup */
1581
1582 #endif
1583 /*-----------------------------------------------------------------------------
1584 * Function: dm_dig_init()
1585 *
1586 * Overview: Set DIG scheme init value.
1587 *
1588 * Input: NONE
1589 *
1590 * Output: NONE
1591 *
1592 * Return: NONE
1593 *
1594 * Revised History:
1595 * When Who Remark
1596 * 05/15/2008 amy Create Version 0 porting from windows code.
1597 *
1598 *---------------------------------------------------------------------------*/
dm_dig_init(struct net_device * dev)1599 static void dm_dig_init(struct net_device *dev)
1600 {
1601 struct r8192_priv *priv = ieee80211_priv(dev);
1602 /* 2007/10/05 MH Disable DIG scheme now. Not tested. */
1603 dm_digtable.dig_enable_flag = true;
1604 dm_digtable.dig_algorithm = DIG_ALGO_BY_RSSI;
1605 dm_digtable.dig_algorithm_switch = 0;
1606
1607 /* 2007/10/04 MH Define init gain threshold. */
1608 dm_digtable.dig_state = DM_STA_DIG_MAX;
1609 dm_digtable.dig_highpwr_state = DM_STA_DIG_MAX;
1610
1611 dm_digtable.rssi_low_thresh = DM_DIG_THRESH_LOW;
1612 dm_digtable.rssi_high_thresh = DM_DIG_THRESH_HIGH;
1613
1614 dm_digtable.rssi_high_power_lowthresh = DM_DIG_HIGH_PWR_THRESH_LOW;
1615 dm_digtable.rssi_high_power_highthresh = DM_DIG_HIGH_PWR_THRESH_HIGH;
1616
1617 dm_digtable.rssi_val = 50; /* for new dig debug rssi value */
1618 dm_digtable.backoff_val = DM_DIG_BACKOFF;
1619 if (priv->CustomerID == RT_CID_819x_Netcore)
1620 dm_digtable.rx_gain_range_min = DM_DIG_MIN_NETCORE;
1621 else
1622 dm_digtable.rx_gain_range_min = DM_DIG_MIN;
1623
1624 } /* dm_dig_init */
1625
1626 /*-----------------------------------------------------------------------------
1627 * Function: dm_ctrl_initgain_byrssi()
1628 *
1629 * Overview: Driver must monitor RSSI and notify firmware to change initial
1630 * gain according to different threshold. BB team provide the
1631 * suggested solution.
1632 *
1633 * Input: struct net_device *dev
1634 *
1635 * Output: NONE
1636 *
1637 * Return: NONE
1638 *
1639 * Revised History:
1640 * When Who Remark
1641 * 05/27/2008 amy Create Version 0 porting from windows code.
1642 *---------------------------------------------------------------------------*/
dm_ctrl_initgain_byrssi(struct net_device * dev)1643 static void dm_ctrl_initgain_byrssi(struct net_device *dev)
1644 {
1645 if (!dm_digtable.dig_enable_flag)
1646 return;
1647
1648 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1649 dm_ctrl_initgain_byrssi_by_fwfalse_alarm(dev);
1650 else if (dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1651 dm_ctrl_initgain_byrssi_by_driverrssi(dev);
1652 /* ; */
1653 else
1654 return;
1655 }
1656
dm_ctrl_initgain_byrssi_by_driverrssi(struct net_device * dev)1657 static void dm_ctrl_initgain_byrssi_by_driverrssi(
1658 struct net_device *dev)
1659 {
1660 struct r8192_priv *priv = ieee80211_priv(dev);
1661 u8 i;
1662 static u8 fw_dig;
1663
1664 if (!dm_digtable.dig_enable_flag)
1665 return;
1666
1667 /*DbgPrint("Dig by Sw Rssi\n");*/
1668 if (dm_digtable.dig_algorithm_switch) /* if switched algorithm, we have to disable FW Dig. */
1669 fw_dig = 0;
1670
1671 if (fw_dig <= 3) { /* execute several times to make sure the FW Dig is disabled */
1672 /* FW DIG Off */
1673 for (i = 0; i < 3; i++)
1674 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); /* Only clear byte 1 and rewrite. */
1675 fw_dig++;
1676 dm_digtable.dig_state = DM_STA_DIG_OFF; /* fw dig off. */
1677 }
1678
1679 if (priv->ieee80211->state == IEEE80211_LINKED)
1680 dm_digtable.cur_connect_state = DIG_CONNECT;
1681 else
1682 dm_digtable.cur_connect_state = DIG_DISCONNECT;
1683
1684 /*DbgPrint("DM_DigTable.PreConnectState = %d, DM_DigTable.CurConnectState = %d\n",
1685 DM_DigTable.PreConnectState, DM_DigTable.CurConnectState);*/
1686
1687 dm_digtable.rssi_val = priv->undecorated_smoothed_pwdb;
1688 /*DbgPrint("DM_DigTable.Rssi_val = %d\n", DM_DigTable.Rssi_val);*/
1689 dm_initial_gain(dev);
1690 dm_pd_th(dev);
1691 dm_cs_ratio(dev);
1692 if (dm_digtable.dig_algorithm_switch)
1693 dm_digtable.dig_algorithm_switch = 0;
1694 dm_digtable.pre_connect_state = dm_digtable.cur_connect_state;
1695
1696 } /* dm_CtrlInitGainByRssi */
1697
dm_ctrl_initgain_byrssi_by_fwfalse_alarm(struct net_device * dev)1698 static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
1699 struct net_device *dev)
1700 {
1701 struct r8192_priv *priv = ieee80211_priv(dev);
1702 static u32 reset_cnt;
1703 u8 i;
1704
1705 if (!dm_digtable.dig_enable_flag)
1706 return;
1707
1708 if (dm_digtable.dig_algorithm_switch) {
1709 dm_digtable.dig_state = DM_STA_DIG_MAX;
1710 /* Fw DIG On. */
1711 for (i = 0; i < 3; i++)
1712 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); /* Only clear byte 1 and rewrite.*/
1713 dm_digtable.dig_algorithm_switch = 0;
1714 }
1715
1716 if (priv->ieee80211->state != IEEE80211_LINKED)
1717 return;
1718
1719 /* For smooth, we can not change DIG state. */
1720 if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_low_thresh) &&
1721 (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_thresh))
1722 return;
1723
1724 /*DbgPrint("Dig by Fw False Alarm\n");*/
1725 /*if (DM_DigTable.Dig_State == DM_STA_DIG_OFF)*/
1726 /*DbgPrint("DIG Check\n\r RSSI=%d LOW=%d HIGH=%d STATE=%d",
1727 pHalData->UndecoratedSmoothedPWDB, DM_DigTable.RssiLowThresh,
1728 DM_DigTable.RssiHighThresh, DM_DigTable.Dig_State);*/
1729 /* 1. When RSSI decrease, We have to judge if it is smaller than a threshold
1730 * and then execute the step below.
1731 */
1732 if (priv->undecorated_smoothed_pwdb <= dm_digtable.rssi_low_thresh) {
1733 /* 2008/02/05 MH When we execute silent reset, the DIG PHY parameters
1734 * will be reset to init value. We must prevent the condition.
1735 */
1736 if (dm_digtable.dig_state == DM_STA_DIG_OFF &&
1737 (priv->reset_count == reset_cnt)) {
1738 return;
1739 }
1740 reset_cnt = priv->reset_count;
1741
1742 /* If DIG is off, DIG high power state must reset. */
1743 dm_digtable.dig_highpwr_state = DM_STA_DIG_MAX;
1744 dm_digtable.dig_state = DM_STA_DIG_OFF;
1745
1746 /* 1.1 DIG Off. */
1747 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); /* Only clear byte 1 and rewrite. */
1748
1749 /* 1.2 Set initial gain. */
1750 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x17);
1751 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x17);
1752 write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x17);
1753 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x17);
1754
1755 /* 1.3 Lower PD_TH for OFDM. */
1756 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
1757 /* 2008/01/11 MH 40MHZ 90/92 register are not the same.
1758 * 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
1759 */
1760 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00);
1761 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1762 write_nic_byte(pAdapter, rOFDM0_RxDetector1, 0x40);
1763 else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)
1764 else
1765 PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x40);
1766 */
1767 } else
1768 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
1769
1770 /* 1.4 Lower CS ratio for CCK. */
1771 write_nic_byte(dev, 0xa0a, 0x08);
1772
1773 /* 1.5 Higher EDCCA. */
1774 /*PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x325);*/
1775 return;
1776
1777 }
1778
1779 /* 2. When RSSI increase, We have to judge if it is larger than a threshold
1780 * and then execute the step below.
1781 */
1782 if (priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh) {
1783 u8 reset_flag = 0;
1784
1785 if (dm_digtable.dig_state == DM_STA_DIG_ON &&
1786 (priv->reset_count == reset_cnt)) {
1787 dm_ctrl_initgain_byrssi_highpwr(dev);
1788 return;
1789 }
1790 if (priv->reset_count != reset_cnt)
1791 reset_flag = 1;
1792
1793 reset_cnt = priv->reset_count;
1794
1795 dm_digtable.dig_state = DM_STA_DIG_ON;
1796 /*DbgPrint("DIG ON\n\r");*/
1797
1798 /* 2.1 Set initial gain.
1799 * 2008/02/26 MH SD3-Jerry suggest to prevent dirty environment.
1800 */
1801 if (reset_flag == 1) {
1802 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x2c);
1803 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x2c);
1804 write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x2c);
1805 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x2c);
1806 } else {
1807 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x20);
1808 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x20);
1809 write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x20);
1810 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x20);
1811 }
1812
1813 /* 2.2 Higher PD_TH for OFDM. */
1814 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
1815 /* 2008/01/11 MH 40MHZ 90/92 register are not the same.
1816 * 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
1817 */
1818 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
1819 /*
1820 else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1821 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
1822 else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)
1823 else
1824 PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x42);
1825 */
1826 } else
1827 write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
1828
1829 /* 2.3 Higher CS ratio for CCK. */
1830 write_nic_byte(dev, 0xa0a, 0xcd);
1831
1832 /* 2.4 Lower EDCCA.
1833 * 2008/01/11 MH 90/92 series are the same.
1834 */
1835 /*PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x346);*/
1836
1837 /* 2.5 DIG On. */
1838 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); /* Only clear byte 1 and rewrite. */
1839
1840 }
1841
1842 dm_ctrl_initgain_byrssi_highpwr(dev);
1843
1844 } /* dm_CtrlInitGainByRssi */
1845
1846 /*-----------------------------------------------------------------------------
1847 * Function: dm_ctrl_initgain_byrssi_highpwr()
1848 *
1849 * Overview:
1850 *
1851 * Input: NONE
1852 *
1853 * Output: NONE
1854 *
1855 * Return: NONE
1856 *
1857 * Revised History:
1858 * When Who Remark
1859 * 05/28/2008 amy Create Version 0 porting from windows code.
1860 *
1861 *---------------------------------------------------------------------------*/
dm_ctrl_initgain_byrssi_highpwr(struct net_device * dev)1862 static void dm_ctrl_initgain_byrssi_highpwr(
1863 struct net_device *dev)
1864 {
1865 struct r8192_priv *priv = ieee80211_priv(dev);
1866 static u32 reset_cnt_highpwr;
1867
1868 /* For smooth, we can not change high power DIG state in the range. */
1869 if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_high_power_lowthresh) &&
1870 (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_highthresh))
1871 return;
1872
1873 /* 3. When RSSI >75% or <70%, it is a high power issue. We have to judge if
1874 * it is larger than a threshold and then execute the step below.
1875 *
1876 * 2008/02/05 MH SD3-Jerry Modify PD_TH for high power issue.
1877 */
1878 if (priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_power_highthresh) {
1879 if (dm_digtable.dig_highpwr_state == DM_STA_DIG_ON &&
1880 (priv->reset_count == reset_cnt_highpwr))
1881 return;
1882 dm_digtable.dig_highpwr_state = DM_STA_DIG_ON;
1883
1884 /* 3.1 Higher PD_TH for OFDM for high power state. */
1885 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
1886 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10);
1887
1888 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1889 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
1890 */
1891
1892 } else
1893 write_nic_byte(dev, rOFDM0_RxDetector1, 0x43);
1894 } else {
1895 if (dm_digtable.dig_highpwr_state == DM_STA_DIG_OFF &&
1896 (priv->reset_count == reset_cnt_highpwr))
1897 return;
1898 dm_digtable.dig_highpwr_state = DM_STA_DIG_OFF;
1899
1900 if (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_lowthresh &&
1901 priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh) {
1902 /* 3.2 Recover PD_TH for OFDM for normal power region. */
1903 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
1904 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
1905 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1906 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
1907 */
1908
1909 } else
1910 write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
1911 }
1912 }
1913
1914 reset_cnt_highpwr = priv->reset_count;
1915
1916 } /* dm_CtrlInitGainByRssiHighPwr */
1917
dm_initial_gain(struct net_device * dev)1918 static void dm_initial_gain(
1919 struct net_device *dev)
1920 {
1921 struct r8192_priv *priv = ieee80211_priv(dev);
1922 u8 initial_gain = 0;
1923 static u8 initialized, force_write;
1924 static u32 reset_cnt;
1925 u8 tmp;
1926
1927 if (dm_digtable.dig_algorithm_switch) {
1928 initialized = 0;
1929 reset_cnt = 0;
1930 }
1931
1932 if (dm_digtable.pre_connect_state == dm_digtable.cur_connect_state) {
1933 if (dm_digtable.cur_connect_state == DIG_CONNECT) {
1934 if ((dm_digtable.rssi_val + 10 - dm_digtable.backoff_val) > DM_DIG_MAX)
1935 dm_digtable.cur_ig_value = DM_DIG_MAX;
1936 else if ((dm_digtable.rssi_val+10-dm_digtable.backoff_val) < dm_digtable.rx_gain_range_min)
1937 dm_digtable.cur_ig_value = dm_digtable.rx_gain_range_min;
1938 else
1939 dm_digtable.cur_ig_value = dm_digtable.rssi_val+10-dm_digtable.backoff_val;
1940 } else { /* current state is disconnected */
1941 if (dm_digtable.cur_ig_value == 0)
1942 dm_digtable.cur_ig_value = priv->DefaultInitialGain[0];
1943 else
1944 dm_digtable.cur_ig_value = dm_digtable.pre_ig_value;
1945 }
1946 } else { /* disconnected -> connected or connected -> disconnected */
1947 dm_digtable.cur_ig_value = priv->DefaultInitialGain[0];
1948 dm_digtable.pre_ig_value = 0;
1949 }
1950 /*DbgPrint("DM_DigTable.CurIGValue = 0x%x, DM_DigTable.PreIGValue = 0x%x\n", DM_DigTable.CurIGValue, DM_DigTable.PreIGValue);*/
1951
1952 /* if silent reset happened, we should rewrite the values back */
1953 if (priv->reset_count != reset_cnt) {
1954 force_write = 1;
1955 reset_cnt = priv->reset_count;
1956 }
1957
1958 read_nic_byte(dev, rOFDM0_XAAGCCore1, &tmp);
1959 if (dm_digtable.pre_ig_value != tmp)
1960 force_write = 1;
1961
1962 {
1963 if ((dm_digtable.pre_ig_value != dm_digtable.cur_ig_value)
1964 || !initialized || force_write) {
1965 initial_gain = (u8)dm_digtable.cur_ig_value;
1966 /*DbgPrint("Write initial gain = 0x%x\n", initial_gain);*/
1967 /* Set initial gain. */
1968 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
1969 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
1970 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
1971 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
1972 dm_digtable.pre_ig_value = dm_digtable.cur_ig_value;
1973 initialized = 1;
1974 force_write = 0;
1975 }
1976 }
1977 }
1978
dm_pd_th(struct net_device * dev)1979 static void dm_pd_th(
1980 struct net_device *dev)
1981 {
1982 struct r8192_priv *priv = ieee80211_priv(dev);
1983 static u8 initialized, force_write;
1984 static u32 reset_cnt;
1985
1986 if (dm_digtable.dig_algorithm_switch) {
1987 initialized = 0;
1988 reset_cnt = 0;
1989 }
1990
1991 if (dm_digtable.pre_connect_state == dm_digtable.cur_connect_state) {
1992 if (dm_digtable.cur_connect_state == DIG_CONNECT) {
1993 if (dm_digtable.rssi_val >= dm_digtable.rssi_high_power_highthresh)
1994 dm_digtable.curpd_thstate = DIG_PD_AT_HIGH_POWER;
1995 else if (dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh)
1996 dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
1997 else if ((dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh) &&
1998 (dm_digtable.rssi_val < dm_digtable.rssi_high_power_lowthresh))
1999 dm_digtable.curpd_thstate = DIG_PD_AT_NORMAL_POWER;
2000 else
2001 dm_digtable.curpd_thstate = dm_digtable.prepd_thstate;
2002 } else {
2003 dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
2004 }
2005 } else { /* disconnected -> connected or connected -> disconnected */
2006 dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
2007 }
2008
2009 /* if silent reset happened, we should rewrite the values back */
2010 if (priv->reset_count != reset_cnt) {
2011 force_write = 1;
2012 reset_cnt = priv->reset_count;
2013 }
2014
2015 {
2016 if ((dm_digtable.prepd_thstate != dm_digtable.curpd_thstate) ||
2017 (initialized <= 3) || force_write) {
2018 /*DbgPrint("Write PD_TH state = %d\n", DM_DigTable.CurPD_THState);*/
2019 if (dm_digtable.curpd_thstate == DIG_PD_AT_LOW_POWER) {
2020 /* Lower PD_TH for OFDM. */
2021 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
2022 /* 2008/01/11 MH 40MHZ 90/92 register are not the same.
2023 * 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
2024 */
2025 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00);
2026 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2027 write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
2028 */
2029 } else
2030 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2031 } else if (dm_digtable.curpd_thstate == DIG_PD_AT_NORMAL_POWER) {
2032 /* Higher PD_TH for OFDM. */
2033 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
2034 /* 2008/01/11 MH 40MHZ 90/92 register are not the same.
2035 * 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
2036 */
2037 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
2038 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2039 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2040 */
2041 } else
2042 write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
2043 } else if (dm_digtable.curpd_thstate == DIG_PD_AT_HIGH_POWER) {
2044 /* Higher PD_TH for OFDM for high power state. */
2045 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
2046 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10);
2047 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2048 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
2049 */
2050 } else
2051 write_nic_byte(dev, rOFDM0_RxDetector1, 0x43);
2052 }
2053 dm_digtable.prepd_thstate = dm_digtable.curpd_thstate;
2054 if (initialized <= 3)
2055 initialized++;
2056 force_write = 0;
2057 }
2058 }
2059 }
2060
dm_cs_ratio(struct net_device * dev)2061 static void dm_cs_ratio(
2062 struct net_device *dev)
2063 {
2064 struct r8192_priv *priv = ieee80211_priv(dev);
2065 static u8 initialized, force_write;
2066 static u32 reset_cnt;
2067
2068 if (dm_digtable.dig_algorithm_switch) {
2069 initialized = 0;
2070 reset_cnt = 0;
2071 }
2072
2073 if (dm_digtable.pre_connect_state == dm_digtable.cur_connect_state) {
2074 if (dm_digtable.cur_connect_state == DIG_CONNECT) {
2075 if (dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh)
2076 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
2077 else if (dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh)
2078 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_HIGHER;
2079 else
2080 dm_digtable.curcs_ratio_state = dm_digtable.precs_ratio_state;
2081 } else {
2082 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
2083 }
2084 } else /* disconnected -> connected or connected -> disconnected */
2085 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
2086
2087 /* if silent reset happened, we should rewrite the values back */
2088 if (priv->reset_count != reset_cnt) {
2089 force_write = 1;
2090 reset_cnt = priv->reset_count;
2091 }
2092
2093 {
2094 if ((dm_digtable.precs_ratio_state != dm_digtable.curcs_ratio_state) ||
2095 !initialized || force_write) {
2096 /*DbgPrint("Write CS_ratio state = %d\n", DM_DigTable.CurCS_ratioState);*/
2097 if (dm_digtable.curcs_ratio_state == DIG_CS_RATIO_LOWER) {
2098 /* Lower CS ratio for CCK. */
2099 write_nic_byte(dev, 0xa0a, 0x08);
2100 } else if (dm_digtable.curcs_ratio_state == DIG_CS_RATIO_HIGHER) {
2101 /* Higher CS ratio for CCK. */
2102 write_nic_byte(dev, 0xa0a, 0xcd);
2103 }
2104 dm_digtable.precs_ratio_state = dm_digtable.curcs_ratio_state;
2105 initialized = 1;
2106 force_write = 0;
2107 }
2108 }
2109 }
2110
dm_init_edca_turbo(struct net_device * dev)2111 void dm_init_edca_turbo(struct net_device *dev)
2112 {
2113 struct r8192_priv *priv = ieee80211_priv(dev);
2114
2115 priv->bcurrent_turbo_EDCA = false;
2116 priv->ieee80211->bis_any_nonbepkts = false;
2117 priv->bis_cur_rdlstate = false;
2118 } /* dm_init_edca_turbo */
2119
dm_check_edca_turbo(struct net_device * dev)2120 static void dm_check_edca_turbo(
2121 struct net_device *dev)
2122 {
2123 struct r8192_priv *priv = ieee80211_priv(dev);
2124 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
2125 /*PSTA_QOS pStaQos = pMgntInfo->pStaQos;*/
2126
2127 /* Keep past Tx/Rx packet count for RT-to-RT EDCA turbo. */
2128 static unsigned long lastTxOkCnt;
2129 static unsigned long lastRxOkCnt;
2130 unsigned long curTxOkCnt = 0;
2131 unsigned long curRxOkCnt = 0;
2132
2133 /* Do not be Turbo if it's under WiFi config and Qos Enabled, because the EDCA parameters
2134 * should follow the settings from QAP. By Bruce, 2007-12-07.
2135 */
2136 if (priv->ieee80211->state != IEEE80211_LINKED)
2137 goto dm_CheckEdcaTurbo_EXIT;
2138 /* We do not turn on EDCA turbo mode for some AP that has IOT issue */
2139 if (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_EDCA_TURBO)
2140 goto dm_CheckEdcaTurbo_EXIT;
2141
2142 /*printk("========>%s():bis_any_nonbepkts is %d\n", __func__, priv->bis_any_nonbepkts);*/
2143 /* Check the status for current condition. */
2144 if (!priv->ieee80211->bis_any_nonbepkts) {
2145 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
2146 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
2147 /* For RT-AP, we needs to turn it on when Rx>Tx */
2148 if (curRxOkCnt > 4*curTxOkCnt) {
2149 /*printk("%s():curRxOkCnt > 4*curTxOkCnt\n");*/
2150 if (!priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA) {
2151 write_nic_dword(dev, EDCAPARA_BE, edca_setting_DL[pHTInfo->IOTPeer]);
2152 priv->bis_cur_rdlstate = true;
2153 }
2154 } else {
2155 /*printk("%s():curRxOkCnt < 4*curTxOkCnt\n");*/
2156 if (priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA) {
2157 write_nic_dword(dev, EDCAPARA_BE, edca_setting_UL[pHTInfo->IOTPeer]);
2158 priv->bis_cur_rdlstate = false;
2159 }
2160
2161 }
2162
2163 priv->bcurrent_turbo_EDCA = true;
2164 } else {
2165 /* Turn Off EDCA turbo here.
2166 * Restore original EDCA according to the declaration of AP.
2167 */
2168 if (priv->bcurrent_turbo_EDCA) {
2169 u8 u1bAIFS;
2170 u32 u4bAcParam, op_limit, cw_max, cw_min;
2171
2172 struct ieee80211_qos_parameters *qos_parameters = &priv->ieee80211->current_network.qos_data.parameters;
2173 u8 mode = priv->ieee80211->mode;
2174
2175 /* For Each time updating EDCA parameter, reset EDCA turbo mode status. */
2176 dm_init_edca_turbo(dev);
2177
2178 u1bAIFS = qos_parameters->aifs[0] * ((mode & (IEEE_G | IEEE_N_24G)) ? 9 : 20) + aSifsTime;
2179
2180 op_limit = (u32)le16_to_cpu(qos_parameters->tx_op_limit[0]);
2181 cw_max = (u32)le16_to_cpu(qos_parameters->cw_max[0]);
2182 cw_min = (u32)le16_to_cpu(qos_parameters->cw_min[0]);
2183
2184 op_limit <<= AC_PARAM_TXOP_LIMIT_OFFSET;
2185 cw_max <<= AC_PARAM_ECW_MAX_OFFSET;
2186 cw_min <<= AC_PARAM_ECW_MIN_OFFSET;
2187 u1bAIFS <<= AC_PARAM_AIFS_OFFSET;
2188
2189 u4bAcParam = op_limit | cw_max | cw_min | u1bAIFS;
2190 cpu_to_le32s(&u4bAcParam);
2191
2192 write_nic_dword(dev, EDCAPARA_BE, u4bAcParam);
2193
2194
2195 /* Check ACM bit.
2196 * If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13.
2197 */
2198 {
2199 /* TODO: Modified this part and try to set acm control in only 1 IO processing!! */
2200
2201 struct aci_aifsn *pAciAifsn = (struct aci_aifsn *)&(qos_parameters->aifs[0]);
2202 u8 AcmCtrl;
2203
2204 read_nic_byte(dev, AcmHwCtrl, &AcmCtrl);
2205
2206 if (pAciAifsn->acm) { /* acm bit is 1. */
2207 AcmCtrl |= AcmHw_BeqEn;
2208 } else { /* ACM bit is 0. */
2209 AcmCtrl &= (~AcmHw_BeqEn);
2210 }
2211
2212 RT_TRACE(COMP_QOS, "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl);
2213 write_nic_byte(dev, AcmHwCtrl, AcmCtrl);
2214 }
2215 priv->bcurrent_turbo_EDCA = false;
2216 }
2217 }
2218
2219 dm_CheckEdcaTurbo_EXIT:
2220 /* Set variables for next time. */
2221 priv->ieee80211->bis_any_nonbepkts = false;
2222 lastTxOkCnt = priv->stats.txbytesunicast;
2223 lastRxOkCnt = priv->stats.rxbytesunicast;
2224 } /* dm_CheckEdcaTurbo */
2225
dm_init_ctstoself(struct net_device * dev)2226 static void dm_init_ctstoself(struct net_device *dev)
2227 {
2228 struct r8192_priv *priv = ieee80211_priv(dev);
2229
2230 priv->ieee80211->bCTSToSelfEnable = true;
2231 priv->ieee80211->CTSToSelfTH = CTS_TO_SELF_TH_VAL;
2232 }
2233
dm_ctstoself(struct net_device * dev)2234 static void dm_ctstoself(struct net_device *dev)
2235 {
2236 struct r8192_priv *priv = ieee80211_priv(dev);
2237 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
2238 static unsigned long lastTxOkCnt;
2239 static unsigned long lastRxOkCnt;
2240 unsigned long curTxOkCnt = 0;
2241 unsigned long curRxOkCnt = 0;
2242
2243 if (priv->ieee80211->bCTSToSelfEnable != true) {
2244 pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;
2245 return;
2246 }
2247 /* 1. Uplink
2248 * 2. Linksys350/Linksys300N
2249 * 3. <50 disable, >55 enable
2250 */
2251
2252 if (pHTInfo->IOTPeer == HT_IOT_PEER_BROADCOM) {
2253 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
2254 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
2255 if (curRxOkCnt > 4*curTxOkCnt) { /* downlink, disable CTS to self */
2256 pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;
2257 /*DbgPrint("dm_CTSToSelf() ==> CTS to self disabled -- downlink\n");*/
2258 } else { /* uplink */
2259 pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_CTS2SELF;
2260 }
2261
2262 lastTxOkCnt = priv->stats.txbytesunicast;
2263 lastRxOkCnt = priv->stats.rxbytesunicast;
2264 }
2265 }
2266
2267 /*-----------------------------------------------------------------------------
2268 * Function: dm_check_pbc_gpio()
2269 *
2270 * Overview: Check if PBC button is pressed.
2271 *
2272 * Input: NONE
2273 *
2274 * Output: NONE
2275 *
2276 * Return: NONE
2277 *
2278 * Revised History:
2279 * When Who Remark
2280 * 05/28/2008 amy Create Version 0 porting from windows code.
2281 *
2282 *---------------------------------------------------------------------------*/
dm_check_pbc_gpio(struct net_device * dev)2283 static void dm_check_pbc_gpio(struct net_device *dev)
2284 {
2285 struct r8192_priv *priv = ieee80211_priv(dev);
2286 u8 tmp1byte;
2287
2288 read_nic_byte(dev, GPI, &tmp1byte);
2289 if (tmp1byte == 0xff)
2290 return;
2291
2292 if (tmp1byte & BIT(6) || tmp1byte & BIT(0)) {
2293 /* Here we only set bPbcPressed to TRUE
2294 * After trigger PBC, the variable will be set to FALSE
2295 */
2296 RT_TRACE(COMP_IO, "CheckPbcGPIO - PBC is pressed\n");
2297 priv->bpbc_pressed = true;
2298 }
2299
2300 }
2301
2302 /*-----------------------------------------------------------------------------
2303 * Function: DM_RFPathCheckWorkItemCallBack()
2304 *
2305 * Overview: Check if Current RF RX path is enabled
2306 *
2307 * Input: NONE
2308 *
2309 * Output: NONE
2310 *
2311 * Return: NONE
2312 *
2313 * Revised History:
2314 * When Who Remark
2315 * 01/30/2008 MHC Create Version 0.
2316 *
2317 *---------------------------------------------------------------------------*/
dm_rf_pathcheck_workitemcallback(struct work_struct * work)2318 void dm_rf_pathcheck_workitemcallback(struct work_struct *work)
2319 {
2320 struct delayed_work *dwork = to_delayed_work(work);
2321 struct r8192_priv *priv = container_of(dwork, struct r8192_priv, rfpath_check_wq);
2322 struct net_device *dev = priv->ieee80211->dev;
2323 /*bool bactually_set = false;*/
2324 u8 rfpath = 0, i;
2325
2326 /* 2008/01/30 MH After discussing with SD3 Jerry, 0xc04/0xd04 register will
2327 * always be the same. We only read 0xc04 now.
2328 */
2329 read_nic_byte(dev, 0xc04, &rfpath);
2330
2331 /* Check Bit 0-3, it means if RF A-D is enabled. */
2332 for (i = 0; i < RF90_PATH_MAX; i++) {
2333 if (rfpath & (0x01<<i))
2334 priv->brfpath_rxenable[i] = true;
2335 else
2336 priv->brfpath_rxenable[i] = false;
2337 }
2338
2339 dm_rxpath_sel_byrssi(dev);
2340 } /* DM_RFPathCheckWorkItemCallBack */
2341
dm_init_rxpath_selection(struct net_device * dev)2342 static void dm_init_rxpath_selection(struct net_device *dev)
2343 {
2344 u8 i;
2345 struct r8192_priv *priv = ieee80211_priv(dev);
2346
2347 if (priv->CustomerID == RT_CID_819x_Netcore)
2348 DM_RxPathSelTable.cck_method = CCK_RX_VERSION_2;
2349 else
2350 DM_RxPathSelTable.cck_method = CCK_RX_VERSION_1;
2351 DM_RxPathSelTable.disabled_rf = 0;
2352 for (i = 0; i < 4; i++) {
2353 DM_RxPathSelTable.rf_rssi[i] = 50;
2354 DM_RxPathSelTable.cck_pwdb_sta[i] = -64;
2355 DM_RxPathSelTable.rf_enable_rssi_th[i] = 100;
2356 }
2357 }
2358
dm_rxpath_sel_byrssi(struct net_device * dev)2359 static void dm_rxpath_sel_byrssi(struct net_device *dev)
2360 {
2361 struct r8192_priv *priv = ieee80211_priv(dev);
2362 u8 i, max_rssi_index = 0, min_rssi_index = 0, sec_rssi_index = 0, rf_num = 0;
2363 u8 tmp_max_rssi = 0, tmp_min_rssi = 0, tmp_sec_rssi = 0;
2364 u8 cck_default_Rx = 0x2; /* RF-C */
2365 u8 cck_optional_Rx = 0x3; /* RF-D */
2366 long tmp_cck_max_pwdb = 0, tmp_cck_min_pwdb = 0, tmp_cck_sec_pwdb = 0;
2367 u8 cck_rx_ver2_max_index = 0, cck_rx_ver2_min_index = 0, cck_rx_ver2_sec_index = 0;
2368 u8 cur_rf_rssi;
2369 long cur_cck_pwdb;
2370 static u8 disabled_rf_cnt, cck_Rx_Path_initialized;
2371 u8 update_cck_rx_path;
2372
2373 if (priv->rf_type != RF_2T4R)
2374 return;
2375
2376 if (!cck_Rx_Path_initialized) {
2377 read_nic_byte(dev, 0xa07, &DM_RxPathSelTable.cck_rx_path);
2378 DM_RxPathSelTable.cck_rx_path &= 0xf;
2379 cck_Rx_Path_initialized = 1;
2380 }
2381
2382 read_nic_byte(dev, 0xc04, &DM_RxPathSelTable.disabled_rf);
2383 DM_RxPathSelTable.disabled_rf = ~DM_RxPathSelTable.disabled_rf & 0xf;
2384
2385 if (priv->ieee80211->mode == WIRELESS_MODE_B) {
2386 DM_RxPathSelTable.cck_method = CCK_RX_VERSION_2; /* pure B mode, fixed cck version2 */
2387 /*DbgPrint("Pure B mode, use cck rx version2\n");*/
2388 }
2389
2390 /* decide max/sec/min rssi index */
2391 for (i = 0; i < RF90_PATH_MAX; i++) {
2392 DM_RxPathSelTable.rf_rssi[i] = priv->stats.rx_rssi_percentage[i];
2393
2394 if (priv->brfpath_rxenable[i]) {
2395 rf_num++;
2396 cur_rf_rssi = DM_RxPathSelTable.rf_rssi[i];
2397
2398 if (rf_num == 1) { /* find first enabled rf path and the rssi values */
2399 /* initialize, set all rssi index to the same one */
2400 max_rssi_index = min_rssi_index = sec_rssi_index = i;
2401 tmp_max_rssi = tmp_min_rssi = tmp_sec_rssi = cur_rf_rssi;
2402 } else if (rf_num == 2) { /* we pick up the max index first, and let sec and min to be the same one */
2403 if (cur_rf_rssi >= tmp_max_rssi) {
2404 tmp_max_rssi = cur_rf_rssi;
2405 max_rssi_index = i;
2406 } else {
2407 tmp_sec_rssi = tmp_min_rssi = cur_rf_rssi;
2408 sec_rssi_index = min_rssi_index = i;
2409 }
2410 } else {
2411 if (cur_rf_rssi > tmp_max_rssi) {
2412 tmp_sec_rssi = tmp_max_rssi;
2413 sec_rssi_index = max_rssi_index;
2414 tmp_max_rssi = cur_rf_rssi;
2415 max_rssi_index = i;
2416 } else if (cur_rf_rssi == tmp_max_rssi) { /* let sec and min point to the different index */
2417 tmp_sec_rssi = cur_rf_rssi;
2418 sec_rssi_index = i;
2419 } else if ((cur_rf_rssi < tmp_max_rssi) && (cur_rf_rssi > tmp_sec_rssi)) {
2420 tmp_sec_rssi = cur_rf_rssi;
2421 sec_rssi_index = i;
2422 } else if (cur_rf_rssi == tmp_sec_rssi) {
2423 if (tmp_sec_rssi == tmp_min_rssi) {
2424 /* let sec and min point to the different index */
2425 tmp_sec_rssi = cur_rf_rssi;
2426 sec_rssi_index = i;
2427 } else {
2428 /* This case we don't need to set any index */
2429 }
2430 } else if ((cur_rf_rssi < tmp_sec_rssi) && (cur_rf_rssi > tmp_min_rssi)) {
2431 /* This case we don't need to set any index */
2432 } else if (cur_rf_rssi == tmp_min_rssi) {
2433 if (tmp_sec_rssi == tmp_min_rssi) {
2434 /* let sec and min point to the different index */
2435 tmp_min_rssi = cur_rf_rssi;
2436 min_rssi_index = i;
2437 } else {
2438 /* This case we don't need to set any index */
2439 }
2440 } else if (cur_rf_rssi < tmp_min_rssi) {
2441 tmp_min_rssi = cur_rf_rssi;
2442 min_rssi_index = i;
2443 }
2444 }
2445 }
2446 }
2447
2448 rf_num = 0;
2449 /* decide max/sec/min cck pwdb index */
2450 if (DM_RxPathSelTable.cck_method == CCK_RX_VERSION_2) {
2451 for (i = 0; i < RF90_PATH_MAX; i++) {
2452 if (priv->brfpath_rxenable[i]) {
2453 rf_num++;
2454 cur_cck_pwdb = DM_RxPathSelTable.cck_pwdb_sta[i];
2455
2456 if (rf_num == 1) { /* find first enabled rf path and the rssi values */
2457 /* initialize, set all rssi index to the same one */
2458 cck_rx_ver2_max_index = cck_rx_ver2_min_index = cck_rx_ver2_sec_index = i;
2459 tmp_cck_max_pwdb = tmp_cck_min_pwdb = tmp_cck_sec_pwdb = cur_cck_pwdb;
2460 } else if (rf_num == 2) { /* we pick up the max index first, and let sec and min to be the same one */
2461 if (cur_cck_pwdb >= tmp_cck_max_pwdb) {
2462 tmp_cck_max_pwdb = cur_cck_pwdb;
2463 cck_rx_ver2_max_index = i;
2464 } else {
2465 tmp_cck_sec_pwdb = tmp_cck_min_pwdb = cur_cck_pwdb;
2466 cck_rx_ver2_sec_index = cck_rx_ver2_min_index = i;
2467 }
2468 } else {
2469 if (cur_cck_pwdb > tmp_cck_max_pwdb) {
2470 tmp_cck_sec_pwdb = tmp_cck_max_pwdb;
2471 cck_rx_ver2_sec_index = cck_rx_ver2_max_index;
2472 tmp_cck_max_pwdb = cur_cck_pwdb;
2473 cck_rx_ver2_max_index = i;
2474 } else if (cur_cck_pwdb == tmp_cck_max_pwdb) {
2475 /* let sec and min point to the different index */
2476 tmp_cck_sec_pwdb = cur_cck_pwdb;
2477 cck_rx_ver2_sec_index = i;
2478 } else if ((cur_cck_pwdb < tmp_cck_max_pwdb) && (cur_cck_pwdb > tmp_cck_sec_pwdb)) {
2479 tmp_cck_sec_pwdb = cur_cck_pwdb;
2480 cck_rx_ver2_sec_index = i;
2481 } else if (cur_cck_pwdb == tmp_cck_sec_pwdb && tmp_cck_sec_pwdb == tmp_cck_min_pwdb) {
2482 /* let sec and min point to the different index */
2483 tmp_cck_sec_pwdb = cur_cck_pwdb;
2484 cck_rx_ver2_sec_index = i;
2485 /* otherwise we don't need to set any index */
2486 } else if ((cur_cck_pwdb < tmp_cck_sec_pwdb) && (cur_cck_pwdb > tmp_cck_min_pwdb)) {
2487 /* This case we don't need to set any index */
2488 } else if (cur_cck_pwdb == tmp_cck_min_pwdb && tmp_cck_sec_pwdb == tmp_cck_min_pwdb) {
2489 /* let sec and min point to the different index */
2490 tmp_cck_min_pwdb = cur_cck_pwdb;
2491 cck_rx_ver2_min_index = i;
2492 /* otherwise we don't need to set any index */
2493 } else if (cur_cck_pwdb < tmp_cck_min_pwdb) {
2494 tmp_cck_min_pwdb = cur_cck_pwdb;
2495 cck_rx_ver2_min_index = i;
2496 }
2497 }
2498
2499 }
2500 }
2501 }
2502
2503 /* Set CCK Rx path
2504 * reg0xA07[3:2]=cck default rx path, reg0xa07[1:0]=cck optional rx path.
2505 */
2506 update_cck_rx_path = 0;
2507 if (DM_RxPathSelTable.cck_method == CCK_RX_VERSION_2) {
2508 cck_default_Rx = cck_rx_ver2_max_index;
2509 cck_optional_Rx = cck_rx_ver2_sec_index;
2510 if (tmp_cck_max_pwdb != -64)
2511 update_cck_rx_path = 1;
2512 }
2513
2514 if (tmp_min_rssi < RX_PATH_SELECTION_SS_TH_LOW && disabled_rf_cnt < 2) {
2515 if ((tmp_max_rssi - tmp_min_rssi) >= RX_PATH_SELECTION_DIFF_TH) {
2516 /* record the enabled rssi threshold */
2517 DM_RxPathSelTable.rf_enable_rssi_th[min_rssi_index] = tmp_max_rssi+5;
2518 /* disable the BB Rx path, OFDM */
2519 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<min_rssi_index, 0x0); /* 0xc04[3:0] */
2520 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<min_rssi_index, 0x0); /* 0xd04[3:0] */
2521 disabled_rf_cnt++;
2522 }
2523 if (DM_RxPathSelTable.cck_method == CCK_RX_VERSION_1) {
2524 cck_default_Rx = max_rssi_index;
2525 cck_optional_Rx = sec_rssi_index;
2526 if (tmp_max_rssi)
2527 update_cck_rx_path = 1;
2528 }
2529 }
2530
2531 if (update_cck_rx_path) {
2532 DM_RxPathSelTable.cck_rx_path = (cck_default_Rx<<2)|(cck_optional_Rx);
2533 rtl8192_setBBreg(dev, rCCK0_AFESetting, 0x0f000000, DM_RxPathSelTable.cck_rx_path);
2534 }
2535
2536 if (DM_RxPathSelTable.disabled_rf) {
2537 for (i = 0; i < 4; i++) {
2538 if ((DM_RxPathSelTable.disabled_rf >> i) & 0x1) { /* disabled rf */
2539 if (tmp_max_rssi >= DM_RxPathSelTable.rf_enable_rssi_th[i]) {
2540 /* enable the BB Rx path */
2541 /*DbgPrint("RF-%d is enabled.\n", 0x1<<i);*/
2542 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<i, 0x1); /* 0xc04[3:0] */
2543 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<i, 0x1); /* 0xd04[3:0] */
2544 DM_RxPathSelTable.rf_enable_rssi_th[i] = 100;
2545 disabled_rf_cnt--;
2546 }
2547 }
2548 }
2549 }
2550 }
2551
2552 /*-----------------------------------------------------------------------------
2553 * Function: dm_check_rx_path_selection()
2554 *
2555 * Overview: Call a workitem to check current RXRF path and Rx Path selection by RSSI.
2556 *
2557 * Input: NONE
2558 *
2559 * Output: NONE
2560 *
2561 * Return: NONE
2562 *
2563 * Revised History:
2564 * When Who Remark
2565 * 05/28/2008 amy Create Version 0 porting from windows code.
2566 *
2567 *---------------------------------------------------------------------------*/
dm_check_rx_path_selection(struct net_device * dev)2568 static void dm_check_rx_path_selection(struct net_device *dev)
2569 {
2570 struct r8192_priv *priv = ieee80211_priv(dev);
2571
2572 queue_delayed_work(priv->priv_wq, &priv->rfpath_check_wq, 0);
2573 } /* dm_CheckRxRFPath */
2574
dm_init_fsync(struct net_device * dev)2575 static void dm_init_fsync(struct net_device *dev)
2576 {
2577 struct r8192_priv *priv = ieee80211_priv(dev);
2578
2579 priv->ieee80211->fsync_time_interval = 500;
2580 priv->ieee80211->fsync_rate_bitmap = 0x0f000800;
2581 priv->ieee80211->fsync_rssi_threshold = 30;
2582 priv->ieee80211->bfsync_enable = false;
2583 priv->ieee80211->fsync_multiple_timeinterval = 3;
2584 priv->ieee80211->fsync_firstdiff_ratethreshold = 100;
2585 priv->ieee80211->fsync_seconddiff_ratethreshold = 200;
2586 priv->ieee80211->fsync_state = Default_Fsync;
2587 priv->framesyncMonitor = 1; /* current default 0xc38 monitor on */
2588 timer_setup(&priv->fsync_timer, dm_fsync_timer_callback, 0);
2589 }
2590
dm_deInit_fsync(struct net_device * dev)2591 static void dm_deInit_fsync(struct net_device *dev)
2592 {
2593 struct r8192_priv *priv = ieee80211_priv(dev);
2594
2595 del_timer_sync(&priv->fsync_timer);
2596 }
2597
dm_fsync_timer_callback(struct timer_list * t)2598 void dm_fsync_timer_callback(struct timer_list *t)
2599 {
2600 struct r8192_priv *priv = from_timer(priv, t, fsync_timer);
2601 struct net_device *dev = priv->ieee80211->dev;
2602 u32 rate_index, rate_count = 0, rate_count_diff = 0;
2603 bool bSwitchFromCountDiff = false;
2604 bool bDoubleTimeInterval = false;
2605
2606 if (priv->ieee80211->state == IEEE80211_LINKED &&
2607 priv->ieee80211->bfsync_enable &&
2608 (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC)) {
2609 /* Count rate 54, MCS [7], [12, 13, 14, 15] */
2610 u32 rate_bitmap;
2611
2612 for (rate_index = 0; rate_index <= 27; rate_index++) {
2613 rate_bitmap = 1 << rate_index;
2614 if (priv->ieee80211->fsync_rate_bitmap & rate_bitmap)
2615 rate_count += priv->stats.received_rate_histogram[1][rate_index];
2616 }
2617
2618 if (rate_count < priv->rate_record)
2619 rate_count_diff = 0xffffffff - rate_count + priv->rate_record;
2620 else
2621 rate_count_diff = rate_count - priv->rate_record;
2622 if (rate_count_diff < priv->rateCountDiffRecord) {
2623 u32 DiffNum = priv->rateCountDiffRecord - rate_count_diff;
2624 /* Continue count */
2625 if (DiffNum >= priv->ieee80211->fsync_seconddiff_ratethreshold)
2626 priv->ContinueDiffCount++;
2627 else
2628 priv->ContinueDiffCount = 0;
2629
2630 /* Continue count over */
2631 if (priv->ContinueDiffCount >= 2) {
2632 bSwitchFromCountDiff = true;
2633 priv->ContinueDiffCount = 0;
2634 }
2635 } else {
2636 /* Stop the continued count */
2637 priv->ContinueDiffCount = 0;
2638 }
2639
2640 /* If Count diff <= FsyncRateCountThreshold */
2641 if (rate_count_diff <= priv->ieee80211->fsync_firstdiff_ratethreshold) {
2642 bSwitchFromCountDiff = true;
2643 priv->ContinueDiffCount = 0;
2644 }
2645 priv->rate_record = rate_count;
2646 priv->rateCountDiffRecord = rate_count_diff;
2647 RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff, priv->bswitch_fsync);
2648 /* if we never receive those mcs rate and rssi > 30 % then switch fsyn */
2649 if (priv->undecorated_smoothed_pwdb > priv->ieee80211->fsync_rssi_threshold && bSwitchFromCountDiff) {
2650 bDoubleTimeInterval = true;
2651 priv->bswitch_fsync = !priv->bswitch_fsync;
2652 if (priv->bswitch_fsync) {
2653 write_nic_byte(dev, 0xC36, 0x1c);
2654 write_nic_byte(dev, 0xC3e, 0x90);
2655 } else {
2656 write_nic_byte(dev, 0xC36, 0x5c);
2657 write_nic_byte(dev, 0xC3e, 0x96);
2658 }
2659 } else if (priv->undecorated_smoothed_pwdb <= priv->ieee80211->fsync_rssi_threshold) {
2660 if (priv->bswitch_fsync) {
2661 priv->bswitch_fsync = false;
2662 write_nic_byte(dev, 0xC36, 0x5c);
2663 write_nic_byte(dev, 0xC3e, 0x96);
2664 }
2665 }
2666 if (bDoubleTimeInterval) {
2667 if (timer_pending(&priv->fsync_timer))
2668 del_timer_sync(&priv->fsync_timer);
2669 priv->fsync_timer.expires = jiffies +
2670 msecs_to_jiffies(priv->ieee80211->fsync_time_interval*priv->ieee80211->fsync_multiple_timeinterval);
2671 add_timer(&priv->fsync_timer);
2672 } else {
2673 if (timer_pending(&priv->fsync_timer))
2674 del_timer_sync(&priv->fsync_timer);
2675 priv->fsync_timer.expires = jiffies +
2676 msecs_to_jiffies(priv->ieee80211->fsync_time_interval);
2677 add_timer(&priv->fsync_timer);
2678 }
2679 } else {
2680 /* Let Register return to default value; */
2681 if (priv->bswitch_fsync) {
2682 priv->bswitch_fsync = false;
2683 write_nic_byte(dev, 0xC36, 0x5c);
2684 write_nic_byte(dev, 0xC3e, 0x96);
2685 }
2686 priv->ContinueDiffCount = 0;
2687 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
2688 }
2689 RT_TRACE(COMP_HALDM, "ContinueDiffCount %d\n", priv->ContinueDiffCount);
2690 RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff, priv->bswitch_fsync);
2691 }
2692
dm_StartHWFsync(struct net_device * dev)2693 static void dm_StartHWFsync(struct net_device *dev)
2694 {
2695 RT_TRACE(COMP_HALDM, "%s\n", __func__);
2696 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cf);
2697 write_nic_byte(dev, 0xc3b, 0x41);
2698 }
2699
dm_EndSWFsync(struct net_device * dev)2700 static void dm_EndSWFsync(struct net_device *dev)
2701 {
2702 struct r8192_priv *priv = ieee80211_priv(dev);
2703
2704 RT_TRACE(COMP_HALDM, "%s\n", __func__);
2705 del_timer_sync(&(priv->fsync_timer));
2706
2707 /* Let Register return to default value; */
2708 if (priv->bswitch_fsync) {
2709 priv->bswitch_fsync = false;
2710
2711 write_nic_byte(dev, 0xC36, 0x5c);
2712
2713 write_nic_byte(dev, 0xC3e, 0x96);
2714 }
2715
2716 priv->ContinueDiffCount = 0;
2717 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
2718
2719 }
2720
dm_StartSWFsync(struct net_device * dev)2721 static void dm_StartSWFsync(struct net_device *dev)
2722 {
2723 struct r8192_priv *priv = ieee80211_priv(dev);
2724 u32 rateIndex;
2725 u32 rateBitmap;
2726
2727 RT_TRACE(COMP_HALDM, "%s\n", __func__);
2728 /* Initial rate record to zero, start to record. */
2729 priv->rate_record = 0;
2730 /* Initialize continue diff count to zero, start to record. */
2731 priv->ContinueDiffCount = 0;
2732 priv->rateCountDiffRecord = 0;
2733 priv->bswitch_fsync = false;
2734
2735 if (priv->ieee80211->mode == WIRELESS_MODE_N_24G) {
2736 priv->ieee80211->fsync_firstdiff_ratethreshold = 600;
2737 priv->ieee80211->fsync_seconddiff_ratethreshold = 0xffff;
2738 } else {
2739 priv->ieee80211->fsync_firstdiff_ratethreshold = 200;
2740 priv->ieee80211->fsync_seconddiff_ratethreshold = 200;
2741 }
2742 for (rateIndex = 0; rateIndex <= 27; rateIndex++) {
2743 rateBitmap = 1 << rateIndex;
2744 if (priv->ieee80211->fsync_rate_bitmap & rateBitmap)
2745 priv->rate_record += priv->stats.received_rate_histogram[1][rateIndex];
2746 }
2747 if (timer_pending(&priv->fsync_timer))
2748 del_timer_sync(&priv->fsync_timer);
2749 priv->fsync_timer.expires = jiffies +
2750 msecs_to_jiffies(priv->ieee80211->fsync_time_interval);
2751 add_timer(&priv->fsync_timer);
2752
2753 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cd);
2754
2755 }
2756
dm_EndHWFsync(struct net_device * dev)2757 static void dm_EndHWFsync(struct net_device *dev)
2758 {
2759 RT_TRACE(COMP_HALDM, "%s\n", __func__);
2760 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
2761 write_nic_byte(dev, 0xc3b, 0x49);
2762
2763 }
2764
dm_check_fsync(struct net_device * dev)2765 void dm_check_fsync(struct net_device *dev)
2766 {
2767 #define RegC38_Default 0
2768 #define RegC38_NonFsync_Other_AP 1
2769 #define RegC38_Fsync_AP_BCM 2
2770 struct r8192_priv *priv = ieee80211_priv(dev);
2771 /*u32 framesyncC34;*/
2772 static u8 reg_c38_State = RegC38_Default;
2773 static u32 reset_cnt;
2774
2775 RT_TRACE(COMP_HALDM, "RSSI %d TimeInterval %d MultipleTimeInterval %d\n", priv->ieee80211->fsync_rssi_threshold, priv->ieee80211->fsync_time_interval, priv->ieee80211->fsync_multiple_timeinterval);
2776 RT_TRACE(COMP_HALDM, "RateBitmap 0x%x FirstDiffRateThreshold %d SecondDiffRateThreshold %d\n", priv->ieee80211->fsync_rate_bitmap, priv->ieee80211->fsync_firstdiff_ratethreshold, priv->ieee80211->fsync_seconddiff_ratethreshold);
2777
2778 if (priv->ieee80211->state == IEEE80211_LINKED &&
2779 (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC)) {
2780 if (priv->ieee80211->bfsync_enable == 0) {
2781 switch (priv->ieee80211->fsync_state) {
2782 case Default_Fsync:
2783 dm_StartHWFsync(dev);
2784 priv->ieee80211->fsync_state = HW_Fsync;
2785 break;
2786 case SW_Fsync:
2787 dm_EndSWFsync(dev);
2788 dm_StartHWFsync(dev);
2789 priv->ieee80211->fsync_state = HW_Fsync;
2790 break;
2791 case HW_Fsync:
2792 default:
2793 break;
2794 }
2795 } else {
2796 switch (priv->ieee80211->fsync_state) {
2797 case Default_Fsync:
2798 dm_StartSWFsync(dev);
2799 priv->ieee80211->fsync_state = SW_Fsync;
2800 break;
2801 case HW_Fsync:
2802 dm_EndHWFsync(dev);
2803 dm_StartSWFsync(dev);
2804 priv->ieee80211->fsync_state = SW_Fsync;
2805 break;
2806 case SW_Fsync:
2807 default:
2808 break;
2809 }
2810 }
2811 if (priv->framesyncMonitor) {
2812 if (reg_c38_State != RegC38_Fsync_AP_BCM) {
2813 /* For broadcom AP we write different default value */
2814 write_nic_byte(dev, rOFDM0_RxDetector3, 0x95);
2815
2816 reg_c38_State = RegC38_Fsync_AP_BCM;
2817 }
2818 }
2819 } else {
2820 switch (priv->ieee80211->fsync_state) {
2821 case HW_Fsync:
2822 dm_EndHWFsync(dev);
2823 priv->ieee80211->fsync_state = Default_Fsync;
2824 break;
2825 case SW_Fsync:
2826 dm_EndSWFsync(dev);
2827 priv->ieee80211->fsync_state = Default_Fsync;
2828 break;
2829 case Default_Fsync:
2830 default:
2831 break;
2832 }
2833
2834 if (priv->framesyncMonitor) {
2835 if (priv->ieee80211->state == IEEE80211_LINKED) {
2836 if (priv->undecorated_smoothed_pwdb <= REG_C38_TH) {
2837 if (reg_c38_State != RegC38_NonFsync_Other_AP) {
2838 write_nic_byte(dev, rOFDM0_RxDetector3, 0x90);
2839
2840 reg_c38_State = RegC38_NonFsync_Other_AP;
2841 }
2842 } else if (priv->undecorated_smoothed_pwdb >= (REG_C38_TH + 5)) {
2843 if (reg_c38_State) {
2844 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
2845 reg_c38_State = RegC38_Default;
2846 /*DbgPrint("Fsync is idle, rssi>=40, write 0xc38 = 0x%x\n", pHalData->framesync);*/
2847 }
2848 }
2849 } else {
2850 if (reg_c38_State) {
2851 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
2852 reg_c38_State = RegC38_Default;
2853 /*DbgPrint("Fsync is idle, not connected, write 0xc38 = 0x%x\n", pHalData->framesync);*/
2854 }
2855 }
2856 }
2857 }
2858 if (priv->framesyncMonitor) {
2859 if (priv->reset_count != reset_cnt) { /* After silent reset, the reg_c38_State will be returned to default value */
2860 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
2861 reg_c38_State = RegC38_Default;
2862 reset_cnt = priv->reset_count;
2863 /*DbgPrint("reg_c38_State = 0 for silent reset.\n");*/
2864 }
2865 } else {
2866 if (reg_c38_State) {
2867 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
2868 reg_c38_State = RegC38_Default;
2869 /*DbgPrint("framesync no monitor, write 0xc38 = 0x%x\n", pHalData->framesync);*/
2870 }
2871 }
2872 }
2873
2874 /*-----------------------------------------------------------------------------
2875 * Function: dm_shadow_init()
2876 *
2877 * Overview: Store all NIC MAC/BB register content.
2878 *
2879 * Input: NONE
2880 *
2881 * Output: NONE
2882 *
2883 * Return: NONE
2884 *
2885 * Revised History:
2886 * When Who Remark
2887 * 05/29/2008 amy Create Version 0 porting from windows code.
2888 *
2889 *---------------------------------------------------------------------------*/
dm_shadow_init(struct net_device * dev)2890 void dm_shadow_init(struct net_device *dev)
2891 {
2892 u8 page;
2893 u16 offset;
2894
2895 for (page = 0; page < 5; page++)
2896 for (offset = 0; offset < 256; offset++) {
2897 read_nic_byte(dev, offset + page * 256, &dm_shadow[page][offset]);
2898 /*DbgPrint("P-%d/O-%02x=%02x\r\n", page, offset, DM_Shadow[page][offset]);*/
2899 }
2900
2901 for (page = 8; page < 11; page++)
2902 for (offset = 0; offset < 256; offset++)
2903 read_nic_byte(dev, offset + page * 256, &dm_shadow[page][offset]);
2904
2905 for (page = 12; page < 15; page++)
2906 for (offset = 0; offset < 256; offset++)
2907 read_nic_byte(dev, offset + page * 256, &dm_shadow[page][offset]);
2908
2909 } /* dm_shadow_init */
2910
2911 /*---------------------------Define function prototype------------------------*/
2912 /*-----------------------------------------------------------------------------
2913 * Function: DM_DynamicTxPower()
2914 *
2915 * Overview: Detect Signal strength to control TX Registry
2916 Tx Power Control For Near/Far Range
2917 *
2918 * Input: NONE
2919 *
2920 * Output: NONE
2921 *
2922 * Return: NONE
2923 *
2924 * Revised History:
2925 * When Who Remark
2926 * 03/06/2008 Jacken Create Version 0.
2927 *
2928 *---------------------------------------------------------------------------*/
dm_init_dynamic_txpower(struct net_device * dev)2929 static void dm_init_dynamic_txpower(struct net_device *dev)
2930 {
2931 struct r8192_priv *priv = ieee80211_priv(dev);
2932
2933 /* Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code. */
2934 priv->ieee80211->bdynamic_txpower_enable = true; /* Default to enable Tx Power Control */
2935 priv->bLastDTPFlag_High = false;
2936 priv->bLastDTPFlag_Low = false;
2937 priv->bDynamicTxHighPower = false;
2938 priv->bDynamicTxLowPower = false;
2939 }
2940
dm_dynamic_txpower(struct net_device * dev)2941 static void dm_dynamic_txpower(struct net_device *dev)
2942 {
2943 struct r8192_priv *priv = ieee80211_priv(dev);
2944 unsigned int txhipower_threshold = 0;
2945 unsigned int txlowpower_threshold = 0;
2946
2947 if (priv->ieee80211->bdynamic_txpower_enable != true) {
2948 priv->bDynamicTxHighPower = false;
2949 priv->bDynamicTxLowPower = false;
2950 return;
2951 }
2952 /*printk("priv->ieee80211->current_network.unknown_cap_exist is %d , priv->ieee80211->current_network.broadcom_cap_exist is %d\n", priv->ieee80211->current_network.unknown_cap_exist, priv->ieee80211->current_network.broadcom_cap_exist);*/
2953 if ((priv->ieee80211->current_network.atheros_cap_exist) && (priv->ieee80211->mode == IEEE_G)) {
2954 txhipower_threshold = TX_POWER_ATHEROAP_THRESH_HIGH;
2955 txlowpower_threshold = TX_POWER_ATHEROAP_THRESH_LOW;
2956 } else {
2957 txhipower_threshold = TX_POWER_NEAR_FIELD_THRESH_HIGH;
2958 txlowpower_threshold = TX_POWER_NEAR_FIELD_THRESH_LOW;
2959 }
2960
2961 /*printk("=======>%s(): txhipower_threshold is %d, txlowpower_threshold is %d\n", __func__, txhipower_threshold, txlowpower_threshold);*/
2962 RT_TRACE(COMP_TXAGC, "priv->undecorated_smoothed_pwdb = %ld\n", priv->undecorated_smoothed_pwdb);
2963
2964 if (priv->ieee80211->state == IEEE80211_LINKED) {
2965 if (priv->undecorated_smoothed_pwdb >= txhipower_threshold) {
2966 priv->bDynamicTxHighPower = true;
2967 priv->bDynamicTxLowPower = false;
2968 } else {
2969 /* high power state check */
2970 if (priv->undecorated_smoothed_pwdb < txlowpower_threshold && priv->bDynamicTxHighPower)
2971 priv->bDynamicTxHighPower = false;
2972
2973 /* low power state check */
2974 if (priv->undecorated_smoothed_pwdb < 35)
2975 priv->bDynamicTxLowPower = true;
2976 else if (priv->undecorated_smoothed_pwdb >= 40)
2977 priv->bDynamicTxLowPower = false;
2978 }
2979 } else {
2980 /*pHalData->bTXPowerCtrlforNearFarRange = !pHalData->bTXPowerCtrlforNearFarRange;*/
2981 priv->bDynamicTxHighPower = false;
2982 priv->bDynamicTxLowPower = false;
2983 }
2984
2985 if ((priv->bDynamicTxHighPower != priv->bLastDTPFlag_High) ||
2986 (priv->bDynamicTxLowPower != priv->bLastDTPFlag_Low)) {
2987 RT_TRACE(COMP_TXAGC, "SetTxPowerLevel8190() channel = %d\n", priv->ieee80211->current_network.channel);
2988
2989 #if defined(RTL8190P) || defined(RTL8192E)
2990 SetTxPowerLevel8190(Adapter, pHalData->CurrentChannel);
2991 #endif
2992
2993 rtl8192_phy_setTxPower(dev, priv->ieee80211->current_network.channel);
2994 /*pHalData->bStartTxCtrlByTPCNFR = FALSE; Clear th flag of Set TX Power from Sitesurvey*/
2995 }
2996 priv->bLastDTPFlag_High = priv->bDynamicTxHighPower;
2997 priv->bLastDTPFlag_Low = priv->bDynamicTxLowPower;
2998
2999 } /* dm_dynamic_txpower */
3000
3001 /* added by vivi, for read tx rate and retrycount */
dm_check_txrateandretrycount(struct net_device * dev)3002 static void dm_check_txrateandretrycount(struct net_device *dev)
3003 {
3004 struct r8192_priv *priv = ieee80211_priv(dev);
3005 struct ieee80211_device *ieee = priv->ieee80211;
3006 /* for 11n tx rate */
3007 /*priv->stats.CurrentShowTxate = read_nic_byte(dev, CURRENT_TX_RATE_REG);*/
3008 read_nic_byte(dev, CURRENT_TX_RATE_REG, &ieee->softmac_stats.CurrentShowTxate);
3009 /*printk("=============>tx_rate_reg:%x\n", ieee->softmac_stats.CurrentShowTxate);*/
3010 /* for initial tx rate */
3011 /*priv->stats.last_packet_rate = read_nic_byte(dev, INITIAL_TX_RATE_REG);*/
3012 read_nic_byte(dev, INITIAL_TX_RATE_REG, &ieee->softmac_stats.last_packet_rate);
3013 /* for tx tx retry count */
3014 /*priv->stats.txretrycount = read_nic_dword(dev, TX_RETRY_COUNT_REG);*/
3015 read_nic_dword(dev, TX_RETRY_COUNT_REG, &ieee->softmac_stats.txretrycount);
3016 }
3017
dm_send_rssi_tofw(struct net_device * dev)3018 static void dm_send_rssi_tofw(struct net_device *dev)
3019 {
3020 struct r8192_priv *priv = ieee80211_priv(dev);
3021
3022 /* If we test chariot, we should stop the TX command ?
3023 * Because 92E will always silent reset when we send tx command. We use register
3024 * 0x1e0(byte) to notify driver.
3025 */
3026 write_nic_byte(dev, DRIVER_RSSI, (u8)priv->undecorated_smoothed_pwdb);
3027 }
3028
3029 /*---------------------------Define function prototype------------------------*/
3030
