1/* 2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public 20 * License along with this file; if not, write to the Free 21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 22 * MA 02110-1301 USA 23 * 24 * Or, alternatively, 25 * 26 * b) Permission is hereby granted, free of charge, to any person 27 * obtaining a copy of this software and associated documentation 28 * files (the "Software"), to deal in the Software without 29 * restriction, including without limitation the rights to use, 30 * copy, modify, merge, publish, distribute, sublicense, and/or 31 * sell copies of the Software, and to permit persons to whom the 32 * Software is furnished to do so, subject to the following 33 * conditions: 34 * 35 * The above copyright notice and this permission notice shall be 36 * included in all copies or substantial portions of the Software. 37 * 38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 45 * OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48#include <dt-bindings/interrupt-controller/arm-gic.h> 49#include <dt-bindings/thermal/thermal.h> 50 51/ { 52 #address-cells = <2>; 53 #size-cells = <2>; 54 compatible = "fsl,ls1021a"; 55 interrupt-parent = <&gic>; 56 57 aliases { 58 crypto = &crypto; 59 ethernet0 = &enet0; 60 ethernet1 = &enet1; 61 ethernet2 = &enet2; 62 rtc1 = &ftm_alarm0; 63 serial0 = &lpuart0; 64 serial1 = &lpuart1; 65 serial2 = &lpuart2; 66 serial3 = &lpuart3; 67 serial4 = &lpuart4; 68 serial5 = &lpuart5; 69 sysclk = &sysclk; 70 }; 71 72 cpus { 73 #address-cells = <1>; 74 #size-cells = <0>; 75 76 cpu0: cpu@f00 { 77 compatible = "arm,cortex-a7"; 78 device_type = "cpu"; 79 reg = <0xf00>; 80 clocks = <&clockgen 1 0>; 81 #cooling-cells = <2>; 82 }; 83 84 cpu1: cpu@f01 { 85 compatible = "arm,cortex-a7"; 86 device_type = "cpu"; 87 reg = <0xf01>; 88 clocks = <&clockgen 1 0>; 89 #cooling-cells = <2>; 90 }; 91 }; 92 93 memory { 94 device_type = "memory"; 95 reg = <0x0 0x0 0x0 0x0>; 96 }; 97 98 sysclk: sysclk { 99 compatible = "fixed-clock"; 100 #clock-cells = <0>; 101 clock-frequency = <100000000>; 102 clock-output-names = "sysclk"; 103 }; 104 105 timer { 106 compatible = "arm,armv7-timer"; 107 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 108 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 109 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 110 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 111 }; 112 113 pmu { 114 compatible = "arm,cortex-a7-pmu"; 115 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 117 interrupt-affinity = <&cpu0>, <&cpu1>; 118 }; 119 120 reboot { 121 compatible = "syscon-reboot"; 122 regmap = <&dcfg>; 123 offset = <0xb0>; 124 mask = <0x02>; 125 }; 126 127 soc { 128 compatible = "simple-bus"; 129 #address-cells = <2>; 130 #size-cells = <2>; 131 device_type = "soc"; 132 interrupt-parent = <&gic>; 133 ranges; 134 135 ddr: memory-controller@1080000 { 136 compatible = "fsl,qoriq-memory-controller"; 137 reg = <0x0 0x1080000 0x0 0x1000>; 138 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 139 big-endian; 140 }; 141 142 gic: interrupt-controller@1400000 { 143 compatible = "arm,gic-400", "arm,cortex-a7-gic"; 144 #interrupt-cells = <3>; 145 interrupt-controller; 146 reg = <0x0 0x1401000 0x0 0x1000>, 147 <0x0 0x1402000 0x0 0x2000>, 148 <0x0 0x1404000 0x0 0x2000>, 149 <0x0 0x1406000 0x0 0x2000>; 150 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 151 152 }; 153 154 msi1: msi-controller@1570e00 { 155 compatible = "fsl,ls1021a-msi"; 156 reg = <0x0 0x1570e00 0x0 0x8>; 157 msi-controller; 158 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 159 }; 160 161 msi2: msi-controller@1570e08 { 162 compatible = "fsl,ls1021a-msi"; 163 reg = <0x0 0x1570e08 0x0 0x8>; 164 msi-controller; 165 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 166 }; 167 168 ifc: ifc@1530000 { 169 compatible = "fsl,ifc", "simple-bus"; 170 reg = <0x0 0x1530000 0x0 0x10000>; 171 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 172 }; 173 174 dcfg: dcfg@1ee0000 { 175 compatible = "fsl,ls1021a-dcfg", "syscon"; 176 reg = <0x0 0x1ee0000 0x0 0x10000>; 177 big-endian; 178 }; 179 180 qspi: spi@1550000 { 181 compatible = "fsl,ls1021a-qspi"; 182 #address-cells = <1>; 183 #size-cells = <0>; 184 reg = <0x0 0x1550000 0x0 0x10000>, 185 <0x0 0x40000000 0x0 0x20000000>; 186 reg-names = "QuadSPI", "QuadSPI-memory"; 187 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 188 clock-names = "qspi_en", "qspi"; 189 clocks = <&clockgen 4 1>, <&clockgen 4 1>; 190 status = "disabled"; 191 }; 192 193 esdhc: esdhc@1560000 { 194 compatible = "fsl,ls1021a-esdhc", "fsl,esdhc"; 195 reg = <0x0 0x1560000 0x0 0x10000>; 196 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 197 clock-frequency = <0>; 198 voltage-ranges = <1800 1800 3300 3300>; 199 sdhci,auto-cmd12; 200 big-endian; 201 bus-width = <4>; 202 status = "disabled"; 203 }; 204 205 sata: sata@3200000 { 206 compatible = "fsl,ls1021a-ahci"; 207 reg = <0x0 0x3200000 0x0 0x10000>, 208 <0x0 0x20220520 0x0 0x4>; 209 reg-names = "ahci", "sata-ecc"; 210 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&clockgen 4 1>; 212 dma-coherent; 213 status = "disabled"; 214 }; 215 216 scfg: scfg@1570000 { 217 compatible = "fsl,ls1021a-scfg", "syscon"; 218 reg = <0x0 0x1570000 0x0 0x10000>; 219 big-endian; 220 #address-cells = <1>; 221 #size-cells = <1>; 222 ranges = <0x0 0x0 0x1570000 0x10000>; 223 224 extirq: interrupt-controller@1ac { 225 compatible = "fsl,ls1021a-extirq"; 226 #interrupt-cells = <2>; 227 #address-cells = <0>; 228 interrupt-controller; 229 reg = <0x1ac 4>; 230 interrupt-map = 231 <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 232 <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 233 <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 234 <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 235 <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 236 <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 237 interrupt-map-mask = <0xffffffff 0x0>; 238 }; 239 }; 240 241 crypto: crypto@1700000 { 242 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 243 fsl,sec-era = <7>; 244 #address-cells = <1>; 245 #size-cells = <1>; 246 reg = <0x0 0x1700000 0x0 0x100000>; 247 ranges = <0x0 0x0 0x1700000 0x100000>; 248 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 249 250 sec_jr0: jr@10000 { 251 compatible = "fsl,sec-v5.0-job-ring", 252 "fsl,sec-v4.0-job-ring"; 253 reg = <0x10000 0x10000>; 254 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 255 }; 256 257 sec_jr1: jr@20000 { 258 compatible = "fsl,sec-v5.0-job-ring", 259 "fsl,sec-v4.0-job-ring"; 260 reg = <0x20000 0x10000>; 261 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 262 }; 263 264 sec_jr2: jr@30000 { 265 compatible = "fsl,sec-v5.0-job-ring", 266 "fsl,sec-v4.0-job-ring"; 267 reg = <0x30000 0x10000>; 268 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 269 }; 270 271 sec_jr3: jr@40000 { 272 compatible = "fsl,sec-v5.0-job-ring", 273 "fsl,sec-v4.0-job-ring"; 274 reg = <0x40000 0x10000>; 275 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 276 }; 277 278 }; 279 280 clockgen: clocking@1ee1000 { 281 compatible = "fsl,ls1021a-clockgen"; 282 reg = <0x0 0x1ee1000 0x0 0x1000>; 283 #clock-cells = <2>; 284 clocks = <&sysclk>; 285 }; 286 287 tmu: tmu@1f00000 { 288 compatible = "fsl,qoriq-tmu"; 289 reg = <0x0 0x1f00000 0x0 0x10000>; 290 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 291 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>; 292 fsl,tmu-calibration = <0x00000000 0x0000000f 293 0x00000001 0x00000017 294 0x00000002 0x0000001e 295 0x00000003 0x00000026 296 0x00000004 0x0000002e 297 0x00000005 0x00000035 298 0x00000006 0x0000003d 299 0x00000007 0x00000044 300 0x00000008 0x0000004c 301 0x00000009 0x00000053 302 0x0000000a 0x0000005b 303 0x0000000b 0x00000064 304 305 0x00010000 0x00000011 306 0x00010001 0x0000001c 307 0x00010002 0x00000024 308 0x00010003 0x0000002b 309 0x00010004 0x00000034 310 0x00010005 0x00000039 311 0x00010006 0x00000042 312 0x00010007 0x0000004c 313 0x00010008 0x00000051 314 0x00010009 0x0000005a 315 0x0001000a 0x00000063 316 317 0x00020000 0x00000013 318 0x00020001 0x00000019 319 0x00020002 0x00000024 320 0x00020003 0x0000002c 321 0x00020004 0x00000035 322 0x00020005 0x0000003d 323 0x00020006 0x00000046 324 0x00020007 0x00000050 325 0x00020008 0x00000059 326 327 0x00030000 0x00000002 328 0x00030001 0x0000000d 329 0x00030002 0x00000019 330 0x00030003 0x00000024>; 331 #thermal-sensor-cells = <1>; 332 }; 333 334 thermal-zones { 335 cpu_thermal: cpu-thermal { 336 polling-delay-passive = <1000>; 337 polling-delay = <5000>; 338 339 thermal-sensors = <&tmu 0>; 340 341 trips { 342 cpu_alert: cpu-alert { 343 temperature = <85000>; 344 hysteresis = <2000>; 345 type = "passive"; 346 }; 347 cpu_crit: cpu-crit { 348 temperature = <95000>; 349 hysteresis = <2000>; 350 type = "critical"; 351 }; 352 }; 353 354 cooling-maps { 355 map0 { 356 trip = <&cpu_alert>; 357 cooling-device = 358 <&cpu0 THERMAL_NO_LIMIT 359 THERMAL_NO_LIMIT>, 360 <&cpu1 THERMAL_NO_LIMIT 361 THERMAL_NO_LIMIT>; 362 }; 363 }; 364 }; 365 }; 366 367 dspi0: spi@2100000 { 368 compatible = "fsl,ls1021a-v1.0-dspi"; 369 #address-cells = <1>; 370 #size-cells = <0>; 371 reg = <0x0 0x2100000 0x0 0x10000>; 372 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 373 clock-names = "dspi"; 374 clocks = <&clockgen 4 1>; 375 spi-num-chipselects = <6>; 376 big-endian; 377 status = "disabled"; 378 }; 379 380 dspi1: spi@2110000 { 381 compatible = "fsl,ls1021a-v1.0-dspi"; 382 #address-cells = <1>; 383 #size-cells = <0>; 384 reg = <0x0 0x2110000 0x0 0x10000>; 385 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 386 clock-names = "dspi"; 387 clocks = <&clockgen 4 1>; 388 spi-num-chipselects = <6>; 389 big-endian; 390 status = "disabled"; 391 }; 392 393 i2c0: i2c@2180000 { 394 compatible = "fsl,vf610-i2c"; 395 #address-cells = <1>; 396 #size-cells = <0>; 397 reg = <0x0 0x2180000 0x0 0x10000>; 398 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 399 clock-names = "i2c"; 400 clocks = <&clockgen 4 1>; 401 dma-names = "tx", "rx"; 402 dmas = <&edma0 1 39>, <&edma0 1 38>; 403 status = "disabled"; 404 }; 405 406 i2c1: i2c@2190000 { 407 compatible = "fsl,vf610-i2c"; 408 #address-cells = <1>; 409 #size-cells = <0>; 410 reg = <0x0 0x2190000 0x0 0x10000>; 411 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 412 clock-names = "i2c"; 413 clocks = <&clockgen 4 1>; 414 dma-names = "tx", "rx"; 415 dmas = <&edma0 1 37>, <&edma0 1 36>; 416 status = "disabled"; 417 }; 418 419 i2c2: i2c@21a0000 { 420 compatible = "fsl,vf610-i2c"; 421 #address-cells = <1>; 422 #size-cells = <0>; 423 reg = <0x0 0x21a0000 0x0 0x10000>; 424 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 425 clock-names = "i2c"; 426 clocks = <&clockgen 4 1>; 427 dma-names = "tx", "rx"; 428 dmas = <&edma0 1 35>, <&edma0 1 34>; 429 status = "disabled"; 430 }; 431 432 uart0: serial@21c0500 { 433 compatible = "fsl,16550-FIFO64", "ns16550a"; 434 reg = <0x0 0x21c0500 0x0 0x100>; 435 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 436 clock-frequency = <0>; 437 fifo-size = <15>; 438 status = "disabled"; 439 }; 440 441 uart1: serial@21c0600 { 442 compatible = "fsl,16550-FIFO64", "ns16550a"; 443 reg = <0x0 0x21c0600 0x0 0x100>; 444 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 445 clock-frequency = <0>; 446 fifo-size = <15>; 447 status = "disabled"; 448 }; 449 450 uart2: serial@21d0500 { 451 compatible = "fsl,16550-FIFO64", "ns16550a"; 452 reg = <0x0 0x21d0500 0x0 0x100>; 453 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 454 clock-frequency = <0>; 455 fifo-size = <15>; 456 status = "disabled"; 457 }; 458 459 uart3: serial@21d0600 { 460 compatible = "fsl,16550-FIFO64", "ns16550a"; 461 reg = <0x0 0x21d0600 0x0 0x100>; 462 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 463 clock-frequency = <0>; 464 fifo-size = <15>; 465 status = "disabled"; 466 }; 467 468 counter0: counter@29d0000 { 469 compatible = "fsl,ftm-quaddec"; 470 reg = <0x0 0x29d0000 0x0 0x10000>; 471 big-endian; 472 status = "disabled"; 473 }; 474 475 counter1: counter@29e0000 { 476 compatible = "fsl,ftm-quaddec"; 477 reg = <0x0 0x29e0000 0x0 0x10000>; 478 big-endian; 479 status = "disabled"; 480 }; 481 482 counter2: counter@29f0000 { 483 compatible = "fsl,ftm-quaddec"; 484 reg = <0x0 0x29f0000 0x0 0x10000>; 485 big-endian; 486 status = "disabled"; 487 }; 488 489 counter3: counter@2a00000 { 490 compatible = "fsl,ftm-quaddec"; 491 reg = <0x0 0x2a00000 0x0 0x10000>; 492 big-endian; 493 status = "disabled"; 494 }; 495 496 gpio0: gpio@2300000 { 497 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 498 reg = <0x0 0x2300000 0x0 0x10000>; 499 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 500 gpio-controller; 501 #gpio-cells = <2>; 502 interrupt-controller; 503 #interrupt-cells = <2>; 504 }; 505 506 gpio1: gpio@2310000 { 507 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 508 reg = <0x0 0x2310000 0x0 0x10000>; 509 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 510 gpio-controller; 511 #gpio-cells = <2>; 512 interrupt-controller; 513 #interrupt-cells = <2>; 514 }; 515 516 gpio2: gpio@2320000 { 517 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 518 reg = <0x0 0x2320000 0x0 0x10000>; 519 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 520 gpio-controller; 521 #gpio-cells = <2>; 522 interrupt-controller; 523 #interrupt-cells = <2>; 524 }; 525 526 gpio3: gpio@2330000 { 527 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 528 reg = <0x0 0x2330000 0x0 0x10000>; 529 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 530 gpio-controller; 531 #gpio-cells = <2>; 532 interrupt-controller; 533 #interrupt-cells = <2>; 534 }; 535 536 lpuart0: serial@2950000 { 537 compatible = "fsl,ls1021a-lpuart"; 538 reg = <0x0 0x2950000 0x0 0x1000>; 539 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&sysclk>; 541 clock-names = "ipg"; 542 status = "disabled"; 543 }; 544 545 lpuart1: serial@2960000 { 546 compatible = "fsl,ls1021a-lpuart"; 547 reg = <0x0 0x2960000 0x0 0x1000>; 548 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 549 clocks = <&clockgen 4 1>; 550 clock-names = "ipg"; 551 status = "disabled"; 552 }; 553 554 lpuart2: serial@2970000 { 555 compatible = "fsl,ls1021a-lpuart"; 556 reg = <0x0 0x2970000 0x0 0x1000>; 557 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 558 clocks = <&clockgen 4 1>; 559 clock-names = "ipg"; 560 status = "disabled"; 561 }; 562 563 lpuart3: serial@2980000 { 564 compatible = "fsl,ls1021a-lpuart"; 565 reg = <0x0 0x2980000 0x0 0x1000>; 566 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 567 clocks = <&clockgen 4 1>; 568 clock-names = "ipg"; 569 status = "disabled"; 570 }; 571 572 lpuart4: serial@2990000 { 573 compatible = "fsl,ls1021a-lpuart"; 574 reg = <0x0 0x2990000 0x0 0x1000>; 575 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 576 clocks = <&clockgen 4 1>; 577 clock-names = "ipg"; 578 status = "disabled"; 579 }; 580 581 lpuart5: serial@29a0000 { 582 compatible = "fsl,ls1021a-lpuart"; 583 reg = <0x0 0x29a0000 0x0 0x1000>; 584 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&clockgen 4 1>; 586 clock-names = "ipg"; 587 status = "disabled"; 588 }; 589 590 pwm0: pwm@29d0000 { 591 compatible = "fsl,vf610-ftm-pwm"; 592 #pwm-cells = <3>; 593 reg = <0x0 0x29d0000 0x0 0x10000>; 594 clock-names = "ftm_sys", "ftm_ext", 595 "ftm_fix", "ftm_cnt_clk_en"; 596 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 597 <&clockgen 4 1>, <&clockgen 4 1>; 598 big-endian; 599 status = "disabled"; 600 }; 601 602 pwm1: pwm@29e0000 { 603 compatible = "fsl,vf610-ftm-pwm"; 604 #pwm-cells = <3>; 605 reg = <0x0 0x29e0000 0x0 0x10000>; 606 clock-names = "ftm_sys", "ftm_ext", 607 "ftm_fix", "ftm_cnt_clk_en"; 608 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 609 <&clockgen 4 1>, <&clockgen 4 1>; 610 big-endian; 611 status = "disabled"; 612 }; 613 614 pwm2: pwm@29f0000 { 615 compatible = "fsl,vf610-ftm-pwm"; 616 #pwm-cells = <3>; 617 reg = <0x0 0x29f0000 0x0 0x10000>; 618 clock-names = "ftm_sys", "ftm_ext", 619 "ftm_fix", "ftm_cnt_clk_en"; 620 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 621 <&clockgen 4 1>, <&clockgen 4 1>; 622 big-endian; 623 status = "disabled"; 624 }; 625 626 pwm3: pwm@2a00000 { 627 compatible = "fsl,vf610-ftm-pwm"; 628 #pwm-cells = <3>; 629 reg = <0x0 0x2a00000 0x0 0x10000>; 630 clock-names = "ftm_sys", "ftm_ext", 631 "ftm_fix", "ftm_cnt_clk_en"; 632 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 633 <&clockgen 4 1>, <&clockgen 4 1>; 634 big-endian; 635 status = "disabled"; 636 }; 637 638 pwm4: pwm@2a10000 { 639 compatible = "fsl,vf610-ftm-pwm"; 640 #pwm-cells = <3>; 641 reg = <0x0 0x2a10000 0x0 0x10000>; 642 clock-names = "ftm_sys", "ftm_ext", 643 "ftm_fix", "ftm_cnt_clk_en"; 644 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 645 <&clockgen 4 1>, <&clockgen 4 1>; 646 big-endian; 647 status = "disabled"; 648 }; 649 650 pwm5: pwm@2a20000 { 651 compatible = "fsl,vf610-ftm-pwm"; 652 #pwm-cells = <3>; 653 reg = <0x0 0x2a20000 0x0 0x10000>; 654 clock-names = "ftm_sys", "ftm_ext", 655 "ftm_fix", "ftm_cnt_clk_en"; 656 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 657 <&clockgen 4 1>, <&clockgen 4 1>; 658 big-endian; 659 status = "disabled"; 660 }; 661 662 pwm6: pwm@2a30000 { 663 compatible = "fsl,vf610-ftm-pwm"; 664 #pwm-cells = <3>; 665 reg = <0x0 0x2a30000 0x0 0x10000>; 666 clock-names = "ftm_sys", "ftm_ext", 667 "ftm_fix", "ftm_cnt_clk_en"; 668 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 669 <&clockgen 4 1>, <&clockgen 4 1>; 670 big-endian; 671 status = "disabled"; 672 }; 673 674 pwm7: pwm@2a40000 { 675 compatible = "fsl,vf610-ftm-pwm"; 676 #pwm-cells = <3>; 677 reg = <0x0 0x2a40000 0x0 0x10000>; 678 clock-names = "ftm_sys", "ftm_ext", 679 "ftm_fix", "ftm_cnt_clk_en"; 680 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 681 <&clockgen 4 1>, <&clockgen 4 1>; 682 big-endian; 683 status = "disabled"; 684 }; 685 686 wdog0: watchdog@2ad0000 { 687 compatible = "fsl,imx21-wdt"; 688 reg = <0x0 0x2ad0000 0x0 0x10000>; 689 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 690 clocks = <&clockgen 4 1>; 691 clock-names = "wdog-en"; 692 big-endian; 693 }; 694 695 sai1: sai@2b50000 { 696 #sound-dai-cells = <0>; 697 compatible = "fsl,vf610-sai"; 698 reg = <0x0 0x2b50000 0x0 0x10000>; 699 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 701 <&clockgen 4 1>, <&clockgen 4 1>; 702 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 703 dma-names = "tx", "rx"; 704 dmas = <&edma0 1 47>, 705 <&edma0 1 46>; 706 status = "disabled"; 707 }; 708 709 sai2: sai@2b60000 { 710 #sound-dai-cells = <0>; 711 compatible = "fsl,vf610-sai"; 712 reg = <0x0 0x2b60000 0x0 0x10000>; 713 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 715 <&clockgen 4 1>, <&clockgen 4 1>; 716 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 717 dma-names = "tx", "rx"; 718 dmas = <&edma0 1 45>, 719 <&edma0 1 44>; 720 status = "disabled"; 721 }; 722 723 edma0: edma@2c00000 { 724 #dma-cells = <2>; 725 compatible = "fsl,vf610-edma"; 726 reg = <0x0 0x2c00000 0x0 0x10000>, 727 <0x0 0x2c10000 0x0 0x10000>, 728 <0x0 0x2c20000 0x0 0x10000>; 729 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 731 interrupt-names = "edma-tx", "edma-err"; 732 dma-channels = <32>; 733 big-endian; 734 clock-names = "dmamux0", "dmamux1"; 735 clocks = <&clockgen 4 1>, 736 <&clockgen 4 1>; 737 }; 738 739 dcu: dcu@2ce0000 { 740 compatible = "fsl,ls1021a-dcu"; 741 reg = <0x0 0x2ce0000 0x0 0x10000>; 742 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 743 clocks = <&clockgen 4 0>, 744 <&clockgen 4 0>; 745 clock-names = "dcu", "pix"; 746 big-endian; 747 status = "disabled"; 748 }; 749 750 mdio0: mdio@2d24000 { 751 compatible = "gianfar"; 752 device_type = "mdio"; 753 #address-cells = <1>; 754 #size-cells = <0>; 755 reg = <0x0 0x2d24000 0x0 0x4000>, 756 <0x0 0x2d10030 0x0 0x4>; 757 }; 758 759 mdio1: mdio@2d64000 { 760 compatible = "gianfar"; 761 device_type = "mdio"; 762 #address-cells = <1>; 763 #size-cells = <0>; 764 reg = <0x0 0x2d64000 0x0 0x4000>, 765 <0x0 0x2d50030 0x0 0x4>; 766 }; 767 768 ptp_clock@2d10e00 { 769 compatible = "fsl,etsec-ptp"; 770 reg = <0x0 0x2d10e00 0x0 0xb0>; 771 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 772 fsl,tclk-period = <5>; 773 fsl,tmr-prsc = <2>; 774 fsl,tmr-add = <0xaaaaaaab>; 775 fsl,tmr-fiper1 = <999999995>; 776 fsl,tmr-fiper2 = <999999995>; 777 fsl,max-adj = <499999999>; 778 fsl,extts-fifo; 779 }; 780 781 enet0: ethernet@2d10000 { 782 compatible = "fsl,etsec2"; 783 device_type = "network"; 784 #address-cells = <2>; 785 #size-cells = <2>; 786 interrupt-parent = <&gic>; 787 model = "eTSEC"; 788 fsl,magic-packet; 789 ranges; 790 dma-coherent; 791 792 queue-group@2d10000 { 793 #address-cells = <2>; 794 #size-cells = <2>; 795 reg = <0x0 0x2d10000 0x0 0x1000>; 796 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 799 }; 800 801 queue-group@2d14000 { 802 #address-cells = <2>; 803 #size-cells = <2>; 804 reg = <0x0 0x2d14000 0x0 0x1000>; 805 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 806 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 808 }; 809 }; 810 811 enet1: ethernet@2d50000 { 812 compatible = "fsl,etsec2"; 813 device_type = "network"; 814 #address-cells = <2>; 815 #size-cells = <2>; 816 interrupt-parent = <&gic>; 817 model = "eTSEC"; 818 ranges; 819 dma-coherent; 820 821 queue-group@2d50000 { 822 #address-cells = <2>; 823 #size-cells = <2>; 824 reg = <0x0 0x2d50000 0x0 0x1000>; 825 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 826 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 828 }; 829 830 queue-group@2d54000 { 831 #address-cells = <2>; 832 #size-cells = <2>; 833 reg = <0x0 0x2d54000 0x0 0x1000>; 834 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 837 }; 838 }; 839 840 enet2: ethernet@2d90000 { 841 compatible = "fsl,etsec2"; 842 device_type = "network"; 843 #address-cells = <2>; 844 #size-cells = <2>; 845 interrupt-parent = <&gic>; 846 model = "eTSEC"; 847 ranges; 848 dma-coherent; 849 850 queue-group@2d90000 { 851 #address-cells = <2>; 852 #size-cells = <2>; 853 reg = <0x0 0x2d90000 0x0 0x1000>; 854 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 855 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 857 }; 858 859 queue-group@2d94000 { 860 #address-cells = <2>; 861 #size-cells = <2>; 862 reg = <0x0 0x2d94000 0x0 0x1000>; 863 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 864 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 866 }; 867 }; 868 869 usb2: usb@8600000 { 870 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; 871 reg = <0x0 0x8600000 0x0 0x1000>; 872 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 873 dr_mode = "host"; 874 phy_type = "ulpi"; 875 }; 876 877 usb3: usb3@3100000 { 878 compatible = "snps,dwc3"; 879 reg = <0x0 0x3100000 0x0 0x10000>; 880 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 881 dr_mode = "host"; 882 snps,quirk-frame-length-adjustment = <0x20>; 883 snps,dis_rxdet_inp3_quirk; 884 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 885 }; 886 887 pcie@3400000 { 888 compatible = "fsl,ls1021a-pcie"; 889 reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */ 890 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 891 reg-names = "regs", "config"; 892 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 893 fsl,pcie-scfg = <&scfg 0>; 894 #address-cells = <3>; 895 #size-cells = <2>; 896 device_type = "pci"; 897 num-viewport = <6>; 898 bus-range = <0x0 0xff>; 899 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 900 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 901 msi-parent = <&msi1>, <&msi2>; 902 #interrupt-cells = <1>; 903 interrupt-map-mask = <0 0 0 7>; 904 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 905 <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 906 <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 907 <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 908 status = "disabled"; 909 }; 910 911 pcie@3500000 { 912 compatible = "fsl,ls1021a-pcie"; 913 reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */ 914 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ 915 reg-names = "regs", "config"; 916 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 917 fsl,pcie-scfg = <&scfg 1>; 918 #address-cells = <3>; 919 #size-cells = <2>; 920 device_type = "pci"; 921 num-viewport = <6>; 922 bus-range = <0x0 0xff>; 923 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ 924 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 925 msi-parent = <&msi1>, <&msi2>; 926 #interrupt-cells = <1>; 927 interrupt-map-mask = <0 0 0 7>; 928 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 929 <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 930 <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 931 <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 932 status = "disabled"; 933 }; 934 935 can0: can@2a70000 { 936 compatible = "fsl,ls1021ar2-flexcan"; 937 reg = <0x0 0x2a70000 0x0 0x1000>; 938 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 939 clocks = <&clockgen 4 1>, <&clockgen 4 1>; 940 clock-names = "ipg", "per"; 941 big-endian; 942 }; 943 944 can1: can@2a80000 { 945 compatible = "fsl,ls1021ar2-flexcan"; 946 reg = <0x0 0x2a80000 0x0 0x1000>; 947 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 948 clocks = <&clockgen 4 1>, <&clockgen 4 1>; 949 clock-names = "ipg", "per"; 950 big-endian; 951 }; 952 953 can2: can@2a90000 { 954 compatible = "fsl,ls1021ar2-flexcan"; 955 reg = <0x0 0x2a90000 0x0 0x1000>; 956 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 957 clocks = <&clockgen 4 1>, <&clockgen 4 1>; 958 clock-names = "ipg", "per"; 959 big-endian; 960 }; 961 962 can3: can@2aa0000 { 963 compatible = "fsl,ls1021ar2-flexcan"; 964 reg = <0x0 0x2aa0000 0x0 0x1000>; 965 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 966 clocks = <&clockgen 4 1>, <&clockgen 4 1>; 967 clock-names = "ipg", "per"; 968 big-endian; 969 }; 970 971 ocram1: sram@10000000 { 972 compatible = "mmio-sram"; 973 reg = <0x0 0x10000000 0x0 0x10000>; 974 #address-cells = <1>; 975 #size-cells = <1>; 976 ranges = <0x0 0x0 0x10000000 0x10000>; 977 }; 978 979 ocram2: sram@10010000 { 980 compatible = "mmio-sram"; 981 reg = <0x0 0x10010000 0x0 0x10000>; 982 #address-cells = <1>; 983 #size-cells = <1>; 984 ranges = <0x0 0x0 0x10010000 0x10000>; 985 }; 986 987 qdma: dma-controller@8390000 { 988 compatible = "fsl,ls1021a-qdma"; 989 reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */ 990 <0x0 0x8389000 0x0 0x1000>, /* Status regs */ 991 <0x0 0x838a000 0x0 0x2000>; /* Block regs */ 992 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 995 interrupt-names = "qdma-error", 996 "qdma-queue0", "qdma-queue1"; 997 dma-channels = <8>; 998 block-number = <1>; 999 block-offset = <0x1000>; 1000 fsl,dma-queues = <2>; 1001 status-sizes = <64>; 1002 queue-sizes = <64 64>; 1003 big-endian; 1004 }; 1005 1006 rcpm: power-controller@1ee2140 { 1007 compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1008 reg = <0x0 0x1ee2140 0x0 0x8>; 1009 #fsl,rcpm-wakeup-cells = <2>; 1010 }; 1011 1012 ftm_alarm0: timer0@29d0000 { 1013 compatible = "fsl,ls1021a-ftm-alarm"; 1014 reg = <0x0 0x29d0000 0x0 0x10000>; 1015 reg-names = "ftm"; 1016 fsl,rcpm-wakeup = <&rcpm 0x20000 0x0>; 1017 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1018 big-endian; 1019 }; 1020 }; 1021}; 1022
