1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "dc_bios_types.h"
28 #include "dcn30/dcn30_dio_stream_encoder.h"
29 #include "dcn32_dio_stream_encoder.h"
30 #include "reg_helper.h"
31 #include "hw_shared.h"
32 #include "inc/link_dpcd.h"
33 #include "dpcd_defs.h"
34
35 #define DC_LOGGER \
36 enc1->base.ctx->logger
37
38 #define REG(reg)\
39 (enc1->regs->reg)
40
41 #undef FN
42 #define FN(reg_name, field_name) \
43 enc1->se_shift->field_name, enc1->se_mask->field_name
44
45 #define VBI_LINE_0 0
46 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
47
48 #define CTX \
49 enc1->base.ctx
50
51
52
enc32_dp_set_odm_combine(struct stream_encoder * enc,bool odm_combine)53 static void enc32_dp_set_odm_combine(
54 struct stream_encoder *enc,
55 bool odm_combine)
56 {
57 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
58
59 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_PER_CYCLE_PROCESSING_MODE, odm_combine ? 1 : 0);
60 }
61
62 /* setup stream encoder in dvi mode */
enc32_stream_encoder_dvi_set_stream_attribute(struct stream_encoder * enc,struct dc_crtc_timing * crtc_timing,bool is_dual_link)63 static void enc32_stream_encoder_dvi_set_stream_attribute(
64 struct stream_encoder *enc,
65 struct dc_crtc_timing *crtc_timing,
66 bool is_dual_link)
67 {
68 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
69
70 if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
71 struct bp_encoder_control cntl = {0};
72
73 cntl.action = ENCODER_CONTROL_SETUP;
74 cntl.engine_id = enc1->base.id;
75 cntl.signal = is_dual_link ?
76 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
77 cntl.enable_dp_audio = false;
78 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
79 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
80
81 if (enc1->base.bp->funcs->encoder_control(
82 enc1->base.bp, &cntl) != BP_RESULT_OK)
83 return;
84
85 } else {
86
87 //Set pattern for clock channel, default vlue 0x63 does not work
88 REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);
89
90 //DIG_BE_TMDS_DVI_MODE : TMDS-DVI mode is already set in link_encoder_setup
91
92 //DIG_SOURCE_SELECT is already set in dig_connect_to_otg
93
94 /* DIG_START is removed from the register spec */
95 }
96
97 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
98 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
99 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
100 }
101
102 /* setup stream encoder in hdmi mode */
enc32_stream_encoder_hdmi_set_stream_attribute(struct stream_encoder * enc,struct dc_crtc_timing * crtc_timing,int actual_pix_clk_khz,bool enable_audio)103 static void enc32_stream_encoder_hdmi_set_stream_attribute(
104 struct stream_encoder *enc,
105 struct dc_crtc_timing *crtc_timing,
106 int actual_pix_clk_khz,
107 bool enable_audio)
108 {
109 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
110
111 if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
112 struct bp_encoder_control cntl = {0};
113
114 cntl.action = ENCODER_CONTROL_SETUP;
115 cntl.engine_id = enc1->base.id;
116 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
117 cntl.enable_dp_audio = enable_audio;
118 cntl.pixel_clock = actual_pix_clk_khz;
119 cntl.lanes_number = LANE_COUNT_FOUR;
120
121 if (enc1->base.bp->funcs->encoder_control(
122 enc1->base.bp, &cntl) != BP_RESULT_OK)
123 return;
124
125 } else {
126
127 //Set pattern for clock channel, default vlue 0x63 does not work
128 REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);
129
130 //DIG_BE_TMDS_HDMI_MODE : TMDS-HDMI mode is already set in link_encoder_setup
131
132 //DIG_SOURCE_SELECT is already set in dig_connect_to_otg
133
134 /* DIG_START is removed from the register spec */
135 }
136
137 /* Configure pixel encoding */
138 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
139
140 /* setup HDMI engine */
141 REG_UPDATE_6(HDMI_CONTROL,
142 HDMI_PACKET_GEN_VERSION, 1,
143 HDMI_KEEPOUT_MODE, 1,
144 HDMI_DEEP_COLOR_ENABLE, 0,
145 HDMI_DATA_SCRAMBLE_EN, 0,
146 HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1,
147 HDMI_CLOCK_CHANNEL_RATE, 0);
148
149 /* Configure color depth */
150 switch (crtc_timing->display_color_depth) {
151 case COLOR_DEPTH_888:
152 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
153 break;
154 case COLOR_DEPTH_101010:
155 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
156 REG_UPDATE_2(HDMI_CONTROL,
157 HDMI_DEEP_COLOR_DEPTH, 1,
158 HDMI_DEEP_COLOR_ENABLE, 0);
159 } else {
160 REG_UPDATE_2(HDMI_CONTROL,
161 HDMI_DEEP_COLOR_DEPTH, 1,
162 HDMI_DEEP_COLOR_ENABLE, 1);
163 }
164 break;
165 case COLOR_DEPTH_121212:
166 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
167 REG_UPDATE_2(HDMI_CONTROL,
168 HDMI_DEEP_COLOR_DEPTH, 2,
169 HDMI_DEEP_COLOR_ENABLE, 0);
170 } else {
171 REG_UPDATE_2(HDMI_CONTROL,
172 HDMI_DEEP_COLOR_DEPTH, 2,
173 HDMI_DEEP_COLOR_ENABLE, 1);
174 }
175 break;
176 case COLOR_DEPTH_161616:
177 REG_UPDATE_2(HDMI_CONTROL,
178 HDMI_DEEP_COLOR_DEPTH, 3,
179 HDMI_DEEP_COLOR_ENABLE, 1);
180 break;
181 default:
182 break;
183 }
184
185 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
186 /* enable HDMI data scrambler
187 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
188 * Clock channel frequency is 1/4 of character rate.
189 */
190 REG_UPDATE_2(HDMI_CONTROL,
191 HDMI_DATA_SCRAMBLE_EN, 1,
192 HDMI_CLOCK_CHANNEL_RATE, 1);
193 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
194
195 /* TODO: New feature for DCE11, still need to implement */
196
197 /* enable HDMI data scrambler
198 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
199 * Clock channel frequency is the same
200 * as character rate
201 */
202 REG_UPDATE_2(HDMI_CONTROL,
203 HDMI_DATA_SCRAMBLE_EN, 1,
204 HDMI_CLOCK_CHANNEL_RATE, 0);
205 }
206
207
208 /* Enable transmission of General Control packet on every frame */
209 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
210 HDMI_GC_CONT, 1,
211 HDMI_GC_SEND, 1,
212 HDMI_NULL_SEND, 1);
213
214 #if defined(CONFIG_DRM_AMD_DC_HDCP)
215 /* Disable Audio Content Protection packet transmission */
216 REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);
217 #endif
218
219 /* following belongs to audio */
220 /* Enable Audio InfoFrame packet transmission. */
221 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
222
223 /* update double-buffered AUDIO_INFO registers immediately */
224 ASSERT(enc->afmt);
225 enc->afmt->funcs->audio_info_immediate_update(enc->afmt);
226
227 /* Select line number on which to send Audio InfoFrame packets */
228 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
229 VBI_LINE_0 + 2);
230
231 /* set HDMI GC AVMUTE */
232 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
233 }
234
235
236
is_two_pixels_per_containter(const struct dc_crtc_timing * timing)237 static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
238 {
239 bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
240
241 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
242 && !timing->dsc_cfg.ycbcr422_simple);
243 return two_pix;
244 }
245
is_h_timing_divisible_by_2(const struct dc_crtc_timing * timing)246 static bool is_h_timing_divisible_by_2(const struct dc_crtc_timing *timing)
247 {
248 /* math borrowed from function of same name in inc/resource
249 * checks if h_timing is divisible by 2
250 */
251
252 bool divisible = false;
253 uint16_t h_blank_start = 0;
254 uint16_t h_blank_end = 0;
255
256 if (timing) {
257 h_blank_start = timing->h_total - timing->h_front_porch;
258 h_blank_end = h_blank_start - timing->h_addressable;
259
260 /* HTOTAL, Hblank start/end, and Hsync start/end all must be
261 * divisible by 2 in order for the horizontal timing params
262 * to be considered divisible by 2. Hsync start is always 0.
263 */
264 divisible = (timing->h_total % 2 == 0) &&
265 (h_blank_start % 2 == 0) &&
266 (h_blank_end % 2 == 0) &&
267 (timing->h_sync_width % 2 == 0);
268 }
269 return divisible;
270 }
271
is_dp_dig_pixel_rate_div_policy(struct dc * dc,const struct dc_crtc_timing * timing)272 static bool is_dp_dig_pixel_rate_div_policy(struct dc *dc, const struct dc_crtc_timing *timing)
273 {
274 /* should be functionally the same as dcn32_is_dp_dig_pixel_rate_div_policy for DP encoders*/
275 return is_h_timing_divisible_by_2(timing) &&
276 dc->debug.enable_dp_dig_pixel_rate_div_policy;
277 }
278
enc32_stream_encoder_dp_unblank(struct dc_link * link,struct stream_encoder * enc,const struct encoder_unblank_param * param)279 static void enc32_stream_encoder_dp_unblank(
280 struct dc_link *link,
281 struct stream_encoder *enc,
282 const struct encoder_unblank_param *param)
283 {
284 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
285 struct dc *dc = enc->ctx->dc;
286
287 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
288 uint32_t n_vid = 0x8000;
289 uint32_t m_vid;
290 uint32_t n_multiply = 0;
291 uint64_t m_vid_l = n_vid;
292
293 /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */
294 if (is_two_pixels_per_containter(¶m->timing) || param->opp_cnt > 1
295 || is_dp_dig_pixel_rate_div_policy(dc, ¶m->timing)) {
296 /*this logic should be the same in get_pixel_clock_parameters() */
297 n_multiply = 1;
298 }
299 /* M / N = Fstream / Flink
300 * m_vid / n_vid = pixel rate / link rate
301 */
302
303 m_vid_l *= param->timing.pix_clk_100hz / 10;
304 m_vid_l = div_u64(m_vid_l,
305 param->link_settings.link_rate
306 * LINK_RATE_REF_FREQ_IN_KHZ);
307
308 m_vid = (uint32_t) m_vid_l;
309
310 /* enable auto measurement */
311
312 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
313
314 /* auto measurement need 1 full 0x8000 symbol cycle to kick in,
315 * therefore program initial value for Mvid and Nvid
316 */
317
318 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
319
320 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
321
322 REG_UPDATE_2(DP_VID_TIMING,
323 DP_VID_M_N_GEN_EN, 1,
324 DP_VID_N_MUL, n_multiply);
325 }
326
327 /* make sure stream is disabled before resetting steer fifo */
328 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false);
329 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000);
330
331 /* DIG_START is removed from the register spec */
332
333 /* switch DP encoder to CRTC data, but reset it the fifo first. It may happen
334 * that it overflows during mode transition, and sometimes doesn't recover.
335 */
336 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1);
337 udelay(10);
338
339 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
340
341 /* DIG Resync FIFO now needs to be explicitly enabled
342 */
343 // TODO: Confirm if we need to wait for DIG_SYMCLK_FE_ON
344 REG_WAIT(DIG_FE_CNTL, DIG_SYMCLK_FE_ON, 1, 10, 5000);
345
346 /* read start level = 0 will bring underflow / overflow and DIG_FIFO_ERROR = 1
347 * so set it to 1/2 full = 7 before reset as suggested by hardware team.
348 */
349 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7);
350
351 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 1);
352
353 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 1, 10, 5000);
354
355 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 0);
356
357 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 0, 10, 5000);
358
359 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1);
360
361 /* wait 100us for DIG/DP logic to prime
362 * (i.e. a few video lines)
363 */
364 udelay(100);
365
366 /* the hardware would start sending video at the start of the next DP
367 * frame (i.e. rising edge of the vblank).
368 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
369 * register has no effect on enable transition! HW always guarantees
370 * VID_STREAM enable at start of next frame, and this is not
371 * programmable
372 */
373
374 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
375
376 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM);
377 }
378
379 /* Set DSC-related configuration.
380 * dsc_mode: 0 disables DSC, other values enable DSC in specified format
381 * sc_bytes_per_pixel: DP_DSC_BYTES_PER_PIXEL removed in DCN32
382 * dsc_slice_width: DP_DSC_SLICE_WIDTH removed in DCN32
383 */
enc32_dp_set_dsc_config(struct stream_encoder * enc,enum optc_dsc_mode dsc_mode,uint32_t dsc_bytes_per_pixel,uint32_t dsc_slice_width)384 static void enc32_dp_set_dsc_config(struct stream_encoder *enc,
385 enum optc_dsc_mode dsc_mode,
386 uint32_t dsc_bytes_per_pixel,
387 uint32_t dsc_slice_width)
388 {
389 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
390
391 REG_UPDATE(DP_DSC_CNTL, DP_DSC_MODE, dsc_mode == OPTC_DSC_DISABLED ? 0 : 1);
392 }
393
394 /* this function read dsc related register fields to be logged later in dcn10_log_hw_state
395 * into a dcn_dsc_state struct.
396 */
enc32_read_state(struct stream_encoder * enc,struct enc_state * s)397 static void enc32_read_state(struct stream_encoder *enc, struct enc_state *s)
398 {
399 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
400
401 //if dsc is enabled, continue to read
402 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode);
403 if (s->dsc_mode) {
404 REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, &s->sec_gsp_pps_line_num);
405
406 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference);
407 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num);
408
409 REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, &s->sec_gsp_pps_enable);
410 REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable);
411 }
412 }
413
enc32_set_dig_input_mode(struct stream_encoder * enc,unsigned int pix_per_container)414 static void enc32_set_dig_input_mode(struct stream_encoder *enc, unsigned int pix_per_container)
415 {
416 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
417
418 /* The naming of this field is confusing, what it means is the output mode of otg, which
419 * is the input mode of the dig
420 */
421 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, pix_per_container == 2 ? 0x1 : 0x0);
422 }
423
424 static const struct stream_encoder_funcs dcn32_str_enc_funcs = {
425 .dp_set_odm_combine =
426 enc32_dp_set_odm_combine,
427 .dp_set_stream_attribute =
428 enc2_stream_encoder_dp_set_stream_attribute,
429 .hdmi_set_stream_attribute =
430 enc32_stream_encoder_hdmi_set_stream_attribute,
431 .dvi_set_stream_attribute =
432 enc32_stream_encoder_dvi_set_stream_attribute,
433 .set_throttled_vcp_size =
434 enc1_stream_encoder_set_throttled_vcp_size,
435 .update_hdmi_info_packets =
436 enc3_stream_encoder_update_hdmi_info_packets,
437 .stop_hdmi_info_packets =
438 enc3_stream_encoder_stop_hdmi_info_packets,
439 .update_dp_info_packets =
440 enc3_stream_encoder_update_dp_info_packets,
441 .stop_dp_info_packets =
442 enc1_stream_encoder_stop_dp_info_packets,
443 .dp_blank =
444 enc1_stream_encoder_dp_blank,
445 .dp_unblank =
446 enc32_stream_encoder_dp_unblank,
447 .audio_mute_control = enc3_audio_mute_control,
448
449 .dp_audio_setup = enc3_se_dp_audio_setup,
450 .dp_audio_enable = enc3_se_dp_audio_enable,
451 .dp_audio_disable = enc1_se_dp_audio_disable,
452
453 .hdmi_audio_setup = enc3_se_hdmi_audio_setup,
454 .hdmi_audio_disable = enc1_se_hdmi_audio_disable,
455 .setup_stereo_sync = enc1_setup_stereo_sync,
456 .set_avmute = enc1_stream_encoder_set_avmute,
457 .dig_connect_to_otg = enc1_dig_connect_to_otg,
458 .dig_source_otg = enc1_dig_source_otg,
459
460 .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format,
461
462 .enc_read_state = enc32_read_state,
463 .dp_set_dsc_config = enc32_dp_set_dsc_config,
464 .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet,
465 .set_dynamic_metadata = enc2_set_dynamic_metadata,
466 .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
467
468 .set_input_mode = enc32_set_dig_input_mode,
469 };
470
dcn32_dio_stream_encoder_construct(struct dcn10_stream_encoder * enc1,struct dc_context * ctx,struct dc_bios * bp,enum engine_id eng_id,struct vpg * vpg,struct afmt * afmt,const struct dcn10_stream_enc_registers * regs,const struct dcn10_stream_encoder_shift * se_shift,const struct dcn10_stream_encoder_mask * se_mask)471 void dcn32_dio_stream_encoder_construct(
472 struct dcn10_stream_encoder *enc1,
473 struct dc_context *ctx,
474 struct dc_bios *bp,
475 enum engine_id eng_id,
476 struct vpg *vpg,
477 struct afmt *afmt,
478 const struct dcn10_stream_enc_registers *regs,
479 const struct dcn10_stream_encoder_shift *se_shift,
480 const struct dcn10_stream_encoder_mask *se_mask)
481 {
482 enc1->base.funcs = &dcn32_str_enc_funcs;
483 enc1->base.ctx = ctx;
484 enc1->base.id = eng_id;
485 enc1->base.bp = bp;
486 enc1->base.vpg = vpg;
487 enc1->base.afmt = afmt;
488 enc1->regs = regs;
489 enc1->se_shift = se_shift;
490 enc1->se_mask = se_mask;
491 enc1->base.stream_enc_inst = vpg->inst;
492 }
493
494
