1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "reg_helper.h"
28
29 #include "core_types.h"
30 #include "link_encoder.h"
31 #include "dcn321_dio_link_encoder.h"
32 #include "dcn31/dcn31_dio_link_encoder.h"
33 #include "stream_encoder.h"
34 #include "i2caux_interface.h"
35 #include "dc_bios_types.h"
36
37 #include "gpio_service_interface.h"
38
39 #ifndef MIN
40 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
41 #endif
42
43 #define CTX \
44 enc10->base.ctx
45 #define DC_LOGGER \
46 enc10->base.ctx->logger
47
48 #define REG(reg)\
49 (enc10->link_regs->reg)
50
51 #undef FN
52 #define FN(reg_name, field_name) \
53 enc10->link_shift->field_name, enc10->link_mask->field_name
54
55 #define AUX_REG(reg)\
56 (enc10->aux_regs->reg)
57
58 #define AUX_REG_READ(reg_name) \
59 dm_read_reg(CTX, AUX_REG(reg_name))
60
61 #define AUX_REG_WRITE(reg_name, val) \
62 dm_write_reg(CTX, AUX_REG(reg_name), val)
63
64 static const struct link_encoder_funcs dcn321_link_enc_funcs = {
65 .read_state = link_enc2_read_state,
66 .validate_output_with_stream =
67 dcn30_link_encoder_validate_output_with_stream,
68 .hw_init = enc32_hw_init,
69 .setup = dcn10_link_encoder_setup,
70 .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
71 .enable_dp_output = dcn32_link_encoder_enable_dp_output,
72 .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
73 .disable_output = dcn10_link_encoder_disable_output,
74 .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
75 .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
76 .update_mst_stream_allocation_table =
77 dcn10_link_encoder_update_mst_stream_allocation_table,
78 .psr_program_dp_dphy_fast_training =
79 dcn10_psr_program_dp_dphy_fast_training,
80 .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
81 .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
82 .enable_hpd = dcn10_link_encoder_enable_hpd,
83 .disable_hpd = dcn10_link_encoder_disable_hpd,
84 .is_dig_enabled = dcn10_is_dig_enabled,
85 .destroy = dcn10_link_encoder_destroy,
86 .fec_set_enable = enc2_fec_set_enable,
87 .fec_set_ready = enc2_fec_set_ready,
88 .fec_is_active = enc2_fec_is_active,
89 .get_dig_frontend = dcn10_get_dig_frontend,
90 .get_dig_mode = dcn10_get_dig_mode,
91 .is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode,
92 .get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
93 .set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,
94 };
95
dcn321_link_encoder_construct(struct dcn20_link_encoder * enc20,const struct encoder_init_data * init_data,const struct encoder_feature_support * enc_features,const struct dcn10_link_enc_registers * link_regs,const struct dcn10_link_enc_aux_registers * aux_regs,const struct dcn10_link_enc_hpd_registers * hpd_regs,const struct dcn10_link_enc_shift * link_shift,const struct dcn10_link_enc_mask * link_mask)96 void dcn321_link_encoder_construct(
97 struct dcn20_link_encoder *enc20,
98 const struct encoder_init_data *init_data,
99 const struct encoder_feature_support *enc_features,
100 const struct dcn10_link_enc_registers *link_regs,
101 const struct dcn10_link_enc_aux_registers *aux_regs,
102 const struct dcn10_link_enc_hpd_registers *hpd_regs,
103 const struct dcn10_link_enc_shift *link_shift,
104 const struct dcn10_link_enc_mask *link_mask)
105 {
106 struct bp_connector_speed_cap_info bp_cap_info = {0};
107 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
108 enum bp_result result = BP_RESULT_OK;
109 struct dcn10_link_encoder *enc10 = &enc20->enc10;
110
111 enc10->base.funcs = &dcn321_link_enc_funcs;
112 enc10->base.ctx = init_data->ctx;
113 enc10->base.id = init_data->encoder;
114
115 enc10->base.hpd_source = init_data->hpd_source;
116 enc10->base.connector = init_data->connector;
117
118 if (enc10->base.connector.id == CONNECTOR_ID_USBC)
119 enc10->base.features.flags.bits.DP_IS_USB_C = 1;
120
121 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
122
123 enc10->base.features = *enc_features;
124
125 enc10->base.transmitter = init_data->transmitter;
126
127 /* set the flag to indicate whether driver poll the I2C data pin
128 * while doing the DP sink detect
129 */
130
131 /* if (dal_adapter_service_is_feature_supported(as,
132 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
133 enc10->base.features.flags.bits.
134 DP_SINK_DETECT_POLL_DATA_PIN = true;*/
135
136 enc10->base.output_signals =
137 SIGNAL_TYPE_DVI_SINGLE_LINK |
138 SIGNAL_TYPE_DVI_DUAL_LINK |
139 SIGNAL_TYPE_LVDS |
140 SIGNAL_TYPE_DISPLAY_PORT |
141 SIGNAL_TYPE_DISPLAY_PORT_MST |
142 SIGNAL_TYPE_EDP |
143 SIGNAL_TYPE_HDMI_TYPE_A;
144
145 enc10->link_regs = link_regs;
146 enc10->aux_regs = aux_regs;
147 enc10->hpd_regs = hpd_regs;
148 enc10->link_shift = link_shift;
149 enc10->link_mask = link_mask;
150
151 switch (enc10->base.transmitter) {
152 case TRANSMITTER_UNIPHY_A:
153 enc10->base.preferred_engine = ENGINE_ID_DIGA;
154 break;
155 case TRANSMITTER_UNIPHY_B:
156 enc10->base.preferred_engine = ENGINE_ID_DIGB;
157 break;
158 case TRANSMITTER_UNIPHY_C:
159 enc10->base.preferred_engine = ENGINE_ID_DIGC;
160 break;
161 case TRANSMITTER_UNIPHY_D:
162 enc10->base.preferred_engine = ENGINE_ID_DIGD;
163 break;
164 case TRANSMITTER_UNIPHY_E:
165 enc10->base.preferred_engine = ENGINE_ID_DIGE;
166 break;
167 default:
168 ASSERT_CRITICAL(false);
169 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
170 }
171
172 /* default to one to mirror Windows behavior */
173 enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
174
175 if (bp_funcs->get_connector_speed_cap_info)
176 result = bp_funcs->get_connector_speed_cap_info(enc10->base.ctx->dc_bios,
177 enc10->base.connector, &bp_cap_info);
178
179 /* Override features with DCE-specific values */
180 if (result == BP_RESULT_OK) {
181 enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
182 bp_cap_info.DP_HBR2_EN;
183 enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
184 bp_cap_info.DP_HBR3_EN;
185 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
186 enc10->base.features.flags.bits.IS_DP2_CAPABLE = 1;
187 enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN;
188 enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN;
189 enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN;
190 } else {
191 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
192 __func__,
193 result);
194 }
195 if (enc10->base.ctx->dc->debug.hdmi20_disable) {
196 enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
197 }
198 }
199
