1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "dm_services.h"
28 #include "dm_helpers.h"
29 #include "core_types.h"
30 #include "resource.h"
31 #include "dccg.h"
32 #include "dce/dce_hwseq.h"
33 #include "clk_mgr.h"
34 #include "reg_helper.h"
35 #include "abm.h"
36 #include "hubp.h"
37 #include "dchubbub.h"
38 #include "timing_generator.h"
39 #include "opp.h"
40 #include "ipp.h"
41 #include "mpc.h"
42 #include "mcif_wb.h"
43 #include "dc_dmub_srv.h"
44 #include "dcn31_hwseq.h"
45 #include "link_hwss.h"
46 #include "dpcd_defs.h"
47 #include "dce/dmub_outbox.h"
48 #include "link.h"
49 #include "dcn10/dcn10_hw_sequencer.h"
50 #include "inc/link_enc_cfg.h"
51 #include "dcn30/dcn30_vpg.h"
52 #include "dce/dce_i2c_hw.h"
53
54 #define DC_LOGGER_INIT(logger)
55
56 #define CTX \
57 hws->ctx
58 #define REG(reg)\
59 hws->regs->reg
60 #define DC_LOGGER \
61 dc->ctx->logger
62
63
64 #undef FN
65 #define FN(reg_name, field_name) \
66 hws->shifts->field_name, hws->masks->field_name
67
enable_memory_low_power(struct dc * dc)68 static void enable_memory_low_power(struct dc *dc)
69 {
70 struct dce_hwseq *hws = dc->hwseq;
71 int i;
72
73 if (dc->debug.enable_mem_low_power.bits.dmcu) {
74 // Force ERAM to shutdown if DMCU is not enabled
75 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {
76 REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3);
77 }
78 }
79
80 // Set default OPTC memory power states
81 if (dc->debug.enable_mem_low_power.bits.optc) {
82 // Shutdown when unassigned and light sleep in VBLANK
83 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
84 }
85
86 if (dc->debug.enable_mem_low_power.bits.vga) {
87 // Power down VGA memory
88 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
89 }
90
91 if (dc->debug.enable_mem_low_power.bits.mpc &&
92 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode)
93 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc);
94
95
96 if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerdown) {
97 // Power down VPGs
98 for (i = 0; i < dc->res_pool->stream_enc_count; i++)
99 dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg);
100 #if defined(CONFIG_DRM_AMD_DC_FP)
101 for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++)
102 dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->vpg);
103 #endif
104 }
105
106 }
107
dcn31_init_hw(struct dc * dc)108 void dcn31_init_hw(struct dc *dc)
109 {
110 struct abm **abms = dc->res_pool->multiple_abms;
111 struct dce_hwseq *hws = dc->hwseq;
112 struct dc_bios *dcb = dc->ctx->dc_bios;
113 struct resource_pool *res_pool = dc->res_pool;
114 uint32_t backlight = MAX_BACKLIGHT_LEVEL;
115 int i;
116
117 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
118 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
119
120 if (!dcb->funcs->is_accelerated_mode(dcb)) {
121 hws->funcs.bios_golden_init(dc);
122 if (hws->funcs.disable_vga)
123 hws->funcs.disable_vga(dc->hwseq);
124 }
125 // Initialize the dccg
126 if (res_pool->dccg->funcs->dccg_init)
127 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
128
129 enable_memory_low_power(dc);
130
131 if (dc->ctx->dc_bios->fw_info_valid) {
132 res_pool->ref_clocks.xtalin_clock_inKhz =
133 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
134
135 if (res_pool->dccg && res_pool->hubbub) {
136
137 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
138 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
139 &res_pool->ref_clocks.dccg_ref_clock_inKhz);
140
141 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
142 res_pool->ref_clocks.dccg_ref_clock_inKhz,
143 &res_pool->ref_clocks.dchub_ref_clock_inKhz);
144 } else {
145 // Not all ASICs have DCCG sw component
146 res_pool->ref_clocks.dccg_ref_clock_inKhz =
147 res_pool->ref_clocks.xtalin_clock_inKhz;
148 res_pool->ref_clocks.dchub_ref_clock_inKhz =
149 res_pool->ref_clocks.xtalin_clock_inKhz;
150 }
151 } else
152 ASSERT_CRITICAL(false);
153
154 for (i = 0; i < dc->link_count; i++) {
155 /* Power up AND update implementation according to the
156 * required signal (which may be different from the
157 * default signal on connector).
158 */
159 struct dc_link *link = dc->links[i];
160
161 if (link->ep_type != DISPLAY_ENDPOINT_PHY)
162 continue;
163
164 link->link_enc->funcs->hw_init(link->link_enc);
165
166 /* Check for enabled DIG to identify enabled display */
167 if (link->link_enc->funcs->is_dig_enabled &&
168 link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
169 link->link_status.link_active = true;
170 if (link->link_enc->funcs->fec_is_active &&
171 link->link_enc->funcs->fec_is_active(link->link_enc))
172 link->fec_state = dc_link_fec_enabled;
173 }
174 }
175
176 /* we want to turn off all dp displays before doing detection */
177 dc->link_srv->blank_all_dp_displays(dc);
178
179 if (hws->funcs.enable_power_gating_plane)
180 hws->funcs.enable_power_gating_plane(dc->hwseq, true);
181
182 /* If taking control over from VBIOS, we may want to optimize our first
183 * mode set, so we need to skip powering down pipes until we know which
184 * pipes we want to use.
185 * Otherwise, if taking control is not possible, we need to power
186 * everything down.
187 */
188 if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {
189
190 // we want to turn off edp displays if odm is enabled and no seamless boot
191 if (!dc->caps.seamless_odm) {
192 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
193 struct timing_generator *tg = dc->res_pool->timing_generators[i];
194 uint32_t num_opps, opp_id_src0, opp_id_src1;
195
196 num_opps = 1;
197 if (tg) {
198 if (tg->funcs->is_tg_enabled(tg) && tg->funcs->get_optc_source) {
199 tg->funcs->get_optc_source(tg, &num_opps,
200 &opp_id_src0, &opp_id_src1);
201 }
202 }
203
204 if (num_opps > 1) {
205 dc->link_srv->blank_all_edp_displays(dc);
206 break;
207 }
208 }
209 }
210
211 hws->funcs.init_pipes(dc, dc->current_state);
212 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
213 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
214 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
215 }
216
217 for (i = 0; i < res_pool->audio_count; i++) {
218 struct audio *audio = res_pool->audios[i];
219
220 audio->funcs->hw_init(audio);
221 }
222
223 for (i = 0; i < dc->link_count; i++) {
224 struct dc_link *link = dc->links[i];
225
226 if (link->panel_cntl)
227 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
228 }
229
230 for (i = 0; i < dc->res_pool->pipe_count; i++) {
231 if (abms[i] != NULL)
232 abms[i]->funcs->abm_init(abms[i], backlight);
233 }
234
235 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
236 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
237
238 // Set i2c to light sleep until engine is setup
239 if (dc->debug.enable_mem_low_power.bits.i2c)
240 REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1);
241
242 if (hws->funcs.setup_hpo_hw_control)
243 hws->funcs.setup_hpo_hw_control(hws, false);
244
245 if (!dc->debug.disable_clock_gate) {
246 /* enable all DCN clock gating */
247 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
248
249 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
250
251 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
252 }
253
254 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
255 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
256
257 if (dc->clk_mgr->funcs->notify_wm_ranges)
258 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
259
260 if (dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled)
261 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
262
263 if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
264 dc->res_pool->hubbub->funcs->force_pstate_change_control(
265 dc->res_pool->hubbub, false, false);
266 #if defined(CONFIG_DRM_AMD_DC_FP)
267 if (dc->res_pool->hubbub->funcs->init_crb)
268 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
269 #endif
270
271 // Get DMCUB capabilities
272 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);
273 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
274 dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch;
275 }
276
dcn31_dsc_pg_control(struct dce_hwseq * hws,unsigned int dsc_inst,bool power_on)277 void dcn31_dsc_pg_control(
278 struct dce_hwseq *hws,
279 unsigned int dsc_inst,
280 bool power_on)
281 {
282 uint32_t power_gate = power_on ? 0 : 1;
283 uint32_t pwr_status = power_on ? 0 : 2;
284 uint32_t org_ip_request_cntl = 0;
285
286 if (hws->ctx->dc->debug.disable_dsc_power_gate)
287 return;
288
289 if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc &&
290 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc &&
291 power_on)
292 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc(
293 hws->ctx->dc->res_pool->dccg, dsc_inst);
294
295 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
296 if (org_ip_request_cntl == 0)
297 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
298
299 switch (dsc_inst) {
300 case 0: /* DSC0 */
301 REG_UPDATE(DOMAIN16_PG_CONFIG,
302 DOMAIN_POWER_GATE, power_gate);
303
304 REG_WAIT(DOMAIN16_PG_STATUS,
305 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
306 1, 1000);
307 break;
308 case 1: /* DSC1 */
309 REG_UPDATE(DOMAIN17_PG_CONFIG,
310 DOMAIN_POWER_GATE, power_gate);
311
312 REG_WAIT(DOMAIN17_PG_STATUS,
313 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
314 1, 1000);
315 break;
316 case 2: /* DSC2 */
317 REG_UPDATE(DOMAIN18_PG_CONFIG,
318 DOMAIN_POWER_GATE, power_gate);
319
320 REG_WAIT(DOMAIN18_PG_STATUS,
321 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
322 1, 1000);
323 break;
324 default:
325 BREAK_TO_DEBUGGER();
326 break;
327 }
328
329 if (org_ip_request_cntl == 0)
330 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
331
332 if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) {
333 if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on)
334 hws->ctx->dc->res_pool->dccg->funcs->disable_dsc(
335 hws->ctx->dc->res_pool->dccg, dsc_inst);
336 }
337
338 }
339
340
dcn31_enable_power_gating_plane(struct dce_hwseq * hws,bool enable)341 void dcn31_enable_power_gating_plane(
342 struct dce_hwseq *hws,
343 bool enable)
344 {
345 bool force_on = true; /* disable power gating */
346 uint32_t org_ip_request_cntl = 0;
347
348 if (enable && !hws->ctx->dc->debug.disable_hubp_power_gate)
349 force_on = false;
350
351 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
352 if (org_ip_request_cntl == 0)
353 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
354 /* DCHUBP0/1/2/3/4/5 */
355 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
356 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
357 /* DPP0/1/2/3/4/5 */
358 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
359 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
360
361 force_on = true; /* disable power gating */
362 if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate)
363 force_on = false;
364
365 /* DCS0/1/2/3/4/5 */
366 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
367 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
368 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
369
370 if (org_ip_request_cntl == 0)
371 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
372 }
373
dcn31_update_info_frame(struct pipe_ctx * pipe_ctx)374 void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx)
375 {
376 bool is_hdmi_tmds;
377 bool is_dp;
378
379 ASSERT(pipe_ctx->stream);
380
381 if (pipe_ctx->stream_res.stream_enc == NULL)
382 return; /* this is not root pipe */
383
384 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
385 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
386
387 if (!is_hdmi_tmds && !is_dp)
388 return;
389
390 if (is_hdmi_tmds)
391 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
392 pipe_ctx->stream_res.stream_enc,
393 &pipe_ctx->stream_res.encoder_info_frame);
394 else if (pipe_ctx->stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
395 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets(
396 pipe_ctx->stream_res.hpo_dp_stream_enc,
397 &pipe_ctx->stream_res.encoder_info_frame);
398 return;
399 } else {
400 if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num)
401 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num(
402 pipe_ctx->stream_res.stream_enc,
403 &pipe_ctx->stream_res.encoder_info_frame);
404
405 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
406 pipe_ctx->stream_res.stream_enc,
407 &pipe_ctx->stream_res.encoder_info_frame);
408 }
409 }
dcn31_z10_save_init(struct dc * dc)410 void dcn31_z10_save_init(struct dc *dc)
411 {
412 union dmub_rb_cmd cmd;
413
414 memset(&cmd, 0, sizeof(cmd));
415 cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT;
416 cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT;
417
418 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
419 }
420
dcn31_z10_restore(const struct dc * dc)421 void dcn31_z10_restore(const struct dc *dc)
422 {
423 union dmub_rb_cmd cmd;
424
425 /*
426 * DMUB notifies whether restore is required.
427 * Optimization to avoid sending commands when not required.
428 */
429 if (!dc_dmub_srv_is_restore_required(dc->ctx->dmub_srv))
430 return;
431
432 memset(&cmd, 0, sizeof(cmd));
433 cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT;
434 cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_RESTORE;
435
436 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
437 }
438
dcn31_hubp_pg_control(struct dce_hwseq * hws,unsigned int hubp_inst,bool power_on)439 void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
440 {
441 uint32_t power_gate = power_on ? 0 : 1;
442 uint32_t pwr_status = power_on ? 0 : 2;
443 uint32_t org_ip_request_cntl;
444 if (hws->ctx->dc->debug.disable_hubp_power_gate)
445 return;
446
447 if (REG(DOMAIN0_PG_CONFIG) == 0)
448 return;
449 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
450 if (org_ip_request_cntl == 0)
451 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
452
453 switch (hubp_inst) {
454 case 0:
455 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
456 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
457 break;
458 case 1:
459 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
460 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
461 break;
462 case 2:
463 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
464 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
465 break;
466 case 3:
467 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
468 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
469 break;
470 default:
471 BREAK_TO_DEBUGGER();
472 break;
473 }
474 if (org_ip_request_cntl == 0)
475 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
476 }
477
dcn31_init_sys_ctx(struct dce_hwseq * hws,struct dc * dc,struct dc_phy_addr_space_config * pa_config)478 int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
479 {
480 struct dcn_hubbub_phys_addr_config config;
481
482 config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
483 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
484 config.system_aperture.fb_base = pa_config->system_aperture.fb_base;
485 config.system_aperture.agp_top = pa_config->system_aperture.agp_top;
486 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;
487 config.system_aperture.agp_base = pa_config->system_aperture.agp_base;
488 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
489 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
490
491 if (pa_config->gart_config.base_addr_is_mc_addr) {
492 /* Convert from MC address to offset into FB */
493 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr -
494 pa_config->system_aperture.fb_base +
495 pa_config->system_aperture.fb_offset;
496 } else
497 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
498
499 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
500 }
501
dcn31_reset_back_end_for_pipe(struct dc * dc,struct pipe_ctx * pipe_ctx,struct dc_state * context)502 static void dcn31_reset_back_end_for_pipe(
503 struct dc *dc,
504 struct pipe_ctx *pipe_ctx,
505 struct dc_state *context)
506 {
507 struct dc_link *link;
508
509 DC_LOGGER_INIT(dc->ctx->logger);
510 if (pipe_ctx->stream_res.stream_enc == NULL) {
511 pipe_ctx->stream = NULL;
512 return;
513 }
514 ASSERT(!pipe_ctx->top_pipe);
515
516 dc->hwss.set_abm_immediate_disable(pipe_ctx);
517
518 pipe_ctx->stream_res.tg->funcs->set_dsc_config(
519 pipe_ctx->stream_res.tg,
520 OPTC_DSC_DISABLED, 0, 0);
521 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
522 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
523 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
524 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
525 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
526 pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 0;
527
528 if (pipe_ctx->stream_res.tg->funcs->set_drr)
529 pipe_ctx->stream_res.tg->funcs->set_drr(
530 pipe_ctx->stream_res.tg, NULL);
531
532 link = pipe_ctx->stream->link;
533 /* DPMS may already disable or */
534 /* dpms_off status is incorrect due to fastboot
535 * feature. When system resume from S4 with second
536 * screen only, the dpms_off would be true but
537 * VBIOS lit up eDP, so check link status too.
538 */
539 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)
540 dc->link_srv->set_dpms_off(pipe_ctx);
541 else if (pipe_ctx->stream_res.audio)
542 dc->hwss.disable_audio_stream(pipe_ctx);
543
544 /* free acquired resources */
545 if (pipe_ctx->stream_res.audio) {
546 /*disable az_endpoint*/
547 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
548
549 /*free audio*/
550 if (dc->caps.dynamic_audio == true) {
551 /*we have to dynamic arbitrate the audio endpoints*/
552 /*we free the resource, need reset is_audio_acquired*/
553 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
554 pipe_ctx->stream_res.audio, false);
555 pipe_ctx->stream_res.audio = NULL;
556 }
557 }
558
559 pipe_ctx->stream = NULL;
560 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
561 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
562 }
563
dcn31_reset_hw_ctx_wrap(struct dc * dc,struct dc_state * context)564 void dcn31_reset_hw_ctx_wrap(
565 struct dc *dc,
566 struct dc_state *context)
567 {
568 int i;
569 struct dce_hwseq *hws = dc->hwseq;
570
571 /* Reset Back End*/
572 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
573 struct pipe_ctx *pipe_ctx_old =
574 &dc->current_state->res_ctx.pipe_ctx[i];
575 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
576
577 if (!pipe_ctx_old->stream)
578 continue;
579
580 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
581 continue;
582
583 if (!pipe_ctx->stream ||
584 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
585 struct clock_source *old_clk = pipe_ctx_old->clock_source;
586
587 dcn31_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
588 if (hws->funcs.enable_stream_gating)
589 hws->funcs.enable_stream_gating(dc, pipe_ctx_old);
590 if (old_clk)
591 old_clk->funcs->cs_power_down(old_clk);
592 }
593 }
594
595 /* New dc_state in the process of being applied to hardware. */
596 link_enc_cfg_set_transient_mode(dc, dc->current_state, context);
597 }
598
dcn31_setup_hpo_hw_control(const struct dce_hwseq * hws,bool enable)599 void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable)
600 {
601 if (hws->ctx->dc->debug.hpo_optimization)
602 REG_UPDATE(HPO_TOP_HW_CONTROL, HPO_IO_EN, !!enable);
603 }
604
