1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27
28 #include "dccg.h"
29 #include "clk_mgr_internal.h"
30
31 // For dce12_get_dp_ref_freq_khz
32 #include "dce100/dce_clk_mgr.h"
33
34 // For dcn20_update_clocks_update_dpp_dto
35 #include "dcn20/dcn20_clk_mgr.h"
36
37
38
39 #include "dcn31_clk_mgr.h"
40
41 #include "reg_helper.h"
42 #include "core_types.h"
43 #include "dcn31_smu.h"
44 #include "dm_helpers.h"
45
46 /* TODO: remove this include once we ported over remaining clk mgr functions*/
47 #include "dcn30/dcn30_clk_mgr.h"
48
49 #include "dc_dmub_srv.h"
50
51 #include "yellow_carp_offset.h"
52
53 #define regCLK1_CLK_PLL_REQ 0x0237
54 #define regCLK1_CLK_PLL_REQ_BASE_IDX 0
55
56 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
57 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
58 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
59 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
60 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
61 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
62
63 #define REG(reg_name) \
64 (CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
65
66 #define TO_CLK_MGR_DCN31(clk_mgr)\
67 container_of(clk_mgr, struct clk_mgr_dcn31, base)
68
dcn31_get_active_display_cnt_wa(struct dc * dc,struct dc_state * context)69 int dcn31_get_active_display_cnt_wa(
70 struct dc *dc,
71 struct dc_state *context)
72 {
73 int i, display_count;
74 bool tmds_present = false;
75
76 display_count = 0;
77 for (i = 0; i < context->stream_count; i++) {
78 const struct dc_stream_state *stream = context->streams[i];
79
80 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
81 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
82 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
83 tmds_present = true;
84 }
85
86 for (i = 0; i < dc->link_count; i++) {
87 const struct dc_link *link = dc->links[i];
88
89 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
90 if (link->link_enc->funcs->is_dig_enabled &&
91 link->link_enc->funcs->is_dig_enabled(link->link_enc))
92 display_count++;
93 }
94
95 /* WA for hang on HDMI after display off back back on*/
96 if (display_count == 0 && tmds_present)
97 display_count = 1;
98
99 return display_count;
100 }
101
dcn31_disable_otg_wa(struct clk_mgr * clk_mgr_base,bool disable)102 static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
103 {
104 struct dc *dc = clk_mgr_base->ctx->dc;
105 int i;
106
107 for (i = 0; i < dc->res_pool->pipe_count; ++i) {
108 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
109
110 if (pipe->top_pipe || pipe->prev_odm_pipe)
111 continue;
112 if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) {
113 if (disable)
114 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
115 else
116 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
117 }
118 }
119 }
120
dcn31_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)121 static void dcn31_update_clocks(struct clk_mgr *clk_mgr_base,
122 struct dc_state *context,
123 bool safe_to_lower)
124 {
125 union dmub_rb_cmd cmd;
126 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
127 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
128 struct dc *dc = clk_mgr_base->ctx->dc;
129 int display_count;
130 bool update_dppclk = false;
131 bool update_dispclk = false;
132 bool dpp_clock_lowered = false;
133
134 if (dc->work_arounds.skip_clock_update)
135 return;
136
137 /*
138 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
139 * also if safe to lower is false, we just go in the higher state
140 */
141 if (safe_to_lower) {
142 if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_ALLOW &&
143 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
144 dcn31_smu_set_Z9_support(clk_mgr, true);
145 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
146 }
147
148 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) {
149 dcn31_smu_set_dtbclk(clk_mgr, false);
150 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
151 }
152 /* check that we're not already in lower */
153 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
154 display_count = dcn31_get_active_display_cnt_wa(dc, context);
155 /* if we can go lower, go lower */
156 if (display_count == 0) {
157 union display_idle_optimization_u idle_info = { 0 };
158 idle_info.idle_info.df_request_disabled = 1;
159 idle_info.idle_info.phy_ref_clk_off = 1;
160 dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
161 /* update power state */
162 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
163 }
164 }
165 } else {
166 if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_DISALLOW &&
167 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
168 dcn31_smu_set_Z9_support(clk_mgr, false);
169 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
170 }
171
172 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
173 dcn31_smu_set_dtbclk(clk_mgr, true);
174 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
175 }
176
177 /* check that we're not already in D0 */
178 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
179 union display_idle_optimization_u idle_info = { 0 };
180 dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
181 /* update power state */
182 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
183 }
184 }
185
186 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
187 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
188 dcn31_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
189 }
190
191 if (should_set_clock(safe_to_lower,
192 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
193 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
194 dcn31_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
195 }
196
197 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
198 if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
199 if (new_clocks->dppclk_khz < 100000)
200 new_clocks->dppclk_khz = 100000;
201 }
202
203 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
204 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
205 dpp_clock_lowered = true;
206 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
207 update_dppclk = true;
208 }
209
210 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
211 dcn31_disable_otg_wa(clk_mgr_base, true);
212
213 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
214 dcn31_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
215 dcn31_disable_otg_wa(clk_mgr_base, false);
216
217 update_dispclk = true;
218 }
219
220 /* TODO: add back DTO programming when DPPCLK restore is fixed in FSDL*/
221 if (dpp_clock_lowered) {
222 // increase per DPP DTO before lowering global dppclk
223 dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
224 } else {
225 // increase global DPPCLK before lowering per DPP DTO
226 if (update_dppclk || update_dispclk)
227 dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
228 }
229
230 // notify DMCUB of latest clocks
231 memset(&cmd, 0, sizeof(cmd));
232 cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
233 cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS;
234 cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
235 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =
236 clk_mgr_base->clks.dcfclk_deep_sleep_khz;
237 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
238 cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
239
240 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
241 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
242 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
243 }
244
get_vco_frequency_from_reg(struct clk_mgr_internal * clk_mgr)245 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
246 {
247 /* get FbMult value */
248 struct fixed31_32 pll_req;
249 unsigned int fbmult_frac_val = 0;
250 unsigned int fbmult_int_val = 0;
251
252 /*
253 * Register value of fbmult is in 8.16 format, we are converting to 31.32
254 * to leverage the fix point operations available in driver
255 */
256
257 REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
258 REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
259
260 pll_req = dc_fixpt_from_int(fbmult_int_val);
261
262 /*
263 * since fractional part is only 16 bit in register definition but is 32 bit
264 * in our fix point definiton, need to shift left by 16 to obtain correct value
265 */
266 pll_req.value |= fbmult_frac_val << 16;
267
268 /* multiply by REFCLK period */
269 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
270
271 /* integer part is now VCO frequency in kHz */
272 return dc_fixpt_floor(pll_req);
273 }
274
dcn31_enable_pme_wa(struct clk_mgr * clk_mgr_base)275 static void dcn31_enable_pme_wa(struct clk_mgr *clk_mgr_base)
276 {
277 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
278
279 dcn31_smu_enable_pme_wa(clk_mgr);
280 }
281
dcn31_init_clocks(struct clk_mgr * clk_mgr)282 static void dcn31_init_clocks(struct clk_mgr *clk_mgr)
283 {
284 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
285 // Assumption is that boot state always supports pstate
286 clk_mgr->clks.p_state_change_support = true;
287 clk_mgr->clks.prev_p_state_change_support = true;
288 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
289 clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;
290 }
291
dcn31_are_clock_states_equal(struct dc_clocks * a,struct dc_clocks * b)292 static bool dcn31_are_clock_states_equal(struct dc_clocks *a,
293 struct dc_clocks *b)
294 {
295 if (a->dispclk_khz != b->dispclk_khz)
296 return false;
297 else if (a->dppclk_khz != b->dppclk_khz)
298 return false;
299 else if (a->dcfclk_khz != b->dcfclk_khz)
300 return false;
301 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
302 return false;
303 else if (a->zstate_support != b->zstate_support)
304 return false;
305 else if (a->dtbclk_en != b->dtbclk_en)
306 return false;
307
308 return true;
309 }
310
dcn31_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr * clk_mgr_base,struct clk_log_info * log_info)311 static void dcn31_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
312 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
313 {
314 return;
315 }
316
317 static struct clk_bw_params dcn31_bw_params = {
318 .vram_type = Ddr4MemType,
319 .num_channels = 1,
320 .clk_table = {
321 .num_entries = 4,
322 },
323
324 };
325
326 static struct wm_table ddr4_wm_table = {
327 .entries = {
328 {
329 .wm_inst = WM_A,
330 .wm_type = WM_TYPE_PSTATE_CHG,
331 .pstate_latency_us = 11.72,
332 .sr_exit_time_us = 6.09,
333 .sr_enter_plus_exit_time_us = 7.14,
334 .valid = true,
335 },
336 {
337 .wm_inst = WM_B,
338 .wm_type = WM_TYPE_PSTATE_CHG,
339 .pstate_latency_us = 11.72,
340 .sr_exit_time_us = 10.12,
341 .sr_enter_plus_exit_time_us = 11.48,
342 .valid = true,
343 },
344 {
345 .wm_inst = WM_C,
346 .wm_type = WM_TYPE_PSTATE_CHG,
347 .pstate_latency_us = 11.72,
348 .sr_exit_time_us = 10.12,
349 .sr_enter_plus_exit_time_us = 11.48,
350 .valid = true,
351 },
352 {
353 .wm_inst = WM_D,
354 .wm_type = WM_TYPE_PSTATE_CHG,
355 .pstate_latency_us = 11.72,
356 .sr_exit_time_us = 10.12,
357 .sr_enter_plus_exit_time_us = 11.48,
358 .valid = true,
359 },
360 }
361 };
362
363 static struct wm_table lpddr5_wm_table = {
364 .entries = {
365 {
366 .wm_inst = WM_A,
367 .wm_type = WM_TYPE_PSTATE_CHG,
368 .pstate_latency_us = 11.65333,
369 .sr_exit_time_us = 11.5,
370 .sr_enter_plus_exit_time_us = 14.5,
371 .valid = true,
372 },
373 {
374 .wm_inst = WM_B,
375 .wm_type = WM_TYPE_PSTATE_CHG,
376 .pstate_latency_us = 11.65333,
377 .sr_exit_time_us = 11.5,
378 .sr_enter_plus_exit_time_us = 14.5,
379 .valid = true,
380 },
381 {
382 .wm_inst = WM_C,
383 .wm_type = WM_TYPE_PSTATE_CHG,
384 .pstate_latency_us = 11.65333,
385 .sr_exit_time_us = 11.5,
386 .sr_enter_plus_exit_time_us = 14.5,
387 .valid = true,
388 },
389 {
390 .wm_inst = WM_D,
391 .wm_type = WM_TYPE_PSTATE_CHG,
392 .pstate_latency_us = 11.65333,
393 .sr_exit_time_us = 11.5,
394 .sr_enter_plus_exit_time_us = 14.5,
395 .valid = true,
396 },
397 }
398 };
399
400 static DpmClocks_t dummy_clocks;
401
402 static struct dcn31_watermarks dummy_wms = { 0 };
403
dcn31_build_watermark_ranges(struct clk_bw_params * bw_params,struct dcn31_watermarks * table)404 static void dcn31_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn31_watermarks *table)
405 {
406 int i, num_valid_sets;
407
408 num_valid_sets = 0;
409
410 for (i = 0; i < WM_SET_COUNT; i++) {
411 /* skip empty entries, the smu array has no holes*/
412 if (!bw_params->wm_table.entries[i].valid)
413 continue;
414
415 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
416 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
417 /* We will not select WM based on fclk, so leave it as unconstrained */
418 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
419 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
420
421 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
422 if (i == 0)
423 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
424 else {
425 /* add 1 to make it non-overlapping with next lvl */
426 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
427 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
428 }
429 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
430 bw_params->clk_table.entries[i].dcfclk_mhz;
431
432 } else {
433 /* unconstrained for memory retraining */
434 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
435 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
436
437 /* Modify previous watermark range to cover up to max */
438 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
439 }
440 num_valid_sets++;
441 }
442
443 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
444
445 /* modify the min and max to make sure we cover the whole range*/
446 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
447 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
448 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
449 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
450
451 /* This is for writeback only, does not matter currently as no writeback support*/
452 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
453 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
454 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
455 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
456 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
457 }
458
dcn31_notify_wm_ranges(struct clk_mgr * clk_mgr_base)459 static void dcn31_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
460 {
461 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
462 struct clk_mgr_dcn31 *clk_mgr_dcn31 = TO_CLK_MGR_DCN31(clk_mgr);
463 struct dcn31_watermarks *table = clk_mgr_dcn31->smu_wm_set.wm_set;
464
465 if (!clk_mgr->smu_ver)
466 return;
467
468 if (!table || clk_mgr_dcn31->smu_wm_set.mc_address.quad_part == 0)
469 return;
470
471 memset(table, 0, sizeof(*table));
472
473 dcn31_build_watermark_ranges(clk_mgr_base->bw_params, table);
474
475 dcn31_smu_set_dram_addr_high(clk_mgr,
476 clk_mgr_dcn31->smu_wm_set.mc_address.high_part);
477 dcn31_smu_set_dram_addr_low(clk_mgr,
478 clk_mgr_dcn31->smu_wm_set.mc_address.low_part);
479 dcn31_smu_transfer_wm_table_dram_2_smu(clk_mgr);
480 }
481
dcn31_get_dpm_table_from_smu(struct clk_mgr_internal * clk_mgr,struct dcn31_smu_dpm_clks * smu_dpm_clks)482 static void dcn31_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
483 struct dcn31_smu_dpm_clks *smu_dpm_clks)
484 {
485 DpmClocks_t *table = smu_dpm_clks->dpm_clks;
486
487 if (!clk_mgr->smu_ver)
488 return;
489
490 if (!table || smu_dpm_clks->mc_address.quad_part == 0)
491 return;
492
493 memset(table, 0, sizeof(*table));
494
495 dcn31_smu_set_dram_addr_high(clk_mgr,
496 smu_dpm_clks->mc_address.high_part);
497 dcn31_smu_set_dram_addr_low(clk_mgr,
498 smu_dpm_clks->mc_address.low_part);
499 dcn31_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
500 }
501
find_max_clk_value(const uint32_t clocks[],uint32_t num_clocks)502 static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)
503 {
504 uint32_t max = 0;
505 int i;
506
507 for (i = 0; i < num_clocks; ++i) {
508 if (clocks[i] > max)
509 max = clocks[i];
510 }
511
512 return max;
513 }
514
find_clk_for_voltage(const DpmClocks_t * clock_table,const uint32_t clocks[],unsigned int voltage)515 static unsigned int find_clk_for_voltage(
516 const DpmClocks_t *clock_table,
517 const uint32_t clocks[],
518 unsigned int voltage)
519 {
520 int i;
521 int max_voltage = 0;
522 int clock = 0;
523
524 for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) {
525 if (clock_table->SocVoltage[i] == voltage) {
526 return clocks[i];
527 } else if (clock_table->SocVoltage[i] >= max_voltage &&
528 clock_table->SocVoltage[i] < voltage) {
529 max_voltage = clock_table->SocVoltage[i];
530 clock = clocks[i];
531 }
532 }
533
534 ASSERT(clock);
535 return clock;
536 }
537
dcn31_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal * clk_mgr,struct integrated_info * bios_info,const DpmClocks_t * clock_table)538 void dcn31_clk_mgr_helper_populate_bw_params(
539 struct clk_mgr_internal *clk_mgr,
540 struct integrated_info *bios_info,
541 const DpmClocks_t *clock_table)
542 {
543 int i, j;
544 struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
545 uint32_t max_dispclk = 0, max_dppclk = 0;
546
547 j = -1;
548
549 ASSERT(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL);
550
551 /* Find lowest DPM, FCLK is filled in reverse order*/
552
553 for (i = NUM_DF_PSTATE_LEVELS - 1; i >= 0; i--) {
554 if (clock_table->DfPstateTable[i].FClk != 0) {
555 j = i;
556 break;
557 }
558 }
559
560 if (j == -1) {
561 /* clock table is all 0s, just use our own hardcode */
562 ASSERT(0);
563 return;
564 }
565
566 bw_params->clk_table.num_entries = j + 1;
567
568 /* dispclk and dppclk can be max at any voltage, same number of levels for both */
569 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
570 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) {
571 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled);
572 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled);
573 } else {
574 ASSERT(0);
575 }
576
577 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
578 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk;
579 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk;
580 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage;
581 switch (clock_table->DfPstateTable[j].WckRatio) {
582 case WCK_RATIO_1_2:
583 bw_params->clk_table.entries[i].wck_ratio = 2;
584 break;
585 case WCK_RATIO_1_4:
586 bw_params->clk_table.entries[i].wck_ratio = 4;
587 break;
588 default:
589 bw_params->clk_table.entries[i].wck_ratio = 1;
590 }
591 bw_params->clk_table.entries[i].dcfclk_mhz = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage);
592 bw_params->clk_table.entries[i].socclk_mhz = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage);
593 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
594 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
595 }
596
597 bw_params->vram_type = bios_info->memory_type;
598 bw_params->num_channels = bios_info->ma_channel_number;
599
600 for (i = 0; i < WM_SET_COUNT; i++) {
601 bw_params->wm_table.entries[i].wm_inst = i;
602
603 if (i >= bw_params->clk_table.num_entries) {
604 bw_params->wm_table.entries[i].valid = false;
605 continue;
606 }
607
608 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
609 bw_params->wm_table.entries[i].valid = true;
610 }
611 }
612
613 static struct clk_mgr_funcs dcn31_funcs = {
614 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
615 .update_clocks = dcn31_update_clocks,
616 .init_clocks = dcn31_init_clocks,
617 .enable_pme_wa = dcn31_enable_pme_wa,
618 .are_clock_states_equal = dcn31_are_clock_states_equal,
619 .notify_wm_ranges = dcn31_notify_wm_ranges
620 };
621 extern struct clk_mgr_funcs dcn3_fpga_funcs;
622
dcn31_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_dcn31 * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)623 void dcn31_clk_mgr_construct(
624 struct dc_context *ctx,
625 struct clk_mgr_dcn31 *clk_mgr,
626 struct pp_smu_funcs *pp_smu,
627 struct dccg *dccg)
628 {
629 struct dcn31_smu_dpm_clks smu_dpm_clks = { 0 };
630
631 clk_mgr->base.base.ctx = ctx;
632 clk_mgr->base.base.funcs = &dcn31_funcs;
633
634 clk_mgr->base.pp_smu = pp_smu;
635
636 clk_mgr->base.dccg = dccg;
637 clk_mgr->base.dfs_bypass_disp_clk = 0;
638
639 clk_mgr->base.dprefclk_ss_percentage = 0;
640 clk_mgr->base.dprefclk_ss_divider = 1000;
641 clk_mgr->base.ss_on_dprefclk = false;
642 clk_mgr->base.dfs_ref_freq_khz = 48000;
643
644 clk_mgr->smu_wm_set.wm_set = (struct dcn31_watermarks *)dm_helpers_allocate_gpu_mem(
645 clk_mgr->base.base.ctx,
646 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
647 sizeof(struct dcn31_watermarks),
648 &clk_mgr->smu_wm_set.mc_address.quad_part);
649
650 if (clk_mgr->smu_wm_set.wm_set == 0) {
651 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
652 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
653 }
654 ASSERT(clk_mgr->smu_wm_set.wm_set);
655
656 smu_dpm_clks.dpm_clks = (DpmClocks_t *)dm_helpers_allocate_gpu_mem(
657 clk_mgr->base.base.ctx,
658 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
659 sizeof(DpmClocks_t),
660 &smu_dpm_clks.mc_address.quad_part);
661
662 if (smu_dpm_clks.dpm_clks == NULL) {
663 smu_dpm_clks.dpm_clks = &dummy_clocks;
664 smu_dpm_clks.mc_address.quad_part = 0;
665 }
666
667 ASSERT(smu_dpm_clks.dpm_clks);
668
669 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
670 clk_mgr->base.base.funcs = &dcn3_fpga_funcs;
671 } else {
672 struct clk_log_info log_info = {0};
673
674 clk_mgr->base.smu_ver = dcn31_smu_get_smu_version(&clk_mgr->base);
675
676 if (clk_mgr->base.smu_ver)
677 clk_mgr->base.smu_present = true;
678
679 /* TODO: Check we get what we expect during bringup */
680 clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
681
682 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
683 dcn31_bw_params.wm_table = lpddr5_wm_table;
684 } else {
685 dcn31_bw_params.wm_table = ddr4_wm_table;
686 }
687 /* Saved clocks configured at boot for debug purposes */
688 dcn31_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info);
689
690 }
691
692 clk_mgr->base.base.dprefclk_khz = 600000;
693 clk_mgr->base.dccg->ref_dtbclk_khz = 600000;
694 dce_clock_read_ss_info(&clk_mgr->base);
695
696 clk_mgr->base.base.bw_params = &dcn31_bw_params;
697
698 if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
699 dcn31_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
700
701 if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
702 dcn31_clk_mgr_helper_populate_bw_params(
703 &clk_mgr->base,
704 ctx->dc_bios->integrated_info,
705 smu_dpm_clks.dpm_clks);
706 }
707 }
708
709 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
710 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
711 smu_dpm_clks.dpm_clks);
712 }
713
dcn31_clk_mgr_destroy(struct clk_mgr_internal * clk_mgr_int)714 void dcn31_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
715 {
716 struct clk_mgr_dcn31 *clk_mgr = TO_CLK_MGR_DCN31(clk_mgr_int);
717
718 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
719 dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
720 clk_mgr->smu_wm_set.wm_set);
721 }
722
