1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "core_types.h"
27 #include "clk_mgr_internal.h"
28 #include "reg_helper.h"
29 #include "dm_helpers.h"
30 #include "dcn315_smu.h"
31 #include "mp/mp_13_0_5_offset.h"
32
33 #define MAX_INSTANCE 6
34 #define MAX_SEGMENT 6
35 #define SMU_REGISTER_WRITE_RETRY_COUNT 5
36
37 struct IP_BASE_INSTANCE {
38 unsigned int segment[MAX_SEGMENT];
39 };
40
41 struct IP_BASE {
42 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
43 };
44
45 static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } },
46 { { 0, 0, 0, 0, 0, 0 } },
47 { { 0, 0, 0, 0, 0, 0 } },
48 { { 0, 0, 0, 0, 0, 0 } },
49 { { 0, 0, 0, 0, 0, 0 } },
50 { { 0, 0, 0, 0, 0, 0 } } } };
51 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
52 { { 0, 0, 0, 0, 0, 0 } },
53 { { 0, 0, 0, 0, 0, 0 } },
54 { { 0, 0, 0, 0, 0, 0 } },
55 { { 0, 0, 0, 0, 0, 0 } },
56 { { 0, 0, 0, 0, 0, 0 } } } };
57
58 #define regBIF_BX_PF2_RSMU_INDEX 0x0000
59 #define regBIF_BX_PF2_RSMU_INDEX_BASE_IDX 1
60 #define regBIF_BX_PF2_RSMU_DATA 0x0001
61 #define regBIF_BX_PF2_RSMU_DATA_BASE_IDX 1
62
63 #define REG(reg_name) \
64 (MP0_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
65
66 #define FN(reg_name, field) \
67 FD(reg_name##__##field)
68
69 #define REG_NBIO(reg_name) \
70 (NBIO_BASE.instance[0].segment[regBIF_BX_PF2_ ## reg_name ## _BASE_IDX] + regBIF_BX_PF2_ ## reg_name)
71
72 #include "logger_types.h"
73 #undef DC_LOGGER
74 #define DC_LOGGER \
75 CTX->logger
76 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
77
78 #define mmMP1_C2PMSG_3 0x3B1050C
79
80 #define VBIOSSMC_MSG_TestMessage 0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team
81 #define VBIOSSMC_MSG_GetPmfwVersion 0x02 ///< Get PMFW version
82 #define VBIOSSMC_MSG_Spare0 0x03 ///< Spare0
83 #define VBIOSSMC_MSG_SetDispclkFreq 0x04 ///< Set display clock frequency in MHZ
84 #define VBIOSSMC_MSG_Spare1 0x05 ///< Spare1
85 #define VBIOSSMC_MSG_SetDppclkFreq 0x06 ///< Set DPP clock frequency in MHZ
86 #define VBIOSSMC_MSG_SetHardMinDcfclkByFreq 0x07 ///< Set DCF clock frequency hard min in MHZ
87 #define VBIOSSMC_MSG_SetMinDeepSleepDcfclk 0x08 ///< Set DCF clock minimum frequency in deep sleep in MHZ
88 #define VBIOSSMC_MSG_GetDtbclkFreq 0x09 ///< Get display dtb clock frequency in MHZ in case VMIN does not support phy frequency
89 #define VBIOSSMC_MSG_SetDtbClk 0x0A ///< Set dtb clock frequency, return frequemcy in MHZ
90 #define VBIOSSMC_MSG_SetDisplayCount 0x0B ///< Inform PMFW of number of display connected
91 #define VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown 0x0C ///< To ask PMFW turn off TMDP 48MHz refclk during display off to save power
92 #define VBIOSSMC_MSG_UpdatePmeRestore 0x0D ///< To ask PMFW to write into Azalia for PME wake up event
93 #define VBIOSSMC_MSG_SetVbiosDramAddrHigh 0x0E ///< Set DRAM address high 32 bits for WM table transfer
94 #define VBIOSSMC_MSG_SetVbiosDramAddrLow 0x0F ///< Set DRAM address low 32 bits for WM table transfer
95 #define VBIOSSMC_MSG_TransferTableSmu2Dram 0x10 ///< Transfer table from PMFW SRAM to system DRAM
96 #define VBIOSSMC_MSG_TransferTableDram2Smu 0x11 ///< Transfer table from system DRAM to PMFW
97 #define VBIOSSMC_MSG_SetDisplayIdleOptimizations 0x12 ///< Set Idle state optimization for display off
98 #define VBIOSSMC_MSG_GetDprefclkFreq 0x13 ///< Get DPREF clock frequency. Return in MHZ
99 #define VBIOSSMC_Message_Count 0x14 ///< Total number of VBIS and DAL messages
100
101 #define VBIOSSMC_Status_BUSY 0x0
102 #define VBIOSSMC_Result_OK 0x01 ///< Message Response OK
103 #define VBIOSSMC_Result_Failed 0xFF ///< Message Response Failed
104 #define VBIOSSMC_Result_UnknownCmd 0xFE ///< Message Response Unknown Command
105 #define VBIOSSMC_Result_CmdRejectedPrereq 0xFD ///< Message Response Command Failed Prerequisite
106 #define VBIOSSMC_Result_CmdRejectedBusy 0xFC ///< Message Response Command Rejected due to PMFW is busy. Sender should retry sending this message
107
108 /*
109 * Function to be used instead of REG_WAIT macro because the wait ends when
110 * the register is NOT EQUAL to zero, and because the translation in msg_if.h
111 * won't work with REG_WAIT.
112 */
dcn315_smu_wait_for_response(struct clk_mgr_internal * clk_mgr,unsigned int delay_us,unsigned int max_retries)113 static uint32_t dcn315_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)
114 {
115 uint32_t res_val = VBIOSSMC_Status_BUSY;
116
117 do {
118 res_val = REG_READ(MP1_SMN_C2PMSG_38);
119 if (res_val != VBIOSSMC_Status_BUSY)
120 break;
121
122 if (delay_us >= 1000)
123 msleep(delay_us/1000);
124 else if (delay_us > 0)
125 udelay(delay_us);
126 } while (max_retries--);
127
128 return res_val;
129 }
130
dcn315_smu_send_msg_with_param(struct clk_mgr_internal * clk_mgr,unsigned int msg_id,unsigned int param)131 static int dcn315_smu_send_msg_with_param(
132 struct clk_mgr_internal *clk_mgr,
133 unsigned int msg_id, unsigned int param)
134 {
135 uint32_t result;
136 uint32_t i = 0;
137 uint32_t read_back_data;
138
139 result = dcn315_smu_wait_for_response(clk_mgr, 10, 200000);
140
141 if (result != VBIOSSMC_Result_OK)
142 smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result);
143
144 if (result == VBIOSSMC_Status_BUSY) {
145 return -1;
146 }
147
148 /* First clear response register */
149 REG_WRITE(MP1_SMN_C2PMSG_38, VBIOSSMC_Status_BUSY);
150
151 /* Set the parameter register for the SMU message, unit is Mhz */
152 REG_WRITE(MP1_SMN_C2PMSG_37, param);
153
154 for (i = 0; i < SMU_REGISTER_WRITE_RETRY_COUNT; i++) {
155 /* Trigger the message transaction by writing the message ID */
156 generic_write_indirect_reg(CTX,
157 REG_NBIO(RSMU_INDEX), REG_NBIO(RSMU_DATA),
158 mmMP1_C2PMSG_3, msg_id);
159 read_back_data = generic_read_indirect_reg(CTX,
160 REG_NBIO(RSMU_INDEX), REG_NBIO(RSMU_DATA),
161 mmMP1_C2PMSG_3);
162 if (read_back_data == msg_id)
163 break;
164 udelay(2);
165 smu_print("SMU msg id write fail %x times. \n", i + 1);
166 }
167
168 result = dcn315_smu_wait_for_response(clk_mgr, 10, 200000);
169
170 if (result == VBIOSSMC_Status_BUSY) {
171 ASSERT(0);
172 dm_helpers_smu_timeout(CTX, msg_id, param, 10 * 200000);
173 }
174
175 return REG_READ(MP1_SMN_C2PMSG_37);
176 }
177
dcn315_smu_get_smu_version(struct clk_mgr_internal * clk_mgr)178 int dcn315_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)
179 {
180 return dcn315_smu_send_msg_with_param(
181 clk_mgr,
182 VBIOSSMC_MSG_GetPmfwVersion,
183 0);
184 }
185
186
dcn315_smu_set_dispclk(struct clk_mgr_internal * clk_mgr,int requested_dispclk_khz)187 int dcn315_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
188 {
189 int actual_dispclk_set_mhz = -1;
190
191 if (!clk_mgr->smu_present)
192 return requested_dispclk_khz;
193
194 /* Unit of SMU msg parameter is Mhz */
195 actual_dispclk_set_mhz = dcn315_smu_send_msg_with_param(
196 clk_mgr,
197 VBIOSSMC_MSG_SetDispclkFreq,
198 khz_to_mhz_ceil(requested_dispclk_khz));
199
200 return actual_dispclk_set_mhz * 1000;
201 }
202
dcn315_smu_set_hard_min_dcfclk(struct clk_mgr_internal * clk_mgr,int requested_dcfclk_khz)203 int dcn315_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)
204 {
205 int actual_dcfclk_set_mhz = -1;
206
207 if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)
208 return -1;
209
210 if (!clk_mgr->smu_present)
211 return requested_dcfclk_khz;
212
213 actual_dcfclk_set_mhz = dcn315_smu_send_msg_with_param(
214 clk_mgr,
215 VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
216 khz_to_mhz_ceil(requested_dcfclk_khz));
217
218 #ifdef DBG
219 smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", actual_dcfclk_set_mhz, actual_dcfclk_set_mhz * 1000);
220 #endif
221
222 return actual_dcfclk_set_mhz * 1000;
223 }
224
dcn315_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal * clk_mgr,int requested_min_ds_dcfclk_khz)225 int dcn315_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)
226 {
227 int actual_min_ds_dcfclk_mhz = -1;
228
229 if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)
230 return -1;
231
232 if (!clk_mgr->smu_present)
233 return requested_min_ds_dcfclk_khz;
234
235 actual_min_ds_dcfclk_mhz = dcn315_smu_send_msg_with_param(
236 clk_mgr,
237 VBIOSSMC_MSG_SetMinDeepSleepDcfclk,
238 khz_to_mhz_ceil(requested_min_ds_dcfclk_khz));
239
240 return actual_min_ds_dcfclk_mhz * 1000;
241 }
242
dcn315_smu_set_dppclk(struct clk_mgr_internal * clk_mgr,int requested_dpp_khz)243 int dcn315_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)
244 {
245 int actual_dppclk_set_mhz = -1;
246
247 if (!clk_mgr->smu_present)
248 return requested_dpp_khz;
249
250 actual_dppclk_set_mhz = dcn315_smu_send_msg_with_param(
251 clk_mgr,
252 VBIOSSMC_MSG_SetDppclkFreq,
253 khz_to_mhz_ceil(requested_dpp_khz));
254
255 return actual_dppclk_set_mhz * 1000;
256 }
257
dcn315_smu_set_display_idle_optimization(struct clk_mgr_internal * clk_mgr,uint32_t idle_info)258 void dcn315_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)
259 {
260 if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)
261 return;
262
263 if (!clk_mgr->smu_present)
264 return;
265
266 //TODO: Work with smu team to define optimization options.
267 dcn315_smu_send_msg_with_param(
268 clk_mgr,
269 VBIOSSMC_MSG_SetDisplayIdleOptimizations,
270 idle_info);
271 }
272
dcn315_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal * clk_mgr,bool enable)273 void dcn315_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)
274 {
275 union display_idle_optimization_u idle_info = { 0 };
276
277 if (!clk_mgr->smu_present)
278 return;
279
280 if (enable) {
281 idle_info.idle_info.df_request_disabled = 1;
282 idle_info.idle_info.phy_ref_clk_off = 1;
283 }
284
285 dcn315_smu_send_msg_with_param(
286 clk_mgr,
287 VBIOSSMC_MSG_SetDisplayIdleOptimizations,
288 idle_info.data);
289 }
290
dcn315_smu_enable_pme_wa(struct clk_mgr_internal * clk_mgr)291 void dcn315_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)
292 {
293 if (!clk_mgr->smu_present)
294 return;
295
296 dcn315_smu_send_msg_with_param(
297 clk_mgr,
298 VBIOSSMC_MSG_UpdatePmeRestore,
299 0);
300 }
dcn315_smu_set_dram_addr_high(struct clk_mgr_internal * clk_mgr,uint32_t addr_high)301 void dcn315_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)
302 {
303 if (!clk_mgr->smu_present)
304 return;
305
306 dcn315_smu_send_msg_with_param(clk_mgr,
307 VBIOSSMC_MSG_SetVbiosDramAddrHigh, addr_high);
308 }
309
dcn315_smu_set_dram_addr_low(struct clk_mgr_internal * clk_mgr,uint32_t addr_low)310 void dcn315_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)
311 {
312 if (!clk_mgr->smu_present)
313 return;
314
315 dcn315_smu_send_msg_with_param(clk_mgr,
316 VBIOSSMC_MSG_SetVbiosDramAddrLow, addr_low);
317 }
318
dcn315_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal * clk_mgr)319 void dcn315_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)
320 {
321 if (!clk_mgr->smu_present)
322 return;
323
324 dcn315_smu_send_msg_with_param(clk_mgr,
325 VBIOSSMC_MSG_TransferTableSmu2Dram, TABLE_DPMCLOCKS);
326 }
327
dcn315_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal * clk_mgr)328 void dcn315_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)
329 {
330 if (!clk_mgr->smu_present)
331 return;
332
333 dcn315_smu_send_msg_with_param(clk_mgr,
334 VBIOSSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS);
335 }
336
dcn315_smu_get_dpref_clk(struct clk_mgr_internal * clk_mgr)337 int dcn315_smu_get_dpref_clk(struct clk_mgr_internal *clk_mgr)
338 {
339 int dprefclk_get_mhz = -1;
340 if (clk_mgr->smu_present) {
341 dprefclk_get_mhz = dcn315_smu_send_msg_with_param(
342 clk_mgr,
343 VBIOSSMC_MSG_GetDprefclkFreq,
344 0);
345 }
346 return (dprefclk_get_mhz * 1000);
347 }
348
dcn315_smu_get_dtbclk(struct clk_mgr_internal * clk_mgr)349 int dcn315_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr)
350 {
351 int fclk_get_mhz = -1;
352
353 if (clk_mgr->smu_present) {
354 fclk_get_mhz = dcn315_smu_send_msg_with_param(
355 clk_mgr,
356 VBIOSSMC_MSG_GetDtbclkFreq,
357 0);
358 }
359 return (fclk_get_mhz * 1000);
360 }
361
dcn315_smu_set_dtbclk(struct clk_mgr_internal * clk_mgr,bool enable)362 void dcn315_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)
363 {
364 if (!clk_mgr->smu_present)
365 return;
366
367 dcn315_smu_send_msg_with_param(
368 clk_mgr,
369 VBIOSSMC_MSG_SetDtbClk,
370 enable);
371 }
372
