1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dcn302_init.h"
27 #include "dcn302_resource.h"
28 #include "dcn302_dccg.h"
29 #include "irq/dcn302/irq_service_dcn302.h"
30
31 #include "dcn30/dcn30_dio_link_encoder.h"
32 #include "dcn30/dcn30_dio_stream_encoder.h"
33 #include "dcn30/dcn30_dwb.h"
34 #include "dcn30/dcn30_dpp.h"
35 #include "dcn30/dcn30_hubbub.h"
36 #include "dcn30/dcn30_hubp.h"
37 #include "dcn30/dcn30_mmhubbub.h"
38 #include "dcn30/dcn30_mpc.h"
39 #include "dcn30/dcn30_opp.h"
40 #include "dcn30/dcn30_optc.h"
41 #include "dcn30/dcn30_resource.h"
42
43 #include "dcn20/dcn20_dsc.h"
44 #include "dcn20/dcn20_resource.h"
45
46 #include "dml/dcn30/dcn30_fpu.h"
47
48 #include "dcn10/dcn10_resource.h"
49
50 #include "link.h"
51 #include "dce/dce_abm.h"
52 #include "dce/dce_audio.h"
53 #include "dce/dce_aux.h"
54 #include "dce/dce_clock_source.h"
55 #include "dce/dce_hwseq.h"
56 #include "dce/dce_i2c_hw.h"
57 #include "dce/dce_panel_cntl.h"
58 #include "dce/dmub_abm.h"
59 #include "dce/dmub_psr.h"
60 #include "clk_mgr.h"
61
62 #include "hw_sequencer_private.h"
63 #include "reg_helper.h"
64 #include "resource.h"
65 #include "vm_helper.h"
66
67 #include "dml/dcn302/dcn302_fpu.h"
68
69 #include "dimgrey_cavefish_ip_offset.h"
70 #include "dcn/dcn_3_0_2_offset.h"
71 #include "dcn/dcn_3_0_2_sh_mask.h"
72 #include "dpcs/dpcs_3_0_0_offset.h"
73 #include "dpcs/dpcs_3_0_0_sh_mask.h"
74 #include "nbio/nbio_7_4_offset.h"
75 #include "amdgpu_socbb.h"
76
77 #define DC_LOGGER_INIT(logger)
78
79 static const struct dc_debug_options debug_defaults_drv = {
80 .disable_dmcu = true,
81 .force_abm_enable = false,
82 .timing_trace = false,
83 .clock_trace = true,
84 .disable_pplib_clock_request = true,
85 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
86 .force_single_disp_pipe_split = false,
87 .disable_dcc = DCC_ENABLE,
88 .vsr_support = true,
89 .performance_trace = false,
90 .max_downscale_src_width = 7680,/*upto 8K*/
91 .disable_pplib_wm_range = false,
92 .scl_reset_length10 = true,
93 .sanity_checks = false,
94 .underflow_assert_delay_us = 0xFFFFFFFF,
95 .dwb_fi_phase = -1, // -1 = disable,
96 .dmub_command_table = true,
97 .use_max_lb = true,
98 .exit_idle_opt_for_cursor_updates = true,
99 .enable_legacy_fast_update = false,
100 };
101
102 static const struct dc_panel_config panel_config_defaults = {
103 .psr = {
104 .disable_psr = false,
105 .disallow_psrsu = false,
106 .disallow_replay = false,
107 },
108 };
109
110 enum dcn302_clk_src_array_id {
111 DCN302_CLK_SRC_PLL0,
112 DCN302_CLK_SRC_PLL1,
113 DCN302_CLK_SRC_PLL2,
114 DCN302_CLK_SRC_PLL3,
115 DCN302_CLK_SRC_PLL4,
116 DCN302_CLK_SRC_TOTAL
117 };
118
119 static const struct resource_caps res_cap_dcn302 = {
120 .num_timing_generator = 5,
121 .num_opp = 5,
122 .num_video_plane = 5,
123 .num_audio = 5,
124 .num_stream_encoder = 5,
125 .num_dwb = 1,
126 .num_ddc = 5,
127 .num_vmid = 16,
128 .num_mpc_3dlut = 2,
129 .num_dsc = 5,
130 };
131
132 static const struct dc_plane_cap plane_cap = {
133 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
134 .per_pixel_alpha = true,
135 .pixel_format_support = {
136 .argb8888 = true,
137 .nv12 = true,
138 .fp16 = true,
139 .p010 = true,
140 .ayuv = false,
141 },
142 .max_upscale_factor = {
143 .argb8888 = 16000,
144 .nv12 = 16000,
145 .fp16 = 16000
146 },
147 /* 6:1 downscaling ratio: 1000/6 = 166.666 */
148 .max_downscale_factor = {
149 .argb8888 = 167,
150 .nv12 = 167,
151 .fp16 = 167
152 },
153 16,
154 16
155 };
156
157 /* NBIO */
158 #define NBIO_BASE_INNER(seg) \
159 NBIO_BASE__INST0_SEG ## seg
160
161 #define NBIO_BASE(seg) \
162 NBIO_BASE_INNER(seg)
163
164 #define NBIO_SR(reg_name)\
165 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
166 mm ## reg_name
167
168 /* DCN */
169 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
170
171 #define BASE(seg) BASE_INNER(seg)
172
173 #define SR(reg_name)\
174 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
175
176 #define SF(reg_name, field_name, post_fix)\
177 .field_name = reg_name ## __ ## field_name ## post_fix
178
179 #define SRI(reg_name, block, id)\
180 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name
181
182 #define SRI2(reg_name, block, id)\
183 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
184
185 #define SRII(reg_name, block, id)\
186 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
187 mm ## block ## id ## _ ## reg_name
188
189 #define DCCG_SRII(reg_name, block, id)\
190 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
191 mm ## block ## id ## _ ## reg_name
192
193 #define VUPDATE_SRII(reg_name, block, id)\
194 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
195 mm ## reg_name ## _ ## block ## id
196
197 #define SRII_DWB(reg_name, temp_name, block, id)\
198 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
199 mm ## block ## id ## _ ## temp_name
200
201 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
202 .field_name = reg_name ## __ ## field_name ## post_fix
203
204 #define SRII_MPC_RMU(reg_name, block, id)\
205 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
206 mm ## block ## id ## _ ## reg_name
207
208 static const struct dcn_hubbub_registers hubbub_reg = {
209 HUBBUB_REG_LIST_DCN30(0)
210 };
211
212 static const struct dcn_hubbub_shift hubbub_shift = {
213 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
214 };
215
216 static const struct dcn_hubbub_mask hubbub_mask = {
217 HUBBUB_MASK_SH_LIST_DCN30(_MASK)
218 };
219
220 #define vmid_regs(id)\
221 [id] = { DCN20_VMID_REG_LIST(id) }
222
223 static const struct dcn_vmid_registers vmid_regs[] = {
224 vmid_regs(0),
225 vmid_regs(1),
226 vmid_regs(2),
227 vmid_regs(3),
228 vmid_regs(4),
229 vmid_regs(5),
230 vmid_regs(6),
231 vmid_regs(7),
232 vmid_regs(8),
233 vmid_regs(9),
234 vmid_regs(10),
235 vmid_regs(11),
236 vmid_regs(12),
237 vmid_regs(13),
238 vmid_regs(14),
239 vmid_regs(15)
240 };
241
242 static const struct dcn20_vmid_shift vmid_shifts = {
243 DCN20_VMID_MASK_SH_LIST(__SHIFT)
244 };
245
246 static const struct dcn20_vmid_mask vmid_masks = {
247 DCN20_VMID_MASK_SH_LIST(_MASK)
248 };
249
dcn302_hubbub_create(struct dc_context * ctx)250 static struct hubbub *dcn302_hubbub_create(struct dc_context *ctx)
251 {
252 int i;
253
254 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL);
255
256 if (!hubbub3)
257 return NULL;
258
259 hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask);
260
261 for (i = 0; i < res_cap_dcn302.num_vmid; i++) {
262 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
263
264 vmid->ctx = ctx;
265
266 vmid->regs = &vmid_regs[i];
267 vmid->shifts = &vmid_shifts;
268 vmid->masks = &vmid_masks;
269 }
270
271 return &hubbub3->base;
272 }
273
274 #define vpg_regs(id)\
275 [id] = { VPG_DCN3_REG_LIST(id) }
276
277 static const struct dcn30_vpg_registers vpg_regs[] = {
278 vpg_regs(0),
279 vpg_regs(1),
280 vpg_regs(2),
281 vpg_regs(3),
282 vpg_regs(4),
283 vpg_regs(5)
284 };
285
286 static const struct dcn30_vpg_shift vpg_shift = {
287 DCN3_VPG_MASK_SH_LIST(__SHIFT)
288 };
289
290 static const struct dcn30_vpg_mask vpg_mask = {
291 DCN3_VPG_MASK_SH_LIST(_MASK)
292 };
293
dcn302_vpg_create(struct dc_context * ctx,uint32_t inst)294 static struct vpg *dcn302_vpg_create(struct dc_context *ctx, uint32_t inst)
295 {
296 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
297
298 if (!vpg3)
299 return NULL;
300
301 vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask);
302
303 return &vpg3->base;
304 }
305
306 #define afmt_regs(id)\
307 [id] = { AFMT_DCN3_REG_LIST(id) }
308
309 static const struct dcn30_afmt_registers afmt_regs[] = {
310 afmt_regs(0),
311 afmt_regs(1),
312 afmt_regs(2),
313 afmt_regs(3),
314 afmt_regs(4),
315 afmt_regs(5)
316 };
317
318 static const struct dcn30_afmt_shift afmt_shift = {
319 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
320 };
321
322 static const struct dcn30_afmt_mask afmt_mask = {
323 DCN3_AFMT_MASK_SH_LIST(_MASK)
324 };
325
dcn302_afmt_create(struct dc_context * ctx,uint32_t inst)326 static struct afmt *dcn302_afmt_create(struct dc_context *ctx, uint32_t inst)
327 {
328 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
329
330 if (!afmt3)
331 return NULL;
332
333 afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask);
334
335 return &afmt3->base;
336 }
337
338 #define audio_regs(id)\
339 [id] = { AUD_COMMON_REG_LIST(id) }
340
341 static const struct dce_audio_registers audio_regs[] = {
342 audio_regs(0),
343 audio_regs(1),
344 audio_regs(2),
345 audio_regs(3),
346 audio_regs(4),
347 audio_regs(5),
348 audio_regs(6)
349 };
350
351 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
352 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
353 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
354 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
355
356 static const struct dce_audio_shift audio_shift = {
357 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
358 };
359
360 static const struct dce_audio_mask audio_mask = {
361 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
362 };
363
dcn302_create_audio(struct dc_context * ctx,unsigned int inst)364 static struct audio *dcn302_create_audio(struct dc_context *ctx, unsigned int inst)
365 {
366 return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask);
367 }
368
369 #define stream_enc_regs(id)\
370 [id] = { SE_DCN3_REG_LIST(id) }
371
372 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
373 stream_enc_regs(0),
374 stream_enc_regs(1),
375 stream_enc_regs(2),
376 stream_enc_regs(3),
377 stream_enc_regs(4)
378 };
379
380 static const struct dcn10_stream_encoder_shift se_shift = {
381 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
382 };
383
384 static const struct dcn10_stream_encoder_mask se_mask = {
385 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
386 };
387
dcn302_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)388 static struct stream_encoder *dcn302_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx)
389 {
390 struct dcn10_stream_encoder *enc1;
391 struct vpg *vpg;
392 struct afmt *afmt;
393 int vpg_inst;
394 int afmt_inst;
395
396 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
397 if (eng_id <= ENGINE_ID_DIGE) {
398 vpg_inst = eng_id;
399 afmt_inst = eng_id;
400 } else
401 return NULL;
402
403 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
404 vpg = dcn302_vpg_create(ctx, vpg_inst);
405 afmt = dcn302_afmt_create(ctx, afmt_inst);
406
407 if (!enc1 || !vpg || !afmt) {
408 kfree(enc1);
409 kfree(vpg);
410 kfree(afmt);
411 return NULL;
412 }
413
414 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id],
415 &se_shift, &se_mask);
416
417 return &enc1->base;
418 }
419
420 #define clk_src_regs(index, pllid)\
421 [index] = { CS_COMMON_REG_LIST_DCN3_02(index, pllid) }
422
423 static const struct dce110_clk_src_regs clk_src_regs[] = {
424 clk_src_regs(0, A),
425 clk_src_regs(1, B),
426 clk_src_regs(2, C),
427 clk_src_regs(3, D),
428 clk_src_regs(4, E)
429 };
430
431 static const struct dce110_clk_src_shift cs_shift = {
432 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
433 };
434
435 static const struct dce110_clk_src_mask cs_mask = {
436 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
437 };
438
dcn302_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)439 static struct clock_source *dcn302_clock_source_create(struct dc_context *ctx, struct dc_bios *bios,
440 enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src)
441 {
442 struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
443
444 if (!clk_src)
445 return NULL;
446
447 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) {
448 clk_src->base.dp_clk_src = dp_clk_src;
449 return &clk_src->base;
450 }
451
452 kfree(clk_src);
453 BREAK_TO_DEBUGGER();
454 return NULL;
455 }
456
457 static const struct dce_hwseq_registers hwseq_reg = {
458 HWSEQ_DCN302_REG_LIST()
459 };
460
461 static const struct dce_hwseq_shift hwseq_shift = {
462 HWSEQ_DCN302_MASK_SH_LIST(__SHIFT)
463 };
464
465 static const struct dce_hwseq_mask hwseq_mask = {
466 HWSEQ_DCN302_MASK_SH_LIST(_MASK)
467 };
468
dcn302_hwseq_create(struct dc_context * ctx)469 static struct dce_hwseq *dcn302_hwseq_create(struct dc_context *ctx)
470 {
471 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
472
473 if (hws) {
474 hws->ctx = ctx;
475 hws->regs = &hwseq_reg;
476 hws->shifts = &hwseq_shift;
477 hws->masks = &hwseq_mask;
478 }
479 return hws;
480 }
481
482 #define hubp_regs(id)\
483 [id] = { HUBP_REG_LIST_DCN30(id) }
484
485 static const struct dcn_hubp2_registers hubp_regs[] = {
486 hubp_regs(0),
487 hubp_regs(1),
488 hubp_regs(2),
489 hubp_regs(3),
490 hubp_regs(4)
491 };
492
493 static const struct dcn_hubp2_shift hubp_shift = {
494 HUBP_MASK_SH_LIST_DCN30(__SHIFT)
495 };
496
497 static const struct dcn_hubp2_mask hubp_mask = {
498 HUBP_MASK_SH_LIST_DCN30(_MASK)
499 };
500
dcn302_hubp_create(struct dc_context * ctx,uint32_t inst)501 static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst)
502 {
503 struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
504
505 if (!hubp2)
506 return NULL;
507
508 if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask))
509 return &hubp2->base;
510
511 BREAK_TO_DEBUGGER();
512 kfree(hubp2);
513 return NULL;
514 }
515
516 #define dpp_regs(id)\
517 [id] = { DPP_REG_LIST_DCN30(id) }
518
519 static const struct dcn3_dpp_registers dpp_regs[] = {
520 dpp_regs(0),
521 dpp_regs(1),
522 dpp_regs(2),
523 dpp_regs(3),
524 dpp_regs(4)
525 };
526
527 static const struct dcn3_dpp_shift tf_shift = {
528 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
529 };
530
531 static const struct dcn3_dpp_mask tf_mask = {
532 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
533 };
534
dcn302_dpp_create(struct dc_context * ctx,uint32_t inst)535 static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst)
536 {
537 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
538
539 if (!dpp)
540 return NULL;
541
542 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))
543 return &dpp->base;
544
545 BREAK_TO_DEBUGGER();
546 kfree(dpp);
547 return NULL;
548 }
549
550 #define opp_regs(id)\
551 [id] = { OPP_REG_LIST_DCN30(id) }
552
553 static const struct dcn20_opp_registers opp_regs[] = {
554 opp_regs(0),
555 opp_regs(1),
556 opp_regs(2),
557 opp_regs(3),
558 opp_regs(4)
559 };
560
561 static const struct dcn20_opp_shift opp_shift = {
562 OPP_MASK_SH_LIST_DCN20(__SHIFT)
563 };
564
565 static const struct dcn20_opp_mask opp_mask = {
566 OPP_MASK_SH_LIST_DCN20(_MASK)
567 };
568
dcn302_opp_create(struct dc_context * ctx,uint32_t inst)569 static struct output_pixel_processor *dcn302_opp_create(struct dc_context *ctx, uint32_t inst)
570 {
571 struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
572
573 if (!opp) {
574 BREAK_TO_DEBUGGER();
575 return NULL;
576 }
577
578 dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
579 return &opp->base;
580 }
581
582 #define optc_regs(id)\
583 [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) }
584
585 static const struct dcn_optc_registers optc_regs[] = {
586 optc_regs(0),
587 optc_regs(1),
588 optc_regs(2),
589 optc_regs(3),
590 optc_regs(4)
591 };
592
593 static const struct dcn_optc_shift optc_shift = {
594 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
595 };
596
597 static const struct dcn_optc_mask optc_mask = {
598 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
599 };
600
dcn302_timing_generator_create(struct dc_context * ctx,uint32_t instance)601 static struct timing_generator *dcn302_timing_generator_create(struct dc_context *ctx, uint32_t instance)
602 {
603 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL);
604
605 if (!tgn10)
606 return NULL;
607
608 tgn10->base.inst = instance;
609 tgn10->base.ctx = ctx;
610
611 tgn10->tg_regs = &optc_regs[instance];
612 tgn10->tg_shift = &optc_shift;
613 tgn10->tg_mask = &optc_mask;
614
615 dcn30_timing_generator_init(tgn10);
616
617 return &tgn10->base;
618 }
619
620 static const struct dcn30_mpc_registers mpc_regs = {
621 MPC_REG_LIST_DCN3_0(0),
622 MPC_REG_LIST_DCN3_0(1),
623 MPC_REG_LIST_DCN3_0(2),
624 MPC_REG_LIST_DCN3_0(3),
625 MPC_REG_LIST_DCN3_0(4),
626 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
627 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
628 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
629 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
630 MPC_OUT_MUX_REG_LIST_DCN3_0(4),
631 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
632 MPC_RMU_REG_LIST_DCN3AG(0),
633 MPC_RMU_REG_LIST_DCN3AG(1),
634 MPC_RMU_REG_LIST_DCN3AG(2),
635 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
636 };
637
638 static const struct dcn30_mpc_shift mpc_shift = {
639 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
640 };
641
642 static const struct dcn30_mpc_mask mpc_mask = {
643 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
644 };
645
dcn302_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)646 static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu)
647 {
648 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL);
649
650 if (!mpc30)
651 return NULL;
652
653 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu);
654
655 return &mpc30->base;
656 }
657
658 #define dsc_regsDCN20(id)\
659 [id] = { DSC_REG_LIST_DCN20(id) }
660
661 static const struct dcn20_dsc_registers dsc_regs[] = {
662 dsc_regsDCN20(0),
663 dsc_regsDCN20(1),
664 dsc_regsDCN20(2),
665 dsc_regsDCN20(3),
666 dsc_regsDCN20(4)
667 };
668
669 static const struct dcn20_dsc_shift dsc_shift = {
670 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
671 };
672
673 static const struct dcn20_dsc_mask dsc_mask = {
674 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
675 };
676
dcn302_dsc_create(struct dc_context * ctx,uint32_t inst)677 static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ctx, uint32_t inst)
678 {
679 struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
680
681 if (!dsc) {
682 BREAK_TO_DEBUGGER();
683 return NULL;
684 }
685
686 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
687 return &dsc->base;
688 }
689
690 #define dwbc_regs_dcn3(id)\
691 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) }
692
693 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
694 dwbc_regs_dcn3(0)
695 };
696
697 static const struct dcn30_dwbc_shift dwbc30_shift = {
698 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
699 };
700
701 static const struct dcn30_dwbc_mask dwbc30_mask = {
702 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
703 };
704
dcn302_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)705 static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
706 {
707 int i;
708 uint32_t pipe_count = pool->res_cap->num_dwb;
709
710 for (i = 0; i < pipe_count; i++) {
711 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL);
712
713 if (!dwbc30) {
714 dm_error("DC: failed to create dwbc30!\n");
715 return false;
716 }
717
718 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i);
719
720 pool->dwbc[i] = &dwbc30->base;
721 }
722 return true;
723 }
724
725 #define mcif_wb_regs_dcn3(id)\
726 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) }
727
728 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
729 mcif_wb_regs_dcn3(0)
730 };
731
732 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
733 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
734 };
735
736 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
737 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
738 };
739
dcn302_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)740 static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
741 {
742 int i;
743 uint32_t pipe_count = pool->res_cap->num_dwb;
744
745 for (i = 0; i < pipe_count; i++) {
746 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL);
747
748 if (!mcif_wb30) {
749 dm_error("DC: failed to create mcif_wb30!\n");
750 return false;
751 }
752
753 dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i);
754
755 pool->mcif_wb[i] = &mcif_wb30->base;
756 }
757 return true;
758 }
759
760 #define aux_engine_regs(id)\
761 [id] = {\
762 AUX_COMMON_REG_LIST0(id), \
763 .AUXN_IMPCAL = 0, \
764 .AUXP_IMPCAL = 0, \
765 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
766 }
767
768 static const struct dce110_aux_registers aux_engine_regs[] = {
769 aux_engine_regs(0),
770 aux_engine_regs(1),
771 aux_engine_regs(2),
772 aux_engine_regs(3),
773 aux_engine_regs(4)
774 };
775
776 static const struct dce110_aux_registers_shift aux_shift = {
777 DCN_AUX_MASK_SH_LIST(__SHIFT)
778 };
779
780 static const struct dce110_aux_registers_mask aux_mask = {
781 DCN_AUX_MASK_SH_LIST(_MASK)
782 };
783
dcn302_aux_engine_create(struct dc_context * ctx,uint32_t inst)784 static struct dce_aux *dcn302_aux_engine_create(struct dc_context *ctx, uint32_t inst)
785 {
786 struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
787
788 if (!aux_engine)
789 return NULL;
790
791 dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
792 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support);
793
794 return &aux_engine->base;
795 }
796
797 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
798
799 static const struct dce_i2c_registers i2c_hw_regs[] = {
800 i2c_inst_regs(1),
801 i2c_inst_regs(2),
802 i2c_inst_regs(3),
803 i2c_inst_regs(4),
804 i2c_inst_regs(5)
805 };
806
807 static const struct dce_i2c_shift i2c_shifts = {
808 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
809 };
810
811 static const struct dce_i2c_mask i2c_masks = {
812 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
813 };
814
dcn302_i2c_hw_create(struct dc_context * ctx,uint32_t inst)815 static struct dce_i2c_hw *dcn302_i2c_hw_create(struct dc_context *ctx, uint32_t inst)
816 {
817 struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
818
819 if (!dce_i2c_hw)
820 return NULL;
821
822 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
823
824 return dce_i2c_hw;
825 }
826
827 static const struct encoder_feature_support link_enc_feature = {
828 .max_hdmi_deep_color = COLOR_DEPTH_121212,
829 .max_hdmi_pixel_clock = 600000,
830 .hdmi_ycbcr420_supported = true,
831 .dp_ycbcr420_supported = true,
832 .fec_supported = true,
833 .flags.bits.IS_HBR2_CAPABLE = true,
834 .flags.bits.IS_HBR3_CAPABLE = true,
835 .flags.bits.IS_TPS3_CAPABLE = true,
836 .flags.bits.IS_TPS4_CAPABLE = true
837 };
838
839 #define link_regs(id, phyid)\
840 [id] = {\
841 LE_DCN3_REG_LIST(id), \
842 UNIPHY_DCN2_REG_LIST(phyid), \
843 DPCS_DCN2_REG_LIST(id), \
844 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
845 }
846
847 static const struct dcn10_link_enc_registers link_enc_regs[] = {
848 link_regs(0, A),
849 link_regs(1, B),
850 link_regs(2, C),
851 link_regs(3, D),
852 link_regs(4, E)
853 };
854
855 static const struct dcn10_link_enc_shift le_shift = {
856 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),
857 DPCS_DCN2_MASK_SH_LIST(__SHIFT)
858 };
859
860 static const struct dcn10_link_enc_mask le_mask = {
861 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),
862 DPCS_DCN2_MASK_SH_LIST(_MASK)
863 };
864
865 #define aux_regs(id)\
866 [id] = { DCN2_AUX_REG_LIST(id) }
867
868 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
869 aux_regs(0),
870 aux_regs(1),
871 aux_regs(2),
872 aux_regs(3),
873 aux_regs(4)
874 };
875
876 #define hpd_regs(id)\
877 [id] = { HPD_REG_LIST(id) }
878
879 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
880 hpd_regs(0),
881 hpd_regs(1),
882 hpd_regs(2),
883 hpd_regs(3),
884 hpd_regs(4)
885 };
886
dcn302_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)887 static struct link_encoder *dcn302_link_encoder_create(
888 struct dc_context *ctx,
889 const struct encoder_init_data *enc_init_data)
890 {
891 struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
892
893 if (!enc20)
894 return NULL;
895
896 dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature,
897 &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1],
898 &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask);
899
900 return &enc20->enc10.base;
901 }
902
903 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
904 { DCN_PANEL_CNTL_REG_LIST() }
905 };
906
907 static const struct dce_panel_cntl_shift panel_cntl_shift = {
908 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
909 };
910
911 static const struct dce_panel_cntl_mask panel_cntl_mask = {
912 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
913 };
914
dcn302_panel_cntl_create(const struct panel_cntl_init_data * init_data)915 static struct panel_cntl *dcn302_panel_cntl_create(const struct panel_cntl_init_data *init_data)
916 {
917 struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
918
919 if (!panel_cntl)
920 return NULL;
921
922 dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst],
923 &panel_cntl_shift, &panel_cntl_mask);
924
925 return &panel_cntl->base;
926 }
927
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)928 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps)
929 {
930 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
931 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
932 }
933
934 static const struct resource_create_funcs res_create_funcs = {
935 .read_dce_straps = read_dce_straps,
936 .create_audio = dcn302_create_audio,
937 .create_stream_encoder = dcn302_stream_encoder_create,
938 .create_hwseq = dcn302_hwseq_create,
939 };
940
is_soc_bounding_box_valid(struct dc * dc)941 static bool is_soc_bounding_box_valid(struct dc *dc)
942 {
943 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
944
945 if (ASICREV_IS_DIMGREY_CAVEFISH_P(hw_internal_rev))
946 return true;
947
948 return false;
949 }
950
init_soc_bounding_box(struct dc * dc,struct resource_pool * pool)951 static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool)
952 {
953 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_02_soc;
954 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_02_ip;
955
956 DC_LOGGER_INIT(dc->ctx->logger);
957
958 if (!is_soc_bounding_box_valid(dc)) {
959 DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
960 return false;
961 }
962
963 loaded_ip->max_num_otg = pool->pipe_count;
964 loaded_ip->max_num_dpp = pool->pipe_count;
965 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
966 DC_FP_START();
967 dcn20_patch_bounding_box(dc, loaded_bb);
968 DC_FP_END();
969
970 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
971 struct bp_soc_bb_info bb_info = { 0 };
972
973 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(
974 dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
975
976 DC_FP_START();
977 dcn302_fpu_init_soc_bounding_box(bb_info);
978 DC_FP_END();
979 }
980 }
981
982 return true;
983 }
984
dcn302_resource_destruct(struct resource_pool * pool)985 static void dcn302_resource_destruct(struct resource_pool *pool)
986 {
987 unsigned int i;
988
989 for (i = 0; i < pool->stream_enc_count; i++) {
990 if (pool->stream_enc[i] != NULL) {
991 if (pool->stream_enc[i]->vpg != NULL) {
992 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg));
993 pool->stream_enc[i]->vpg = NULL;
994 }
995 if (pool->stream_enc[i]->afmt != NULL) {
996 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt));
997 pool->stream_enc[i]->afmt = NULL;
998 }
999 kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i]));
1000 pool->stream_enc[i] = NULL;
1001 }
1002 }
1003
1004 for (i = 0; i < pool->res_cap->num_dsc; i++) {
1005 if (pool->dscs[i] != NULL)
1006 dcn20_dsc_destroy(&pool->dscs[i]);
1007 }
1008
1009 if (pool->mpc != NULL) {
1010 kfree(TO_DCN20_MPC(pool->mpc));
1011 pool->mpc = NULL;
1012 }
1013
1014 if (pool->hubbub != NULL) {
1015 kfree(pool->hubbub);
1016 pool->hubbub = NULL;
1017 }
1018
1019 for (i = 0; i < pool->pipe_count; i++) {
1020 if (pool->dpps[i] != NULL) {
1021 kfree(TO_DCN20_DPP(pool->dpps[i]));
1022 pool->dpps[i] = NULL;
1023 }
1024
1025 if (pool->hubps[i] != NULL) {
1026 kfree(TO_DCN20_HUBP(pool->hubps[i]));
1027 pool->hubps[i] = NULL;
1028 }
1029
1030 if (pool->irqs != NULL)
1031 dal_irq_service_destroy(&pool->irqs);
1032 }
1033
1034 for (i = 0; i < pool->res_cap->num_ddc; i++) {
1035 if (pool->engines[i] != NULL)
1036 dce110_engine_destroy(&pool->engines[i]);
1037 if (pool->hw_i2cs[i] != NULL) {
1038 kfree(pool->hw_i2cs[i]);
1039 pool->hw_i2cs[i] = NULL;
1040 }
1041 if (pool->sw_i2cs[i] != NULL) {
1042 kfree(pool->sw_i2cs[i]);
1043 pool->sw_i2cs[i] = NULL;
1044 }
1045 }
1046
1047 for (i = 0; i < pool->res_cap->num_opp; i++) {
1048 if (pool->opps[i] != NULL)
1049 pool->opps[i]->funcs->opp_destroy(&pool->opps[i]);
1050 }
1051
1052 for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1053 if (pool->timing_generators[i] != NULL) {
1054 kfree(DCN10TG_FROM_TG(pool->timing_generators[i]));
1055 pool->timing_generators[i] = NULL;
1056 }
1057 }
1058
1059 for (i = 0; i < pool->res_cap->num_dwb; i++) {
1060 if (pool->dwbc[i] != NULL) {
1061 kfree(TO_DCN30_DWBC(pool->dwbc[i]));
1062 pool->dwbc[i] = NULL;
1063 }
1064 if (pool->mcif_wb[i] != NULL) {
1065 kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i]));
1066 pool->mcif_wb[i] = NULL;
1067 }
1068 }
1069
1070 for (i = 0; i < pool->audio_count; i++) {
1071 if (pool->audios[i])
1072 dce_aud_destroy(&pool->audios[i]);
1073 }
1074
1075 for (i = 0; i < pool->clk_src_count; i++) {
1076 if (pool->clock_sources[i] != NULL)
1077 dcn20_clock_source_destroy(&pool->clock_sources[i]);
1078 }
1079
1080 if (pool->dp_clock_source != NULL)
1081 dcn20_clock_source_destroy(&pool->dp_clock_source);
1082
1083 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1084 if (pool->mpc_lut[i] != NULL) {
1085 dc_3dlut_func_release(pool->mpc_lut[i]);
1086 pool->mpc_lut[i] = NULL;
1087 }
1088 if (pool->mpc_shaper[i] != NULL) {
1089 dc_transfer_func_release(pool->mpc_shaper[i]);
1090 pool->mpc_shaper[i] = NULL;
1091 }
1092 }
1093
1094 for (i = 0; i < pool->pipe_count; i++) {
1095 if (pool->multiple_abms[i] != NULL)
1096 dce_abm_destroy(&pool->multiple_abms[i]);
1097 }
1098
1099 if (pool->psr != NULL)
1100 dmub_psr_destroy(&pool->psr);
1101
1102 if (pool->dccg != NULL)
1103 dcn_dccg_destroy(&pool->dccg);
1104
1105 if (pool->oem_device != NULL) {
1106 struct dc *dc = pool->oem_device->ctx->dc;
1107
1108 dc->link_srv->destroy_ddc_service(&pool->oem_device);
1109 }
1110 }
1111
dcn302_destroy_resource_pool(struct resource_pool ** pool)1112 static void dcn302_destroy_resource_pool(struct resource_pool **pool)
1113 {
1114 dcn302_resource_destruct(*pool);
1115 kfree(*pool);
1116 *pool = NULL;
1117 }
1118
dcn302_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1119 void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1120 {
1121 DC_FP_START();
1122 dcn302_fpu_update_bw_bounding_box(dc, bw_params);
1123 DC_FP_END();
1124 }
1125
dcn302_get_panel_config_defaults(struct dc_panel_config * panel_config)1126 static void dcn302_get_panel_config_defaults(struct dc_panel_config *panel_config)
1127 {
1128 *panel_config = panel_config_defaults;
1129 }
1130
1131 static struct resource_funcs dcn302_res_pool_funcs = {
1132 .destroy = dcn302_destroy_resource_pool,
1133 .link_enc_create = dcn302_link_encoder_create,
1134 .panel_cntl_create = dcn302_panel_cntl_create,
1135 .validate_bandwidth = dcn30_validate_bandwidth,
1136 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
1137 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1138 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
1139 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1140 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1141 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1142 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1143 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1144 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1145 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1146 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1147 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1148 .update_bw_bounding_box = dcn302_update_bw_bounding_box,
1149 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1150 .get_panel_config_defaults = dcn302_get_panel_config_defaults,
1151 };
1152
1153 static struct dc_cap_funcs cap_funcs = {
1154 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1155 };
1156
1157 static const struct bios_registers bios_regs = {
1158 NBIO_SR(BIOS_SCRATCH_3),
1159 NBIO_SR(BIOS_SCRATCH_6)
1160 };
1161
1162 static const struct dccg_registers dccg_regs = {
1163 DCCG_REG_LIST_DCN3_02()
1164 };
1165
1166 static const struct dccg_shift dccg_shift = {
1167 DCCG_MASK_SH_LIST_DCN3_02(__SHIFT)
1168 };
1169
1170 static const struct dccg_mask dccg_mask = {
1171 DCCG_MASK_SH_LIST_DCN3_02(_MASK)
1172 };
1173
1174 #define abm_regs(id)\
1175 [id] = { ABM_DCN302_REG_LIST(id) }
1176
1177 static const struct dce_abm_registers abm_regs[] = {
1178 abm_regs(0),
1179 abm_regs(1),
1180 abm_regs(2),
1181 abm_regs(3),
1182 abm_regs(4)
1183 };
1184
1185 static const struct dce_abm_shift abm_shift = {
1186 ABM_MASK_SH_LIST_DCN30(__SHIFT)
1187 };
1188
1189 static const struct dce_abm_mask abm_mask = {
1190 ABM_MASK_SH_LIST_DCN30(_MASK)
1191 };
1192
dcn302_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct resource_pool * pool)1193 static bool dcn302_resource_construct(
1194 uint8_t num_virtual_links,
1195 struct dc *dc,
1196 struct resource_pool *pool)
1197 {
1198 int i;
1199 struct dc_context *ctx = dc->ctx;
1200 struct irq_service_init_data init_data;
1201 struct ddc_service_init_data ddc_init_data = {0};
1202
1203 ctx->dc_bios->regs = &bios_regs;
1204
1205 pool->res_cap = &res_cap_dcn302;
1206
1207 pool->funcs = &dcn302_res_pool_funcs;
1208
1209 /*************************************************
1210 * Resource + asic cap harcoding *
1211 *************************************************/
1212 pool->underlay_pipe_index = NO_UNDERLAY_PIPE;
1213 pool->pipe_count = pool->res_cap->num_timing_generator;
1214 pool->mpcc_count = pool->res_cap->num_timing_generator;
1215 dc->caps.max_downscale_ratio = 600;
1216 dc->caps.i2c_speed_in_khz = 100;
1217 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/
1218 dc->caps.max_cursor_size = 256;
1219 dc->caps.min_horizontal_blanking_period = 80;
1220 dc->caps.dmdata_alloc_size = 2048;
1221 dc->caps.mall_size_per_mem_channel = 4;
1222 /* total size = mall per channel * num channels * 1024 * 1024 */
1223 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
1224 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
1225 dc->caps.max_slave_planes = 2;
1226 dc->caps.max_slave_yuv_planes = 2;
1227 dc->caps.max_slave_rgb_planes = 2;
1228 dc->caps.post_blend_color_processing = true;
1229 dc->caps.force_dp_tps4_for_cp2520 = true;
1230 dc->caps.extended_aux_timeout_support = true;
1231 dc->caps.dmcub_support = true;
1232 dc->caps.max_v_total = (1 << 15) - 1;
1233
1234 /* Color pipeline capabilities */
1235 dc->caps.color.dpp.dcn_arch = 1;
1236 dc->caps.color.dpp.input_lut_shared = 0;
1237 dc->caps.color.dpp.icsc = 1;
1238 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1239 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1240 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1241 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1242 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1243 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1244 dc->caps.color.dpp.post_csc = 1;
1245 dc->caps.color.dpp.gamma_corr = 1;
1246 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1247
1248 dc->caps.color.dpp.hw_3d_lut = 1;
1249 dc->caps.color.dpp.ogam_ram = 1;
1250 // no OGAM ROM on DCN3
1251 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1252 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1253 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1254 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1255 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1256 dc->caps.color.dpp.ocsc = 0;
1257
1258 dc->caps.color.mpc.gamut_remap = 1;
1259 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3
1260 dc->caps.color.mpc.ogam_ram = 1;
1261 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1262 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1263 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1264 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1265 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1266 dc->caps.color.mpc.ocsc = 1;
1267
1268 dc->caps.dp_hdmi21_pcon_support = true;
1269
1270 /* read VBIOS LTTPR caps */
1271 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1272 enum bp_result bp_query_result;
1273 uint8_t is_vbios_lttpr_enable = 0;
1274
1275 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1276 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1277 }
1278
1279 if (ctx->dc_bios->funcs->get_lttpr_interop) {
1280 enum bp_result bp_query_result;
1281 uint8_t is_vbios_interop_enabled = 0;
1282
1283 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios,
1284 &is_vbios_interop_enabled);
1285 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
1286 }
1287
1288 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1289 dc->debug = debug_defaults_drv;
1290
1291 // Init the vm_helper
1292 if (dc->vm_helper)
1293 vm_helper_init(dc->vm_helper, 16);
1294
1295 /*************************************************
1296 * Create resources *
1297 *************************************************/
1298
1299 /* Clock Sources for Pixel Clock*/
1300 pool->clock_sources[DCN302_CLK_SRC_PLL0] =
1301 dcn302_clock_source_create(ctx, ctx->dc_bios,
1302 CLOCK_SOURCE_COMBO_PHY_PLL0,
1303 &clk_src_regs[0], false);
1304 pool->clock_sources[DCN302_CLK_SRC_PLL1] =
1305 dcn302_clock_source_create(ctx, ctx->dc_bios,
1306 CLOCK_SOURCE_COMBO_PHY_PLL1,
1307 &clk_src_regs[1], false);
1308 pool->clock_sources[DCN302_CLK_SRC_PLL2] =
1309 dcn302_clock_source_create(ctx, ctx->dc_bios,
1310 CLOCK_SOURCE_COMBO_PHY_PLL2,
1311 &clk_src_regs[2], false);
1312 pool->clock_sources[DCN302_CLK_SRC_PLL3] =
1313 dcn302_clock_source_create(ctx, ctx->dc_bios,
1314 CLOCK_SOURCE_COMBO_PHY_PLL3,
1315 &clk_src_regs[3], false);
1316 pool->clock_sources[DCN302_CLK_SRC_PLL4] =
1317 dcn302_clock_source_create(ctx, ctx->dc_bios,
1318 CLOCK_SOURCE_COMBO_PHY_PLL4,
1319 &clk_src_regs[4], false);
1320
1321 pool->clk_src_count = DCN302_CLK_SRC_TOTAL;
1322
1323 /* todo: not reuse phy_pll registers */
1324 pool->dp_clock_source =
1325 dcn302_clock_source_create(ctx, ctx->dc_bios,
1326 CLOCK_SOURCE_ID_DP_DTO,
1327 &clk_src_regs[0], true);
1328
1329 for (i = 0; i < pool->clk_src_count; i++) {
1330 if (pool->clock_sources[i] == NULL) {
1331 dm_error("DC: failed to create clock sources!\n");
1332 BREAK_TO_DEBUGGER();
1333 goto create_fail;
1334 }
1335 }
1336
1337 /* DCCG */
1338 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1339 if (pool->dccg == NULL) {
1340 dm_error("DC: failed to create dccg!\n");
1341 BREAK_TO_DEBUGGER();
1342 goto create_fail;
1343 }
1344
1345 /* PP Lib and SMU interfaces */
1346 init_soc_bounding_box(dc, pool);
1347
1348 /* DML */
1349 dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30);
1350
1351 /* IRQ */
1352 init_data.ctx = dc->ctx;
1353 pool->irqs = dal_irq_service_dcn302_create(&init_data);
1354 if (!pool->irqs)
1355 goto create_fail;
1356
1357 /* HUBBUB */
1358 pool->hubbub = dcn302_hubbub_create(ctx);
1359 if (pool->hubbub == NULL) {
1360 BREAK_TO_DEBUGGER();
1361 dm_error("DC: failed to create hubbub!\n");
1362 goto create_fail;
1363 }
1364
1365 /* HUBPs, DPPs, OPPs and TGs */
1366 for (i = 0; i < pool->pipe_count; i++) {
1367 pool->hubps[i] = dcn302_hubp_create(ctx, i);
1368 if (pool->hubps[i] == NULL) {
1369 BREAK_TO_DEBUGGER();
1370 dm_error("DC: failed to create hubps!\n");
1371 goto create_fail;
1372 }
1373
1374 pool->dpps[i] = dcn302_dpp_create(ctx, i);
1375 if (pool->dpps[i] == NULL) {
1376 BREAK_TO_DEBUGGER();
1377 dm_error("DC: failed to create dpps!\n");
1378 goto create_fail;
1379 }
1380 }
1381
1382 for (i = 0; i < pool->res_cap->num_opp; i++) {
1383 pool->opps[i] = dcn302_opp_create(ctx, i);
1384 if (pool->opps[i] == NULL) {
1385 BREAK_TO_DEBUGGER();
1386 dm_error("DC: failed to create output pixel processor!\n");
1387 goto create_fail;
1388 }
1389 }
1390
1391 for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1392 pool->timing_generators[i] = dcn302_timing_generator_create(ctx, i);
1393 if (pool->timing_generators[i] == NULL) {
1394 BREAK_TO_DEBUGGER();
1395 dm_error("DC: failed to create tg!\n");
1396 goto create_fail;
1397 }
1398 }
1399 pool->timing_generator_count = i;
1400
1401 /* PSR */
1402 pool->psr = dmub_psr_create(ctx);
1403 if (pool->psr == NULL) {
1404 dm_error("DC: failed to create psr!\n");
1405 BREAK_TO_DEBUGGER();
1406 goto create_fail;
1407 }
1408
1409 /* ABMs */
1410 for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1411 pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask);
1412 if (pool->multiple_abms[i] == NULL) {
1413 dm_error("DC: failed to create abm for pipe %d!\n", i);
1414 BREAK_TO_DEBUGGER();
1415 goto create_fail;
1416 }
1417 }
1418
1419 /* MPC and DSC */
1420 pool->mpc = dcn302_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut);
1421 if (pool->mpc == NULL) {
1422 BREAK_TO_DEBUGGER();
1423 dm_error("DC: failed to create mpc!\n");
1424 goto create_fail;
1425 }
1426
1427 for (i = 0; i < pool->res_cap->num_dsc; i++) {
1428 pool->dscs[i] = dcn302_dsc_create(ctx, i);
1429 if (pool->dscs[i] == NULL) {
1430 BREAK_TO_DEBUGGER();
1431 dm_error("DC: failed to create display stream compressor %d!\n", i);
1432 goto create_fail;
1433 }
1434 }
1435
1436 /* DWB and MMHUBBUB */
1437 if (!dcn302_dwbc_create(ctx, pool)) {
1438 BREAK_TO_DEBUGGER();
1439 dm_error("DC: failed to create dwbc!\n");
1440 goto create_fail;
1441 }
1442
1443 if (!dcn302_mmhubbub_create(ctx, pool)) {
1444 BREAK_TO_DEBUGGER();
1445 dm_error("DC: failed to create mcif_wb!\n");
1446 goto create_fail;
1447 }
1448
1449 /* AUX and I2C */
1450 for (i = 0; i < pool->res_cap->num_ddc; i++) {
1451 pool->engines[i] = dcn302_aux_engine_create(ctx, i);
1452 if (pool->engines[i] == NULL) {
1453 BREAK_TO_DEBUGGER();
1454 dm_error("DC:failed to create aux engine!!\n");
1455 goto create_fail;
1456 }
1457 pool->hw_i2cs[i] = dcn302_i2c_hw_create(ctx, i);
1458 if (pool->hw_i2cs[i] == NULL) {
1459 BREAK_TO_DEBUGGER();
1460 dm_error("DC:failed to create hw i2c!!\n");
1461 goto create_fail;
1462 }
1463 pool->sw_i2cs[i] = NULL;
1464 }
1465
1466 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
1467 if (!resource_construct(num_virtual_links, dc, pool,
1468 &res_create_funcs))
1469 goto create_fail;
1470
1471 /* HW Sequencer and Plane caps */
1472 dcn302_hw_sequencer_construct(dc);
1473
1474 dc->caps.max_planes = pool->pipe_count;
1475
1476 for (i = 0; i < dc->caps.max_planes; ++i)
1477 dc->caps.planes[i] = plane_cap;
1478
1479 dc->cap_funcs = cap_funcs;
1480
1481 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
1482 ddc_init_data.ctx = dc->ctx;
1483 ddc_init_data.link = NULL;
1484 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
1485 ddc_init_data.id.enum_id = 0;
1486 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
1487 pool->oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
1488 } else {
1489 pool->oem_device = NULL;
1490 }
1491
1492 return true;
1493
1494 create_fail:
1495
1496 dcn302_resource_destruct(pool);
1497
1498 return false;
1499 }
1500
dcn302_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)1501 struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc)
1502 {
1503 struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL);
1504
1505 if (!pool)
1506 return NULL;
1507
1508 if (dcn302_resource_construct(init_data->num_virtual_links, dc, pool))
1509 return pool;
1510
1511 BREAK_TO_DEBUGGER();
1512 kfree(pool);
1513 return NULL;
1514 }
1515
