1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 * Copyright 2019 Raptor Engineering, LLC
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include <linux/slab.h>
28
29 #include "dm_services.h"
30 #include "dc.h"
31
32 #include "dcn20_init.h"
33
34 #include "resource.h"
35 #include "include/irq_service_interface.h"
36 #include "dcn20/dcn20_resource.h"
37
38 #include "dcn10/dcn10_hubp.h"
39 #include "dcn10/dcn10_ipp.h"
40 #include "dcn20_hubbub.h"
41 #include "dcn20_mpc.h"
42 #include "dcn20_hubp.h"
43 #include "irq/dcn20/irq_service_dcn20.h"
44 #include "dcn20_dpp.h"
45 #include "dcn20_optc.h"
46 #include "dcn20_hwseq.h"
47 #include "dce110/dce110_hw_sequencer.h"
48 #include "dcn10/dcn10_resource.h"
49 #include "dcn20_opp.h"
50
51 #include "dcn20_dsc.h"
52
53 #include "dcn20_link_encoder.h"
54 #include "dcn20_stream_encoder.h"
55 #include "dce/dce_clock_source.h"
56 #include "dce/dce_audio.h"
57 #include "dce/dce_hwseq.h"
58 #include "virtual/virtual_stream_encoder.h"
59 #include "dce110/dce110_resource.h"
60 #include "dml/display_mode_vba.h"
61 #include "dcn20_dccg.h"
62 #include "dcn20_vmid.h"
63 #include "dc_link_ddc.h"
64 #include "dce/dce_panel_cntl.h"
65
66 #include "navi10_ip_offset.h"
67
68 #include "dcn/dcn_2_0_0_offset.h"
69 #include "dcn/dcn_2_0_0_sh_mask.h"
70 #include "dpcs/dpcs_2_0_0_offset.h"
71 #include "dpcs/dpcs_2_0_0_sh_mask.h"
72
73 #include "nbio/nbio_2_3_offset.h"
74
75 #include "dcn20/dcn20_dwb.h"
76 #include "dcn20/dcn20_mmhubbub.h"
77
78 #include "mmhub/mmhub_2_0_0_offset.h"
79 #include "mmhub/mmhub_2_0_0_sh_mask.h"
80
81 #include "reg_helper.h"
82 #include "dce/dce_abm.h"
83 #include "dce/dce_dmcu.h"
84 #include "dce/dce_aux.h"
85 #include "dce/dce_i2c.h"
86 #include "vm_helper.h"
87
88 #include "amdgpu_socbb.h"
89
90 #define DC_LOGGER_INIT(logger)
91
92 struct _vcs_dpi_ip_params_st dcn2_0_ip = {
93 .odm_capable = 1,
94 .gpuvm_enable = 0,
95 .hostvm_enable = 0,
96 .gpuvm_max_page_table_levels = 4,
97 .hostvm_max_page_table_levels = 4,
98 .hostvm_cached_page_table_levels = 0,
99 .pte_group_size_bytes = 2048,
100 .num_dsc = 6,
101 .rob_buffer_size_kbytes = 168,
102 .det_buffer_size_kbytes = 164,
103 .dpte_buffer_size_in_pte_reqs_luma = 84,
104 .pde_proc_buffer_size_64k_reqs = 48,
105 .dpp_output_buffer_pixels = 2560,
106 .opp_output_buffer_lines = 1,
107 .pixel_chunk_size_kbytes = 8,
108 .pte_chunk_size_kbytes = 2,
109 .meta_chunk_size_kbytes = 2,
110 .writeback_chunk_size_kbytes = 2,
111 .line_buffer_size_bits = 789504,
112 .is_line_buffer_bpp_fixed = 0,
113 .line_buffer_fixed_bpp = 0,
114 .dcc_supported = true,
115 .max_line_buffer_lines = 12,
116 .writeback_luma_buffer_size_kbytes = 12,
117 .writeback_chroma_buffer_size_kbytes = 8,
118 .writeback_chroma_line_buffer_width_pixels = 4,
119 .writeback_max_hscl_ratio = 1,
120 .writeback_max_vscl_ratio = 1,
121 .writeback_min_hscl_ratio = 1,
122 .writeback_min_vscl_ratio = 1,
123 .writeback_max_hscl_taps = 12,
124 .writeback_max_vscl_taps = 12,
125 .writeback_line_buffer_luma_buffer_size = 0,
126 .writeback_line_buffer_chroma_buffer_size = 14643,
127 .cursor_buffer_size = 8,
128 .cursor_chunk_size = 2,
129 .max_num_otg = 6,
130 .max_num_dpp = 6,
131 .max_num_wb = 1,
132 .max_dchub_pscl_bw_pix_per_clk = 4,
133 .max_pscl_lb_bw_pix_per_clk = 2,
134 .max_lb_vscl_bw_pix_per_clk = 4,
135 .max_vscl_hscl_bw_pix_per_clk = 4,
136 .max_hscl_ratio = 8,
137 .max_vscl_ratio = 8,
138 .hscl_mults = 4,
139 .vscl_mults = 4,
140 .max_hscl_taps = 8,
141 .max_vscl_taps = 8,
142 .dispclk_ramp_margin_percent = 1,
143 .underscan_factor = 1.10,
144 .min_vblank_lines = 32, //
145 .dppclk_delay_subtotal = 77, //
146 .dppclk_delay_scl_lb_only = 16,
147 .dppclk_delay_scl = 50,
148 .dppclk_delay_cnvc_formatter = 8,
149 .dppclk_delay_cnvc_cursor = 6,
150 .dispclk_delay_subtotal = 87, //
151 .dcfclk_cstate_latency = 10, // SRExitTime
152 .max_inter_dcn_tile_repeaters = 8,
153 .xfc_supported = true,
154 .xfc_fill_bw_overhead_percent = 10.0,
155 .xfc_fill_constant_bytes = 0,
156 .number_of_cursors = 1,
157 };
158
159 static struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = {
160 .odm_capable = 1,
161 .gpuvm_enable = 0,
162 .hostvm_enable = 0,
163 .gpuvm_max_page_table_levels = 4,
164 .hostvm_max_page_table_levels = 4,
165 .hostvm_cached_page_table_levels = 0,
166 .num_dsc = 5,
167 .rob_buffer_size_kbytes = 168,
168 .det_buffer_size_kbytes = 164,
169 .dpte_buffer_size_in_pte_reqs_luma = 84,
170 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
171 .dpp_output_buffer_pixels = 2560,
172 .opp_output_buffer_lines = 1,
173 .pixel_chunk_size_kbytes = 8,
174 .pte_enable = 1,
175 .max_page_table_levels = 4,
176 .pte_chunk_size_kbytes = 2,
177 .meta_chunk_size_kbytes = 2,
178 .writeback_chunk_size_kbytes = 2,
179 .line_buffer_size_bits = 789504,
180 .is_line_buffer_bpp_fixed = 0,
181 .line_buffer_fixed_bpp = 0,
182 .dcc_supported = true,
183 .max_line_buffer_lines = 12,
184 .writeback_luma_buffer_size_kbytes = 12,
185 .writeback_chroma_buffer_size_kbytes = 8,
186 .writeback_chroma_line_buffer_width_pixels = 4,
187 .writeback_max_hscl_ratio = 1,
188 .writeback_max_vscl_ratio = 1,
189 .writeback_min_hscl_ratio = 1,
190 .writeback_min_vscl_ratio = 1,
191 .writeback_max_hscl_taps = 12,
192 .writeback_max_vscl_taps = 12,
193 .writeback_line_buffer_luma_buffer_size = 0,
194 .writeback_line_buffer_chroma_buffer_size = 14643,
195 .cursor_buffer_size = 8,
196 .cursor_chunk_size = 2,
197 .max_num_otg = 5,
198 .max_num_dpp = 5,
199 .max_num_wb = 1,
200 .max_dchub_pscl_bw_pix_per_clk = 4,
201 .max_pscl_lb_bw_pix_per_clk = 2,
202 .max_lb_vscl_bw_pix_per_clk = 4,
203 .max_vscl_hscl_bw_pix_per_clk = 4,
204 .max_hscl_ratio = 8,
205 .max_vscl_ratio = 8,
206 .hscl_mults = 4,
207 .vscl_mults = 4,
208 .max_hscl_taps = 8,
209 .max_vscl_taps = 8,
210 .dispclk_ramp_margin_percent = 1,
211 .underscan_factor = 1.10,
212 .min_vblank_lines = 32, //
213 .dppclk_delay_subtotal = 77, //
214 .dppclk_delay_scl_lb_only = 16,
215 .dppclk_delay_scl = 50,
216 .dppclk_delay_cnvc_formatter = 8,
217 .dppclk_delay_cnvc_cursor = 6,
218 .dispclk_delay_subtotal = 87, //
219 .dcfclk_cstate_latency = 10, // SRExitTime
220 .max_inter_dcn_tile_repeaters = 8,
221 .xfc_supported = true,
222 .xfc_fill_bw_overhead_percent = 10.0,
223 .xfc_fill_constant_bytes = 0,
224 .ptoi_supported = 0,
225 .number_of_cursors = 1,
226 };
227
228 static struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
229 /* Defaults that get patched on driver load from firmware. */
230 .clock_limits = {
231 {
232 .state = 0,
233 .dcfclk_mhz = 560.0,
234 .fabricclk_mhz = 560.0,
235 .dispclk_mhz = 513.0,
236 .dppclk_mhz = 513.0,
237 .phyclk_mhz = 540.0,
238 .socclk_mhz = 560.0,
239 .dscclk_mhz = 171.0,
240 .dram_speed_mts = 8960.0,
241 },
242 {
243 .state = 1,
244 .dcfclk_mhz = 694.0,
245 .fabricclk_mhz = 694.0,
246 .dispclk_mhz = 642.0,
247 .dppclk_mhz = 642.0,
248 .phyclk_mhz = 600.0,
249 .socclk_mhz = 694.0,
250 .dscclk_mhz = 214.0,
251 .dram_speed_mts = 11104.0,
252 },
253 {
254 .state = 2,
255 .dcfclk_mhz = 875.0,
256 .fabricclk_mhz = 875.0,
257 .dispclk_mhz = 734.0,
258 .dppclk_mhz = 734.0,
259 .phyclk_mhz = 810.0,
260 .socclk_mhz = 875.0,
261 .dscclk_mhz = 245.0,
262 .dram_speed_mts = 14000.0,
263 },
264 {
265 .state = 3,
266 .dcfclk_mhz = 1000.0,
267 .fabricclk_mhz = 1000.0,
268 .dispclk_mhz = 1100.0,
269 .dppclk_mhz = 1100.0,
270 .phyclk_mhz = 810.0,
271 .socclk_mhz = 1000.0,
272 .dscclk_mhz = 367.0,
273 .dram_speed_mts = 16000.0,
274 },
275 {
276 .state = 4,
277 .dcfclk_mhz = 1200.0,
278 .fabricclk_mhz = 1200.0,
279 .dispclk_mhz = 1284.0,
280 .dppclk_mhz = 1284.0,
281 .phyclk_mhz = 810.0,
282 .socclk_mhz = 1200.0,
283 .dscclk_mhz = 428.0,
284 .dram_speed_mts = 16000.0,
285 },
286 /*Extra state, no dispclk ramping*/
287 {
288 .state = 5,
289 .dcfclk_mhz = 1200.0,
290 .fabricclk_mhz = 1200.0,
291 .dispclk_mhz = 1284.0,
292 .dppclk_mhz = 1284.0,
293 .phyclk_mhz = 810.0,
294 .socclk_mhz = 1200.0,
295 .dscclk_mhz = 428.0,
296 .dram_speed_mts = 16000.0,
297 },
298 },
299 .num_states = 5,
300 .sr_exit_time_us = 11.6,
301 .sr_enter_plus_exit_time_us = 13.9,
302 .urgent_latency_us = 4.0,
303 .urgent_latency_pixel_data_only_us = 4.0,
304 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
305 .urgent_latency_vm_data_only_us = 4.0,
306 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
307 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
308 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
309 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
310 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
311 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
312 .max_avg_sdp_bw_use_normal_percent = 40.0,
313 .max_avg_dram_bw_use_normal_percent = 40.0,
314 .writeback_latency_us = 12.0,
315 .ideal_dram_bw_after_urgent_percent = 40.0,
316 .max_request_size_bytes = 256,
317 .dram_channel_width_bytes = 2,
318 .fabric_datapath_to_dcn_data_return_bytes = 64,
319 .dcn_downspread_percent = 0.5,
320 .downspread_percent = 0.38,
321 .dram_page_open_time_ns = 50.0,
322 .dram_rw_turnaround_time_ns = 17.5,
323 .dram_return_buffer_per_channel_bytes = 8192,
324 .round_trip_ping_latency_dcfclk_cycles = 131,
325 .urgent_out_of_order_return_per_channel_bytes = 256,
326 .channel_interleave_bytes = 256,
327 .num_banks = 8,
328 .num_chans = 16,
329 .vmm_page_size_bytes = 4096,
330 .dram_clock_change_latency_us = 404.0,
331 .dummy_pstate_latency_us = 5.0,
332 .writeback_dram_clock_change_latency_us = 23.0,
333 .return_bus_width_bytes = 64,
334 .dispclk_dppclk_vco_speed_mhz = 3850,
335 .xfc_bus_transport_time_us = 20,
336 .xfc_xbuf_latency_tolerance_us = 4,
337 .use_urgent_burst_bw = 0
338 };
339
340 static struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc = {
341 .clock_limits = {
342 {
343 .state = 0,
344 .dcfclk_mhz = 560.0,
345 .fabricclk_mhz = 560.0,
346 .dispclk_mhz = 513.0,
347 .dppclk_mhz = 513.0,
348 .phyclk_mhz = 540.0,
349 .socclk_mhz = 560.0,
350 .dscclk_mhz = 171.0,
351 .dram_speed_mts = 8960.0,
352 },
353 {
354 .state = 1,
355 .dcfclk_mhz = 694.0,
356 .fabricclk_mhz = 694.0,
357 .dispclk_mhz = 642.0,
358 .dppclk_mhz = 642.0,
359 .phyclk_mhz = 600.0,
360 .socclk_mhz = 694.0,
361 .dscclk_mhz = 214.0,
362 .dram_speed_mts = 11104.0,
363 },
364 {
365 .state = 2,
366 .dcfclk_mhz = 875.0,
367 .fabricclk_mhz = 875.0,
368 .dispclk_mhz = 734.0,
369 .dppclk_mhz = 734.0,
370 .phyclk_mhz = 810.0,
371 .socclk_mhz = 875.0,
372 .dscclk_mhz = 245.0,
373 .dram_speed_mts = 14000.0,
374 },
375 {
376 .state = 3,
377 .dcfclk_mhz = 1000.0,
378 .fabricclk_mhz = 1000.0,
379 .dispclk_mhz = 1100.0,
380 .dppclk_mhz = 1100.0,
381 .phyclk_mhz = 810.0,
382 .socclk_mhz = 1000.0,
383 .dscclk_mhz = 367.0,
384 .dram_speed_mts = 16000.0,
385 },
386 {
387 .state = 4,
388 .dcfclk_mhz = 1200.0,
389 .fabricclk_mhz = 1200.0,
390 .dispclk_mhz = 1284.0,
391 .dppclk_mhz = 1284.0,
392 .phyclk_mhz = 810.0,
393 .socclk_mhz = 1200.0,
394 .dscclk_mhz = 428.0,
395 .dram_speed_mts = 16000.0,
396 },
397 /*Extra state, no dispclk ramping*/
398 {
399 .state = 5,
400 .dcfclk_mhz = 1200.0,
401 .fabricclk_mhz = 1200.0,
402 .dispclk_mhz = 1284.0,
403 .dppclk_mhz = 1284.0,
404 .phyclk_mhz = 810.0,
405 .socclk_mhz = 1200.0,
406 .dscclk_mhz = 428.0,
407 .dram_speed_mts = 16000.0,
408 },
409 },
410 .num_states = 5,
411 .sr_exit_time_us = 11.6,
412 .sr_enter_plus_exit_time_us = 13.9,
413 .urgent_latency_us = 4.0,
414 .urgent_latency_pixel_data_only_us = 4.0,
415 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
416 .urgent_latency_vm_data_only_us = 4.0,
417 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
418 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
419 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
420 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
421 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
422 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
423 .max_avg_sdp_bw_use_normal_percent = 40.0,
424 .max_avg_dram_bw_use_normal_percent = 40.0,
425 .writeback_latency_us = 12.0,
426 .ideal_dram_bw_after_urgent_percent = 40.0,
427 .max_request_size_bytes = 256,
428 .dram_channel_width_bytes = 2,
429 .fabric_datapath_to_dcn_data_return_bytes = 64,
430 .dcn_downspread_percent = 0.5,
431 .downspread_percent = 0.38,
432 .dram_page_open_time_ns = 50.0,
433 .dram_rw_turnaround_time_ns = 17.5,
434 .dram_return_buffer_per_channel_bytes = 8192,
435 .round_trip_ping_latency_dcfclk_cycles = 131,
436 .urgent_out_of_order_return_per_channel_bytes = 256,
437 .channel_interleave_bytes = 256,
438 .num_banks = 8,
439 .num_chans = 8,
440 .vmm_page_size_bytes = 4096,
441 .dram_clock_change_latency_us = 404.0,
442 .dummy_pstate_latency_us = 5.0,
443 .writeback_dram_clock_change_latency_us = 23.0,
444 .return_bus_width_bytes = 64,
445 .dispclk_dppclk_vco_speed_mhz = 3850,
446 .xfc_bus_transport_time_us = 20,
447 .xfc_xbuf_latency_tolerance_us = 4,
448 .use_urgent_burst_bw = 0
449 };
450
451 static struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 };
452
453 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
454 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
455 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
456 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f
457 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
458 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f
459 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
460 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f
461 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
462 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f
463 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
464 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f
465 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
466 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f
467 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
468 #endif
469
470
471 enum dcn20_clk_src_array_id {
472 DCN20_CLK_SRC_PLL0,
473 DCN20_CLK_SRC_PLL1,
474 DCN20_CLK_SRC_PLL2,
475 DCN20_CLK_SRC_PLL3,
476 DCN20_CLK_SRC_PLL4,
477 DCN20_CLK_SRC_PLL5,
478 DCN20_CLK_SRC_TOTAL
479 };
480
481 /* begin *********************
482 * macros to expend register list macro defined in HW object header file */
483
484 /* DCN */
485 /* TODO awful hack. fixup dcn20_dwb.h */
486 #undef BASE_INNER
487 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
488
489 #define BASE(seg) BASE_INNER(seg)
490
491 #define SR(reg_name)\
492 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
493 mm ## reg_name
494
495 #define SRI(reg_name, block, id)\
496 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
497 mm ## block ## id ## _ ## reg_name
498
499 #define SRIR(var_name, reg_name, block, id)\
500 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
501 mm ## block ## id ## _ ## reg_name
502
503 #define SRII(reg_name, block, id)\
504 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
505 mm ## block ## id ## _ ## reg_name
506
507 #define DCCG_SRII(reg_name, block, id)\
508 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
509 mm ## block ## id ## _ ## reg_name
510
511 #define VUPDATE_SRII(reg_name, block, id)\
512 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
513 mm ## reg_name ## _ ## block ## id
514
515 /* NBIO */
516 #define NBIO_BASE_INNER(seg) \
517 NBIO_BASE__INST0_SEG ## seg
518
519 #define NBIO_BASE(seg) \
520 NBIO_BASE_INNER(seg)
521
522 #define NBIO_SR(reg_name)\
523 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
524 mm ## reg_name
525
526 /* MMHUB */
527 #define MMHUB_BASE_INNER(seg) \
528 MMHUB_BASE__INST0_SEG ## seg
529
530 #define MMHUB_BASE(seg) \
531 MMHUB_BASE_INNER(seg)
532
533 #define MMHUB_SR(reg_name)\
534 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
535 mmMM ## reg_name
536
537 static const struct bios_registers bios_regs = {
538 NBIO_SR(BIOS_SCRATCH_3),
539 NBIO_SR(BIOS_SCRATCH_6)
540 };
541
542 #define clk_src_regs(index, pllid)\
543 [index] = {\
544 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
545 }
546
547 static const struct dce110_clk_src_regs clk_src_regs[] = {
548 clk_src_regs(0, A),
549 clk_src_regs(1, B),
550 clk_src_regs(2, C),
551 clk_src_regs(3, D),
552 clk_src_regs(4, E),
553 clk_src_regs(5, F)
554 };
555
556 static const struct dce110_clk_src_shift cs_shift = {
557 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
558 };
559
560 static const struct dce110_clk_src_mask cs_mask = {
561 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
562 };
563
564 static const struct dce_dmcu_registers dmcu_regs = {
565 DMCU_DCN10_REG_LIST()
566 };
567
568 static const struct dce_dmcu_shift dmcu_shift = {
569 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
570 };
571
572 static const struct dce_dmcu_mask dmcu_mask = {
573 DMCU_MASK_SH_LIST_DCN10(_MASK)
574 };
575
576 static const struct dce_abm_registers abm_regs = {
577 ABM_DCN20_REG_LIST()
578 };
579
580 static const struct dce_abm_shift abm_shift = {
581 ABM_MASK_SH_LIST_DCN20(__SHIFT)
582 };
583
584 static const struct dce_abm_mask abm_mask = {
585 ABM_MASK_SH_LIST_DCN20(_MASK)
586 };
587
588 #define audio_regs(id)\
589 [id] = {\
590 AUD_COMMON_REG_LIST(id)\
591 }
592
593 static const struct dce_audio_registers audio_regs[] = {
594 audio_regs(0),
595 audio_regs(1),
596 audio_regs(2),
597 audio_regs(3),
598 audio_regs(4),
599 audio_regs(5),
600 audio_regs(6),
601 };
602
603 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
604 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
605 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
606 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
607
608 static const struct dce_audio_shift audio_shift = {
609 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
610 };
611
612 static const struct dce_audio_mask audio_mask = {
613 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
614 };
615
616 #define stream_enc_regs(id)\
617 [id] = {\
618 SE_DCN2_REG_LIST(id)\
619 }
620
621 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
622 stream_enc_regs(0),
623 stream_enc_regs(1),
624 stream_enc_regs(2),
625 stream_enc_regs(3),
626 stream_enc_regs(4),
627 stream_enc_regs(5),
628 };
629
630 static const struct dcn10_stream_encoder_shift se_shift = {
631 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
632 };
633
634 static const struct dcn10_stream_encoder_mask se_mask = {
635 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
636 };
637
638
639 #define aux_regs(id)\
640 [id] = {\
641 DCN2_AUX_REG_LIST(id)\
642 }
643
644 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
645 aux_regs(0),
646 aux_regs(1),
647 aux_regs(2),
648 aux_regs(3),
649 aux_regs(4),
650 aux_regs(5)
651 };
652
653 #define hpd_regs(id)\
654 [id] = {\
655 HPD_REG_LIST(id)\
656 }
657
658 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
659 hpd_regs(0),
660 hpd_regs(1),
661 hpd_regs(2),
662 hpd_regs(3),
663 hpd_regs(4),
664 hpd_regs(5)
665 };
666
667 #define link_regs(id, phyid)\
668 [id] = {\
669 LE_DCN10_REG_LIST(id), \
670 UNIPHY_DCN2_REG_LIST(phyid), \
671 DPCS_DCN2_REG_LIST(id), \
672 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
673 }
674
675 static const struct dcn10_link_enc_registers link_enc_regs[] = {
676 link_regs(0, A),
677 link_regs(1, B),
678 link_regs(2, C),
679 link_regs(3, D),
680 link_regs(4, E),
681 link_regs(5, F)
682 };
683
684 static const struct dcn10_link_enc_shift le_shift = {
685 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
686 DPCS_DCN2_MASK_SH_LIST(__SHIFT)
687 };
688
689 static const struct dcn10_link_enc_mask le_mask = {
690 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
691 DPCS_DCN2_MASK_SH_LIST(_MASK)
692 };
693
694 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
695 { DCN_PANEL_CNTL_REG_LIST() }
696 };
697
698 static const struct dce_panel_cntl_shift panel_cntl_shift = {
699 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
700 };
701
702 static const struct dce_panel_cntl_mask panel_cntl_mask = {
703 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
704 };
705
706 #define ipp_regs(id)\
707 [id] = {\
708 IPP_REG_LIST_DCN20(id),\
709 }
710
711 static const struct dcn10_ipp_registers ipp_regs[] = {
712 ipp_regs(0),
713 ipp_regs(1),
714 ipp_regs(2),
715 ipp_regs(3),
716 ipp_regs(4),
717 ipp_regs(5),
718 };
719
720 static const struct dcn10_ipp_shift ipp_shift = {
721 IPP_MASK_SH_LIST_DCN20(__SHIFT)
722 };
723
724 static const struct dcn10_ipp_mask ipp_mask = {
725 IPP_MASK_SH_LIST_DCN20(_MASK),
726 };
727
728 #define opp_regs(id)\
729 [id] = {\
730 OPP_REG_LIST_DCN20(id),\
731 }
732
733 static const struct dcn20_opp_registers opp_regs[] = {
734 opp_regs(0),
735 opp_regs(1),
736 opp_regs(2),
737 opp_regs(3),
738 opp_regs(4),
739 opp_regs(5),
740 };
741
742 static const struct dcn20_opp_shift opp_shift = {
743 OPP_MASK_SH_LIST_DCN20(__SHIFT)
744 };
745
746 static const struct dcn20_opp_mask opp_mask = {
747 OPP_MASK_SH_LIST_DCN20(_MASK)
748 };
749
750 #define aux_engine_regs(id)\
751 [id] = {\
752 AUX_COMMON_REG_LIST0(id), \
753 .AUXN_IMPCAL = 0, \
754 .AUXP_IMPCAL = 0, \
755 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
756 }
757
758 static const struct dce110_aux_registers aux_engine_regs[] = {
759 aux_engine_regs(0),
760 aux_engine_regs(1),
761 aux_engine_regs(2),
762 aux_engine_regs(3),
763 aux_engine_regs(4),
764 aux_engine_regs(5)
765 };
766
767 #define tf_regs(id)\
768 [id] = {\
769 TF_REG_LIST_DCN20(id),\
770 TF_REG_LIST_DCN20_COMMON_APPEND(id),\
771 }
772
773 static const struct dcn2_dpp_registers tf_regs[] = {
774 tf_regs(0),
775 tf_regs(1),
776 tf_regs(2),
777 tf_regs(3),
778 tf_regs(4),
779 tf_regs(5),
780 };
781
782 static const struct dcn2_dpp_shift tf_shift = {
783 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
784 TF_DEBUG_REG_LIST_SH_DCN20
785 };
786
787 static const struct dcn2_dpp_mask tf_mask = {
788 TF_REG_LIST_SH_MASK_DCN20(_MASK),
789 TF_DEBUG_REG_LIST_MASK_DCN20
790 };
791
792 #define dwbc_regs_dcn2(id)\
793 [id] = {\
794 DWBC_COMMON_REG_LIST_DCN2_0(id),\
795 }
796
797 static const struct dcn20_dwbc_registers dwbc20_regs[] = {
798 dwbc_regs_dcn2(0),
799 };
800
801 static const struct dcn20_dwbc_shift dwbc20_shift = {
802 DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
803 };
804
805 static const struct dcn20_dwbc_mask dwbc20_mask = {
806 DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
807 };
808
809 #define mcif_wb_regs_dcn2(id)\
810 [id] = {\
811 MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\
812 }
813
814 static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = {
815 mcif_wb_regs_dcn2(0),
816 };
817
818 static const struct dcn20_mmhubbub_shift mcif_wb20_shift = {
819 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
820 };
821
822 static const struct dcn20_mmhubbub_mask mcif_wb20_mask = {
823 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
824 };
825
826 static const struct dcn20_mpc_registers mpc_regs = {
827 MPC_REG_LIST_DCN2_0(0),
828 MPC_REG_LIST_DCN2_0(1),
829 MPC_REG_LIST_DCN2_0(2),
830 MPC_REG_LIST_DCN2_0(3),
831 MPC_REG_LIST_DCN2_0(4),
832 MPC_REG_LIST_DCN2_0(5),
833 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
834 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
835 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
836 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
837 MPC_OUT_MUX_REG_LIST_DCN2_0(4),
838 MPC_OUT_MUX_REG_LIST_DCN2_0(5),
839 MPC_DBG_REG_LIST_DCN2_0()
840 };
841
842 static const struct dcn20_mpc_shift mpc_shift = {
843 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
844 MPC_DEBUG_REG_LIST_SH_DCN20
845 };
846
847 static const struct dcn20_mpc_mask mpc_mask = {
848 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
849 MPC_DEBUG_REG_LIST_MASK_DCN20
850 };
851
852 #define tg_regs(id)\
853 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
854
855
856 static const struct dcn_optc_registers tg_regs[] = {
857 tg_regs(0),
858 tg_regs(1),
859 tg_regs(2),
860 tg_regs(3),
861 tg_regs(4),
862 tg_regs(5)
863 };
864
865 static const struct dcn_optc_shift tg_shift = {
866 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
867 };
868
869 static const struct dcn_optc_mask tg_mask = {
870 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
871 };
872
873 #define hubp_regs(id)\
874 [id] = {\
875 HUBP_REG_LIST_DCN20(id)\
876 }
877
878 static const struct dcn_hubp2_registers hubp_regs[] = {
879 hubp_regs(0),
880 hubp_regs(1),
881 hubp_regs(2),
882 hubp_regs(3),
883 hubp_regs(4),
884 hubp_regs(5)
885 };
886
887 static const struct dcn_hubp2_shift hubp_shift = {
888 HUBP_MASK_SH_LIST_DCN20(__SHIFT)
889 };
890
891 static const struct dcn_hubp2_mask hubp_mask = {
892 HUBP_MASK_SH_LIST_DCN20(_MASK)
893 };
894
895 static const struct dcn_hubbub_registers hubbub_reg = {
896 HUBBUB_REG_LIST_DCN20(0)
897 };
898
899 static const struct dcn_hubbub_shift hubbub_shift = {
900 HUBBUB_MASK_SH_LIST_DCN20(__SHIFT)
901 };
902
903 static const struct dcn_hubbub_mask hubbub_mask = {
904 HUBBUB_MASK_SH_LIST_DCN20(_MASK)
905 };
906
907 #define vmid_regs(id)\
908 [id] = {\
909 DCN20_VMID_REG_LIST(id)\
910 }
911
912 static const struct dcn_vmid_registers vmid_regs[] = {
913 vmid_regs(0),
914 vmid_regs(1),
915 vmid_regs(2),
916 vmid_regs(3),
917 vmid_regs(4),
918 vmid_regs(5),
919 vmid_regs(6),
920 vmid_regs(7),
921 vmid_regs(8),
922 vmid_regs(9),
923 vmid_regs(10),
924 vmid_regs(11),
925 vmid_regs(12),
926 vmid_regs(13),
927 vmid_regs(14),
928 vmid_regs(15)
929 };
930
931 static const struct dcn20_vmid_shift vmid_shifts = {
932 DCN20_VMID_MASK_SH_LIST(__SHIFT)
933 };
934
935 static const struct dcn20_vmid_mask vmid_masks = {
936 DCN20_VMID_MASK_SH_LIST(_MASK)
937 };
938
939 static const struct dce110_aux_registers_shift aux_shift = {
940 DCN_AUX_MASK_SH_LIST(__SHIFT)
941 };
942
943 static const struct dce110_aux_registers_mask aux_mask = {
944 DCN_AUX_MASK_SH_LIST(_MASK)
945 };
946
map_transmitter_id_to_phy_instance(enum transmitter transmitter)947 static int map_transmitter_id_to_phy_instance(
948 enum transmitter transmitter)
949 {
950 switch (transmitter) {
951 case TRANSMITTER_UNIPHY_A:
952 return 0;
953 break;
954 case TRANSMITTER_UNIPHY_B:
955 return 1;
956 break;
957 case TRANSMITTER_UNIPHY_C:
958 return 2;
959 break;
960 case TRANSMITTER_UNIPHY_D:
961 return 3;
962 break;
963 case TRANSMITTER_UNIPHY_E:
964 return 4;
965 break;
966 case TRANSMITTER_UNIPHY_F:
967 return 5;
968 break;
969 default:
970 ASSERT(0);
971 return 0;
972 }
973 }
974
975 #define dsc_regsDCN20(id)\
976 [id] = {\
977 DSC_REG_LIST_DCN20(id)\
978 }
979
980 static const struct dcn20_dsc_registers dsc_regs[] = {
981 dsc_regsDCN20(0),
982 dsc_regsDCN20(1),
983 dsc_regsDCN20(2),
984 dsc_regsDCN20(3),
985 dsc_regsDCN20(4),
986 dsc_regsDCN20(5)
987 };
988
989 static const struct dcn20_dsc_shift dsc_shift = {
990 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
991 };
992
993 static const struct dcn20_dsc_mask dsc_mask = {
994 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
995 };
996
997 static const struct dccg_registers dccg_regs = {
998 DCCG_REG_LIST_DCN2()
999 };
1000
1001 static const struct dccg_shift dccg_shift = {
1002 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
1003 };
1004
1005 static const struct dccg_mask dccg_mask = {
1006 DCCG_MASK_SH_LIST_DCN2(_MASK)
1007 };
1008
1009 static const struct resource_caps res_cap_nv10 = {
1010 .num_timing_generator = 6,
1011 .num_opp = 6,
1012 .num_video_plane = 6,
1013 .num_audio = 7,
1014 .num_stream_encoder = 6,
1015 .num_pll = 6,
1016 .num_dwb = 1,
1017 .num_ddc = 6,
1018 .num_vmid = 16,
1019 .num_dsc = 6,
1020 };
1021
1022 static const struct dc_plane_cap plane_cap = {
1023 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
1024 .blends_with_above = true,
1025 .blends_with_below = true,
1026 .per_pixel_alpha = true,
1027
1028 .pixel_format_support = {
1029 .argb8888 = true,
1030 .nv12 = true,
1031 .fp16 = true,
1032 .p010 = true
1033 },
1034
1035 .max_upscale_factor = {
1036 .argb8888 = 16000,
1037 .nv12 = 16000,
1038 .fp16 = 1
1039 },
1040
1041 .max_downscale_factor = {
1042 .argb8888 = 250,
1043 .nv12 = 250,
1044 .fp16 = 1
1045 },
1046 16,
1047 16
1048 };
1049 static const struct resource_caps res_cap_nv14 = {
1050 .num_timing_generator = 5,
1051 .num_opp = 5,
1052 .num_video_plane = 5,
1053 .num_audio = 6,
1054 .num_stream_encoder = 5,
1055 .num_pll = 5,
1056 .num_dwb = 1,
1057 .num_ddc = 5,
1058 .num_vmid = 16,
1059 .num_dsc = 5,
1060 };
1061
1062 static const struct dc_debug_options debug_defaults_drv = {
1063 .disable_dmcu = false,
1064 .force_abm_enable = false,
1065 .timing_trace = false,
1066 .clock_trace = true,
1067 .disable_pplib_clock_request = true,
1068 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
1069 .force_single_disp_pipe_split = false,
1070 .disable_dcc = DCC_ENABLE,
1071 .vsr_support = true,
1072 .performance_trace = false,
1073 .max_downscale_src_width = 5120,/*upto 5K*/
1074 .disable_pplib_wm_range = false,
1075 .scl_reset_length10 = true,
1076 .sanity_checks = false,
1077 .underflow_assert_delay_us = 0xFFFFFFFF,
1078 };
1079
1080 static const struct dc_debug_options debug_defaults_diags = {
1081 .disable_dmcu = false,
1082 .force_abm_enable = false,
1083 .timing_trace = true,
1084 .clock_trace = true,
1085 .disable_dpp_power_gate = true,
1086 .disable_hubp_power_gate = true,
1087 .disable_clock_gate = true,
1088 .disable_pplib_clock_request = true,
1089 .disable_pplib_wm_range = true,
1090 .disable_stutter = true,
1091 .scl_reset_length10 = true,
1092 .underflow_assert_delay_us = 0xFFFFFFFF,
1093 .enable_tri_buf = true,
1094 };
1095
dcn20_dpp_destroy(struct dpp ** dpp)1096 void dcn20_dpp_destroy(struct dpp **dpp)
1097 {
1098 kfree(TO_DCN20_DPP(*dpp));
1099 *dpp = NULL;
1100 }
1101
dcn20_dpp_create(struct dc_context * ctx,uint32_t inst)1102 struct dpp *dcn20_dpp_create(
1103 struct dc_context *ctx,
1104 uint32_t inst)
1105 {
1106 struct dcn20_dpp *dpp =
1107 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
1108
1109 if (!dpp)
1110 return NULL;
1111
1112 if (dpp2_construct(dpp, ctx, inst,
1113 &tf_regs[inst], &tf_shift, &tf_mask))
1114 return &dpp->base;
1115
1116 BREAK_TO_DEBUGGER();
1117 kfree(dpp);
1118 return NULL;
1119 }
1120
dcn20_ipp_create(struct dc_context * ctx,uint32_t inst)1121 struct input_pixel_processor *dcn20_ipp_create(
1122 struct dc_context *ctx, uint32_t inst)
1123 {
1124 struct dcn10_ipp *ipp =
1125 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
1126
1127 if (!ipp) {
1128 BREAK_TO_DEBUGGER();
1129 return NULL;
1130 }
1131
1132 dcn20_ipp_construct(ipp, ctx, inst,
1133 &ipp_regs[inst], &ipp_shift, &ipp_mask);
1134 return &ipp->base;
1135 }
1136
1137
dcn20_opp_create(struct dc_context * ctx,uint32_t inst)1138 struct output_pixel_processor *dcn20_opp_create(
1139 struct dc_context *ctx, uint32_t inst)
1140 {
1141 struct dcn20_opp *opp =
1142 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1143
1144 if (!opp) {
1145 BREAK_TO_DEBUGGER();
1146 return NULL;
1147 }
1148
1149 dcn20_opp_construct(opp, ctx, inst,
1150 &opp_regs[inst], &opp_shift, &opp_mask);
1151 return &opp->base;
1152 }
1153
dcn20_aux_engine_create(struct dc_context * ctx,uint32_t inst)1154 struct dce_aux *dcn20_aux_engine_create(
1155 struct dc_context *ctx,
1156 uint32_t inst)
1157 {
1158 struct aux_engine_dce110 *aux_engine =
1159 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
1160
1161 if (!aux_engine)
1162 return NULL;
1163
1164 dce110_aux_engine_construct(aux_engine, ctx, inst,
1165 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
1166 &aux_engine_regs[inst],
1167 &aux_mask,
1168 &aux_shift,
1169 ctx->dc->caps.extended_aux_timeout_support);
1170
1171 return &aux_engine->base;
1172 }
1173 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
1174
1175 static const struct dce_i2c_registers i2c_hw_regs[] = {
1176 i2c_inst_regs(1),
1177 i2c_inst_regs(2),
1178 i2c_inst_regs(3),
1179 i2c_inst_regs(4),
1180 i2c_inst_regs(5),
1181 i2c_inst_regs(6),
1182 };
1183
1184 static const struct dce_i2c_shift i2c_shifts = {
1185 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
1186 };
1187
1188 static const struct dce_i2c_mask i2c_masks = {
1189 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
1190 };
1191
dcn20_i2c_hw_create(struct dc_context * ctx,uint32_t inst)1192 struct dce_i2c_hw *dcn20_i2c_hw_create(
1193 struct dc_context *ctx,
1194 uint32_t inst)
1195 {
1196 struct dce_i2c_hw *dce_i2c_hw =
1197 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
1198
1199 if (!dce_i2c_hw)
1200 return NULL;
1201
1202 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1203 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1204
1205 return dce_i2c_hw;
1206 }
dcn20_mpc_create(struct dc_context * ctx)1207 struct mpc *dcn20_mpc_create(struct dc_context *ctx)
1208 {
1209 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1210 GFP_KERNEL);
1211
1212 if (!mpc20)
1213 return NULL;
1214
1215 dcn20_mpc_construct(mpc20, ctx,
1216 &mpc_regs,
1217 &mpc_shift,
1218 &mpc_mask,
1219 6);
1220
1221 return &mpc20->base;
1222 }
1223
dcn20_hubbub_create(struct dc_context * ctx)1224 struct hubbub *dcn20_hubbub_create(struct dc_context *ctx)
1225 {
1226 int i;
1227 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1228 GFP_KERNEL);
1229
1230 if (!hubbub)
1231 return NULL;
1232
1233 hubbub2_construct(hubbub, ctx,
1234 &hubbub_reg,
1235 &hubbub_shift,
1236 &hubbub_mask);
1237
1238 for (i = 0; i < res_cap_nv10.num_vmid; i++) {
1239 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1240
1241 vmid->ctx = ctx;
1242
1243 vmid->regs = &vmid_regs[i];
1244 vmid->shifts = &vmid_shifts;
1245 vmid->masks = &vmid_masks;
1246 }
1247
1248 return &hubbub->base;
1249 }
1250
dcn20_timing_generator_create(struct dc_context * ctx,uint32_t instance)1251 struct timing_generator *dcn20_timing_generator_create(
1252 struct dc_context *ctx,
1253 uint32_t instance)
1254 {
1255 struct optc *tgn10 =
1256 kzalloc(sizeof(struct optc), GFP_KERNEL);
1257
1258 if (!tgn10)
1259 return NULL;
1260
1261 tgn10->base.inst = instance;
1262 tgn10->base.ctx = ctx;
1263
1264 tgn10->tg_regs = &tg_regs[instance];
1265 tgn10->tg_shift = &tg_shift;
1266 tgn10->tg_mask = &tg_mask;
1267
1268 dcn20_timing_generator_init(tgn10);
1269
1270 return &tgn10->base;
1271 }
1272
1273 static const struct encoder_feature_support link_enc_feature = {
1274 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1275 .max_hdmi_pixel_clock = 600000,
1276 .hdmi_ycbcr420_supported = true,
1277 .dp_ycbcr420_supported = true,
1278 .fec_supported = true,
1279 .flags.bits.IS_HBR2_CAPABLE = true,
1280 .flags.bits.IS_HBR3_CAPABLE = true,
1281 .flags.bits.IS_TPS3_CAPABLE = true,
1282 .flags.bits.IS_TPS4_CAPABLE = true
1283 };
1284
dcn20_link_encoder_create(const struct encoder_init_data * enc_init_data)1285 struct link_encoder *dcn20_link_encoder_create(
1286 const struct encoder_init_data *enc_init_data)
1287 {
1288 struct dcn20_link_encoder *enc20 =
1289 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1290 int link_regs_id;
1291
1292 if (!enc20)
1293 return NULL;
1294
1295 link_regs_id =
1296 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1297
1298 dcn20_link_encoder_construct(enc20,
1299 enc_init_data,
1300 &link_enc_feature,
1301 &link_enc_regs[link_regs_id],
1302 &link_enc_aux_regs[enc_init_data->channel - 1],
1303 &link_enc_hpd_regs[enc_init_data->hpd_source],
1304 &le_shift,
1305 &le_mask);
1306
1307 return &enc20->enc10.base;
1308 }
1309
dcn20_panel_cntl_create(const struct panel_cntl_init_data * init_data)1310 static struct panel_cntl *dcn20_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1311 {
1312 struct dce_panel_cntl *panel_cntl =
1313 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
1314
1315 if (!panel_cntl)
1316 return NULL;
1317
1318 dce_panel_cntl_construct(panel_cntl,
1319 init_data,
1320 &panel_cntl_regs[init_data->inst],
1321 &panel_cntl_shift,
1322 &panel_cntl_mask);
1323
1324 return &panel_cntl->base;
1325 }
1326
dcn20_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1327 static struct clock_source *dcn20_clock_source_create(
1328 struct dc_context *ctx,
1329 struct dc_bios *bios,
1330 enum clock_source_id id,
1331 const struct dce110_clk_src_regs *regs,
1332 bool dp_clk_src)
1333 {
1334 struct dce110_clk_src *clk_src =
1335 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1336
1337 if (!clk_src)
1338 return NULL;
1339
1340 if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1341 regs, &cs_shift, &cs_mask)) {
1342 clk_src->base.dp_clk_src = dp_clk_src;
1343 return &clk_src->base;
1344 }
1345
1346 kfree(clk_src);
1347 BREAK_TO_DEBUGGER();
1348 return NULL;
1349 }
1350
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1351 static void read_dce_straps(
1352 struct dc_context *ctx,
1353 struct resource_straps *straps)
1354 {
1355 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1356 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1357 }
1358
dcn20_create_audio(struct dc_context * ctx,unsigned int inst)1359 static struct audio *dcn20_create_audio(
1360 struct dc_context *ctx, unsigned int inst)
1361 {
1362 return dce_audio_create(ctx, inst,
1363 &audio_regs[inst], &audio_shift, &audio_mask);
1364 }
1365
dcn20_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1366 struct stream_encoder *dcn20_stream_encoder_create(
1367 enum engine_id eng_id,
1368 struct dc_context *ctx)
1369 {
1370 struct dcn10_stream_encoder *enc1 =
1371 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1372
1373 if (!enc1)
1374 return NULL;
1375
1376 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
1377 if (eng_id >= ENGINE_ID_DIGD)
1378 eng_id++;
1379 }
1380
1381 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1382 &stream_enc_regs[eng_id],
1383 &se_shift, &se_mask);
1384
1385 return &enc1->base;
1386 }
1387
1388 static const struct dce_hwseq_registers hwseq_reg = {
1389 HWSEQ_DCN2_REG_LIST()
1390 };
1391
1392 static const struct dce_hwseq_shift hwseq_shift = {
1393 HWSEQ_DCN2_MASK_SH_LIST(__SHIFT)
1394 };
1395
1396 static const struct dce_hwseq_mask hwseq_mask = {
1397 HWSEQ_DCN2_MASK_SH_LIST(_MASK)
1398 };
1399
dcn20_hwseq_create(struct dc_context * ctx)1400 struct dce_hwseq *dcn20_hwseq_create(
1401 struct dc_context *ctx)
1402 {
1403 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1404
1405 if (hws) {
1406 hws->ctx = ctx;
1407 hws->regs = &hwseq_reg;
1408 hws->shifts = &hwseq_shift;
1409 hws->masks = &hwseq_mask;
1410 }
1411 return hws;
1412 }
1413
1414 static const struct resource_create_funcs res_create_funcs = {
1415 .read_dce_straps = read_dce_straps,
1416 .create_audio = dcn20_create_audio,
1417 .create_stream_encoder = dcn20_stream_encoder_create,
1418 .create_hwseq = dcn20_hwseq_create,
1419 };
1420
1421 static const struct resource_create_funcs res_create_maximus_funcs = {
1422 .read_dce_straps = NULL,
1423 .create_audio = NULL,
1424 .create_stream_encoder = NULL,
1425 .create_hwseq = dcn20_hwseq_create,
1426 };
1427
1428 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
1429
dcn20_clock_source_destroy(struct clock_source ** clk_src)1430 void dcn20_clock_source_destroy(struct clock_source **clk_src)
1431 {
1432 kfree(TO_DCE110_CLK_SRC(*clk_src));
1433 *clk_src = NULL;
1434 }
1435
1436
dcn20_dsc_create(struct dc_context * ctx,uint32_t inst)1437 struct display_stream_compressor *dcn20_dsc_create(
1438 struct dc_context *ctx, uint32_t inst)
1439 {
1440 struct dcn20_dsc *dsc =
1441 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1442
1443 if (!dsc) {
1444 BREAK_TO_DEBUGGER();
1445 return NULL;
1446 }
1447
1448 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1449 return &dsc->base;
1450 }
1451
dcn20_dsc_destroy(struct display_stream_compressor ** dsc)1452 void dcn20_dsc_destroy(struct display_stream_compressor **dsc)
1453 {
1454 kfree(container_of(*dsc, struct dcn20_dsc, base));
1455 *dsc = NULL;
1456 }
1457
1458
dcn20_resource_destruct(struct dcn20_resource_pool * pool)1459 static void dcn20_resource_destruct(struct dcn20_resource_pool *pool)
1460 {
1461 unsigned int i;
1462
1463 for (i = 0; i < pool->base.stream_enc_count; i++) {
1464 if (pool->base.stream_enc[i] != NULL) {
1465 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1466 pool->base.stream_enc[i] = NULL;
1467 }
1468 }
1469
1470 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1471 if (pool->base.dscs[i] != NULL)
1472 dcn20_dsc_destroy(&pool->base.dscs[i]);
1473 }
1474
1475 if (pool->base.mpc != NULL) {
1476 kfree(TO_DCN20_MPC(pool->base.mpc));
1477 pool->base.mpc = NULL;
1478 }
1479 if (pool->base.hubbub != NULL) {
1480 kfree(pool->base.hubbub);
1481 pool->base.hubbub = NULL;
1482 }
1483 for (i = 0; i < pool->base.pipe_count; i++) {
1484 if (pool->base.dpps[i] != NULL)
1485 dcn20_dpp_destroy(&pool->base.dpps[i]);
1486
1487 if (pool->base.ipps[i] != NULL)
1488 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1489
1490 if (pool->base.hubps[i] != NULL) {
1491 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1492 pool->base.hubps[i] = NULL;
1493 }
1494
1495 if (pool->base.irqs != NULL) {
1496 dal_irq_service_destroy(&pool->base.irqs);
1497 }
1498 }
1499
1500 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1501 if (pool->base.engines[i] != NULL)
1502 dce110_engine_destroy(&pool->base.engines[i]);
1503 if (pool->base.hw_i2cs[i] != NULL) {
1504 kfree(pool->base.hw_i2cs[i]);
1505 pool->base.hw_i2cs[i] = NULL;
1506 }
1507 if (pool->base.sw_i2cs[i] != NULL) {
1508 kfree(pool->base.sw_i2cs[i]);
1509 pool->base.sw_i2cs[i] = NULL;
1510 }
1511 }
1512
1513 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1514 if (pool->base.opps[i] != NULL)
1515 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1516 }
1517
1518 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1519 if (pool->base.timing_generators[i] != NULL) {
1520 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1521 pool->base.timing_generators[i] = NULL;
1522 }
1523 }
1524
1525 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1526 if (pool->base.dwbc[i] != NULL) {
1527 kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
1528 pool->base.dwbc[i] = NULL;
1529 }
1530 if (pool->base.mcif_wb[i] != NULL) {
1531 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
1532 pool->base.mcif_wb[i] = NULL;
1533 }
1534 }
1535
1536 for (i = 0; i < pool->base.audio_count; i++) {
1537 if (pool->base.audios[i])
1538 dce_aud_destroy(&pool->base.audios[i]);
1539 }
1540
1541 for (i = 0; i < pool->base.clk_src_count; i++) {
1542 if (pool->base.clock_sources[i] != NULL) {
1543 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1544 pool->base.clock_sources[i] = NULL;
1545 }
1546 }
1547
1548 if (pool->base.dp_clock_source != NULL) {
1549 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1550 pool->base.dp_clock_source = NULL;
1551 }
1552
1553
1554 if (pool->base.abm != NULL)
1555 dce_abm_destroy(&pool->base.abm);
1556
1557 if (pool->base.dmcu != NULL)
1558 dce_dmcu_destroy(&pool->base.dmcu);
1559
1560 if (pool->base.dccg != NULL)
1561 dcn_dccg_destroy(&pool->base.dccg);
1562
1563 if (pool->base.pp_smu != NULL)
1564 dcn20_pp_smu_destroy(&pool->base.pp_smu);
1565
1566 if (pool->base.oem_device != NULL)
1567 dal_ddc_service_destroy(&pool->base.oem_device);
1568 }
1569
dcn20_hubp_create(struct dc_context * ctx,uint32_t inst)1570 struct hubp *dcn20_hubp_create(
1571 struct dc_context *ctx,
1572 uint32_t inst)
1573 {
1574 struct dcn20_hubp *hubp2 =
1575 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1576
1577 if (!hubp2)
1578 return NULL;
1579
1580 if (hubp2_construct(hubp2, ctx, inst,
1581 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1582 return &hubp2->base;
1583
1584 BREAK_TO_DEBUGGER();
1585 kfree(hubp2);
1586 return NULL;
1587 }
1588
get_pixel_clock_parameters(struct pipe_ctx * pipe_ctx,struct pixel_clk_params * pixel_clk_params)1589 static void get_pixel_clock_parameters(
1590 struct pipe_ctx *pipe_ctx,
1591 struct pixel_clk_params *pixel_clk_params)
1592 {
1593 const struct dc_stream_state *stream = pipe_ctx->stream;
1594 struct pipe_ctx *odm_pipe;
1595 int opp_cnt = 1;
1596
1597 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1598 opp_cnt++;
1599
1600 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1601 pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
1602 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1603 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1604 /* TODO: un-hardcode*/
1605 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1606 LINK_RATE_REF_FREQ_IN_KHZ;
1607 pixel_clk_params->flags.ENABLE_SS = 0;
1608 pixel_clk_params->color_depth =
1609 stream->timing.display_color_depth;
1610 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1611 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1612
1613 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1614 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1615
1616 if (opp_cnt == 4)
1617 pixel_clk_params->requested_pix_clk_100hz /= 4;
1618 else if (optc2_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2)
1619 pixel_clk_params->requested_pix_clk_100hz /= 2;
1620
1621 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1622 pixel_clk_params->requested_pix_clk_100hz *= 2;
1623
1624 }
1625
build_clamping_params(struct dc_stream_state * stream)1626 static void build_clamping_params(struct dc_stream_state *stream)
1627 {
1628 stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1629 stream->clamping.c_depth = stream->timing.display_color_depth;
1630 stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1631 }
1632
build_pipe_hw_param(struct pipe_ctx * pipe_ctx)1633 static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1634 {
1635
1636 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1637
1638 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1639 pipe_ctx->clock_source,
1640 &pipe_ctx->stream_res.pix_clk_params,
1641 &pipe_ctx->pll_settings);
1642
1643 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1644
1645 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1646 &pipe_ctx->stream->bit_depth_params);
1647 build_clamping_params(pipe_ctx->stream);
1648
1649 return DC_OK;
1650 }
1651
dcn20_build_mapped_resource(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)1652 enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)
1653 {
1654 enum dc_status status = DC_OK;
1655 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1656
1657 if (!pipe_ctx)
1658 return DC_ERROR_UNEXPECTED;
1659
1660
1661 status = build_pipe_hw_param(pipe_ctx);
1662
1663 return status;
1664 }
1665
1666
dcn20_acquire_dsc(const struct dc * dc,struct resource_context * res_ctx,struct display_stream_compressor ** dsc,int pipe_idx)1667 void dcn20_acquire_dsc(const struct dc *dc,
1668 struct resource_context *res_ctx,
1669 struct display_stream_compressor **dsc,
1670 int pipe_idx)
1671 {
1672 int i;
1673 const struct resource_pool *pool = dc->res_pool;
1674 struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc;
1675
1676 ASSERT(*dsc == NULL); /* If this ASSERT fails, dsc was not released properly */
1677 *dsc = NULL;
1678
1679 /* Always do 1-to-1 mapping when number of DSCs is same as number of pipes */
1680 if (pool->res_cap->num_dsc == pool->res_cap->num_opp) {
1681 *dsc = pool->dscs[pipe_idx];
1682 res_ctx->is_dsc_acquired[pipe_idx] = true;
1683 return;
1684 }
1685
1686 /* Return old DSC to avoid the need for re-programming */
1687 if (dsc_old && !res_ctx->is_dsc_acquired[dsc_old->inst]) {
1688 *dsc = dsc_old;
1689 res_ctx->is_dsc_acquired[dsc_old->inst] = true;
1690 return ;
1691 }
1692
1693 /* Find first free DSC */
1694 for (i = 0; i < pool->res_cap->num_dsc; i++)
1695 if (!res_ctx->is_dsc_acquired[i]) {
1696 *dsc = pool->dscs[i];
1697 res_ctx->is_dsc_acquired[i] = true;
1698 break;
1699 }
1700 }
1701
dcn20_release_dsc(struct resource_context * res_ctx,const struct resource_pool * pool,struct display_stream_compressor ** dsc)1702 void dcn20_release_dsc(struct resource_context *res_ctx,
1703 const struct resource_pool *pool,
1704 struct display_stream_compressor **dsc)
1705 {
1706 int i;
1707
1708 for (i = 0; i < pool->res_cap->num_dsc; i++)
1709 if (pool->dscs[i] == *dsc) {
1710 res_ctx->is_dsc_acquired[i] = false;
1711 *dsc = NULL;
1712 break;
1713 }
1714 }
1715
1716
1717
dcn20_add_dsc_to_stream_resource(struct dc * dc,struct dc_state * dc_ctx,struct dc_stream_state * dc_stream)1718 enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc,
1719 struct dc_state *dc_ctx,
1720 struct dc_stream_state *dc_stream)
1721 {
1722 enum dc_status result = DC_OK;
1723 int i;
1724
1725 /* Get a DSC if required and available */
1726 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1727 struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i];
1728
1729 if (pipe_ctx->stream != dc_stream)
1730 continue;
1731
1732 if (pipe_ctx->stream_res.dsc)
1733 continue;
1734
1735 dcn20_acquire_dsc(dc, &dc_ctx->res_ctx, &pipe_ctx->stream_res.dsc, i);
1736
1737 /* The number of DSCs can be less than the number of pipes */
1738 if (!pipe_ctx->stream_res.dsc) {
1739 result = DC_NO_DSC_RESOURCE;
1740 }
1741
1742 break;
1743 }
1744
1745 return result;
1746 }
1747
1748
remove_dsc_from_stream_resource(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)1749 static enum dc_status remove_dsc_from_stream_resource(struct dc *dc,
1750 struct dc_state *new_ctx,
1751 struct dc_stream_state *dc_stream)
1752 {
1753 struct pipe_ctx *pipe_ctx = NULL;
1754 int i;
1755
1756 for (i = 0; i < MAX_PIPES; i++) {
1757 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1758 pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
1759
1760 if (pipe_ctx->stream_res.dsc)
1761 dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
1762 }
1763 }
1764
1765 if (!pipe_ctx)
1766 return DC_ERROR_UNEXPECTED;
1767 else
1768 return DC_OK;
1769 }
1770
1771
dcn20_add_stream_to_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)1772 enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1773 {
1774 enum dc_status result = DC_ERROR_UNEXPECTED;
1775
1776 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1777
1778 if (result == DC_OK)
1779 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1780
1781 /* Get a DSC if required and available */
1782 if (result == DC_OK && dc_stream->timing.flags.DSC)
1783 result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
1784
1785 if (result == DC_OK)
1786 result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);
1787
1788 return result;
1789 }
1790
1791
dcn20_remove_stream_from_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)1792 enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1793 {
1794 enum dc_status result = DC_OK;
1795
1796 result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream);
1797
1798 return result;
1799 }
1800
1801
swizzle_to_dml_params(enum swizzle_mode_values swizzle,unsigned int * sw_mode)1802 static void swizzle_to_dml_params(
1803 enum swizzle_mode_values swizzle,
1804 unsigned int *sw_mode)
1805 {
1806 switch (swizzle) {
1807 case DC_SW_LINEAR:
1808 *sw_mode = dm_sw_linear;
1809 break;
1810 case DC_SW_4KB_S:
1811 *sw_mode = dm_sw_4kb_s;
1812 break;
1813 case DC_SW_4KB_S_X:
1814 *sw_mode = dm_sw_4kb_s_x;
1815 break;
1816 case DC_SW_4KB_D:
1817 *sw_mode = dm_sw_4kb_d;
1818 break;
1819 case DC_SW_4KB_D_X:
1820 *sw_mode = dm_sw_4kb_d_x;
1821 break;
1822 case DC_SW_64KB_S:
1823 *sw_mode = dm_sw_64kb_s;
1824 break;
1825 case DC_SW_64KB_S_X:
1826 *sw_mode = dm_sw_64kb_s_x;
1827 break;
1828 case DC_SW_64KB_S_T:
1829 *sw_mode = dm_sw_64kb_s_t;
1830 break;
1831 case DC_SW_64KB_D:
1832 *sw_mode = dm_sw_64kb_d;
1833 break;
1834 case DC_SW_64KB_D_X:
1835 *sw_mode = dm_sw_64kb_d_x;
1836 break;
1837 case DC_SW_64KB_D_T:
1838 *sw_mode = dm_sw_64kb_d_t;
1839 break;
1840 case DC_SW_64KB_R_X:
1841 *sw_mode = dm_sw_64kb_r_x;
1842 break;
1843 case DC_SW_VAR_S:
1844 *sw_mode = dm_sw_var_s;
1845 break;
1846 case DC_SW_VAR_S_X:
1847 *sw_mode = dm_sw_var_s_x;
1848 break;
1849 case DC_SW_VAR_D:
1850 *sw_mode = dm_sw_var_d;
1851 break;
1852 case DC_SW_VAR_D_X:
1853 *sw_mode = dm_sw_var_d_x;
1854 break;
1855
1856 default:
1857 ASSERT(0); /* Not supported */
1858 break;
1859 }
1860 }
1861
dcn20_split_stream_for_odm(const struct dc * dc,struct resource_context * res_ctx,struct pipe_ctx * prev_odm_pipe,struct pipe_ctx * next_odm_pipe)1862 bool dcn20_split_stream_for_odm(
1863 const struct dc *dc,
1864 struct resource_context *res_ctx,
1865 struct pipe_ctx *prev_odm_pipe,
1866 struct pipe_ctx *next_odm_pipe)
1867 {
1868 int pipe_idx = next_odm_pipe->pipe_idx;
1869 const struct resource_pool *pool = dc->res_pool;
1870
1871 *next_odm_pipe = *prev_odm_pipe;
1872
1873 next_odm_pipe->pipe_idx = pipe_idx;
1874 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
1875 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];
1876 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx];
1877 next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx];
1878 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];
1879 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
1880 next_odm_pipe->stream_res.dsc = NULL;
1881 if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) {
1882 next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;
1883 next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe;
1884 }
1885 prev_odm_pipe->next_odm_pipe = next_odm_pipe;
1886 next_odm_pipe->prev_odm_pipe = prev_odm_pipe;
1887 ASSERT(next_odm_pipe->top_pipe == NULL);
1888
1889 if (prev_odm_pipe->plane_state) {
1890 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
1891 int new_width;
1892
1893 /* HACTIVE halved for odm combine */
1894 sd->h_active /= 2;
1895 /* Calculate new vp and recout for left pipe */
1896 /* Need at least 16 pixels width per side */
1897 if (sd->recout.x + 16 >= sd->h_active)
1898 return false;
1899 new_width = sd->h_active - sd->recout.x;
1900 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1901 sd->ratios.horz, sd->recout.width - new_width));
1902 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1903 sd->ratios.horz_c, sd->recout.width - new_width));
1904 sd->recout.width = new_width;
1905
1906 /* Calculate new vp and recout for right pipe */
1907 sd = &next_odm_pipe->plane_res.scl_data;
1908 /* HACTIVE halved for odm combine */
1909 sd->h_active /= 2;
1910 /* Need at least 16 pixels width per side */
1911 if (new_width <= 16)
1912 return false;
1913 new_width = sd->recout.width + sd->recout.x - sd->h_active;
1914 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1915 sd->ratios.horz, sd->recout.width - new_width));
1916 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1917 sd->ratios.horz_c, sd->recout.width - new_width));
1918 sd->recout.width = new_width;
1919 sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int(
1920 sd->ratios.horz, sd->h_active - sd->recout.x));
1921 sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(
1922 sd->ratios.horz_c, sd->h_active - sd->recout.x));
1923 sd->recout.x = 0;
1924 }
1925 next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
1926 if (next_odm_pipe->stream->timing.flags.DSC == 1) {
1927 dcn20_acquire_dsc(dc, res_ctx, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx);
1928 ASSERT(next_odm_pipe->stream_res.dsc);
1929 if (next_odm_pipe->stream_res.dsc == NULL)
1930 return false;
1931 }
1932
1933 return true;
1934 }
1935
dcn20_split_stream_for_mpc(struct resource_context * res_ctx,const struct resource_pool * pool,struct pipe_ctx * primary_pipe,struct pipe_ctx * secondary_pipe)1936 void dcn20_split_stream_for_mpc(
1937 struct resource_context *res_ctx,
1938 const struct resource_pool *pool,
1939 struct pipe_ctx *primary_pipe,
1940 struct pipe_ctx *secondary_pipe)
1941 {
1942 int pipe_idx = secondary_pipe->pipe_idx;
1943 struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;
1944
1945 *secondary_pipe = *primary_pipe;
1946 secondary_pipe->bottom_pipe = sec_bot_pipe;
1947
1948 secondary_pipe->pipe_idx = pipe_idx;
1949 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
1950 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
1951 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
1952 secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
1953 secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
1954 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
1955 secondary_pipe->stream_res.dsc = NULL;
1956 if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) {
1957 ASSERT(!secondary_pipe->bottom_pipe);
1958 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
1959 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
1960 }
1961 primary_pipe->bottom_pipe = secondary_pipe;
1962 secondary_pipe->top_pipe = primary_pipe;
1963
1964 ASSERT(primary_pipe->plane_state);
1965 }
1966
dcn20_populate_dml_writeback_from_context(struct dc * dc,struct resource_context * res_ctx,display_e2e_pipe_params_st * pipes)1967 void dcn20_populate_dml_writeback_from_context(
1968 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1969 {
1970 int pipe_cnt, i;
1971
1972 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1973 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0];
1974
1975 if (!res_ctx->pipe_ctx[i].stream)
1976 continue;
1977
1978 /* Set writeback information */
1979 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0;
1980 pipes[pipe_cnt].dout.num_active_wb++;
1981 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height;
1982 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width;
1983 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width;
1984 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height;
1985 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1;
1986 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1;
1987 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
1988 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
1989 pipes[pipe_cnt].dout.wb.wb_hratio = 1.0;
1990 pipes[pipe_cnt].dout.wb.wb_vratio = 1.0;
1991 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
1992 if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
1993 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8;
1994 else
1995 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10;
1996 } else
1997 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32;
1998
1999 pipe_cnt++;
2000 }
2001
2002 }
2003
dcn20_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes)2004 int dcn20_populate_dml_pipes_from_context(
2005 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes)
2006 {
2007 int pipe_cnt, i;
2008 bool synchronized_vblank = true;
2009 struct resource_context *res_ctx = &context->res_ctx;
2010
2011 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
2012 if (!res_ctx->pipe_ctx[i].stream)
2013 continue;
2014
2015 if (pipe_cnt < 0) {
2016 pipe_cnt = i;
2017 continue;
2018 }
2019
2020 if (res_ctx->pipe_ctx[pipe_cnt].stream == res_ctx->pipe_ctx[i].stream)
2021 continue;
2022
2023 if (dc->debug.disable_timing_sync || !resource_are_streams_timing_synchronizable(
2024 res_ctx->pipe_ctx[pipe_cnt].stream,
2025 res_ctx->pipe_ctx[i].stream)) {
2026 synchronized_vblank = false;
2027 break;
2028 }
2029 }
2030
2031 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2032 struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;
2033 unsigned int v_total;
2034 unsigned int front_porch;
2035 int output_bpc;
2036
2037 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
2038 struct audio_check aud_check = {0};
2039 #endif
2040 if (!res_ctx->pipe_ctx[i].stream)
2041 continue;
2042
2043 v_total = timing->v_total;
2044 front_porch = timing->v_front_porch;
2045 /* todo:
2046 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0;
2047 pipes[pipe_cnt].pipe.src.dcc = 0;
2048 pipes[pipe_cnt].pipe.src.vm = 0;*/
2049
2050 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2051
2052 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;
2053 /* todo: rotation?*/
2054 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
2055 if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) {
2056 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;
2057 /* 1/2 vblank */
2058 pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active =
2059 (v_total - timing->v_addressable
2060 - timing->v_border_top - timing->v_border_bottom) / 2;
2061 /* 36 bytes dp, 32 hdmi */
2062 pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes =
2063 dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32;
2064 }
2065 pipes[pipe_cnt].pipe.src.dcc = false;
2066 pipes[pipe_cnt].pipe.src.dcc_rate = 1;
2067 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank;
2068 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch;
2069 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start
2070 - timing->h_addressable
2071 - timing->h_border_left
2072 - timing->h_border_right;
2073 pipes[pipe_cnt].pipe.dest.vblank_start = v_total - front_porch;
2074 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
2075 - timing->v_addressable
2076 - timing->v_border_top
2077 - timing->v_border_bottom;
2078 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;
2079 pipes[pipe_cnt].pipe.dest.vtotal = v_total;
2080 pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable;
2081 pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable;
2082 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
2083 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
2084 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2085 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
2086 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
2087 pipes[pipe_cnt].dout.dp_lanes = 4;
2088 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
2089 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
2090 switch (get_num_odm_splits(&res_ctx->pipe_ctx[i])) {
2091 case 1:
2092 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_2to1;
2093 break;
2094 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
2095 case 3:
2096 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_4to1;
2097 break;
2098 #endif
2099 default:
2100 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_disabled;
2101 }
2102 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
2103 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
2104 == res_ctx->pipe_ctx[i].plane_state) {
2105 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].top_pipe;
2106 int split_idx = 0;
2107
2108 while (first_pipe->top_pipe && first_pipe->top_pipe->plane_state
2109 == res_ctx->pipe_ctx[i].plane_state) {
2110 first_pipe = first_pipe->top_pipe;
2111 split_idx++;
2112 }
2113 /* Treat 4to1 mpc combine as an mpo of 2 2-to-1 combines */
2114 if (split_idx == 0)
2115 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
2116 else if (split_idx == 1)
2117 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
2118 else if (split_idx == 2)
2119 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
2120 } else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {
2121 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe;
2122
2123 while (first_pipe->prev_odm_pipe)
2124 first_pipe = first_pipe->prev_odm_pipe;
2125 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
2126 }
2127
2128 switch (res_ctx->pipe_ctx[i].stream->signal) {
2129 case SIGNAL_TYPE_DISPLAY_PORT_MST:
2130 case SIGNAL_TYPE_DISPLAY_PORT:
2131 pipes[pipe_cnt].dout.output_type = dm_dp;
2132 break;
2133 case SIGNAL_TYPE_EDP:
2134 pipes[pipe_cnt].dout.output_type = dm_edp;
2135 break;
2136 case SIGNAL_TYPE_HDMI_TYPE_A:
2137 case SIGNAL_TYPE_DVI_SINGLE_LINK:
2138 case SIGNAL_TYPE_DVI_DUAL_LINK:
2139 pipes[pipe_cnt].dout.output_type = dm_hdmi;
2140 break;
2141 default:
2142 /* In case there is no signal, set dp with 4 lanes to allow max config */
2143 pipes[pipe_cnt].dout.output_type = dm_dp;
2144 pipes[pipe_cnt].dout.dp_lanes = 4;
2145 }
2146
2147 switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {
2148 case COLOR_DEPTH_666:
2149 output_bpc = 6;
2150 break;
2151 case COLOR_DEPTH_888:
2152 output_bpc = 8;
2153 break;
2154 case COLOR_DEPTH_101010:
2155 output_bpc = 10;
2156 break;
2157 case COLOR_DEPTH_121212:
2158 output_bpc = 12;
2159 break;
2160 case COLOR_DEPTH_141414:
2161 output_bpc = 14;
2162 break;
2163 case COLOR_DEPTH_161616:
2164 output_bpc = 16;
2165 break;
2166 case COLOR_DEPTH_999:
2167 output_bpc = 9;
2168 break;
2169 case COLOR_DEPTH_111111:
2170 output_bpc = 11;
2171 break;
2172 default:
2173 output_bpc = 8;
2174 break;
2175 }
2176
2177 switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
2178 case PIXEL_ENCODING_RGB:
2179 case PIXEL_ENCODING_YCBCR444:
2180 pipes[pipe_cnt].dout.output_format = dm_444;
2181 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
2182 break;
2183 case PIXEL_ENCODING_YCBCR420:
2184 pipes[pipe_cnt].dout.output_format = dm_420;
2185 pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3.0) / 2;
2186 break;
2187 case PIXEL_ENCODING_YCBCR422:
2188 if (true) /* todo */
2189 pipes[pipe_cnt].dout.output_format = dm_s422;
2190 else
2191 pipes[pipe_cnt].dout.output_format = dm_n422;
2192 pipes[pipe_cnt].dout.output_bpp = output_bpc * 2;
2193 break;
2194 default:
2195 pipes[pipe_cnt].dout.output_format = dm_444;
2196 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
2197 }
2198
2199 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC)
2200 pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0;
2201
2202 /* todo: default max for now, until there is logic reflecting this in dc*/
2203 pipes[pipe_cnt].dout.output_bpc = 12;
2204 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
2205 /*fill up the audio sample rate (unit in kHz)*/
2206 get_audio_check(&res_ctx->pipe_ctx[i].stream->audio_info, &aud_check);
2207 pipes[pipe_cnt].dout.max_audio_sample_rate = aud_check.max_audiosample_rate / 1000;
2208 #endif
2209 /*
2210 * For graphic plane, cursor number is 1, nv12 is 0
2211 * bw calculations due to cursor on/off
2212 */
2213 if (res_ctx->pipe_ctx[i].plane_state &&
2214 res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2215 pipes[pipe_cnt].pipe.src.num_cursors = 0;
2216 else
2217 pipes[pipe_cnt].pipe.src.num_cursors = dc->dml.ip.number_of_cursors;
2218
2219 pipes[pipe_cnt].pipe.src.cur0_src_width = 256;
2220 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit;
2221
2222 if (!res_ctx->pipe_ctx[i].plane_state) {
2223 pipes[pipe_cnt].pipe.src.is_hsplit = pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
2224 pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
2225 pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_4kb_s;
2226 pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
2227 pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
2228 if (pipes[pipe_cnt].pipe.src.viewport_width > 1920)
2229 pipes[pipe_cnt].pipe.src.viewport_width = 1920;
2230 pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
2231 if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)
2232 pipes[pipe_cnt].pipe.src.viewport_height = 1080;
2233 pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height;
2234 pipes[pipe_cnt].pipe.src.surface_width_y = pipes[pipe_cnt].pipe.src.viewport_width;
2235 pipes[pipe_cnt].pipe.src.surface_height_c = pipes[pipe_cnt].pipe.src.viewport_height;
2236 pipes[pipe_cnt].pipe.src.surface_width_c = pipes[pipe_cnt].pipe.src.viewport_width;
2237 pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 255) / 256) * 256;
2238 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
2239 pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/
2240 pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/
2241 pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width; /*when is_hsplit != 1*/
2242 pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/
2243 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
2244 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0;
2245 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0;
2246 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/
2247 pipes[pipe_cnt].pipe.scale_taps.htaps = 1;
2248 pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
2249 pipes[pipe_cnt].pipe.dest.vtotal_min = v_total;
2250 pipes[pipe_cnt].pipe.dest.vtotal_max = v_total;
2251
2252 if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) {
2253 pipes[pipe_cnt].pipe.src.viewport_width /= 2;
2254 pipes[pipe_cnt].pipe.dest.recout_width /= 2;
2255 }
2256 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
2257 else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1) {
2258 pipes[pipe_cnt].pipe.src.viewport_width /= 4;
2259 pipes[pipe_cnt].pipe.dest.recout_width /= 4;
2260 }
2261 #endif
2262 } else {
2263 struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
2264 struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
2265
2266 pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate;
2267 pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
2268 || (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln)
2269 || pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
2270
2271 /* stereo is not split */
2272 if (pln->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE ||
2273 pln->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM) {
2274 pipes[pipe_cnt].pipe.src.is_hsplit = false;
2275 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
2276 }
2277
2278 pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
2279 || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
2280 pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport_unadjusted.y;
2281 pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c_unadjusted.y;
2282 pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport_unadjusted.width;
2283 pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c_unadjusted.width;
2284 pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport_unadjusted.height;
2285 pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c_unadjusted.height;
2286 pipes[pipe_cnt].pipe.src.surface_width_y = pln->plane_size.surface_size.width;
2287 pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height;
2288 pipes[pipe_cnt].pipe.src.surface_width_c = pln->plane_size.chroma_size.width;
2289 pipes[pipe_cnt].pipe.src.surface_height_c = pln->plane_size.chroma_size.height;
2290 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
2291 if (pln->format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA
2292 || pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2293 #else
2294 if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2295 #endif
2296 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
2297 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;
2298 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
2299 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c;
2300 } else {
2301 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
2302 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
2303 }
2304 pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;
2305 pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;
2306 pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height;
2307 pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height;
2308 pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width;
2309 if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1)
2310 pipes[pipe_cnt].pipe.dest.full_recout_width *= 2;
2311 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
2312 else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1)
2313 pipes[pipe_cnt].pipe.dest.full_recout_width *= 4;
2314 #endif
2315 else {
2316 struct pipe_ctx *split_pipe = res_ctx->pipe_ctx[i].bottom_pipe;
2317
2318 while (split_pipe && split_pipe->plane_state == pln) {
2319 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width;
2320 split_pipe = split_pipe->bottom_pipe;
2321 }
2322 split_pipe = res_ctx->pipe_ctx[i].top_pipe;
2323 while (split_pipe && split_pipe->plane_state == pln) {
2324 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width;
2325 split_pipe = split_pipe->top_pipe;
2326 }
2327 }
2328
2329 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
2330 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32);
2331 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32);
2332 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);
2333 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32);
2334 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable =
2335 scl->ratios.vert.value != dc_fixpt_one.value
2336 || scl->ratios.horz.value != dc_fixpt_one.value
2337 || scl->ratios.vert_c.value != dc_fixpt_one.value
2338 || scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/
2339 || dc->debug.always_scale; /*support always scale*/
2340 pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps;
2341 pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c;
2342 pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
2343 pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c;
2344
2345 pipes[pipe_cnt].pipe.src.macro_tile_size =
2346 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle);
2347 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle,
2348 &pipes[pipe_cnt].pipe.src.sw_mode);
2349
2350 switch (pln->format) {
2351 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2352 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2353 pipes[pipe_cnt].pipe.src.source_format = dm_420_8;
2354 break;
2355 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2356 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2357 pipes[pipe_cnt].pipe.src.source_format = dm_420_10;
2358 break;
2359 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2360 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
2361 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2362 pipes[pipe_cnt].pipe.src.source_format = dm_444_64;
2363 break;
2364 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2365 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2366 pipes[pipe_cnt].pipe.src.source_format = dm_444_16;
2367 break;
2368 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2369 pipes[pipe_cnt].pipe.src.source_format = dm_444_8;
2370 break;
2371 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
2372 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
2373 pipes[pipe_cnt].pipe.src.source_format = dm_rgbe_alpha;
2374 break;
2375 #endif
2376 default:
2377 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
2378 break;
2379 }
2380 }
2381
2382 pipe_cnt++;
2383 }
2384
2385 /* populate writeback information */
2386 dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);
2387
2388 return pipe_cnt;
2389 }
2390
2391 unsigned int dcn20_calc_max_scaled_time(
2392 unsigned int time_per_pixel,
2393 enum mmhubbub_wbif_mode mode,
2394 unsigned int urgent_watermark)
2395 {
2396 unsigned int time_per_byte = 0;
2397 unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */
2398 unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */
2399 unsigned int small_free_entry, max_free_entry;
2400 unsigned int buf_lh_capability;
2401 unsigned int max_scaled_time;
2402
2403 if (mode == PACKED_444) /* packed mode */
2404 time_per_byte = time_per_pixel/4;
2405 else if (mode == PLANAR_420_8BPC)
2406 time_per_byte = time_per_pixel;
2407 else if (mode == PLANAR_420_10BPC) /* p010 */
2408 time_per_byte = time_per_pixel * 819/1024;
2409
2410 if (time_per_byte == 0)
2411 time_per_byte = 1;
2412
2413 small_free_entry = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry;
2414 max_free_entry = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry;
2415 buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */
2416 max_scaled_time = buf_lh_capability - urgent_watermark;
2417 return max_scaled_time;
2418 }
2419
2420 void dcn20_set_mcif_arb_params(
2421 struct dc *dc,
2422 struct dc_state *context,
2423 display_e2e_pipe_params_st *pipes,
2424 int pipe_cnt)
2425 {
2426 enum mmhubbub_wbif_mode wbif_mode;
2427 struct mcif_arb_params *wb_arb_params;
2428 int i, j, k, dwb_pipe;
2429
2430 /* Writeback MCIF_WB arbitration parameters */
2431 dwb_pipe = 0;
2432 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2433
2434 if (!context->res_ctx.pipe_ctx[i].stream)
2435 continue;
2436
2437 for (j = 0; j < MAX_DWB_PIPES; j++) {
2438 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false)
2439 continue;
2440
2441 //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
2442 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
2443
2444 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) {
2445 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
2446 wbif_mode = PLANAR_420_8BPC;
2447 else
2448 wbif_mode = PLANAR_420_10BPC;
2449 } else
2450 wbif_mode = PACKED_444;
2451
2452 for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
2453 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2454 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2455 }
2456 wb_arb_params->time_per_pixel = 16.0 / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* 4 bit fraction, ms */
2457 wb_arb_params->slice_lines = 32;
2458 wb_arb_params->arbitration_slice = 2;
2459 wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel,
2460 wbif_mode,
2461 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
2462
2463 dwb_pipe++;
2464
2465 if (dwb_pipe >= MAX_DWB_PIPES)
2466 return;
2467 }
2468 if (dwb_pipe >= MAX_DWB_PIPES)
2469 return;
2470 }
2471 }
2472
2473 bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
2474 {
2475 int i;
2476
2477 /* Validate DSC config, dsc count validation is already done */
2478 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2479 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
2480 struct dc_stream_state *stream = pipe_ctx->stream;
2481 struct dsc_config dsc_cfg;
2482 struct pipe_ctx *odm_pipe;
2483 int opp_cnt = 1;
2484
2485 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
2486 opp_cnt++;
2487
2488 /* Only need to validate top pipe */
2489 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)
2490 continue;
2491
2492 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left
2493 + stream->timing.h_border_right) / opp_cnt;
2494 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
2495 + stream->timing.v_border_bottom;
2496 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
2497 dsc_cfg.color_depth = stream->timing.display_color_depth;
2498 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
2499 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
2500 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
2501
2502 if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))
2503 return false;
2504 }
2505 return true;
2506 }
2507
2508 struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
2509 struct resource_context *res_ctx,
2510 const struct resource_pool *pool,
2511 const struct pipe_ctx *primary_pipe)
2512 {
2513 struct pipe_ctx *secondary_pipe = NULL;
2514
2515 if (dc && primary_pipe) {
2516 int j;
2517 int preferred_pipe_idx = 0;
2518
2519 /* first check the prev dc state:
2520 * if this primary pipe has a bottom pipe in prev. state
2521 * and if the bottom pipe is still available (which it should be),
2522 * pick that pipe as secondary
2523 * Same logic applies for ODM pipes. Since mpo is not allowed with odm
2524 * check in else case.
2525 */
2526 if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) {
2527 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;
2528 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2529 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2530 secondary_pipe->pipe_idx = preferred_pipe_idx;
2531 }
2532 } else if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) {
2533 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx;
2534 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2535 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2536 secondary_pipe->pipe_idx = preferred_pipe_idx;
2537 }
2538 }
2539
2540 /*
2541 * if this primary pipe does not have a bottom pipe in prev. state
2542 * start backward and find a pipe that did not used to be a bottom pipe in
2543 * prev. dc state. This way we make sure we keep the same assignment as
2544 * last state and will not have to reprogram every pipe
2545 */
2546 if (secondary_pipe == NULL) {
2547 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2548 if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL
2549 && dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) {
2550 preferred_pipe_idx = j;
2551
2552 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2553 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2554 secondary_pipe->pipe_idx = preferred_pipe_idx;
2555 break;
2556 }
2557 }
2558 }
2559 }
2560 /*
2561 * We should never hit this assert unless assignments are shuffled around
2562 * if this happens we will prob. hit a vsync tdr
2563 */
2564 ASSERT(secondary_pipe);
2565 /*
2566 * search backwards for the second pipe to keep pipe
2567 * assignment more consistent
2568 */
2569 if (secondary_pipe == NULL) {
2570 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2571 preferred_pipe_idx = j;
2572
2573 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2574 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2575 secondary_pipe->pipe_idx = preferred_pipe_idx;
2576 break;
2577 }
2578 }
2579 }
2580 }
2581
2582 return secondary_pipe;
2583 }
2584
2585 static void dcn20_merge_pipes_for_validate(
2586 struct dc *dc,
2587 struct dc_state *context)
2588 {
2589 int i;
2590
2591 /* merge previously split odm pipes since mode support needs to make the decision */
2592 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2593 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2594 struct pipe_ctx *odm_pipe = pipe->next_odm_pipe;
2595
2596 if (pipe->prev_odm_pipe)
2597 continue;
2598
2599 pipe->next_odm_pipe = NULL;
2600 while (odm_pipe) {
2601 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
2602
2603 odm_pipe->plane_state = NULL;
2604 odm_pipe->stream = NULL;
2605 odm_pipe->top_pipe = NULL;
2606 odm_pipe->bottom_pipe = NULL;
2607 odm_pipe->prev_odm_pipe = NULL;
2608 odm_pipe->next_odm_pipe = NULL;
2609 if (odm_pipe->stream_res.dsc)
2610 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
2611 /* Clear plane_res and stream_res */
2612 memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res));
2613 memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res));
2614 odm_pipe = next_odm_pipe;
2615 }
2616 if (pipe->plane_state)
2617 resource_build_scaling_params(pipe);
2618 }
2619
2620 /* merge previously mpc split pipes since mode support needs to make the decision */
2621 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2622 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2623 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2624
2625 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)
2626 continue;
2627
2628 pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
2629 if (hsplit_pipe->bottom_pipe)
2630 hsplit_pipe->bottom_pipe->top_pipe = pipe;
2631 hsplit_pipe->plane_state = NULL;
2632 hsplit_pipe->stream = NULL;
2633 hsplit_pipe->top_pipe = NULL;
2634 hsplit_pipe->bottom_pipe = NULL;
2635
2636 /* Clear plane_res and stream_res */
2637 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
2638 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
2639 if (pipe->plane_state)
2640 resource_build_scaling_params(pipe);
2641 }
2642 }
2643
2644 int dcn20_validate_apply_pipe_split_flags(
2645 struct dc *dc,
2646 struct dc_state *context,
2647 int vlevel,
2648 int *split,
2649 bool *merge)
2650 {
2651 int i, pipe_idx, vlevel_split;
2652 int plane_count = 0;
2653 bool force_split = false;
2654 bool avoid_split = dc->debug.pipe_split_policy == MPC_SPLIT_AVOID;
2655 struct vba_vars_st *v = &context->bw_ctx.dml.vba;
2656 int max_mpc_comb = v->maxMpcComb;
2657
2658 if (context->stream_count > 1) {
2659 if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP)
2660 avoid_split = true;
2661 } else if (dc->debug.force_single_disp_pipe_split)
2662 force_split = true;
2663
2664 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2665 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2666
2667 /**
2668 * Workaround for avoiding pipe-split in cases where we'd split
2669 * planes that are too small, resulting in splits that aren't
2670 * valid for the scaler.
2671 */
2672 if (pipe->plane_state &&
2673 (pipe->plane_state->dst_rect.width <= 16 ||
2674 pipe->plane_state->dst_rect.height <= 16 ||
2675 pipe->plane_state->src_rect.width <= 16 ||
2676 pipe->plane_state->src_rect.height <= 16))
2677 avoid_split = true;
2678
2679 /* TODO: fix dc bugs and remove this split threshold thing */
2680 if (pipe->stream && !pipe->prev_odm_pipe &&
2681 (!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state))
2682 ++plane_count;
2683 }
2684 if (plane_count > dc->res_pool->pipe_count / 2)
2685 avoid_split = true;
2686
2687 /* W/A: Mode timing with borders may not work well with pipe split, avoid for this corner case */
2688 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2689 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2690 struct dc_crtc_timing timing;
2691
2692 if (!pipe->stream)
2693 continue;
2694 else {
2695 timing = pipe->stream->timing;
2696 if (timing.h_border_left + timing.h_border_right
2697 + timing.v_border_top + timing.v_border_bottom > 0) {
2698 avoid_split = true;
2699 break;
2700 }
2701 }
2702 }
2703
2704 /* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */
2705 if (avoid_split) {
2706 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2707 if (!context->res_ctx.pipe_ctx[i].stream)
2708 continue;
2709
2710 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
2711 if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 &&
2712 v->ModeSupport[vlevel][0])
2713 break;
2714 /* Impossible to not split this pipe */
2715 if (vlevel > context->bw_ctx.dml.soc.num_states)
2716 vlevel = vlevel_split;
2717 else
2718 max_mpc_comb = 0;
2719 pipe_idx++;
2720 }
2721 v->maxMpcComb = max_mpc_comb;
2722 }
2723
2724 /* Split loop sets which pipe should be split based on dml outputs and dc flags */
2725 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2726 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2727 int pipe_plane = v->pipe_plane[pipe_idx];
2728 bool split4mpc = context->stream_count == 1 && plane_count == 1
2729 && dc->config.enable_4to1MPC && dc->res_pool->pipe_count >= 4;
2730
2731 if (!context->res_ctx.pipe_ctx[i].stream)
2732 continue;
2733
2734 if (split4mpc || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 4)
2735 split[i] = 4;
2736 else if (force_split || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 2)
2737 split[i] = 2;
2738
2739 if ((pipe->stream->view_format ==
2740 VIEW_3D_FORMAT_SIDE_BY_SIDE ||
2741 pipe->stream->view_format ==
2742 VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
2743 (pipe->stream->timing.timing_3d_format ==
2744 TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
2745 pipe->stream->timing.timing_3d_format ==
2746 TIMING_3D_FORMAT_SIDE_BY_SIDE))
2747 split[i] = 2;
2748 if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {
2749 split[i] = 2;
2750 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1;
2751 }
2752 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
2753 if (dc->debug.force_odm_combine_4to1 & (1 << pipe->stream_res.tg->inst)) {
2754 split[i] = 4;
2755 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_4to1;
2756 }
2757 /*420 format workaround*/
2758 if (pipe->stream->timing.h_addressable > 7680 &&
2759 pipe->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
2760 split[i] = 4;
2761 }
2762 #endif
2763 v->ODMCombineEnabled[pipe_plane] =
2764 v->ODMCombineEnablePerState[vlevel][pipe_plane];
2765
2766 if (v->ODMCombineEnabled[pipe_plane] == dm_odm_combine_mode_disabled) {
2767 if (get_num_mpc_splits(pipe) == 1) {
2768 /*If need split for mpc but 2 way split already*/
2769 if (split[i] == 4)
2770 split[i] = 2; /* 2 -> 4 MPC */
2771 else if (split[i] == 2)
2772 split[i] = 0; /* 2 -> 2 MPC */
2773 else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
2774 merge[i] = true; /* 2 -> 1 MPC */
2775 } else if (get_num_mpc_splits(pipe) == 3) {
2776 /*If need split for mpc but 4 way split already*/
2777 if (split[i] == 2 && ((pipe->top_pipe && !pipe->top_pipe->top_pipe)
2778 || !pipe->bottom_pipe)) {
2779 merge[i] = true; /* 4 -> 2 MPC */
2780 } else if (split[i] == 0 && pipe->top_pipe &&
2781 pipe->top_pipe->plane_state == pipe->plane_state)
2782 merge[i] = true; /* 4 -> 1 MPC */
2783 split[i] = 0;
2784 } else if (get_num_odm_splits(pipe)) {
2785 /* ODM -> MPC transition */
2786 ASSERT(0); /* NOT expected yet */
2787 if (pipe->prev_odm_pipe) {
2788 split[i] = 0;
2789 merge[i] = true;
2790 }
2791 }
2792 } else {
2793 if (get_num_odm_splits(pipe) == 1) {
2794 /*If need split for odm but 2 way split already*/
2795 if (split[i] == 4)
2796 split[i] = 2; /* 2 -> 4 ODM */
2797 else if (split[i] == 2)
2798 split[i] = 0; /* 2 -> 2 ODM */
2799 else if (pipe->prev_odm_pipe) {
2800 ASSERT(0); /* NOT expected yet */
2801 merge[i] = true; /* exit ODM */
2802 }
2803 } else if (get_num_odm_splits(pipe) == 3) {
2804 /*If need split for odm but 4 way split already*/
2805 if (split[i] == 2 && ((pipe->prev_odm_pipe && !pipe->prev_odm_pipe->prev_odm_pipe)
2806 || !pipe->next_odm_pipe)) {
2807 ASSERT(0); /* NOT expected yet */
2808 merge[i] = true; /* 4 -> 2 ODM */
2809 } else if (split[i] == 0 && pipe->prev_odm_pipe) {
2810 ASSERT(0); /* NOT expected yet */
2811 merge[i] = true; /* exit ODM */
2812 }
2813 split[i] = 0;
2814 } else if (get_num_mpc_splits(pipe)) {
2815 /* MPC -> ODM transition */
2816 ASSERT(0); /* NOT expected yet */
2817 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
2818 split[i] = 0;
2819 merge[i] = true;
2820 }
2821 }
2822 }
2823
2824 /* Adjust dppclk when split is forced, do not bother with dispclk */
2825 if (split[i] != 0 && v->NoOfDPP[vlevel][max_mpc_comb][pipe_idx] == 1)
2826 v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] /= 2;
2827 pipe_idx++;
2828 }
2829
2830 return vlevel;
2831 }
2832
2833 bool dcn20_fast_validate_bw(
2834 struct dc *dc,
2835 struct dc_state *context,
2836 display_e2e_pipe_params_st *pipes,
2837 int *pipe_cnt_out,
2838 int *pipe_split_from,
2839 int *vlevel_out)
2840 {
2841 bool out = false;
2842 int split[MAX_PIPES] = { 0 };
2843 int pipe_cnt, i, pipe_idx, vlevel;
2844
2845 ASSERT(pipes);
2846 if (!pipes)
2847 return false;
2848
2849 dcn20_merge_pipes_for_validate(dc, context);
2850
2851 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes);
2852
2853 *pipe_cnt_out = pipe_cnt;
2854
2855 if (!pipe_cnt) {
2856 out = true;
2857 goto validate_out;
2858 }
2859
2860 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2861
2862 if (vlevel > context->bw_ctx.dml.soc.num_states)
2863 goto validate_fail;
2864
2865 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL);
2866
2867 /*initialize pipe_just_split_from to invalid idx*/
2868 for (i = 0; i < MAX_PIPES; i++)
2869 pipe_split_from[i] = -1;
2870
2871 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
2872 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2873 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2874
2875 if (!pipe->stream || pipe_split_from[i] >= 0)
2876 continue;
2877
2878 pipe_idx++;
2879
2880 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2881 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
2882 ASSERT(hsplit_pipe);
2883 if (!dcn20_split_stream_for_odm(
2884 dc, &context->res_ctx,
2885 pipe, hsplit_pipe))
2886 goto validate_fail;
2887 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2888 dcn20_build_mapped_resource(dc, context, pipe->stream);
2889 }
2890
2891 if (!pipe->plane_state)
2892 continue;
2893 /* Skip 2nd half of already split pipe */
2894 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
2895 continue;
2896
2897 /* We do not support mpo + odm at the moment */
2898 if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state
2899 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])
2900 goto validate_fail;
2901
2902 if (split[i] == 2) {
2903 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
2904 /* pipe not split previously needs split */
2905 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
2906 ASSERT(hsplit_pipe);
2907 if (!hsplit_pipe) {
2908 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2;
2909 continue;
2910 }
2911 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2912 if (!dcn20_split_stream_for_odm(
2913 dc, &context->res_ctx,
2914 pipe, hsplit_pipe))
2915 goto validate_fail;
2916 dcn20_build_mapped_resource(dc, context, pipe->stream);
2917 } else {
2918 dcn20_split_stream_for_mpc(
2919 &context->res_ctx, dc->res_pool,
2920 pipe, hsplit_pipe);
2921 resource_build_scaling_params(pipe);
2922 resource_build_scaling_params(hsplit_pipe);
2923 }
2924 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2925 }
2926 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
2927 /* merge should already have been done */
2928 ASSERT(0);
2929 }
2930 }
2931 /* Actual dsc count per stream dsc validation*/
2932 if (!dcn20_validate_dsc(dc, context)) {
2933 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
2934 DML_FAIL_DSC_VALIDATION_FAILURE;
2935 goto validate_fail;
2936 }
2937
2938 *vlevel_out = vlevel;
2939
2940 out = true;
2941 goto validate_out;
2942
2943 validate_fail:
2944 out = false;
2945
2946 validate_out:
2947 return out;
2948 }
2949
2950 static void dcn20_calculate_wm(
2951 struct dc *dc, struct dc_state *context,
2952 display_e2e_pipe_params_st *pipes,
2953 int *out_pipe_cnt,
2954 int *pipe_split_from,
2955 int vlevel)
2956 {
2957 int pipe_cnt, i, pipe_idx;
2958
2959 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2960 if (!context->res_ctx.pipe_ctx[i].stream)
2961 continue;
2962
2963 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2964 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2965
2966 if (pipe_split_from[i] < 0) {
2967 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2968 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
2969 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
2970 pipes[pipe_cnt].pipe.dest.odm_combine =
2971 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx];
2972 else
2973 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2974 pipe_idx++;
2975 } else {
2976 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2977 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
2978 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
2979 pipes[pipe_cnt].pipe.dest.odm_combine =
2980 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_split_from[i]];
2981 else
2982 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2983 }
2984
2985 if (dc->config.forced_clocks) {
2986 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2987 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
2988 }
2989 if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
2990 pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
2991 if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)
2992 pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
2993
2994 pipe_cnt++;
2995 }
2996
2997 if (pipe_cnt != pipe_idx) {
2998 if (dc->res_pool->funcs->populate_dml_pipes)
2999 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
3000 context, pipes);
3001 else
3002 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
3003 context, pipes);
3004 }
3005
3006 *out_pipe_cnt = pipe_cnt;
3007
3008 pipes[0].clks_cfg.voltage = vlevel;
3009 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
3010 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
3011
3012 /* only pipe 0 is read for voltage and dcf/soc clocks */
3013 if (vlevel < 1) {
3014 pipes[0].clks_cfg.voltage = 1;
3015 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
3016 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
3017 }
3018 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3019 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3020 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3021 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3022 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3023 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3024 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3025 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3026
3027 if (vlevel < 2) {
3028 pipes[0].clks_cfg.voltage = 2;
3029 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
3030 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
3031 }
3032 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3033 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3034 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3035 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3036 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3037 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3038 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3039
3040 if (vlevel < 3) {
3041 pipes[0].clks_cfg.voltage = 3;
3042 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
3043 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
3044 }
3045 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3046 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3047 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3048 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3049 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3050 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3051 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3052
3053 pipes[0].clks_cfg.voltage = vlevel;
3054 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
3055 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
3056 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3057 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3058 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3059 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3060 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3061 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3062 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3063 }
3064
3065 void dcn20_calculate_dlg_params(
3066 struct dc *dc, struct dc_state *context,
3067 display_e2e_pipe_params_st *pipes,
3068 int pipe_cnt,
3069 int vlevel)
3070 {
3071 int i, pipe_idx;
3072
3073 /* Writeback MCIF_WB arbitration parameters */
3074 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
3075
3076 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
3077 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
3078 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
3079 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
3080 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
3081 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
3082 context->bw_ctx.bw.dcn.clk.p_state_change_support =
3083 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
3084 != dm_dram_clock_change_unsupported;
3085 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
3086
3087 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
3088 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
3089
3090 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
3091 if (!context->res_ctx.pipe_ctx[i].stream)
3092 continue;
3093 pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
3094 pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
3095 pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
3096 pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
3097 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
3098 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
3099 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
3100 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
3101 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
3102 pipe_idx++;
3103 }
3104 /*save a original dppclock copy*/
3105 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
3106 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
3107 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;
3108 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;
3109
3110 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
3111 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
3112
3113 if (!context->res_ctx.pipe_ctx[i].stream)
3114 continue;
3115
3116 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml,
3117 &context->res_ctx.pipe_ctx[i].dlg_regs,
3118 &context->res_ctx.pipe_ctx[i].ttu_regs,
3119 pipes,
3120 pipe_cnt,
3121 pipe_idx,
3122 cstate_en,
3123 context->bw_ctx.bw.dcn.clk.p_state_change_support,
3124 false, false, true);
3125
3126 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
3127 &context->res_ctx.pipe_ctx[i].rq_regs,
3128 pipes[pipe_idx].pipe);
3129 pipe_idx++;
3130 }
3131 }
3132
3133 static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,
3134 bool fast_validate)
3135 {
3136 bool out = false;
3137
3138 BW_VAL_TRACE_SETUP();
3139
3140 int vlevel = 0;
3141 int pipe_split_from[MAX_PIPES];
3142 int pipe_cnt = 0;
3143 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
3144 DC_LOGGER_INIT(dc->ctx->logger);
3145
3146 BW_VAL_TRACE_COUNT();
3147
3148 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
3149
3150 if (pipe_cnt == 0)
3151 goto validate_out;
3152
3153 if (!out)
3154 goto validate_fail;
3155
3156 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
3157
3158 if (fast_validate) {
3159 BW_VAL_TRACE_SKIP(fast);
3160 goto validate_out;
3161 }
3162
3163 dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
3164 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
3165
3166 BW_VAL_TRACE_END_WATERMARKS();
3167
3168 goto validate_out;
3169
3170 validate_fail:
3171 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
3172 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
3173
3174 BW_VAL_TRACE_SKIP(fail);
3175 out = false;
3176
3177 validate_out:
3178 kfree(pipes);
3179
3180 BW_VAL_TRACE_FINISH();
3181
3182 return out;
3183 }
3184
3185 /*
3186 * This must be noinline to ensure anything that deals with FP registers
3187 * is contained within this call; previously our compiling with hard-float
3188 * would result in fp instructions being emitted outside of the boundaries
3189 * of the DC_FP_START/END macros, which makes sense as the compiler has no
3190 * idea about what is wrapped and what is not
3191 *
3192 * This is largely just a workaround to avoid breakage introduced with 5.6,
3193 * ideally all fp-using code should be moved into its own file, only that
3194 * should be compiled with hard-float, and all code exported from there
3195 * should be strictly wrapped with DC_FP_START/END
3196 */
3197 static noinline bool dcn20_validate_bandwidth_fp(struct dc *dc,
3198 struct dc_state *context, bool fast_validate)
3199 {
3200 bool voltage_supported = false;
3201 bool full_pstate_supported = false;
3202 bool dummy_pstate_supported = false;
3203 double p_state_latency_us;
3204
3205 p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;
3206 context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support =
3207 dc->debug.disable_dram_clock_change_vactive_support;
3208 context->bw_ctx.dml.soc.allow_dram_clock_one_display_vactive =
3209 dc->debug.enable_dram_clock_change_one_display_vactive;
3210
3211 /*Unsafe due to current pipe merge and split logic*/
3212 ASSERT(context != dc->current_state);
3213
3214 if (fast_validate) {
3215 return dcn20_validate_bandwidth_internal(dc, context, true);
3216 }
3217
3218 // Best case, we support full UCLK switch latency
3219 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
3220 full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
3221
3222 if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 ||
3223 (voltage_supported && full_pstate_supported)) {
3224 context->bw_ctx.bw.dcn.clk.p_state_change_support = full_pstate_supported;
3225 goto restore_dml_state;
3226 }
3227
3228 // Fallback: Try to only support G6 temperature read latency
3229 context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
3230
3231 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
3232 dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
3233
3234 if (voltage_supported && dummy_pstate_supported) {
3235 context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
3236 goto restore_dml_state;
3237 }
3238
3239 // ERROR: fallback is supposed to always work.
3240 ASSERT(false);
3241
3242 restore_dml_state:
3243 context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;
3244 return voltage_supported;
3245 }
3246
3247 bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
3248 bool fast_validate)
3249 {
3250 bool voltage_supported = false;
3251 DC_FP_START();
3252 voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate);
3253 DC_FP_END();
3254 return voltage_supported;
3255 }
3256
3257 struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(
3258 struct dc_state *state,
3259 const struct resource_pool *pool,
3260 struct dc_stream_state *stream)
3261 {
3262 struct resource_context *res_ctx = &state->res_ctx;
3263 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
3264 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe);
3265
3266 if (!head_pipe)
3267 ASSERT(0);
3268
3269 if (!idle_pipe)
3270 return NULL;
3271
3272 idle_pipe->stream = head_pipe->stream;
3273 idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
3274 idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
3275
3276 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
3277 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
3278 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
3279 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
3280
3281 return idle_pipe;
3282 }
3283
3284 bool dcn20_get_dcc_compression_cap(const struct dc *dc,
3285 const struct dc_dcc_surface_param *input,
3286 struct dc_surface_dcc_cap *output)
3287 {
3288 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
3289 dc->res_pool->hubbub,
3290 input,
3291 output);
3292 }
3293
3294 static void dcn20_destroy_resource_pool(struct resource_pool **pool)
3295 {
3296 struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool);
3297
3298 dcn20_resource_destruct(dcn20_pool);
3299 kfree(dcn20_pool);
3300 *pool = NULL;
3301 }
3302
3303
3304 static struct dc_cap_funcs cap_funcs = {
3305 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
3306 };
3307
3308
3309 enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state)
3310 {
3311 enum surface_pixel_format surf_pix_format = plane_state->format;
3312 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
3313
3314 enum swizzle_mode_values swizzle = DC_SW_LINEAR;
3315
3316 if (bpp == 64)
3317 swizzle = DC_SW_64KB_D;
3318 else
3319 swizzle = DC_SW_64KB_S;
3320
3321 plane_state->tiling_info.gfx9.swizzle = swizzle;
3322 return DC_OK;
3323 }
3324
3325 static const struct resource_funcs dcn20_res_pool_funcs = {
3326 .destroy = dcn20_destroy_resource_pool,
3327 .link_enc_create = dcn20_link_encoder_create,
3328 .panel_cntl_create = dcn20_panel_cntl_create,
3329 .validate_bandwidth = dcn20_validate_bandwidth,
3330 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
3331 .add_stream_to_ctx = dcn20_add_stream_to_ctx,
3332 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
3333 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
3334 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
3335 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
3336 .set_mcif_arb_params = dcn20_set_mcif_arb_params,
3337 .populate_dml_pipes = dcn20_populate_dml_pipes_from_context,
3338 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
3339 };
3340
3341 bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
3342 {
3343 int i;
3344 uint32_t pipe_count = pool->res_cap->num_dwb;
3345
3346 for (i = 0; i < pipe_count; i++) {
3347 struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc),
3348 GFP_KERNEL);
3349
3350 if (!dwbc20) {
3351 dm_error("DC: failed to create dwbc20!\n");
3352 return false;
3353 }
3354 dcn20_dwbc_construct(dwbc20, ctx,
3355 &dwbc20_regs[i],
3356 &dwbc20_shift,
3357 &dwbc20_mask,
3358 i);
3359 pool->dwbc[i] = &dwbc20->base;
3360 }
3361 return true;
3362 }
3363
3364 bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
3365 {
3366 int i;
3367 uint32_t pipe_count = pool->res_cap->num_dwb;
3368
3369 ASSERT(pipe_count > 0);
3370
3371 for (i = 0; i < pipe_count; i++) {
3372 struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub),
3373 GFP_KERNEL);
3374
3375 if (!mcif_wb20) {
3376 dm_error("DC: failed to create mcif_wb20!\n");
3377 return false;
3378 }
3379
3380 dcn20_mmhubbub_construct(mcif_wb20, ctx,
3381 &mcif_wb20_regs[i],
3382 &mcif_wb20_shift,
3383 &mcif_wb20_mask,
3384 i);
3385
3386 pool->mcif_wb[i] = &mcif_wb20->base;
3387 }
3388 return true;
3389 }
3390
3391 static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
3392 {
3393 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
3394
3395 if (!pp_smu)
3396 return pp_smu;
3397
3398 dm_pp_get_funcs(ctx, pp_smu);
3399
3400 if (pp_smu->ctx.ver != PP_SMU_VER_NV)
3401 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
3402
3403 return pp_smu;
3404 }
3405
3406 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
3407 {
3408 if (pp_smu && *pp_smu) {
3409 kfree(*pp_smu);
3410 *pp_smu = NULL;
3411 }
3412 }
3413
3414 void dcn20_cap_soc_clocks(
3415 struct _vcs_dpi_soc_bounding_box_st *bb,
3416 struct pp_smu_nv_clock_table max_clocks)
3417 {
3418 int i;
3419
3420 // First pass - cap all clocks higher than the reported max
3421 for (i = 0; i < bb->num_states; i++) {
3422 if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000))
3423 && max_clocks.dcfClockInKhz != 0)
3424 bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000);
3425
3426 if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16)
3427 && max_clocks.uClockInKhz != 0)
3428 bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
3429
3430 if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
3431 && max_clocks.fabricClockInKhz != 0)
3432 bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
3433
3434 if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000))
3435 && max_clocks.displayClockInKhz != 0)
3436 bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000);
3437
3438 if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000))
3439 && max_clocks.dppClockInKhz != 0)
3440 bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000);
3441
3442 if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000))
3443 && max_clocks.phyClockInKhz != 0)
3444 bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000);
3445
3446 if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000))
3447 && max_clocks.socClockInKhz != 0)
3448 bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000);
3449
3450 if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000))
3451 && max_clocks.dscClockInKhz != 0)
3452 bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000);
3453 }
3454
3455 // Second pass - remove all duplicate clock states
3456 for (i = bb->num_states - 1; i > 1; i--) {
3457 bool duplicate = true;
3458
3459 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz)
3460 duplicate = false;
3461 if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz)
3462 duplicate = false;
3463 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz)
3464 duplicate = false;
3465 if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts)
3466 duplicate = false;
3467 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz)
3468 duplicate = false;
3469 if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz)
3470 duplicate = false;
3471 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz)
3472 duplicate = false;
3473 if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz)
3474 duplicate = false;
3475
3476 if (duplicate)
3477 bb->num_states--;
3478 }
3479 }
3480
3481 void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
3482 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
3483 {
3484 struct _vcs_dpi_voltage_scaling_st calculated_states[DC__VOLTAGE_STATES];
3485 int i;
3486 int num_calculated_states = 0;
3487 int min_dcfclk = 0;
3488
3489 if (num_states == 0)
3490 return;
3491
3492 memset(calculated_states, 0, sizeof(calculated_states));
3493
3494 if (dc->bb_overrides.min_dcfclk_mhz > 0)
3495 min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
3496 else {
3497 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
3498 min_dcfclk = 310;
3499 else
3500 // Accounting for SOC/DCF relationship, we can go as high as
3501 // 506Mhz in Vmin.
3502 min_dcfclk = 506;
3503 }
3504
3505 for (i = 0; i < num_states; i++) {
3506 int min_fclk_required_by_uclk;
3507 calculated_states[i].state = i;
3508 calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
3509
3510 // FCLK:UCLK ratio is 1.08
3511 min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32);
3512
3513 calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
3514 min_dcfclk : min_fclk_required_by_uclk;
3515
3516 calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
3517 max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
3518
3519 calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
3520 max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
3521
3522 calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
3523 calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
3524 calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
3525
3526 calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
3527
3528 num_calculated_states++;
3529 }
3530
3531 calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
3532 calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
3533 calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
3534
3535 memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits));
3536 bb->num_states = num_calculated_states;
3537
3538 // Duplicate the last state, DML always an extra state identical to max state to work
3539 memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st));
3540 bb->clock_limits[num_calculated_states].state = bb->num_states;
3541 }
3542
3543 void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
3544 {
3545 if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
3546 && dc->bb_overrides.sr_exit_time_ns) {
3547 bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
3548 }
3549
3550 if ((int)(bb->sr_enter_plus_exit_time_us * 1000)
3551 != dc->bb_overrides.sr_enter_plus_exit_time_ns
3552 && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
3553 bb->sr_enter_plus_exit_time_us =
3554 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
3555 }
3556
3557 if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
3558 && dc->bb_overrides.urgent_latency_ns) {
3559 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
3560 }
3561
3562 if ((int)(bb->dram_clock_change_latency_us * 1000)
3563 != dc->bb_overrides.dram_clock_change_latency_ns
3564 && dc->bb_overrides.dram_clock_change_latency_ns) {
3565 bb->dram_clock_change_latency_us =
3566 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
3567 }
3568
3569 if ((int)(bb->dummy_pstate_latency_us * 1000)
3570 != dc->bb_overrides.dummy_clock_change_latency_ns
3571 && dc->bb_overrides.dummy_clock_change_latency_ns) {
3572 bb->dummy_pstate_latency_us =
3573 dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;
3574 }
3575 }
3576
3577 static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(
3578 uint32_t hw_internal_rev)
3579 {
3580 if (ASICREV_IS_NAVI14_M(hw_internal_rev))
3581 return &dcn2_0_nv14_soc;
3582
3583 if (ASICREV_IS_NAVI12_P(hw_internal_rev))
3584 return &dcn2_0_nv12_soc;
3585
3586 return &dcn2_0_soc;
3587 }
3588
3589 static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params(
3590 uint32_t hw_internal_rev)
3591 {
3592 /* NV14 */
3593 if (ASICREV_IS_NAVI14_M(hw_internal_rev))
3594 return &dcn2_0_nv14_ip;
3595
3596 /* NV12 and NV10 */
3597 return &dcn2_0_ip;
3598 }
3599
3600 static enum dml_project get_dml_project_version(uint32_t hw_internal_rev)
3601 {
3602 return DML_PROJECT_NAVI10v2;
3603 }
3604
3605 #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
3606 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
3607
3608 static bool init_soc_bounding_box(struct dc *dc,
3609 struct dcn20_resource_pool *pool)
3610 {
3611 const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box;
3612 struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
3613 get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev);
3614 struct _vcs_dpi_ip_params_st *loaded_ip =
3615 get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev);
3616
3617 DC_LOGGER_INIT(dc->ctx->logger);
3618
3619 /* TODO: upstream NV12 bounding box when its launched */
3620 if (!bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
3621 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
3622 return false;
3623 }
3624
3625 if (bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
3626 int i;
3627
3628 dcn2_0_nv12_soc.sr_exit_time_us =
3629 fixed16_to_double_to_cpu(bb->sr_exit_time_us);
3630 dcn2_0_nv12_soc.sr_enter_plus_exit_time_us =
3631 fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us);
3632 dcn2_0_nv12_soc.urgent_latency_us =
3633 fixed16_to_double_to_cpu(bb->urgent_latency_us);
3634 dcn2_0_nv12_soc.urgent_latency_pixel_data_only_us =
3635 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us);
3636 dcn2_0_nv12_soc.urgent_latency_pixel_mixed_with_vm_data_us =
3637 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us);
3638 dcn2_0_nv12_soc.urgent_latency_vm_data_only_us =
3639 fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us);
3640 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes =
3641 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes);
3642 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes =
3643 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes);
3644 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_vm_only_bytes =
3645 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes);
3646 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only =
3647 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only);
3648 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm =
3649 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm);
3650 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only =
3651 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only);
3652 dcn2_0_nv12_soc.max_avg_sdp_bw_use_normal_percent =
3653 fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent);
3654 dcn2_0_nv12_soc.max_avg_dram_bw_use_normal_percent =
3655 fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent);
3656 dcn2_0_nv12_soc.writeback_latency_us =
3657 fixed16_to_double_to_cpu(bb->writeback_latency_us);
3658 dcn2_0_nv12_soc.ideal_dram_bw_after_urgent_percent =
3659 fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent);
3660 dcn2_0_nv12_soc.max_request_size_bytes =
3661 le32_to_cpu(bb->max_request_size_bytes);
3662 dcn2_0_nv12_soc.dram_channel_width_bytes =
3663 le32_to_cpu(bb->dram_channel_width_bytes);
3664 dcn2_0_nv12_soc.fabric_datapath_to_dcn_data_return_bytes =
3665 le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes);
3666 dcn2_0_nv12_soc.dcn_downspread_percent =
3667 fixed16_to_double_to_cpu(bb->dcn_downspread_percent);
3668 dcn2_0_nv12_soc.downspread_percent =
3669 fixed16_to_double_to_cpu(bb->downspread_percent);
3670 dcn2_0_nv12_soc.dram_page_open_time_ns =
3671 fixed16_to_double_to_cpu(bb->dram_page_open_time_ns);
3672 dcn2_0_nv12_soc.dram_rw_turnaround_time_ns =
3673 fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns);
3674 dcn2_0_nv12_soc.dram_return_buffer_per_channel_bytes =
3675 le32_to_cpu(bb->dram_return_buffer_per_channel_bytes);
3676 dcn2_0_nv12_soc.round_trip_ping_latency_dcfclk_cycles =
3677 le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles);
3678 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_bytes =
3679 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes);
3680 dcn2_0_nv12_soc.channel_interleave_bytes =
3681 le32_to_cpu(bb->channel_interleave_bytes);
3682 dcn2_0_nv12_soc.num_banks =
3683 le32_to_cpu(bb->num_banks);
3684 dcn2_0_nv12_soc.num_chans =
3685 le32_to_cpu(bb->num_chans);
3686 dcn2_0_nv12_soc.vmm_page_size_bytes =
3687 le32_to_cpu(bb->vmm_page_size_bytes);
3688 dcn2_0_nv12_soc.dram_clock_change_latency_us =
3689 fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
3690 // HACK!! Lower uclock latency switch time so we don't switch
3691 dcn2_0_nv12_soc.dram_clock_change_latency_us = 10;
3692 dcn2_0_nv12_soc.writeback_dram_clock_change_latency_us =
3693 fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us);
3694 dcn2_0_nv12_soc.return_bus_width_bytes =
3695 le32_to_cpu(bb->return_bus_width_bytes);
3696 dcn2_0_nv12_soc.dispclk_dppclk_vco_speed_mhz =
3697 le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz);
3698 dcn2_0_nv12_soc.xfc_bus_transport_time_us =
3699 le32_to_cpu(bb->xfc_bus_transport_time_us);
3700 dcn2_0_nv12_soc.xfc_xbuf_latency_tolerance_us =
3701 le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us);
3702 dcn2_0_nv12_soc.use_urgent_burst_bw =
3703 le32_to_cpu(bb->use_urgent_burst_bw);
3704 dcn2_0_nv12_soc.num_states =
3705 le32_to_cpu(bb->num_states);
3706
3707 for (i = 0; i < dcn2_0_nv12_soc.num_states; i++) {
3708 dcn2_0_nv12_soc.clock_limits[i].state =
3709 le32_to_cpu(bb->clock_limits[i].state);
3710 dcn2_0_nv12_soc.clock_limits[i].dcfclk_mhz =
3711 fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz);
3712 dcn2_0_nv12_soc.clock_limits[i].fabricclk_mhz =
3713 fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz);
3714 dcn2_0_nv12_soc.clock_limits[i].dispclk_mhz =
3715 fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz);
3716 dcn2_0_nv12_soc.clock_limits[i].dppclk_mhz =
3717 fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz);
3718 dcn2_0_nv12_soc.clock_limits[i].phyclk_mhz =
3719 fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz);
3720 dcn2_0_nv12_soc.clock_limits[i].socclk_mhz =
3721 fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz);
3722 dcn2_0_nv12_soc.clock_limits[i].dscclk_mhz =
3723 fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz);
3724 dcn2_0_nv12_soc.clock_limits[i].dram_speed_mts =
3725 fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts);
3726 }
3727 }
3728
3729 if (pool->base.pp_smu) {
3730 struct pp_smu_nv_clock_table max_clocks = {0};
3731 unsigned int uclk_states[8] = {0};
3732 unsigned int num_states = 0;
3733 enum pp_smu_status status;
3734 bool clock_limits_available = false;
3735 bool uclk_states_available = false;
3736
3737 if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {
3738 status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)
3739 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
3740
3741 uclk_states_available = (status == PP_SMU_RESULT_OK);
3742 }
3743
3744 if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {
3745 status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
3746 (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);
3747 /* SMU cannot set DCF clock to anything equal to or higher than SOC clock
3748 */
3749 if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz)
3750 max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000;
3751 clock_limits_available = (status == PP_SMU_RESULT_OK);
3752 }
3753
3754 if (clock_limits_available && uclk_states_available && num_states)
3755 dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
3756 else if (clock_limits_available)
3757 dcn20_cap_soc_clocks(loaded_bb, max_clocks);
3758 }
3759
3760 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
3761 loaded_ip->max_num_dpp = pool->base.pipe_count;
3762 dcn20_patch_bounding_box(dc, loaded_bb);
3763
3764 return true;
3765 }
3766
3767 static bool dcn20_resource_construct(
3768 uint8_t num_virtual_links,
3769 struct dc *dc,
3770 struct dcn20_resource_pool *pool)
3771 {
3772 int i;
3773 struct dc_context *ctx = dc->ctx;
3774 struct irq_service_init_data init_data;
3775 struct ddc_service_init_data ddc_init_data;
3776 struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
3777 get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev);
3778 struct _vcs_dpi_ip_params_st *loaded_ip =
3779 get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev);
3780 enum dml_project dml_project_version =
3781 get_dml_project_version(ctx->asic_id.hw_internal_rev);
3782
3783 DC_FP_START();
3784
3785 ctx->dc_bios->regs = &bios_regs;
3786 pool->base.funcs = &dcn20_res_pool_funcs;
3787
3788 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
3789 pool->base.res_cap = &res_cap_nv14;
3790 pool->base.pipe_count = 5;
3791 pool->base.mpcc_count = 5;
3792 } else {
3793 pool->base.res_cap = &res_cap_nv10;
3794 pool->base.pipe_count = 6;
3795 pool->base.mpcc_count = 6;
3796 }
3797 /*************************************************
3798 * Resource + asic cap harcoding *
3799 *************************************************/
3800 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
3801
3802 dc->caps.max_downscale_ratio = 200;
3803 dc->caps.i2c_speed_in_khz = 100;
3804 dc->caps.max_cursor_size = 256;
3805 dc->caps.dmdata_alloc_size = 2048;
3806
3807 dc->caps.max_slave_planes = 1;
3808 dc->caps.post_blend_color_processing = true;
3809 dc->caps.force_dp_tps4_for_cp2520 = true;
3810 dc->caps.extended_aux_timeout_support = true;
3811
3812 /* Color pipeline capabilities */
3813 dc->caps.color.dpp.dcn_arch = 1;
3814 dc->caps.color.dpp.input_lut_shared = 0;
3815 dc->caps.color.dpp.icsc = 1;
3816 dc->caps.color.dpp.dgam_ram = 1;
3817 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
3818 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
3819 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
3820 dc->caps.color.dpp.dgam_rom_caps.pq = 0;
3821 dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
3822 dc->caps.color.dpp.post_csc = 0;
3823 dc->caps.color.dpp.gamma_corr = 0;
3824
3825 dc->caps.color.dpp.hw_3d_lut = 1;
3826 dc->caps.color.dpp.ogam_ram = 1;
3827 // no OGAM ROM on DCN2, only MPC ROM
3828 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
3829 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
3830 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
3831 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
3832 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
3833 dc->caps.color.dpp.ocsc = 0;
3834
3835 dc->caps.color.mpc.gamut_remap = 0;
3836 dc->caps.color.mpc.num_3dluts = 0;
3837 dc->caps.color.mpc.shared_3d_lut = 0;
3838 dc->caps.color.mpc.ogam_ram = 1;
3839 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
3840 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
3841 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
3842 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
3843 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
3844 dc->caps.color.mpc.ocsc = 1;
3845
3846 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) {
3847 dc->debug = debug_defaults_drv;
3848 } else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
3849 pool->base.pipe_count = 4;
3850 pool->base.mpcc_count = pool->base.pipe_count;
3851 dc->debug = debug_defaults_diags;
3852 } else {
3853 dc->debug = debug_defaults_diags;
3854 }
3855 //dcn2.0x
3856 dc->work_arounds.dedcn20_305_wa = true;
3857
3858 // Init the vm_helper
3859 if (dc->vm_helper)
3860 vm_helper_init(dc->vm_helper, 16);
3861
3862 /*************************************************
3863 * Create resources *
3864 *************************************************/
3865
3866 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
3867 dcn20_clock_source_create(ctx, ctx->dc_bios,
3868 CLOCK_SOURCE_COMBO_PHY_PLL0,
3869 &clk_src_regs[0], false);
3870 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
3871 dcn20_clock_source_create(ctx, ctx->dc_bios,
3872 CLOCK_SOURCE_COMBO_PHY_PLL1,
3873 &clk_src_regs[1], false);
3874 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
3875 dcn20_clock_source_create(ctx, ctx->dc_bios,
3876 CLOCK_SOURCE_COMBO_PHY_PLL2,
3877 &clk_src_regs[2], false);
3878 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
3879 dcn20_clock_source_create(ctx, ctx->dc_bios,
3880 CLOCK_SOURCE_COMBO_PHY_PLL3,
3881 &clk_src_regs[3], false);
3882 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
3883 dcn20_clock_source_create(ctx, ctx->dc_bios,
3884 CLOCK_SOURCE_COMBO_PHY_PLL4,
3885 &clk_src_regs[4], false);
3886 pool->base.clock_sources[DCN20_CLK_SRC_PLL5] =
3887 dcn20_clock_source_create(ctx, ctx->dc_bios,
3888 CLOCK_SOURCE_COMBO_PHY_PLL5,
3889 &clk_src_regs[5], false);
3890 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL;
3891 /* todo: not reuse phy_pll registers */
3892 pool->base.dp_clock_source =
3893 dcn20_clock_source_create(ctx, ctx->dc_bios,
3894 CLOCK_SOURCE_ID_DP_DTO,
3895 &clk_src_regs[0], true);
3896
3897 for (i = 0; i < pool->base.clk_src_count; i++) {
3898 if (pool->base.clock_sources[i] == NULL) {
3899 dm_error("DC: failed to create clock sources!\n");
3900 BREAK_TO_DEBUGGER();
3901 goto create_fail;
3902 }
3903 }
3904
3905 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
3906 if (pool->base.dccg == NULL) {
3907 dm_error("DC: failed to create dccg!\n");
3908 BREAK_TO_DEBUGGER();
3909 goto create_fail;
3910 }
3911
3912 pool->base.dmcu = dcn20_dmcu_create(ctx,
3913 &dmcu_regs,
3914 &dmcu_shift,
3915 &dmcu_mask);
3916 if (pool->base.dmcu == NULL) {
3917 dm_error("DC: failed to create dmcu!\n");
3918 BREAK_TO_DEBUGGER();
3919 goto create_fail;
3920 }
3921
3922 pool->base.abm = dce_abm_create(ctx,
3923 &abm_regs,
3924 &abm_shift,
3925 &abm_mask);
3926 if (pool->base.abm == NULL) {
3927 dm_error("DC: failed to create abm!\n");
3928 BREAK_TO_DEBUGGER();
3929 goto create_fail;
3930 }
3931
3932 pool->base.pp_smu = dcn20_pp_smu_create(ctx);
3933
3934
3935 if (!init_soc_bounding_box(dc, pool)) {
3936 dm_error("DC: failed to initialize soc bounding box!\n");
3937 BREAK_TO_DEBUGGER();
3938 goto create_fail;
3939 }
3940
3941 dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version);
3942
3943 if (!dc->debug.disable_pplib_wm_range) {
3944 struct pp_smu_wm_range_sets ranges = {0};
3945 int i = 0;
3946
3947 ranges.num_reader_wm_sets = 0;
3948
3949 if (loaded_bb->num_states == 1) {
3950 ranges.reader_wm_sets[0].wm_inst = i;
3951 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3952 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3953 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3954 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3955
3956 ranges.num_reader_wm_sets = 1;
3957 } else if (loaded_bb->num_states > 1) {
3958 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
3959 ranges.reader_wm_sets[i].wm_inst = i;
3960 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3961 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3962 ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
3963 ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;
3964
3965 ranges.num_reader_wm_sets = i + 1;
3966 }
3967
3968 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3969 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3970 }
3971
3972 ranges.num_writer_wm_sets = 1;
3973
3974 ranges.writer_wm_sets[0].wm_inst = 0;
3975 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3976 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3977 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3978 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3979
3980 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
3981 if (pool->base.pp_smu->nv_funcs.set_wm_ranges)
3982 pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges);
3983 }
3984
3985 init_data.ctx = dc->ctx;
3986 pool->base.irqs = dal_irq_service_dcn20_create(&init_data);
3987 if (!pool->base.irqs)
3988 goto create_fail;
3989
3990 /* mem input -> ipp -> dpp -> opp -> TG */
3991 for (i = 0; i < pool->base.pipe_count; i++) {
3992 pool->base.hubps[i] = dcn20_hubp_create(ctx, i);
3993 if (pool->base.hubps[i] == NULL) {
3994 BREAK_TO_DEBUGGER();
3995 dm_error(
3996 "DC: failed to create memory input!\n");
3997 goto create_fail;
3998 }
3999
4000 pool->base.ipps[i] = dcn20_ipp_create(ctx, i);
4001 if (pool->base.ipps[i] == NULL) {
4002 BREAK_TO_DEBUGGER();
4003 dm_error(
4004 "DC: failed to create input pixel processor!\n");
4005 goto create_fail;
4006 }
4007
4008 pool->base.dpps[i] = dcn20_dpp_create(ctx, i);
4009 if (pool->base.dpps[i] == NULL) {
4010 BREAK_TO_DEBUGGER();
4011 dm_error(
4012 "DC: failed to create dpps!\n");
4013 goto create_fail;
4014 }
4015 }
4016 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
4017 pool->base.engines[i] = dcn20_aux_engine_create(ctx, i);
4018 if (pool->base.engines[i] == NULL) {
4019 BREAK_TO_DEBUGGER();
4020 dm_error(
4021 "DC:failed to create aux engine!!\n");
4022 goto create_fail;
4023 }
4024 pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i);
4025 if (pool->base.hw_i2cs[i] == NULL) {
4026 BREAK_TO_DEBUGGER();
4027 dm_error(
4028 "DC:failed to create hw i2c!!\n");
4029 goto create_fail;
4030 }
4031 pool->base.sw_i2cs[i] = NULL;
4032 }
4033
4034 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
4035 pool->base.opps[i] = dcn20_opp_create(ctx, i);
4036 if (pool->base.opps[i] == NULL) {
4037 BREAK_TO_DEBUGGER();
4038 dm_error(
4039 "DC: failed to create output pixel processor!\n");
4040 goto create_fail;
4041 }
4042 }
4043
4044 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
4045 pool->base.timing_generators[i] = dcn20_timing_generator_create(
4046 ctx, i);
4047 if (pool->base.timing_generators[i] == NULL) {
4048 BREAK_TO_DEBUGGER();
4049 dm_error("DC: failed to create tg!\n");
4050 goto create_fail;
4051 }
4052 }
4053
4054 pool->base.timing_generator_count = i;
4055
4056 pool->base.mpc = dcn20_mpc_create(ctx);
4057 if (pool->base.mpc == NULL) {
4058 BREAK_TO_DEBUGGER();
4059 dm_error("DC: failed to create mpc!\n");
4060 goto create_fail;
4061 }
4062
4063 pool->base.hubbub = dcn20_hubbub_create(ctx);
4064 if (pool->base.hubbub == NULL) {
4065 BREAK_TO_DEBUGGER();
4066 dm_error("DC: failed to create hubbub!\n");
4067 goto create_fail;
4068 }
4069
4070 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
4071 pool->base.dscs[i] = dcn20_dsc_create(ctx, i);
4072 if (pool->base.dscs[i] == NULL) {
4073 BREAK_TO_DEBUGGER();
4074 dm_error("DC: failed to create display stream compressor %d!\n", i);
4075 goto create_fail;
4076 }
4077 }
4078
4079 if (!dcn20_dwbc_create(ctx, &pool->base)) {
4080 BREAK_TO_DEBUGGER();
4081 dm_error("DC: failed to create dwbc!\n");
4082 goto create_fail;
4083 }
4084 if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
4085 BREAK_TO_DEBUGGER();
4086 dm_error("DC: failed to create mcif_wb!\n");
4087 goto create_fail;
4088 }
4089
4090 if (!resource_construct(num_virtual_links, dc, &pool->base,
4091 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
4092 &res_create_funcs : &res_create_maximus_funcs)))
4093 goto create_fail;
4094
4095 dcn20_hw_sequencer_construct(dc);
4096
4097 // IF NV12, set PG function pointer to NULL. It's not that
4098 // PG isn't supported for NV12, it's that we don't want to
4099 // program the registers because that will cause more power
4100 // to be consumed. We could have created dcn20_init_hw to get
4101 // the same effect by checking ASIC rev, but there was a
4102 // request at some point to not check ASIC rev on hw sequencer.
4103 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
4104 dc->hwseq->funcs.enable_power_gating_plane = NULL;
4105 dc->debug.disable_dpp_power_gate = true;
4106 dc->debug.disable_hubp_power_gate = true;
4107 }
4108
4109
4110 dc->caps.max_planes = pool->base.pipe_count;
4111
4112 for (i = 0; i < dc->caps.max_planes; ++i)
4113 dc->caps.planes[i] = plane_cap;
4114
4115 dc->cap_funcs = cap_funcs;
4116
4117 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
4118 ddc_init_data.ctx = dc->ctx;
4119 ddc_init_data.link = NULL;
4120 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
4121 ddc_init_data.id.enum_id = 0;
4122 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
4123 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
4124 } else {
4125 pool->base.oem_device = NULL;
4126 }
4127
4128 DC_FP_END();
4129 return true;
4130
4131 create_fail:
4132
4133 DC_FP_END();
4134 dcn20_resource_destruct(pool);
4135
4136 return false;
4137 }
4138
4139 struct resource_pool *dcn20_create_resource_pool(
4140 const struct dc_init_data *init_data,
4141 struct dc *dc)
4142 {
4143 struct dcn20_resource_pool *pool =
4144 kzalloc(sizeof(struct dcn20_resource_pool), GFP_KERNEL);
4145
4146 if (!pool)
4147 return NULL;
4148
4149 if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool))
4150 return &pool->base;
4151
4152 BREAK_TO_DEBUGGER();
4153 kfree(pool);
4154 return NULL;
4155 }
4156
