1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _CORE_TYPES_H_ 27 #define _CORE_TYPES_H_ 28 29 #include "dc.h" 30 #include "dce_calcs.h" 31 #include "dcn_calcs.h" 32 #include "ddc_service_types.h" 33 #include "dc_bios_types.h" 34 #include "mem_input.h" 35 #include "hubp.h" 36 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 37 #include "mpc.h" 38 #endif 39 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 40 #include "dwb.h" 41 #include "mcif_wb.h" 42 #endif 43 44 #define MAX_CLOCK_SOURCES 7 45 46 void enable_surface_flip_reporting(struct dc_plane_state *plane_state, 47 uint32_t controller_id); 48 49 #include "grph_object_id.h" 50 #include "link_encoder.h" 51 #include "stream_encoder.h" 52 #include "clock_source.h" 53 #include "audio.h" 54 #include "dm_pp_smu.h" 55 56 57 /************ link *****************/ 58 struct link_init_data { 59 const struct dc *dc; 60 struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */ 61 uint32_t connector_index; /* this will be mapped to the HPD pins */ 62 uint32_t link_index; /* this is mapped to DAL display_index 63 TODO: remove it when DC is complete. */ 64 }; 65 66 struct dc_link *link_create(const struct link_init_data *init_params); 67 void link_destroy(struct dc_link **link); 68 69 enum dc_status dc_link_validate_mode_timing( 70 const struct dc_stream_state *stream, 71 struct dc_link *link, 72 const struct dc_crtc_timing *timing); 73 74 void core_link_resume(struct dc_link *link); 75 76 void core_link_enable_stream( 77 struct dc_state *state, 78 struct pipe_ctx *pipe_ctx); 79 80 void core_link_disable_stream(struct pipe_ctx *pipe_ctx); 81 82 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); 83 /********** DAL Core*********************/ 84 #include "transform.h" 85 #include "dpp.h" 86 87 struct resource_pool; 88 struct dc_state; 89 struct resource_context; 90 #if defined(CONFIG_DRM_AMD_DC_DCN2_1) 91 struct clk_bw_params; 92 #endif 93 94 struct resource_funcs { 95 void (*destroy)(struct resource_pool **pool); 96 void (*link_init)(struct dc_link *link); 97 struct link_encoder *(*link_enc_create)( 98 const struct encoder_init_data *init); 99 bool (*validate_bandwidth)( 100 struct dc *dc, 101 struct dc_state *context, 102 bool fast_validate); 103 104 int (*populate_dml_pipes)( 105 struct dc *dc, 106 struct resource_context *res_ctx, 107 display_e2e_pipe_params_st *pipes); 108 109 enum dc_status (*validate_global)( 110 struct dc *dc, 111 struct dc_state *context); 112 113 struct pipe_ctx *(*acquire_idle_pipe_for_layer)( 114 struct dc_state *context, 115 const struct resource_pool *pool, 116 struct dc_stream_state *stream); 117 118 enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state, struct dc_caps *caps); 119 120 enum dc_status (*add_stream_to_ctx)( 121 struct dc *dc, 122 struct dc_state *new_ctx, 123 struct dc_stream_state *dc_stream); 124 125 enum dc_status (*remove_stream_from_ctx)( 126 struct dc *dc, 127 struct dc_state *new_ctx, 128 struct dc_stream_state *stream); 129 enum dc_status (*get_default_swizzle_mode)( 130 struct dc_plane_state *plane_state); 131 132 struct stream_encoder *(*find_first_free_match_stream_enc_for_link)( 133 struct resource_context *res_ctx, 134 const struct resource_pool *pool, 135 struct dc_stream_state *stream); 136 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 137 void (*populate_dml_writeback_from_context)( 138 struct dc *dc, 139 struct resource_context *res_ctx, 140 display_e2e_pipe_params_st *pipes); 141 142 void (*set_mcif_arb_params)( 143 struct dc *dc, 144 struct dc_state *context, 145 display_e2e_pipe_params_st *pipes, 146 int pipe_cnt); 147 #endif 148 #if defined(CONFIG_DRM_AMD_DC_DCN2_1) 149 void (*update_bw_bounding_box)( 150 struct dc *dc, 151 struct clk_bw_params *bw_params); 152 #endif 153 154 }; 155 156 struct audio_support{ 157 bool dp_audio; 158 bool hdmi_audio_on_dongle; 159 bool hdmi_audio_native; 160 }; 161 162 #define NO_UNDERLAY_PIPE -1 163 164 struct resource_pool { 165 struct mem_input *mis[MAX_PIPES]; 166 struct hubp *hubps[MAX_PIPES]; 167 struct input_pixel_processor *ipps[MAX_PIPES]; 168 struct transform *transforms[MAX_PIPES]; 169 struct dpp *dpps[MAX_PIPES]; 170 struct output_pixel_processor *opps[MAX_PIPES]; 171 struct timing_generator *timing_generators[MAX_PIPES]; 172 struct stream_encoder *stream_enc[MAX_PIPES * 2]; 173 struct hubbub *hubbub; 174 struct mpc *mpc; 175 struct pp_smu_funcs *pp_smu; 176 struct dce_aux *engines[MAX_PIPES]; 177 struct dce_i2c_hw *hw_i2cs[MAX_PIPES]; 178 struct dce_i2c_sw *sw_i2cs[MAX_PIPES]; 179 bool i2c_hw_buffer_in_use; 180 181 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 182 struct dwbc *dwbc[MAX_DWB_PIPES]; 183 struct mcif_wb *mcif_wb[MAX_DWB_PIPES]; 184 struct { 185 unsigned int gsl_0:1; 186 unsigned int gsl_1:1; 187 unsigned int gsl_2:1; 188 } gsl_groups; 189 #endif 190 191 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 192 struct display_stream_compressor *dscs[MAX_PIPES]; 193 #endif 194 195 unsigned int pipe_count; 196 unsigned int underlay_pipe_index; 197 unsigned int stream_enc_count; 198 199 struct { 200 unsigned int xtalin_clock_inKhz; 201 unsigned int dccg_ref_clock_inKhz; 202 unsigned int dchub_ref_clock_inKhz; 203 } ref_clocks; 204 unsigned int timing_generator_count; 205 unsigned int mpcc_count; 206 207 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 208 unsigned int writeback_pipe_count; 209 #endif 210 /* 211 * reserved clock source for DP 212 */ 213 struct clock_source *dp_clock_source; 214 215 struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; 216 unsigned int clk_src_count; 217 218 struct audio *audios[MAX_AUDIOS]; 219 unsigned int audio_count; 220 struct audio_support audio_support; 221 222 struct dccg *dccg; 223 struct irq_service *irqs; 224 225 struct abm *abm; 226 struct dmcu *dmcu; 227 228 const struct resource_funcs *funcs; 229 const struct resource_caps *res_cap; 230 }; 231 232 struct dcn_fe_bandwidth { 233 int dppclk_khz; 234 }; 235 236 struct stream_resource { 237 struct output_pixel_processor *opp; 238 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 239 struct display_stream_compressor *dsc; 240 #endif 241 struct timing_generator *tg; 242 struct stream_encoder *stream_enc; 243 struct audio *audio; 244 245 struct pixel_clk_params pix_clk_params; 246 struct encoder_info_frame encoder_info_frame; 247 248 struct abm *abm; 249 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 250 /* There are only (num_pipes+1)/2 groups. 0 means unassigned, 251 * otherwise it's using group number 'gsl_group-1' 252 */ 253 uint8_t gsl_group; 254 #endif 255 }; 256 257 struct plane_resource { 258 struct scaler_data scl_data; 259 struct hubp *hubp; 260 struct mem_input *mi; 261 struct input_pixel_processor *ipp; 262 struct transform *xfm; 263 struct dpp *dpp; 264 uint8_t mpcc_inst; 265 266 struct dcn_fe_bandwidth bw; 267 }; 268 269 union pipe_update_flags { 270 struct { 271 uint32_t enable : 1; 272 uint32_t disable : 1; 273 uint32_t odm : 1; 274 uint32_t global_sync : 1; 275 uint32_t opp_changed : 1; 276 uint32_t tg_changed : 1; 277 uint32_t mpcc : 1; 278 uint32_t dppclk : 1; 279 uint32_t hubp_interdependent : 1; 280 uint32_t hubp_rq_dlg_ttu : 1; 281 uint32_t gamut_remap : 1; 282 uint32_t scaler : 1; 283 uint32_t viewport : 1; 284 } bits; 285 uint32_t raw; 286 }; 287 288 struct pipe_ctx { 289 struct dc_plane_state *plane_state; 290 struct dc_stream_state *stream; 291 292 struct plane_resource plane_res; 293 struct stream_resource stream_res; 294 295 struct clock_source *clock_source; 296 297 struct pll_settings pll_settings; 298 299 uint8_t pipe_idx; 300 301 struct pipe_ctx *top_pipe; 302 struct pipe_ctx *bottom_pipe; 303 struct pipe_ctx *next_odm_pipe; 304 struct pipe_ctx *prev_odm_pipe; 305 306 #ifdef CONFIG_DRM_AMD_DC_DCN1_0 307 struct _vcs_dpi_display_dlg_regs_st dlg_regs; 308 struct _vcs_dpi_display_ttu_regs_st ttu_regs; 309 struct _vcs_dpi_display_rq_regs_st rq_regs; 310 struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; 311 #endif 312 union pipe_update_flags update_flags; 313 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 314 struct dwbc *dwbc; 315 struct mcif_wb *mcif_wb; 316 #endif 317 }; 318 319 struct resource_context { 320 struct pipe_ctx pipe_ctx[MAX_PIPES]; 321 bool is_stream_enc_acquired[MAX_PIPES * 2]; 322 bool is_audio_acquired[MAX_PIPES]; 323 uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; 324 uint8_t dp_clock_source_ref_count; 325 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 326 bool is_dsc_acquired[MAX_PIPES]; 327 #endif 328 }; 329 330 struct dce_bw_output { 331 bool cpuc_state_change_enable; 332 bool cpup_state_change_enable; 333 bool stutter_mode_enable; 334 bool nbp_state_change_enable; 335 bool all_displays_in_sync; 336 struct dce_watermarks urgent_wm_ns[MAX_PIPES]; 337 struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES]; 338 struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES]; 339 struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES]; 340 int sclk_khz; 341 int sclk_deep_sleep_khz; 342 int yclk_khz; 343 int dispclk_khz; 344 int blackout_recovery_time_us; 345 }; 346 347 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 348 struct dcn_bw_writeback { 349 struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES]; 350 }; 351 #endif 352 353 struct dcn_bw_output { 354 struct dc_clocks clk; 355 struct dcn_watermark_set watermarks; 356 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 357 struct dcn_bw_writeback bw_writeback; 358 #endif 359 }; 360 361 union bw_output { 362 struct dcn_bw_output dcn; 363 struct dce_bw_output dce; 364 }; 365 366 struct bw_context { 367 union bw_output bw; 368 struct display_mode_lib dml; 369 }; 370 /** 371 * struct dc_state - The full description of a state requested by a user 372 * 373 * @streams: Stream properties 374 * @stream_status: The planes on a given stream 375 * @res_ctx: Persistent state of resources 376 * @bw_ctx: The output from bandwidth and watermark calculations and the DML 377 * @pp_display_cfg: PowerPlay clocks and settings 378 * @dcn_bw_vars: non-stack memory to support bandwidth calculations 379 * 380 */ 381 struct dc_state { 382 struct dc_stream_state *streams[MAX_PIPES]; 383 struct dc_stream_status stream_status[MAX_PIPES]; 384 uint8_t stream_count; 385 386 struct resource_context res_ctx; 387 388 struct bw_context bw_ctx; 389 390 /* Note: these are big structures, do *not* put on stack! */ 391 struct dm_pp_display_configuration pp_display_cfg; 392 #ifdef CONFIG_DRM_AMD_DC_DCN1_0 393 struct dcn_bw_internal_vars dcn_bw_vars; 394 #endif 395 396 struct clk_mgr *clk_mgr; 397 398 struct { 399 bool full_update_needed : 1; 400 } commit_hints; 401 402 struct kref refcount; 403 }; 404 405 #endif /* _CORE_TYPES_H_ */ 406
