1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /******************************************************************************* 3 4 Header file for stmmac platform data 5 6 Copyright (C) 2009 STMicroelectronics Ltd 7 8 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 *******************************************************************************/ 11 12 #ifndef __STMMAC_PLATFORM_DATA 13 #define __STMMAC_PLATFORM_DATA 14 15 #include <linux/platform_device.h> 16 #include <linux/phy.h> 17 18 #define MTL_MAX_RX_QUEUES 8 19 #define MTL_MAX_TX_QUEUES 8 20 #define STMMAC_CH_MAX 8 21 22 #define STMMAC_RX_COE_NONE 0 23 #define STMMAC_RX_COE_TYPE1 1 24 #define STMMAC_RX_COE_TYPE2 2 25 26 /* Define the macros for CSR clock range parameters to be passed by 27 * platform code. 28 * This could also be configured at run time using CPU freq framework. */ 29 30 /* MDC Clock Selection define*/ 31 #define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */ 32 #define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */ 33 #define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */ 34 #define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */ 35 #define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */ 36 #define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */ 37 38 /* MTL algorithms identifiers */ 39 #define MTL_TX_ALGORITHM_WRR 0x0 40 #define MTL_TX_ALGORITHM_WFQ 0x1 41 #define MTL_TX_ALGORITHM_DWRR 0x2 42 #define MTL_TX_ALGORITHM_SP 0x3 43 #define MTL_RX_ALGORITHM_SP 0x4 44 #define MTL_RX_ALGORITHM_WSP 0x5 45 46 /* RX/TX Queue Mode */ 47 #define MTL_QUEUE_AVB 0x0 48 #define MTL_QUEUE_DCB 0x1 49 50 /* The MDC clock could be set higher than the IEEE 802.3 51 * specified frequency limit 0f 2.5 MHz, by programming a clock divider 52 * of value different than the above defined values. The resultant MDIO 53 * clock frequency of 12.5 MHz is applicable for the interfacing chips 54 * supporting higher MDC clocks. 55 * The MDC clock selection macros need to be defined for MDC clock rate 56 * of 12.5 MHz, corresponding to the following selection. 57 */ 58 #define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */ 59 #define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */ 60 #define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */ 61 #define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */ 62 #define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */ 63 #define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */ 64 #define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */ 65 #define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */ 66 67 /* AXI DMA Burst length supported */ 68 #define DMA_AXI_BLEN_4 (1 << 1) 69 #define DMA_AXI_BLEN_8 (1 << 2) 70 #define DMA_AXI_BLEN_16 (1 << 3) 71 #define DMA_AXI_BLEN_32 (1 << 4) 72 #define DMA_AXI_BLEN_64 (1 << 5) 73 #define DMA_AXI_BLEN_128 (1 << 6) 74 #define DMA_AXI_BLEN_256 (1 << 7) 75 #define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \ 76 | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \ 77 | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256) 78 79 struct stmmac_priv; 80 81 /* Platfrom data for platform device structure's platform_data field */ 82 83 struct stmmac_mdio_bus_data { 84 unsigned int phy_mask; 85 unsigned int has_xpcs; 86 unsigned int xpcs_an_inband; 87 int *irqs; 88 int probed_phy_irq; 89 bool needs_reset; 90 }; 91 92 struct stmmac_dma_cfg { 93 int pbl; 94 int txpbl; 95 int rxpbl; 96 bool pblx8; 97 int fixed_burst; 98 int mixed_burst; 99 bool aal; 100 bool eame; 101 bool multi_msi_en; 102 bool dche; 103 }; 104 105 #define AXI_BLEN 7 106 struct stmmac_axi { 107 bool axi_lpi_en; 108 bool axi_xit_frm; 109 u32 axi_wr_osr_lmt; 110 u32 axi_rd_osr_lmt; 111 bool axi_kbbe; 112 u32 axi_blen[AXI_BLEN]; 113 bool axi_fb; 114 bool axi_mb; 115 bool axi_rb; 116 }; 117 118 #define EST_GCL 1024 119 struct stmmac_est { 120 struct mutex lock; 121 int enable; 122 u32 btr_reserve[2]; 123 u32 btr_offset[2]; 124 u32 btr[2]; 125 u32 ctr[2]; 126 u32 ter; 127 u32 gcl_unaligned[EST_GCL]; 128 u32 gcl[EST_GCL]; 129 u32 gcl_size; 130 }; 131 132 struct stmmac_rxq_cfg { 133 u8 mode_to_use; 134 u32 chan; 135 u8 pkt_route; 136 bool use_prio; 137 u32 prio; 138 }; 139 140 struct stmmac_txq_cfg { 141 u32 weight; 142 u8 mode_to_use; 143 /* Credit Base Shaper parameters */ 144 u32 send_slope; 145 u32 idle_slope; 146 u32 high_credit; 147 u32 low_credit; 148 bool use_prio; 149 u32 prio; 150 int tbs_en; 151 }; 152 153 /* FPE link state */ 154 enum stmmac_fpe_state { 155 FPE_STATE_OFF = 0, 156 FPE_STATE_CAPABLE = 1, 157 FPE_STATE_ENTERING_ON = 2, 158 FPE_STATE_ON = 3, 159 }; 160 161 /* FPE link-partner hand-shaking mPacket type */ 162 enum stmmac_mpacket_type { 163 MPACKET_VERIFY = 0, 164 MPACKET_RESPONSE = 1, 165 }; 166 167 enum stmmac_fpe_task_state_t { 168 __FPE_REMOVING, 169 __FPE_TASK_SCHED, 170 }; 171 172 struct stmmac_fpe_cfg { 173 bool enable; /* FPE enable */ 174 bool hs_enable; /* FPE handshake enable */ 175 enum stmmac_fpe_state lp_fpe_state; /* Link Partner FPE state */ 176 enum stmmac_fpe_state lo_fpe_state; /* Local station FPE state */ 177 }; 178 179 struct stmmac_safety_feature_cfg { 180 u32 tsoee; 181 u32 mrxpee; 182 u32 mestee; 183 u32 mrxee; 184 u32 mtxee; 185 u32 epsi; 186 u32 edpp; 187 u32 prtyen; 188 u32 tmouten; 189 }; 190 191 /* Addresses that may be customized by a platform */ 192 struct dwmac4_addrs { 193 u32 dma_chan; 194 u32 dma_chan_offset; 195 u32 mtl_chan; 196 u32 mtl_chan_offset; 197 u32 mtl_ets_ctrl; 198 u32 mtl_ets_ctrl_offset; 199 u32 mtl_txq_weight; 200 u32 mtl_txq_weight_offset; 201 u32 mtl_send_slp_cred; 202 u32 mtl_send_slp_cred_offset; 203 u32 mtl_high_cred; 204 u32 mtl_high_cred_offset; 205 u32 mtl_low_cred; 206 u32 mtl_low_cred_offset; 207 }; 208 209 #define STMMAC_FLAG_HAS_INTEGRATED_PCS BIT(0) 210 #define STMMAC_FLAG_SPH_DISABLE BIT(1) 211 #define STMMAC_FLAG_USE_PHY_WOL BIT(2) 212 #define STMMAC_FLAG_HAS_SUN8I BIT(3) 213 #define STMMAC_FLAG_TSO_EN BIT(4) 214 #define STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP BIT(5) 215 #define STMMAC_FLAG_VLAN_FAIL_Q_EN BIT(6) 216 #define STMMAC_FLAG_MULTI_MSI_EN BIT(7) 217 #define STMMAC_FLAG_EXT_SNAPSHOT_EN BIT(8) 218 #define STMMAC_FLAG_INT_SNAPSHOT_EN BIT(9) 219 #define STMMAC_FLAG_RX_CLK_RUNS_IN_LPI BIT(10) 220 #define STMMAC_FLAG_EN_TX_LPI_CLOCKGATING BIT(11) 221 #define STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY BIT(12) 222 223 struct plat_stmmacenet_data { 224 int bus_id; 225 int phy_addr; 226 /* MAC ----- optional PCS ----- SerDes ----- optional PHY ----- Media 227 * ^ ^ 228 * mac_interface phy_interface 229 * 230 * mac_interface is the MAC-side interface, which may be the same 231 * as phy_interface if there is no intervening PCS. If there is a 232 * PCS, then mac_interface describes the interface mode between the 233 * MAC and PCS, and phy_interface describes the interface mode 234 * between the PCS and PHY. 235 */ 236 phy_interface_t mac_interface; 237 /* phy_interface is the PHY-side interface - the interface used by 238 * an attached PHY. 239 */ 240 phy_interface_t phy_interface; 241 struct stmmac_mdio_bus_data *mdio_bus_data; 242 struct device_node *phy_node; 243 struct fwnode_handle *port_node; 244 struct device_node *mdio_node; 245 struct stmmac_dma_cfg *dma_cfg; 246 struct stmmac_est *est; 247 struct stmmac_fpe_cfg *fpe_cfg; 248 struct stmmac_safety_feature_cfg *safety_feat_cfg; 249 int clk_csr; 250 int has_gmac; 251 int enh_desc; 252 int tx_coe; 253 int rx_coe; 254 int bugged_jumbo; 255 int pmt; 256 int force_sf_dma_mode; 257 int force_thresh_dma_mode; 258 int riwt_off; 259 int max_speed; 260 int maxmtu; 261 int multicast_filter_bins; 262 int unicast_filter_entries; 263 int tx_fifo_size; 264 int rx_fifo_size; 265 u32 host_dma_width; 266 u32 rx_queues_to_use; 267 u32 tx_queues_to_use; 268 u8 rx_sched_algorithm; 269 u8 tx_sched_algorithm; 270 struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES]; 271 struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES]; 272 void (*fix_mac_speed)(void *priv, unsigned int speed, unsigned int mode); 273 int (*fix_soc_reset)(void *priv, void __iomem *ioaddr); 274 int (*serdes_powerup)(struct net_device *ndev, void *priv); 275 void (*serdes_powerdown)(struct net_device *ndev, void *priv); 276 void (*speed_mode_2500)(struct net_device *ndev, void *priv); 277 void (*ptp_clk_freq_config)(struct stmmac_priv *priv); 278 int (*init)(struct platform_device *pdev, void *priv); 279 void (*exit)(struct platform_device *pdev, void *priv); 280 struct mac_device_info *(*setup)(void *priv); 281 int (*clks_config)(void *priv, bool enabled); 282 int (*crosststamp)(ktime_t *device, struct system_counterval_t *system, 283 void *ctx); 284 void (*dump_debug_regs)(void *priv); 285 void *bsp_priv; 286 struct clk *stmmac_clk; 287 struct clk *pclk; 288 struct clk *clk_ptp_ref; 289 unsigned int clk_ptp_rate; 290 unsigned int clk_ref_rate; 291 unsigned int mult_fact_100ns; 292 s32 ptp_max_adj; 293 u32 cdc_error_adj; 294 struct reset_control *stmmac_rst; 295 struct reset_control *stmmac_ahb_rst; 296 struct stmmac_axi *axi; 297 int has_gmac4; 298 int rss_en; 299 int mac_port_sel_speed; 300 int has_xgmac; 301 u8 vlan_fail_q; 302 unsigned int eee_usecs_rate; 303 struct pci_dev *pdev; 304 int int_snapshot_num; 305 int ext_snapshot_num; 306 int msi_mac_vec; 307 int msi_wol_vec; 308 int msi_lpi_vec; 309 int msi_sfty_ce_vec; 310 int msi_sfty_ue_vec; 311 int msi_rx_base_vec; 312 int msi_tx_base_vec; 313 const struct dwmac4_addrs *dwmac4_addrs; 314 unsigned int flags; 315 }; 316 #endif 317
